JP2018525811A - Inspection of defects in preceding layers using design - Google Patents

Abstract

Disclosed are systems and methods for imaging a layer of a wafer based on the coordinates of a defect in a preceding layer of the wafer. The current layer image can be used to align the current layer design file with the wafer. The design file of the previous layer can be aligned with the design file of the current layer.

Description

  The present disclosure relates to inspection and analysis of semiconductor wafer defects.

Cross-reference to related applications This application takes precedence over Indian Patent Application 3079 / CHE / 2015 filed June 19, 2015, and US Provisional Patent Application 62 / 204,328 filed August 12, 2015. The contents of both disclosures are cited in this specification.

  Wafer inspection systems help semiconductor manufacturers improve and maintain integrated circuit (IC) yields by detecting defects that occur during the chip manufacturing process. One purpose of the inspection system is to monitor whether the manufacturing process meets specifications. The inspection system indicates the problem and / or source of the problem when the manufacturing process deviates from established standards, and then the semiconductor manufacturer can address the problem.

  With the development of the semiconductor manufacturing industry, more demands have been made for yield management, and in particular for measurement and inspection systems. While the wafer size increases, the critical dimension decreases. Economic demands have driven industry to reduce the time to achieve high yield / value added production. Therefore, minimizing the total time from when a yield problem is detected until it is dealt with becomes a decisive factor for the return on investment of the semiconductor manufacturer.

  The semiconductor wafer may include a plurality of layers. Defects in one layer can affect manufacturing in subsequently formed layers. Defects can also affect wafer yield regardless of the location of the defect. A portion having a defect in a previously formed layer or a previously formed layer may be referred to as a “preceding layer defect portion”. It would be useful to monitor defects and their impact on subsequent layers. Therefore, the semiconductor manufacturer may inspect the defects in the preceding layer for further mass production.

US Patent Application Publication No. 2012/0131529 US Pat. No. 6,035,244 US Patent Application Publication No. 2008/0032429

  During semiconductor fabrication, defect inspection tools such as broadband plasma, laser scanning, or electron beam can be used to find potential defects in each layer of the wafer. Next, the location of the defect is inspected, for example, under a scanning electron microscope (SEM) capable of forming a high resolution image to confirm the presence and / or type of the defect.

  It is difficult to monitor the effect of defects in a previously formed layer on one or more subsequent layers. The images of the various wafer layers are not aligned. Therefore, by visually recognizing the site of a defect in a certain layer using coordinates from a previously formed layer using, for example, an SEM tool, there is a possibility that an erroneous area of the wafer is visually recognized. Since the coordinate system can be different for different layers of the wafer, it is impossible to correct the inclination of the image of the layer. Often the user guesses whether, for example, the SEM image is an area corresponding to a defect location in the preceding layer. Semiconductor manufacturers waste time in confirming that a particular location in the image corresponds to a preceding layer defect location. This comparison is cumbersome because approximate pattern matching can only be obtained with a few layers. If the spacing between images is wider than several layers, the pattern differences in the images may be too great to confirm that the features in the image of the later formed layer correspond to the position of the preceding layer defect. There is.

  Accordingly, there is a need for improved systems and methods for wafer inspection.

  In the first embodiment, a system is provided. The system includes a defect inspection tool and a controller configured to communicate with the defect inspection tool. The defect inspection tool includes a mounting table configured to secure the wafer and an image generation system configured to generate an image of a layer on the surface of the wafer. The controller aligns the design file of the current layer of the wafer with the image of the current layer, aligns the design file of the previous layer of the wafer with the design file of the current layer, and based on the coordinates of the defects in the previous layer, It is configured to identify an image area. The preceding layer is formed before the current layer. The region corresponds to the coordinates of the defect in the preceding layer. The image of the current layer may be a scanning electron microscope image.

  The controller may include a processor, a storage device in electronic communication with the processor, and a communication port in electronic communication with the processor.

  At least one mold corner of the wafer can be marked. The controller can be further configured to align the mold corners with the mold coordinate system of the preceding layer after aligning the design files of the preceding layer.

  The controller can be further configured to perform tilt correction of the current layer image.

  The controller can be further configured to generate a coordinate system for the current layer and a corresponding coordinate system for the preceding layer.

  The controller is further configurable to align the previous layer image with at least one of the previous layer design file or the current layer design file.

  The image generation system can be configured to use at least one of an electron beam, a broadband plasma, or a laser.

  In a second embodiment, a method is provided. The method includes aligning a wafer of a defect inspection tool using a mounting table, marking at least one mold corner of the wafer, and using a controller to obtain a design file for the current layer of the wafer. Aligning the image of the previous layer of the wafer with the design file of the current layer using the controller, and aligning the region of the image of the current layer with the coordinates of the defect in the previous layer using the controller. Identifying based on. The preceding layer is formed before the current layer. This area corresponds to the coordinates of the defect in the preceding layer. The image of the current layer may be a scanning electron microscope image.

  The method may further include aligning the mold corners with the mold coordinate system of the preceding layer after aligning the design file of the preceding layer.

  The method may further comprise generating a lot having defect images of the current layer and the previous layer using a controller.

  The method may further include the step of correcting the tilt of the current layer image using a controller.

  The method may further include generating a coordinate system for the current layer using the controller and generating a corresponding coordinate system for the preceding layer.

  The method may further comprise aligning the image of the previous layer with at least one of the previous layer design file or the current layer design file.

  The method may further comprise the step of identifying the position of the defect in the image of the previous layer using the controller before identifying the region of the image of the current layer. The image of the previous layer can be aligned with the design file of the previous layer.

For a fuller understanding of the nature and purpose of the present disclosure, reference should be made to the following detailed description taken together with the accompanying figures.
It is a block diagram of the defect inspection tool by this indication 2 is an exemplary pre-layer and current layer design and SEM image. 2 is an exemplary pre-layer and current layer design and SEM image. 2 is an exemplary pre-layer and current layer design and SEM image. 2 is an exemplary pre-layer and current layer design and SEM image. FIG. 3 is an exemplary pre-layer image. FIG. 2 is an example current layer image. FIG. 3 is a flow diagram illustrating an embodiment according to the present disclosure.

  Other embodiments, including embodiments that claim claimed subject matter as specific embodiments, but do not provide all of the advantages and features described herein are also within the scope of this disclosure. . Various structural, logical, processing step, and electronic changes can be made without departing from the scope of the present disclosure. Accordingly, the scope of the present disclosure is defined only by the appended claims.

  Embodiments of the systems and methods disclosed herein allow for improved wafer layer inspection or wafer defect monitoring. The area of the layer can be quickly inspected or inspected based on the location of the preceding layer ("pre-layer") defect location. Semiconductor manufacturers can monitor defect locations in the preceding layer at multiple stages or points in the manufacturing process. For example, defect locations in the preceding layer can be monitored during or after performing some or all of the subsequent processing steps. The classification of defects in the preceding layer allows semiconductor manufacturers to focus on the type of defect of interest (DOI) that affects multiple layers of the wafer and reduces yield. Embodiments of the systems and methods disclosed herein can also provide improved and / or accelerated inspection throughput and eliminate manual inspection.

  As used herein, the term “wafer” generally refers to a substrate formed of a semiconductor or non-semiconductor material. Examples of such semiconductor or non-semiconductor materials include, but are not limited to, single crystal silicon, gallium nitride, gallium arsenide, indium phosphide, sapphire, and glass. Such substrates are commonly found and / or processed in semiconductor manufacturing facilities.

  The wafer may include one or more layers formed on the substrate. For example, such layers include, but are not limited to, photoresists, dielectric materials, conductive materials, and semiconductor materials. Although many such different types of layers are known in the art, the term wafer as used herein is intended for wafers containing all such types of layers.

  One or more layers formed on the wafer may or may not be patterned. For example, the wafer may include a plurality of molds each having a repeatable patterned feature or periodic structure. Forming and processing a layer of such a material results in a final finished device. Many different types of devices can be formed on a wafer, and the term wafer as used herein is intended for wafers on which any type of device known in the art is formed.

  FIG. 1 is a block diagram of a defect inspection tool 100 according to the present disclosure. The defect inspection tool 100 includes a mounting table 104 configured to secure the wafer 103. The mounting table 104 can be configured to move or rotate in one, two, or three axial directions.

  As shown in FIG. 1, the wafer 103 includes a plurality of layers. The current layer 110 is formed after the preceding layer 109. However, defects in the leading layer 109 can affect the current layer 110. If the current layer 110 is imaged as shown in FIG. 1, the preceding layer 109 may be imaged prior to the formation of the current layer 110. The number of layers may be more or less than the three layers shown in FIG.

  The defect inspection tool 100 also includes an image generation system 101 configured to generate an image of the surface of the wafer 103. The image may be of a specific layer of the wafer 103. In this example, the image generation system 101 emits an electron beam 102 to generate an image of the wafer 103. Other image generation systems 101 are possible, such as those using broadband plasma or laser scanning.

  In certain embodiments, defect inspection tool 100 is a scanning electron microscope (SEM) or part thereof. An image of the wafer 103 is generated by scanning the wafer 103 with the focused electron beam 102. Electrons are used to generate a signal that contains information about the surface shape and composition of the wafer 103. The electron beam 102 can be irradiated along the raster scanning pattern, and the position of the electron beam 102 can be combined with the detection signal to generate an image.

  The defect inspection tool 100 communicates with the controller 105. For example, the controller 105 can communicate with the image generation system 101 or other components of the defect inspection tool 100. The controller 105 may include a processor 106, a storage device 107 in electronic communication with the processor 106, and a communication port 108 in electronic communication with the processor 106. It should be understood that the controller 105 may actually be implemented by any combination of hardware, software, and firmware. The functions can also be performed by a single device, as described herein, or divided into different elements that can each be implemented by any combination of hardware, software, and firmware. Program code or instructions for controller 105 implementing the various methods and functions described herein may be stored in a controller-readable storage medium, such as memory in controller 105, outside controller 105, or a combination thereof.

  2-5 are exemplary leading and current layer designs and SEM images. FIG. 2 is a design file of the preceding layer, and FIG. 3 is a corresponding SEM image of the preceding layer. FIG. 4 is a design file of the current layer, and FIG. 5 is a corresponding SEM image of the current layer. The design files shown in FIGS. 2 and 4 and the SEM images shown in FIGS. 3 and 5 correspond to the same region of the wafer in this example. As can be seen when comparing FIGS. 3 and 5, images of different layers of the wafer can be different, making it difficult to pinpoint the location of the defect in the previous layer within the layer formed after the wafer. become.

  FIG. 6 is an exemplary preceding layer image. An area 201 of the wafer 200 is shown enlarged. Region 201 may correspond to another region of the mold or wafer. There is a preceding layer defect portion 202 (enclosed by a broken line) in the region 201. The defect at the preceding layer defect location 202 may be any defect found during semiconductor manufacturing. For example, defects include particles or contamination, pattern defects, scratches, etched cross-sectional defects, etch selectivity issues, inaccurate removal during planarization, critical dimensional issues, overlay issues, and other types of It may be a defect.

  FIG. 7 is an exemplary current layer image. The area 301 in the current layer corresponds to the area 201. However, the current layer in FIG. 7 is different from the preceding layer in FIG. The preceding layer in FIG. 6 is formed before the current layer in FIG. The current layer in FIG. 7 may be located directly above the preceding layer in FIG. The current layer of FIG. 7 may also be separated from the preceding layer of FIG. 6 with one or more additional layers between the current layer and the preceding layer.

  As shown in FIG. 7, the preceding layer defect location 202 above the current layer does not include elements or features found in the preceding layer of FIG. However, semiconductor manufacturers are interested in determining the impact of leading layer defect locations 202 on the current layer or other layers of wafer 200 formed after the preceding layer of FIG.

  FIG. 8 is a flow diagram illustrating an embodiment according to the present disclosure. The design file of the previous layer including the location of the original DOI and the design file of the current layer are used. Inspect the preceding layer with an inspection tool (eg, optical inspection, laser scanning, etc.) to find the defect coordinates of the preceding layer. These defect coordinates may be reported in the preceding layer design coordinate system. The position of the defective portion is confirmed using an image of the preceding layer, for example, an SEM image. The coordinates of the defect from the preceding layer are provided by a defect inspection tool, such as defect inspection tool 100, or some other defect inspection tool.

  In method 400, the wafer is placed on a defect inspection tool in step 401. In step 402, the wafer is aligned in the defect inspection tool using a mounting table for the defect inspection tool. The defect inspection tool may be a scanning electron microscope, for example. The wafer can be placed on a mounting table that rotates or moves to allow alignment. The image generation system can also be rotated or moved to allow alignment. The rotation or movement of the image generation system may be independent or complementary to the rotation or movement of the mounting table.

  In step 403, at least one mold corner of the wafer is marked for a defect inspection tool. Mold corners can be marked on a defect inspection tool. By marking the corner of the mold, the same mold corner can be referred to, confirmed, or separately used by two or more defect inspection tools and / or defect inspection tools. Therefore, the same XY coordinates can be used later. The mold corners can be marked manually by the user or automatically using the inspection tool mold corners. The mark may be physical or virtual. The same mold corner is marked in the preceding layer, the current layer, and one or more design files to accurately align with the defect location.

  In step 404, the design file of the current layer is aligned with the image of the current layer. The image may be an SEM image, for example. The current layer design file can be aligned with the image of the current layer at anchor points (eg, mold corners). The alignment position can be any anchor point with sufficient horizontal and vertical features. This facilitates or matches the design coordinate system with the wafer coordinate system. If any misalignment occurs in the design coordinate system, the transformation is calculated and / or applied to ensure that the defects identified and reported in the previous layer design coordinate system are converted to the current layer design coordinate system. If a defect is reported in the current design coordinate system, the user can identify the defect location in the preceding layer because the current layer design is already aligned with the wafer coordinate system of the current layer. Although alignment step 404 is shown between steps 403 and 405, it may be performed at other times during the execution of method 400.

  In step 405, the design file of the previous layer is aligned with the design layer of the current layer. As an example, by superimposing two design files on the same anchor point (eg, the same mold corner), the coordinate systems of both layers can be matched. The overlay may be complete or within acceptable tolerances.

  Between steps 405 and 407, if necessary, in step 406, the mold corners may be aligned with the mold coordinate system of the preceding layer. For example, the mold corners can be adjusted manually or automatically. Therefore, the same XY coordinates can be used later.

  In step 407, the current layer image is identified based on the coordinates of the defects in the previous layer. Accordingly, the SEM image of the current layer at the coordinates corresponding to the coordinates of the defective portion in the preceding layer can be visually recognized. By selecting the coordinates on the preceding layer, the corresponding coordinates in the current layer can be visually recognized as a result. Therefore, if the defect location of a certain layer is known, the position of the defect location of one or more layers formed later on the wafer can be visually confirmed. In another example, if the defect location of a layer is known, the location of the defect location of one or more previously formed layers can also be viewed. Thereby, it can be determined whether or not a certain defect is caused by a defect in the preceding layer. These previously formed layer images and / or design files may all be aligned in a single layer in this example.

  The user can simultaneously verify the defect portion marked on the preceding layer design clip, the current layer design clip, and / or the current layer SEM image and verify that the portions are not displaced. If there is a misalignment, the user can perform tilt correction or use misalignment correction to ensure that all three coordinate systems are aligned.

  The method 400 can be automatically performed once the alignment is complete to collect SEM images of all previous layer defect locations.

  Optionally, for example, at step 408, a lot having defect location images of the current layer and the previous layer can be generated. Grasping the influence of a defective part in a lot can be used for testing a semiconductor element or improving yield.

  The preceding layer image can optionally be aligned with at least the preceding layer design file. This may be done at any point during the execution of the method 400. By aligning the image of the preceding layer with the design file, it becomes possible to visually recognize defects on the preceding layer. For example, a defect at coordinates in the image of the preceding layer can be compared to a defect in the current layer at the corresponding coordinates.

  The position of the defect in the image of the previous layer can be identified or separately confirmed before identifying or viewing the region of the image of the current layer. The image of the previous layer may be aligned with the design file of the previous layer before confirming the position of the defect.

  In one embodiment, the current layer and previous layer design files and images may all be aligned prior to viewing the image of the current layer region based on the coordinates of the defects in the previous layer.

  A controller, such as controller 105 in FIG. 1, can be configured to perform the steps in method 400. The controller can also instruct the image generation system to form an image of a particular region or group of regions in the current layer based on defects or potential defects in the previous layer.

  The alignment of the design file with respect to an image of one layer or another design file may be based on a coordinate system and / or at least one mold corner. The algorithm used to align the design file relative to the image of the layer or another design file may be based on strength and / or characteristics. The algorithm used to align the design file in the image layer or relative to another design file may use a transformation model, such as a linear transformation model.

  A current layer coordinate system can be generated, and a corresponding previous layer coordinate system can be generated. The coordinate system may be, for example, a three-dimensional coordinate system using a grid, a pole, or a matrix. In one example, a grid-like XY coordinate system is used. The coordinate system can be defined using a defect inspection tool or a mounting table for the defect inspection tool. The same coordinate system can be used for the preceding layer and the current layer. If there is a known relationship between the two coordinate systems, different coordinate systems may be used for the current layer and the preceding layer.

  The technology disclosed herein can be automated. For example, automated SEM inspection can be utilized. Data management techniques can be used to analyze images from one or more layers on the wafer.

  By using the technique disclosed in this specification, defects in the preceding layer can be identified or monitored earlier or more frequently, which makes it easier for semiconductor manufacturers to improve the manufacturing process. Since the time required for wafer inspection is shortened, throughput is improved. The classification of defects based on the manufacturing stage of the predecessor layer allows semiconductor manufacturers to focus on the type of DOI that affects multiple layers of the wafer and reduces yield.

  Although the present disclosure has been described with respect to one or more specific embodiments, it is to be understood that other embodiments of the present disclosure can be implemented without departing from the scope of the present disclosure. Accordingly, the present disclosure is defined only by the appended claims and the reasonable interpretation thereof.

Claims (18)

A system including a defect inspection tool and a controller configured to communicate with the defect inspection tool,
A mounting table configured to fix the wafer to the defect inspection tool;
An image generation system configured to generate an image of a layer on the surface of the wafer;
The controller is
Aligning the current layer design file of the wafer with the current layer image;
Aligning the design file of the preceding layer of the wafer with the design file of the current layer;
Configured to identify an area of the current layer image based on the coordinates of the defect in the preceding layer;
The preceding layer is formed before the current layer;
A system in which the region corresponds to the coordinates of the defect in the preceding layer.   The system of claim 1, wherein the controller includes a processor, a storage element in electronic communication with the processor, and a communication port in electronic communication with the processor.   The system of claim 1, wherein at least one mold corner of the wafer is marked.   The system of claim 3, wherein the controller is further configured to align the mold corners with the mold coordinate system of the preceding layer after aligning the preceding layer design files.   The system of claim 1, wherein the controller is further configured to perform tilt correction of the image of the current layer.   The system of claim 1, wherein the image of the current layer is a scanning electron microscope image.   The system of claim 1, wherein the controller is further configured to generate a coordinate system for the current layer and a corresponding coordinate system for the preceding layer.   The system of claim 1, wherein the controller is further configured to align the preceding layer image with at least one of the preceding layer design file or the current layer design file.   The system of claim 1, wherein the image generation system is configured to use at least one of an electron beam, a broadband plasma, or a laser. Aligning the wafer of the defect inspection tool using the mounting table;
Marking at least one mold corner of the wafer;
Aligning a current layer design file of the wafer with an image of the current layer using a controller;
Aligning the design file of the preceding layer of the wafer with the design file of the current layer using the controller with the leading layer being formed before the current layer;
Using the controller to identify an area of the current layer image based on the coordinates of the defects in the preceding layer, with the areas corresponding to the coordinates of the defects in the preceding layer; Including methods.   The method of claim 10, further comprising aligning the mold corners with the mold coordinate system of the preceding layer after aligning the design file of the preceding layer.   The method of claim 10, further comprising generating a lot having defect location images of the current layer and the preceding layer using the controller.   The method of claim 10, further comprising performing tilt correction of the current layer image using the controller.   The method of claim 10, wherein the image of the current layer is a scanning electron microscope image.   The method of claim 10, further comprising generating a coordinate system for the current layer using the controller and generating a corresponding coordinate system for the preceding layer.   11. The method of claim 10, further comprising aligning the preceding layer image with at least one of the preceding layer design file or the current layer design file.   The method of claim 10, further comprising identifying a position of a defect in the preceding layer image prior to identifying an area of the current layer image using the controller.   The method of claim 17, further comprising aligning the preceding layer image with the preceding layer design file.

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