JP2018523235A5 - - Google Patents
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- Publication number
- JP2018523235A5 JP2018523235A5 JP2018502709A JP2018502709A JP2018523235A5 JP 2018523235 A5 JP2018523235 A5 JP 2018523235A5 JP 2018502709 A JP2018502709 A JP 2018502709A JP 2018502709 A JP2018502709 A JP 2018502709A JP 2018523235 A5 JP2018523235 A5 JP 2018523235A5
- Authority
- JP
- Japan
- Prior art keywords
- memory
- barrier operation
- load
- executing
- data memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/US2015/041322 WO2017014752A1 (fr) | 2015-07-21 | 2015-07-21 | Mise en œuvre d'instructions d'acquisition de chargement/libération de stockage à l'aide d'une opération de chargement/stockage avec une opération dmb |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2018523235A JP2018523235A (ja) | 2018-08-16 |
| JP2018523235A5 true JP2018523235A5 (fr) | 2018-11-15 |
| JP6739513B2 JP6739513B2 (ja) | 2020-08-12 |
Family
ID=57835180
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018502709A Active JP6739513B2 (ja) | 2015-07-21 | 2015-07-21 | Ｄｍｂ操作を伴うロード／ストア操作を使用するロード獲得／ストア解放命令の実装 |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP3326059A4 (fr) |
| JP (1) | JP6739513B2 (fr) |
| CN (2) | CN110795150A (fr) |
| WO (1) | WO2017014752A1 (fr) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10417002B2 (en) | 2017-10-06 | 2019-09-17 | International Business Machines Corporation | Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses |
| US10572256B2 (en) | 2017-10-06 | 2020-02-25 | International Business Machines Corporation | Handling effective address synonyms in a load-store unit that operates without address translation |
| US11175924B2 (en) | 2017-10-06 | 2021-11-16 | International Business Machines Corporation | Load-store unit with partitioned reorder queues with single cam port |
| US10394558B2 (en) | 2017-10-06 | 2019-08-27 | International Business Machines Corporation | Executing load-store operations without address translation hardware per load-store unit port |
| US10606591B2 (en) | 2017-10-06 | 2020-03-31 | International Business Machines Corporation | Handling effective address synonyms in a load-store unit that operates without address translation |
| US10606590B2 (en) | 2017-10-06 | 2020-03-31 | International Business Machines Corporation | Effective address based load store unit in out of order processors |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07302200A (ja) * | 1994-04-28 | 1995-11-14 | Hewlett Packard Co <Hp> | 順次付けロード動作および順序付け記憶動作を強制する命令を有するコンピュータのロード命令方法。 |
| JP2000181891A (ja) * | 1998-12-18 | 2000-06-30 | Hitachi Ltd | 共有メモリアクセス順序保証方式 |
| US7552317B2 (en) * | 2004-05-04 | 2009-06-23 | Sun Microsystems, Inc. | Methods and systems for grouping instructions using memory barrier instructions |
| WO2005121948A1 (fr) * | 2004-06-02 | 2005-12-22 | Sun Microsystems, Inc. | Procede et appareil de realisation forcee de semantiques d'instructions de barriere de memoire dans un processeur d'execution avancee |
| US7725618B2 (en) * | 2004-07-29 | 2010-05-25 | International Business Machines Corporation | Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment |
| US8060482B2 (en) * | 2006-12-28 | 2011-11-15 | Intel Corporation | Efficient and consistent software transactional memory |
| US20100241812A1 (en) * | 2007-10-18 | 2010-09-23 | Nxp B.V. | Data processing system with a plurality of processors, cache circuits and a shared memory |
| GB2461716A (en) * | 2008-07-09 | 2010-01-13 | Advanced Risc Mach Ltd | Monitoring circuitry for monitoring accesses to addressable locations in data processing apparatus that occur between the start and end events. |
| US8997103B2 (en) * | 2009-09-25 | 2015-03-31 | Nvidia Corporation | N-way memory barrier operation coalescing |
| US8935513B2 (en) * | 2012-02-08 | 2015-01-13 | International Business Machines Corporation | Processor performance improvement for instruction sequences that include barrier instructions |
| US9582276B2 (en) * | 2012-09-27 | 2017-02-28 | Apple Inc. | Processor and method for implementing barrier operation using speculative and architectural color values |
| US9442755B2 (en) * | 2013-03-15 | 2016-09-13 | Nvidia Corporation | System and method for hardware scheduling of indexed barriers |
| US9477599B2 (en) * | 2013-08-07 | 2016-10-25 | Advanced Micro Devices, Inc. | Write combining cache microarchitecture for synchronization events |
-
2015
- 2015-07-21 CN CN201910999320.5A patent/CN110795150A/zh active Pending
- 2015-07-21 WO PCT/US2015/041322 patent/WO2017014752A1/fr unknown
- 2015-07-21 CN CN201580082189.6A patent/CN108139903B/zh not_active Expired - Fee Related
- 2015-07-21 EP EP15899072.1A patent/EP3326059A4/fr active Pending
- 2015-07-21 JP JP2018502709A patent/JP6739513B2/ja active Active
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