JP2018170356A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, by which a conduction path not having a defect such as a void can be formed without causing a failure in sputtering even after oxide layer formation.SOLUTION: A method for manufacturing a semiconductor device comprises a process for forming a conduction path in a silicon substrate 40 in its thickness direction. The process includes the steps of: fabricating a first bore 42 from a surface by a Bosch process; then fabricating a second bore 43 further from a bottom of the first bore 42 by a typical etching process; thereafter, fabricating an insulator layer 45 on the inner wall of the first bore 42 and second bore 43; fabricating a seed metal layer 46 on a surface of the insulator layer 45 by sputtering; and then, filling a metal 47 in the first bore and second bore by electrolysis using the seed metal layer 46 as an electrode to fabricate a conductive bore.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a method for manufacturing a semiconductor device in which an electronic circuit is formed on a semiconductor substrate. In particular, it relates to a method of forming a conductive path that penetrates the upper and lower surfaces of the substrate.

  In order to increase the degree of integration of semiconductor devices, a plurality of semiconductor substrates are stacked and conductive paths that penetrate the upper and lower surfaces thereof are formed. When the semiconductor substrate is silicon, such a conductive path is called TSV (Through Si Via).

  When a TSV is provided on a semiconductor substrate, the following steps are usually performed. First, a hole that does not penetrate to the back surface (non-through hole) is formed in the semiconductor substrate. An oxide layer as an insulating layer is formed on the inner surface of the non-through hole, and a metal film (referred to as seed metal) is formed on the surface by sputtering. Using this seed metal as an electrode, a metal as a conductor is filled in the hole by electrolysis. Finally, the conductive path is formed by grinding the back side of the substrate (the bottom side of the non-through hole) and exposing the conductor to the back side. As this metal, copper (Cu) is usually used.

With the demand for higher functionality and downsizing of equipment using semiconductor devices, it is desired to further increase the degree of integration. To that end, the distance between TSVs must be reduced and the diameter must be reduced. I must. Currently, the TSV diameter is about 10 μm, and the minimum adjacent spacing (pitch) is about the same. On the other hand, the thickness of the semiconductor substrate is about 50 μm even at the thinnest due to restrictions in the manufacturing process of the semiconductor device. Therefore, the ratio of the diameter and the depth of TSV (this is called the aspect ratio) is 5 or more. Such a hole with a large aspect ratio is difficult to open by ordinary etching, and a method called a Bosch process is used (Patent Documents 1 and 2). As shown in FIG. 1, in the Bosch process, a plasma etching step (a) for forming a hole 82 in a substrate 81 using an etching gas such as SF ₆ gas and a deposition gas such as C ₄ F ₈ gas are used. (C) (d) is a method of digging a hole by a process (alternating process) in which the step (b) of plasma deposition in which a fluorocarbon polymer is deposited on the inner wall surface of the hole 82 as a protective layer 83 is alternately repeated. A vertical hole structure or column structure with an aspect ratio of 100 or more can be formed (e).

  However, when the hole is formed by the Bosch process, as shown in FIG. 1 (d), the side wall has a shell-shaped unevenness (this is called a scallop) corresponding to the repetition of both steps. As shown in FIG. 2 (a), due to the unevenness, a portion 91 in which the seed metal is difficult to adhere is generated in the seed metal forming process by sputtering. This phenomenon becomes particularly prominent in the deep part of the hole, and in the deepest part of the hole, a part 92 where no seed metal is formed on the surface of the side wall is generated (FIG. 2B). As a result, there is a problem that voids 93 are generated in the subsequent electrolytic filling step (FIG. 2 (c)).

  In Patent Document 3, in order to cope with such a problem, when forming a hole by the Bosch process, the conditions are changed from the middle, and both the scallop width and the notch depth are made smaller in the deeper part than in the shallower part. (FIG. 5 of Patent Document 3).

JP 2007-311584 A International Publication No. 2008/75715 JP 2013-165100 A

  In the method described in Patent Document 3, the scallop width and the notch depth are both made smaller in the deeper hole than in the shallower one, so that the side wall surface becomes flat in shape, but an oxide layer is formed on the surface. In this case, the unevenness of the scallop shape is emphasized and the unevenness tends to increase. Therefore, the sputtering after forming the oxide layer has a problem that seed metal formation defects cannot be sufficiently reduced.

  The present invention has been made to solve such problems, and the object of the present invention is to form a conductive path free from defects such as voids without causing sputtering defects even after forming an oxide layer. The present invention provides a method for manufacturing a semiconductor device.

The present invention, which has been made to solve the above problems, is a method of manufacturing a semiconductor device by forming a conduction path in the thickness direction of a semiconductor substrate.
a) creating a first hole from the surface by a Bosch process;
b) forming a second hole from the bottom of the first hole by a normal etching process;
c) producing an insulating layer on the inner walls of the first hole and the second hole;
d) producing a metal electrode layer by sputtering on the surface of the insulating layer;
e) filling the metal into the first hole and the second hole by electrolysis using the metal electrode layer as an electrode.

  Here, the diameter of the second hole is desirably substantially the same as the diameter of the first hole, but may be slightly smaller (for example, about 30% smaller). Further, it is desirable that the depth (length) of the second hole is about 5 times or less of the diameter. When the depth (length) of the second hole is larger than this, the diameter becomes smaller at the bottom of the second hole or the diameter near the entrance of the first hole becomes larger depending on the normal etching process. There is a possibility that.

  The seed metal and the metal filled in the first hole and the second hole are preferably both copper, but the seed metal is not necessarily the same as the filled metal.

  The normal etching process of the second hole forming process is not a process of repeating etching and deposition like the Bosch process, but a process (process) of simply performing etching. The gas used in the normal etching process can be mixed with a film forming gas having a film forming function in addition to an etching gas having a function of etching the semiconductor substrate. Thereby, also in the second hole manufacturing step, a protective film can be formed on the side wall, and anisotropic etching in which etching proceeds only in the vertical direction can be performed.

When the material of the semiconductor substrate is silicon (Si), it is desirable to use SF ₆ (sulfur hexafluoride) as an etching gas and C ₄ F ₈ (perfluorocyclobutane) as a film forming gas. In addition, a fluorocarbon-based dry etching agent represented by C _x F _y (x = any integer from 1 to 4, y = any integer from 4 to 10) as an etching gas, and C _x H as a film forming gas A fluorohydrocarbon dry etching agent represented by _y F _z (an integer of x = 1 to 4, an integer of y = 1 to 2, an integer of z = 3 to 9) is used. be able to.

  In the semiconductor device manufacturing method according to the present invention, when forming the conductive holes penetrating both surfaces of the semiconductor substrate, first the first hole is formed from the surface by the Bosch process, and the second hole is further formed from the bottom by the usual etching process. By making, a hole without a scalloped shape toward the bottom is made. As a result, seed metal formation defects do not occur when seed metal is produced by sputtering after an insulating layer is produced on the inner wall of the hole. As a result, a conductive path free from defects such as voids can be produced by metal filling by electrolysis based thereon.

Explanatory drawing which shows the procedure of hole preparation by a Bosch process. Explanatory drawing which shows the problem in the case of forming a seed metal layer in the hole produced from the Bosch process. Sectional drawing which shows schematic structure of the plasma processing apparatus used in order to produce a hole in one Example of this invention. The flowchart which shows the procedure which produces a through-conduction hole in a silicon substrate in an Example. Plasma gas mixing ratio (SF ₆ / (SF ₆ + C ₄ F ₈ ) in the second hole manufacturing step, and the depth of the Cu conductor according to each condition when Cu is filled to prepare Cu conductor The graph which shows the result of having measured the thickness. The schematic explanatory drawing of the process of producing a penetration conductive hole (TSV) in a silicon substrate. A cross-sectional photograph (a) of the non-through hole formed in the silicon substrate, a cross-sectional photograph (b) of the first hole, and a cross-sectional photograph (c) of the lower part of the first hole and the second hole part. When the seed metal layer is made by making only the first hole by the Bosch process, the cross section of the through-hole after making the seed metal layer by sputtering (a) (c) and Cu by EDS analysis Distribution diagrams (b) and (d). Electron microscope observation photographs (a) and (c) and Cu distribution diagrams (b) and (d) of the cross-section of the non-through holes when the second hole is formed by a normal etching process and the seed metal layer is formed. It is an optical micrograph of a cross section after filling a non-through hole with a Cu conductor by electrolysis. (A) produced only a first hole by a Bosch process, produced a seed metal layer, and performed Cu electrolytic filling. In this case, (b) is a photograph of the case where a second hole is formed by a normal etching process after the first hole to form a seed metal layer and Cu electrolytic filling is performed. When the mixing ratio of plasma gas (SF ₆ / (SF ₆ + C ₄ F ₈ ) in the second hole manufacturing step is 0.5 (a) (b), 0.6 (c) (d), 0.7 The electron micrograph of the 1st hole and the 2nd hole of case (e) (f) and 0.8 (g) (h).

  An embodiment of the present invention will be described below with reference to FIGS. First, using a plasma processing apparatus 10 as shown in FIG. 3, a non-through hole serving as a pilot hole of TSV is provided in a silicon substrate to be processed. The plasma processing apparatus 10 used in this embodiment is an inductively coupled reactive ion etching apparatus, and is disposed above a processing chamber 11 provided with a lower electrode (cathode) 12 on which a substrate S to be processed is placed. A spiral high frequency coil 21 is provided through the dielectric window 13. One end of the high frequency coil 21 is connected to the high frequency coil power source 23 via the matching unit 22, and the other end is directly connected to the high frequency coil power source 23. A lower high frequency power supply 26 is also connected to the lower electrode 12 via a blocking capacitor 24 and a matching unit 25. The lower electrode 12 is provided with a cooling gas flow path (not shown) through which helium gas flows.

A gas inlet 14 for introducing an etching gas into the processing chamber 11 and a gas outlet 15 for exhausting the processing chamber 11 are provided on the side wall of the processing chamber 11. The gas introduction port 14 is provided with a gas switch 16 for switching the processing gas, and sends a gas corresponding to each processing stage to the processing chamber 11. A vacuum pump 17 is connected to the gas outlet 15. The overall operation of the plasma processing apparatus 10, such as the gas switch 16, the vacuum pump 17, the high frequency coil power supply 23, and the lower high frequency power supply 26, is controlled by the control unit 30.
When high frequency power is supplied from the high frequency coil power source 23 to the high frequency coil 21 with the processing gas introduced from the gas inlet 14, plasma of the processing gas is generated. When high frequency power is supplied to the lower electrode 12 from the lower high frequency power source 26 in this state, electrons in the plasma jump into the lower electrode 12 following the fluctuation of the electric field formed by the high frequency. Since the blocking capacitor 24 is connected to the lower electrode 12, when electrons jump in, a negative bias voltage (self-bias) is applied to the lower electrode 12, and ions are accelerated toward the lower electrode 12. Thus, etching or film formation is performed on the substrate S to be processed according to the type of the processing gas.

  Next, a process for producing a through hole (TSV) in the silicon substrate will be described with reference to the flowchart of FIG. 4 and FIG. First, a TSV pattern mask 41 to be provided is formed on a silicon substrate 40 having a thickness of 720 μm to be processed (step S1). Each TSV has a diameter of 10 μm. Next, using the plasma processing apparatus 10 shown in FIG. 3, the first hole 42 having a depth of 55 μm is first produced by a Bosch process (step S2). Thereafter, the processing gas is switched, and a second hole 43 is further formed from the bottom of the first hole 42 by a normal etching process (step S3, FIG. 6 (a)). The depth of the second hole 43 is 3 μm.

  At this stage, the silicon substrate 40 is taken out from the processing chamber 11 of the plasma processing apparatus 10 and insulated by using a CVD apparatus (not shown) on the surface of the non-through hole 44 including the first hole 42 and the second hole 43. An oxide layer 45 having a thickness of 0.5 μm is formed (step S4, FIG. 6B). The silicon substrate 40 is taken out from the CVD apparatus and loaded into a processing chamber of a sputtering apparatus (not shown). With this sputtering apparatus, a seed metal layer 46 made of Cu (copper) is formed on the surface of the oxide layer 45 in the non-through hole 44 (step S5, FIG. 6C). In the case of the present embodiment, the upper part (first hole 42) of the non-through hole 44 is formed by the Bosch process, so that the side wall has irregularities (scallops), but the lower part (second hole 43) has such irregularities. Therefore, there is no portion where the seed metal layer 46 is not covered on the side wall. Thereafter, the silicon substrate 40 is placed in water degassed in a vacuum, the air inside the non-through hole 44 is removed, and then the inside of the non-through hole 44 is formed by electrolysis using the seed metal layer 46 as an electrode. Cu is filled (step S6, FIG. 6 (d)). In FIG. 6 (d), the filled Cu conductor is designated as 47. Finally, the bottom surface of the silicon substrate 40 (the bottom surface on the second hole 43 side) is ground to produce a conductive hole penetrating the silicon substrate 40 (step S7, FIG. 6 (e)).

  The electron micrograph of each part in each said stage is shown in FIGS. 7A is a cross-sectional photograph of the silicon substrate 40 at the stage of FIG. 6A, FIG. 7B is a cross-section of the first hole 42 by the Bosch process, and FIG. 7C is the first hole. 42 is a cross section of a lower portion 42 and a portion of the second hole 43 by a normal etching process. As shown in FIG. 7C, the second hole 43 has no lateral unevenness on the side wall.

  8 and 9 compare the results of electron microscopic observation and EDS analysis of the cross-section of the non-through hole after the seed metal layer is formed by sputtering. FIG. 8 shows only the first hole by the Bosch process. FIG. 9 shows electron micrographs (a) and (c) and Cu distribution photographs (b) and (d) when the seed metal layer is fabricated. FIG. 2 is an electron micrograph (a) and (c) and a Cu distribution photograph (b) and (d). In both cases, (c) and (d) are enlarged views of the bottom of the hole. Compared with FIGS. 8 (b) and (d), it is clear that variations in Cu distribution are reduced in FIGS. 9 (b) and 9 (d). In FIG. 9B, it seems that the Cu distribution is low in the lower part, because this is because the overall contrast at the time of imaging is lowered.

  FIG. 10 is an optical micrograph of a cross-section after filling a non-through hole with Cu conductor by electrolysis. (A) shows only a first hole formed by the Bosch process, a seed metal layer is formed, and Cu electrolysis is performed. When filling is performed, (b) is a photograph of the case where the second hole is formed by a normal etching process after the first hole to form a seed metal layer, and Cu electrolytic filling is performed. In (a), it can be seen that a void is formed below the non-through hole, and in (b), there is no void, and the Cu conductor is completely formed up to the bottom of the hole.

As described above, in the etching process for forming the second hole, as the processing gas introduced into the processing chamber 11, in addition to the etching gas having the function of etching, the film forming gas having the film forming function is mixed. Can do. When SF ₆ is used as the etching gas and C ₄ F ₈ is used as the film forming gas, the ratio of the etching gas in the mixed gas (SF ₆ / (SF ₆ + C ₄ F ₈ ) is changed between 0.4 and 0.9. 5 shows the result of measuring the depth of the Cu conductor under each condition when the Cu conductor was prepared by filling the second hole and then Cu was filled in. Ratio of etching gas (SF ₆ When / (SF ₆ + C ₄ F ₈ ) is 0.6 or more, the depth of the Cu conductor is 50 μm or more, and sufficient conductive holes can be produced.
In addition, FIG. 11 shows electron micrographs of the first hole and the second hole under each mixing ratio condition. It can be seen that as the mixing ratio (SF ₆ / (SF ₆ + C ₄ F ₈ ) increases, the unevenness of the surface of the first hole also decreases.

DESCRIPTION OF SYMBOLS 10 ... Plasma processing apparatus 11 ... Processing chamber 12 ... Lower electrode 13 ... Dielectric window 14 ... Gas introduction port 15 ... Gas discharge port 16 ... Gas switch 17 ... Vacuum pump 21 ... High frequency coils 22, 25 ... Matching device 23 ... High frequency Coil power supply 24 ... blocking capacitor 26 ... lower high frequency power supply 30 ... control unit 40 ... silicon substrate 41 ... mask 41 ... non-through hole 42 ... first hole 43 ... second hole 44 ... non-through hole 45 ... oxide layer 46 ... seed metal Layer 47 ... Cu conductor

Claims (5)

In a method of manufacturing a semiconductor device by forming a conduction path in the thickness direction of a semiconductor substrate,
a) creating a first hole from the surface by a Bosch process;
b) forming a second hole from the bottom of the first hole by a normal etching process;
c) producing an insulating layer on the inner walls of the first hole and the second hole;
d) producing a metal electrode layer by sputtering on the surface of the insulating layer;
e) filling the metal into the first hole and the second hole by electrolysis using the metal electrode layer as an electrode, and a method for manufacturing a semiconductor device.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the diameter of the second hole is 100 to 70% of the diameter of the first hole.   3. The method of manufacturing a semiconductor device according to claim 1, wherein a depth of the second hole is 5 times or less of a diameter of the second hole.   The semiconductor device manufacturing method according to claim 1, wherein a film forming gas is mixed with a gas for etching the semiconductor substrate in the normal etching process.   The semiconductor device manufacturing method according to claim 4, wherein a mixing ratio of the film forming gas is 40% or less of the total gas.