JP2018163907A - Storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a storage by which a mutual interference between memory cells can be kept down.SOLUTION: A storage according to an embodiment hereof comprises: a first conductive layer extending in a first direction; a second conductive layer extending in the first direction; a third conductive layer extending in a second direction crossing the first direction; an insulator layer provided between the first and second conductive layers; a first resistance-changing layer provided between the first and third conductive layers; a second resistance-changing layer provided between the second and third conductive layers; a first rectification layer provided between the first conductive layer and the first resistance-changing layer and between the first conductive layer and the insulator layer; and a second rectification layer provided between the second conductive layer and the second resistance-changing layer and between the second conductive layer and the insulator layer.SELECTED DRAWING: Figure 3

Description

  Embodiments described herein relate generally to a storage device.

  In the resistance change type memory, for example, a memory cell having a resistance change layer is provided at the intersection of a word line and a bit line. By applying a voltage to the resistance change layer, the resistance of the resistance change layer is changed to develop a memory function. When the resistance change layer does not have rectification property or has low rectification property, mutual interference between adjacent memory cells may occur. Mutual interference between adjacent memory cells causes a malfunction of the resistance change type memory.

JP, 2006-192478, A

  An object of the present invention is to provide a memory device that can suppress mutual interference between memory cells.

The storage device according to the embodiment extends in a second direction intersecting the first direction, a first conductive layer extending in the first direction, a second conductive layer extending in the first direction, and the second direction. A third conductive layer, an insulating layer provided between the first conductive layer and the second conductive layer, and provided between the first conductive layer and the third conductive layer. A first variable resistance layer, a second variable resistance layer provided between the second conductive layer and the third conductive layer,
A first rectifying layer provided between the first conductive layer and the first variable resistance layer, and between the first conductive layer and the insulating layer; and the second conductive layer. And a second rectifying layer provided between the second resistance change layer and between the second conductive layer and the insulating layer.

The block diagram of the memory | storage device of 1st Embodiment. FIG. 2 is an equivalent circuit diagram of the memory cell array according to the first embodiment. 1 is a schematic cross-sectional view of a storage device according to a first embodiment. In the manufacturing method of the memory | storage device of 1st Embodiment, the schematic cross section which shows the memory | storage device in the middle of manufacture. In the manufacturing method of the memory | storage device of 1st Embodiment, the schematic cross section which shows the memory | storage device in the middle of manufacture. In the manufacturing method of the memory | storage device of 1st Embodiment, the schematic cross section which shows the memory | storage device in the middle of manufacture. In the manufacturing method of the memory | storage device of 1st Embodiment, the schematic cross section which shows the memory | storage device in the middle of manufacture. In the manufacturing method of the memory | storage device of 1st Embodiment, the schematic cross section which shows the memory | storage device in the middle of manufacture. In the manufacturing method of the memory | storage device of 1st Embodiment, the schematic cross section which shows the memory | storage device in the middle of manufacture. In the manufacturing method of the memory | storage device of 1st Embodiment, the schematic cross section which shows the memory | storage device in the middle of manufacture. In the manufacturing method of the memory | storage device of 1st Embodiment, the schematic cross section which shows the memory | storage device in the middle of manufacture. In the manufacturing method of the memory | storage device of 1st Embodiment, the schematic cross section which shows the memory | storage device in the middle of manufacture. The schematic cross section of the memory | storage device of a 1st comparison form. The schematic cross section of the memory | storage device of a 2nd comparison form. The schematic cross section of the memory | storage device of 2nd Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and description of members once described is omitted as appropriate.

  Hereinafter, a storage device according to an embodiment will be described with reference to the drawings.

(First embodiment)
The storage device of the present embodiment extends in a second direction that intersects the first direction, a first conductive layer that extends in the first direction, a second conductive layer that extends in the first direction, and the second direction. A third conductive layer; an insulating layer provided between the first conductive layer and the second conductive layer; and a first conductive layer provided between the first conductive layer and the third conductive layer. A variable resistance layer; a second variable resistance layer provided between the second conductive layer and the third conductive layer; a first variable resistance layer; a first variable resistance layer; a first variable resistance layer; Between the first rectifying layer provided between the first conductive layer and the insulating layer, between the second conductive layer and the second variable resistance layer, and between the second conductive layer and the insulating layer. And a second rectifying layer provided on.

  FIG. 1 is a block diagram of the storage device of this embodiment. FIG. 2 is an equivalent circuit diagram of the memory cell array. FIG. 2 schematically shows a wiring structure in the memory cell array.

  The storage device 100 of the present embodiment is a phase change memory (Phase Change Memory). The phase change memory stores data using a resistance change accompanying a change in the crystal structure of the resistance change layer.

  In addition, the memory cell array according to the present embodiment has a three-dimensional structure in which memory cells are three-dimensionally arranged. By providing the three-dimensional structure, the degree of integration of the storage device 100 is improved.

  As shown in FIG. 1, the memory device 100 includes a memory cell array 101, a word line driver circuit 102, a row decoder circuit 103, a sense amplifier circuit 104, a column decoder circuit 105, and a control circuit 106.

  In addition, as shown in FIG. 2, a plurality of memory cells MC are three-dimensionally arranged in the memory cell array 101. In FIG. 2, a region surrounded by a broken line corresponds to one memory cell MC.

  The memory cell array 101 includes, for example, a plurality of word lines WL (WL11, WL12, WL13, WL21, WL22, WL23) and a plurality of bit lines BL (BL11, BL12, BL21, BL22). The word line WL extends in the x direction. The bit line BL extends in the z direction. The word line WL and the bit line BL intersect vertically. Memory cells MC are arranged at the intersections between the word lines WL and the bit lines BL.

  The word line WL11 is a first conductive layer, the word line WL21 is a second conductive layer, and the bit line BL11 is a specific example of a third conductive layer. The x direction is a specific example of the first direction, the y direction is a third direction, and the z direction is a second direction.

  The plurality of word lines WL are electrically connected to the row decoder circuit 103. The plurality of bit lines BL are connected to the sense amplifier circuit 104. A selection transistor ST (ST11, ST21, ST12, ST22) and a global bit line GBL (GBL1, GBL2) are provided between the plurality of bit lines BL and the sense amplifier circuit 104.

  The row decoder circuit 103 has a function of selecting the word line WL in accordance with the input row address signal. The word line driver circuit 102 has a function of applying a predetermined voltage to the word line WL selected by the row decoder circuit 103.

  The column decoder circuit 105 has a function of selecting the bit line BL according to the input column address signal. The sense amplifier circuit 104 has a function of applying a predetermined voltage to the bit line BL selected by the column decoder circuit 105. The sense amplifier circuit 104 has a function of detecting and amplifying a current flowing between the selected word line WL and the selected bit line BL.

  The control circuit 106 has a function of controlling the word line driver circuit 102, the row decoder circuit 103, the sense amplifier circuit 104, the column decoder circuit 105, and other circuits not shown.

  Circuits such as the word line driver circuit 102, the row decoder circuit 103, the sense amplifier circuit 104, the column decoder circuit 105, and the control circuit 106 are electronic circuits. For example, a transistor or a wiring layer using a semiconductor layer (not shown) is used.

  FIG. 3A and FIG. 3B are schematic cross-sectional views of the memory cell array 101 of the storage device 100 of this embodiment. FIG. 3A is an xy sectional view of the memory cell array 101. FIG. 3B is a yz sectional view of the memory cell array 101. 3A is a cross-sectional view taken along the line BB ′ in FIG. 3B, and FIG. 3B is a cross-sectional view taken along the line AA ′ in FIG. In FIGS. 3A and 3B, a region surrounded by a broken line is one memory cell MC.

  The memory cell array 101 includes a word line WL11 (first conductive layer), a word line WL21 (second conductive layer), a word line WL12, a word line WL13, a bit line BL11 (third conductive layer), a bit line BL21, a bit Line BL12 is provided. The first variable resistance layer 12a, the second variable resistance layer 12b, the first rectifying layer 14a, the second rectifying layer 14b, the interlayer insulating layer 16 (insulating layer), and the interlayer insulating layer 18 are provided.

  Hereinafter, the word line WL11 (first conductive layer), the word line WL21 (second conductive layer), the word line WL12, the word line WL13, and the like may be simply referred to as the word line WL. In addition, the bit line BL11 (third conductive layer), the bit line BL21, the bit line BL12, and the like may be simply referred to as the bit line BL in some cases.

  The word line WL is a conductive layer. The word line WL is, for example, a metal layer. The word line WL is, for example, tungsten (W) or titanium nitride (TiN). The word line WL may be formed of another metal, a metal semiconductor compound, or a conductive material such as a semiconductor.

  The bit line BL is a conductive layer. The bit line BL is, for example, a metal layer. The bit line BL is, for example, tungsten (W), titanium nitride (TiN), or copper (Cu). The bit line BL may be formed of another metal, a metal semiconductor compound, or a conductive material such as a semiconductor.

  The pitch in the y direction of the word lines WL is, for example, not less than 50 nm and not more than 200 nm. The thickness of the word line WL in the z direction is, for example, 30 nm or less. The pitch of the bit lines BL in the x direction is, for example, not less than 50 nm and not more than 200 nm.

  The pitch of the word lines WL in the y direction, the thickness of the word lines WL in the z direction, and the pitch of the bit lines BL in the x direction can be measured, for example, by observation with a transmission electron microscope.

  An interlayer insulating layer 16 is provided between the word line WL11 and the word line WL21 and between the bit line BL11 and the bit line BL12. An interlayer insulating layer 18 is provided between the word line WL11 and the word line WL12 and between the bit line BL11 and the bit line BL21. The interlayer insulating layer 16 and the interlayer insulating layer 18 are, for example, oxide, oxynitride, or nitride. The interlayer insulating layer 16 and the interlayer insulating layer 18 are, for example, silicon oxide.

  The thickness in the z direction of the interlayer insulating layer 16 is, for example, 30 nm or less. The thickness of the interlayer insulating layer 16 in the z direction is thinner than the thickness of the word line WL11 in the z direction, for example.

  The first resistance change layer 12a is provided between the word line WL11 and the bit line BL11. The second resistance change layer 12b is provided between the word line WL21 and the bit line BL11.

  The first variable resistance layer 12a and the second variable resistance layer 12b are physically continuous. The first variable resistance layer 12a and the second variable resistance layer 12b are continuous layers. The first resistance change layer 12a and the second resistance change layer 12b may be physically separated.

  The first resistance change layer 12a and the second resistance change layer 12b have a function of storing data according to a change in the resistance state. The first resistance change layer 12a and the second resistance change layer 12b can be rewritten by application of voltage or current. The first resistance change layer 12a and the second resistance change layer 12b transition between a high resistance state (reset state) and a resistance state (set state) by application of voltage or current. For example, the high resistance state is defined as data “0”, and the low resistance state is defined as data “1”. The memory cell MC stores 1-bit data of “0” and “1”.

The first resistance change layer 12a and the second resistance change layer 12b are, for example, chalcogenides. The first resistance change layer 12a and the second resistance change layer 12b are chalcogenides including, for example, germanium (Ge), antimony (Sb), and tellurium (Te). The first resistance change layer 12a and the second resistance change layer 12b are, for example, a Ge ₂ Sb ₂ Te ₅ alloy.

  The first variable resistance layer 12a and the second variable resistance layer 12b transition between an amorphous phase and a crystalline phase, for example, by application of voltage or current. In the case of an amorphous phase, a high resistance state is obtained, and in the case of a crystal phase, a low resistance state is obtained.

  The film thicknesses of the first resistance change layer 12a and the second resistance change layer 12b are, for example, not less than 3 nm and not more than 20 nm.

  The first resistance change layer 12a and the second resistance change layer 12b may include a seed layer. The seed layer has a function of promoting the formation of the first resistance change layer 12a and the second resistance change layer 12b.

  The first rectifying layer 14a is provided between the word line WL11 and the first variable resistance layer 12a, and between the word line WL11 and the interlayer insulating layer 16. The first rectifying layer 14a is provided to surround the word line WL11 when viewed in a cross section perpendicular to the x direction (first direction). The first rectifying layer 14a is provided above and below the word line WL11 with the word line WL11 interposed therebetween.

  The second rectifying layer 14b is provided between the word line WL21 and the second resistance change layer 12b, and between the word line WL21 and the interlayer insulating layer 16. The second rectifying layer 14b is provided surrounding the word line WL21 when viewed in a cross section perpendicular to the x direction (first direction). The second rectifying layer 14b is provided above and below the word line WL21 with the word line WL21 interposed therebetween.

  The first rectifying layer 14a and the second rectifying layer 14b have a function of rectifying a current flowing in the film thickness direction.

  The first rectifying layer 14a and the second rectifying layer 14b are, for example, a so-called OTS (Ovonic Threshold Switch). The first rectifying layer 14a and the second rectifying layer 14b are, for example, chalcogenides. The first rectifying layer 14a and the second rectifying layer 14b are, for example, chalcogenides including arsenic (As), germanium (Ge), tellurium (Te), silicon (Si), and nitrogen (N). .

  The first rectifying layer 14a and the second rectifying layer 14b are, for example, strontium titanate. The material of the first rectifying layer 14a and the second rectifying layer 14b is not particularly limited as long as it has a rectifying property.

  The film thicknesses of the first rectifying layer 14a and the second rectifying layer 14b are, for example, 3 nm or more and 20 nm or less.

  Next, a method for manufacturing the storage device of this embodiment will be described. 4 (a), 4 (b), 5 (a), 5 (b), 6 (a), 6 (b), 7 (a), 7 (b), 8 (A), FIG. 8 (b), FIG. 9 (a), FIG. 9 (b), FIG. 10 (a), FIG. 10 (b), FIG. 11 (a), FIG. 11 (b), FIG. FIG. 12B is a schematic cross-sectional view showing the memory device being manufactured in the method for manufacturing the memory device of the first embodiment. 4 (a), 5 (a), 6 (a), 7 (a), 8 (a), 9 (a), 10 (a), 11 (a), and 12 (a). ) Is a cross-sectional view of a portion corresponding to FIG. 4 (b), FIG. 5 (b), FIG. 6 (b), FIG. 7 (b), FIG. 8 (b), FIG. 9 (b), FIG. 10 (b), FIG. 11 (b), FIG. (B) is sectional drawing of the part corresponding to FIG.3 (b).

First, the insulating film 20 and the sacrificial film 22 are alternately stacked on a substrate (not shown) to form a stacked body (FIGS. 4A and 4B). The insulating film 20 is, for example, a silicon oxide film. The sacrificial film 22 is, for example, a polycrystalline silicon film. The insulating film 20 and the sacrificial film 22 are deposited by, for example, a known chemical vapor deposition method (CVD method).
Part of the insulating film 20 later becomes the interlayer insulating layer 16.

  Next, the insulating film 20 and the sacrificial film 22 are patterned to form a trench 24 parallel to the xz plane (FIGS. 5A and 5B). The groove 24 is formed by using, for example, a known lithography method and anisotropic dry etching.

  Next, an insulating film 26 is deposited in the trench 24 (FIGS. 6A and 6B). The insulating film 26 is, for example, a silicon oxide film. Part of the insulating film 26 later becomes the interlayer insulating layer 18. The insulating film 26 is deposited by, for example, a known chemical vapor deposition method (CVD method).

  Next, the insulating film 26 is patterned to form an opening 28 (FIGS. 7A and 7B). The opening 28 is formed using, for example, a known lithography method and anisotropic dry etching.

Next, the resistance change film 30 is deposited on the inner wall of the opening 28 (FIGS. 8A and 8B). The resistance change film 30 is, for example, an amorphous Ge ₂ Sb ₂ Te ₅ alloy film. The resistance change film 30 is deposited by, for example, a known atomic layer deposition method (ALD method).

  When forming the resistance change film 30, it is also possible to form a seed film in the initial stage of the formation of the resistance change film 30. The seed film promotes the formation of the resistance change film 30.

  Next, the inside of the opening 28 is filled with the conductive film 32 (FIGS. 9A and 9B). The conductive film 32 is, for example, a titanium nitride film. The conductive film 32 is deposited by, for example, a known CVD method. The conductive film 32 later becomes the bit line BL.

  Next, the sacrificial film 22 is isotropically etched to form a cavity 34 extending in the x direction (FIGS. 10A and 10B). The cavity 34 is formed, for example, by forming a groove parallel to the yz plane (not shown) that intersects the sacrificial film 22 and then etching the sacrificial film 22 by wet etching.

  Next, a rectifying film 36 is deposited on the inner wall of the cavity 34 (FIGS. 11A and 11B). The rectifying film 36 is, for example, a chalcogenide OTS film. The rectifying film 36 is formed by, for example, a known ALD method.

  Next, the cavity 34 is filled with the conductive film 38 (FIGS. 12A and 12B). The conductive film 38 is, for example, a titanium nitride film. The conductive film 38 is deposited by, for example, a known CVD method. The conductive film 38 later becomes the word line WL.

  With the above manufacturing method, the memory cell array 101 of the storage device 100 of this embodiment shown in FIGS. 3A and 3B is manufactured.

  Next, operations and effects of the storage device 100 of the present embodiment will be described.

  With miniaturization of the resistance change type memory, mutual interference between adjacent memory cells becomes a problem. For example, when the variable resistance layer does not have rectification property or has low rectification property, current may flow between two adjacent word lines via the bit line. Further, for example, when the resistivity of the variable resistance layer itself is low, there is a possibility that a current flows between two adjacent word lines via the variable resistance layer. Mutual interference between adjacent memory cells causes a malfunction of the resistance change type memory.

  13A and 13B are schematic cross-sectional views of the memory cell array of the memory device of the first comparative embodiment. FIG. 13A is an xy sectional view of the memory cell array. FIG. 13B is a yz sectional view of the memory cell array. 13A is a cross-sectional view taken along the line BB ′ of FIG. 13B, and FIG. 13B is a cross-sectional view taken along the line AA ′ of FIG.

  The storage device of the first comparative embodiment is different from the storage device 100 of the present embodiment in that it does not include a rectifying layer. In the case of the first comparative embodiment, when the resistance change layer 12 does not have rectification property or has low rectification property, the word line WL11 and the word line WL21 are connected via the bit line BL11 by a leak path indicated by an arrow P in the drawing. There is a risk of leakage current flowing between them. Further, when the resistivity of the material of the resistance change layer 12 is low, a leak current may flow between the word line WL11 and the word line WL21 via the resistance change layer 12 due to a leak path indicated by an arrow Q in the drawing.

  In particular, in the case of a phase change memory, the resistivity is relatively low even when the resistance change layer 12 is in a high resistance state. For this reason, the leakage current due to the leakage path indicated by the arrow Q becomes relatively large, which causes a problem.

  FIG. 14A and FIG. 14B are schematic cross-sectional views of a memory cell array of the memory device of the second comparative form. FIG. 14A is an xy sectional view of the memory cell array. FIG. 14B is a yz sectional view of the memory cell array. 14A is a BB ′ sectional view of FIG. 14B, and FIG. 14B is an AA ′ sectional view of FIG. 14A.

  The storage device of the second comparative form is different from the first comparative form in that the rectifying layer 14 is provided. The memory device of the second comparative embodiment is different from the memory device 100 of the present embodiment in that the rectifying layer 14 is formed in a state of being laminated with the resistance change layer 12 along the bit line BL11.

  Since the memory device of the second comparative form includes the rectifying layer 14, the leakage current between the word line WL11 and the word line WL21 via the bit line BL11, and the word line WL11 and the word via the resistance change layer 12 The leakage current between the lines WL21 can be suppressed. However, when the memory device is miniaturized in the z direction and the film thickness in the z direction of the interlayer insulating layer 16 is reduced, the word line WL11 and the word line WL21 are interposed through the interlayer insulating layer 16 by a leak path indicated by an arrow R in the drawing. There is a risk of leakage current flowing between them.

  Further, when the resistivity of the material of the rectifying layer 14 is low, a leakage current may flow between the word line WL11 and the word line WL21 via the rectifying layer 14 due to a leakage path indicated by an arrow S in the drawing.

  Further, in the memory device of the second comparative embodiment, the rectifying layer 14 is formed around the bit line BL11 along the bit line BL11. For this reason, when the bit line BL11 becomes thin, the resistance increases, which may cause a problem of wiring delay. Further, when the bit line BL11 is formed, it is necessary to embed an opening having a high aspect ratio, which makes it difficult to form the bit line BL11.

  In the memory device 100 of this embodiment, the first rectifying layer 14a is provided between the word line WL11 and the first resistance change layer 12a, and between the word line WL11 and the interlayer insulating layer 16. The first rectifying layer 14a is provided surrounding the word line WL11. Similarly, the second rectifying layer 14b is provided between the word line WL21 and the second resistance change layer 12b, and between the word line WL21 and the interlayer insulating layer 16. The second rectifying layer 14b is provided surrounding the word line WL21. The first rectifying layer 14a and the second rectifying layer 14b are physically separated.

  Therefore, the leakage current between the word line WL11 and the word line WL21 via the bit line BL11, and the leakage between the word line WL11 and the word line WL21 via the first resistance change layer 12a and the second resistance change layer 12b. It is possible to suppress all of the current, the leakage current between the word line WL11 and the word line WL21 via the interlayer insulating layer 16, and the leakage current between the word line WL11 and the word line WL21 via the rectification layer. is there. Therefore, mutual interference between memory cells can be suppressed, and a resistance change memory in which occurrence of malfunctions is suppressed can be realized.

  Furthermore, the first rectifying layer 14a and the second rectifying layer 14b can be formed independently of the bit line BL11. Therefore, it is possible to suppress an increase in resistance of the bit line BL11. Further, the bit line BL11 can be easily formed.

  The first resistance change layer 12a and the first rectification layer 14a, and the second resistance change layer 12b and the second rectification layer 14b are preferably chalcogenides. Since it has a similar crystal structure, the adhesion between the first resistance change layer 12a and the first rectification layer 14a and the adhesion between the second resistance change layer 12b and the second rectification layer 14b are improved. The reliability of the resistance change type memory is improved.

  As described above, according to this embodiment, it is possible to suppress mutual interference between memory cells, and it is possible to realize a resistance change type memory in which occurrence of malfunction is suppressed. Furthermore, it is possible to suppress an increase in resistance of the bit line. In addition, the bit line can be easily formed.

(Second Embodiment)
The storage device of the present embodiment extends in a second direction that intersects the first direction, a first conductive layer that extends in the first direction, a second conductive layer that extends in the first direction, and the second direction. A third conductive layer; an insulating layer provided between the first conductive layer and the second conductive layer; and a first conductive layer provided between the first conductive layer and the third conductive layer. The rectifying layer, the second rectifying layer provided between the second conductive layer and the third conductive layer, between the first conductive layer and the first rectifying layer, and the first conductive layer Provided between the first variable resistance layer provided between the layer and the insulating layer, the second conductive layer and the second rectifying layer, and between the second conductive layer and the insulating layer. And a second variable resistance layer.

  The memory device of this embodiment is different from that of the first embodiment in that the arrangement positions of the resistance change layer and the rectifying layer are interchanged. Hereinafter, a part of the description overlapping with the first embodiment is omitted.

  FIG. 15A and FIG. 15B are schematic cross-sectional views of the memory cell array 201 of the storage device of this embodiment. FIG. 15A is an xy sectional view of the memory cell array 201. FIG. 15B is a yz sectional view of the memory cell array 201. 15A is a cross-sectional view taken along the line BB ′ of FIG. 15B, and FIG. 15B is a cross-sectional view taken along the line AA ′ of FIG. In FIG. 15A and FIG. 15B, a region surrounded by a broken line is one memory cell MC.

  The memory cell array 201 includes a word line WL11 (first conductive layer), a word line WL21 (second conductive layer), a word line WL12, a word line WL13, a bit line BL11 (third conductive layer), a bit line BL21, a bit Line BL12 is provided. The first variable resistance layer 12a, the second variable resistance layer 12b, the first rectifying layer 14a, the second rectifying layer 14b, the interlayer insulating layer 16 (insulating layer), and the interlayer insulating layer 18 are provided.

  Hereinafter, the word line WL11 (first conductive layer), the word line WL21 (second conductive layer), the word line WL12, the word line WL13, and the like may be simply referred to as the word line WL. In addition, the bit line BL11 (third conductive layer), the bit line BL21, the bit line BL12, and the like may be simply referred to as the bit line BL in some cases.

  The first rectifying layer 14a is provided between the word line WL11 and the bit line BL11. The second rectifying layer 14b is provided between the word line WL21 and the bit line BL11.

  The first rectifying layer 14a and the second rectifying layer 14b are physically continuous. The first rectifying layer 14a and the second rectifying layer 14b are continuous layers. The first rectifying layer 14a and the second rectifying layer 14b may be physically separated.

  The first resistance change layer 12a is provided between the word line WL11 and the first rectifying layer 14a, and between the word line WL11 and the interlayer insulating layer 16. The first variable resistance layer 12a is provided to surround the word line WL11 when viewed in a cross section perpendicular to the x direction (first direction). The first resistance change layer 12a is provided above and below the word line WL11 with the word line WL11 interposed therebetween.

  The first resistance change layer 12a between the word line WL11 and the interlayer insulating layer 16 is, for example, amorphous.

  The second resistance change layer 12b is provided between the word line WL21 and the second rectifying layer 14b, and between the word line WL21 and the interlayer insulating layer 16. The second variable resistance layer 12b is provided surrounding the word line WL21 when viewed in a cross section perpendicular to the x direction (first direction). The second resistance change layer 12b is provided above and below the word line WL21 with the word line WL21 interposed therebetween.

  The second resistance change layer 12b between the word line WL21 and the interlayer insulating layer 16 is, for example, amorphous.

  The first resistance change layer 12a and the second resistance change layer 12b are physically separated.

  Next, the operation and effect of the storage device of this embodiment will be described.

  Since the memory device of this embodiment includes the first rectifying layer 14a and the second rectifying layer 14b, the leakage current between the word line WL11 and the word line WL21 via the bit line BL11 is suppressed. Further, since the first resistance change layer 12a and the second resistance change layer 12b are physically separated, the word line WL11 and the word via the first resistance change layer 12a and the second resistance change layer 12b are connected to the word line WL11. Leakage current between the lines WL21 is suppressed. Therefore, mutual interference between memory cells can be suppressed, and a resistance change memory in which occurrence of malfunctions is suppressed can be realized.

  Furthermore, the first resistance change layer 12a and the second resistance change layer 12b can be formed independently of the bit line BL11. Therefore, it is possible to suppress an increase in resistance of the bit line BL11. Further, the bit line BL11 can be easily formed.

  The first variable resistance layer 12a and the second variable resistance layer 12b are preferably amorphous. By being amorphous, the resistivity increases as compared to the crystalline case. Therefore, leakage current between the word line WL11 and the word line WL21 via the interlayer insulating layer 16 is suppressed.

  As described above, according to this embodiment, it is possible to suppress mutual interference between memory cells, and it is possible to realize a resistance change type memory in which occurrence of malfunction is suppressed. Furthermore, it is possible to suppress an increase in resistance of the bit line. In addition, the bit line can be easily formed.

  In the first and second embodiments, the phase change memory using the resistance difference between the amorphous phase and the crystal phase has been described as an example. However, the present invention can also be applied to other resistance change type memories. For example, the present invention can be applied to a phase change memory in which the first resistance change layer 12a and the second resistance change layer 12b have a superlattice structure. The “superlattice structure” means a structure in which a plurality of types of crystal lattices overlap each other.

  As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. For example, a component in one embodiment may be replaced or changed with a component in another embodiment. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

12a First variable resistance layer 12b Second variable resistance layer 14a First rectifying layer 14b Second rectifying layer 16 Interlayer insulating layer (insulating layer)
100 Memory device WL11 Word line (first conductive layer)
WL21 word line (second conductive layer)
BL11 bit line (third conductive layer)

Claims (20)

A first conductive layer extending in a first direction;
A second conductive layer extending in the first direction;
A third conductive layer extending in a second direction intersecting the first direction;
An insulating layer provided between the first conductive layer and the second conductive layer;
A first variable resistance layer provided between the first conductive layer and the third conductive layer;
A second variable resistance layer provided between the second conductive layer and the third conductive layer;
A first rectifying layer provided between the first conductive layer and the first variable resistance layer, and between the first conductive layer and the insulating layer;
A storage device comprising: a second rectifying layer provided between the second conductive layer and the second variable resistance layer; and a second rectifying layer provided between the second conductive layer and the insulating layer.   The storage device according to claim 1, wherein the first variable resistance layer and the second variable resistance layer are continuous layers.   The storage device according to claim 1, wherein the first resistance change layer is chalcogenide.   The memory device according to claim 1, wherein the first resistance change layer includes germanium (Ge), antimony (Sb), and tellurium (Te).   The storage device according to claim 1, wherein the first variable resistance layer has a superlattice structure.   The storage device according to claim 1, wherein the first rectifying layer is a chalcogenide.   The storage device according to claim 1, wherein the first rectifying layer includes arsenic (As), germanium (Ge), tellurium (Te), silicon (Si), and nitrogen (N).   The memory device according to claim 1, wherein the first conductive layer is tungsten (W) or titanium nitride (TiN).   The storage device according to claim 1, wherein the third conductive layer is tungsten (W), titanium nitride (TiN), or copper (Cu).   The memory device according to claim 1, wherein a thickness of the insulating layer in the second direction is 30 nm or less. A first conductive layer extending in a first direction;
A second conductive layer extending in the first direction;
A third conductive layer extending in a second direction intersecting the first direction;
An insulating layer provided between the first conductive layer and the second conductive layer;
A first rectifying layer provided between the first conductive layer and the third conductive layer;
A second rectifying layer provided between the second conductive layer and the third conductive layer;
A first variable resistance layer provided between the first conductive layer and the first rectifying layer and between the first conductive layer and the insulating layer;
A memory device comprising: a second variable resistance layer provided between the second conductive layer and the second rectifying layer and between the second conductive layer and the insulating layer.   The storage device according to claim 11, wherein the first rectifying layer and the second rectifying layer are continuous layers.   The storage device according to claim 11, wherein the first resistance change layer is chalcogenide.   The memory device according to claim 11, wherein the first variable resistance layer includes germanium (Ge), antimony (Sb), and tellurium (Te).   The storage device according to claim 11, wherein the first variable resistance layer has a superlattice structure.   The storage device according to claim 11, wherein the first rectifying layer is a chalcogenide.   The storage device according to claim 11, wherein the first rectifying layer includes arsenic (As), germanium (Ge), tellurium (Te), silicon (Si), and nitrogen (N).   The memory device according to claim 11, wherein the first conductive layer is tungsten (W) or titanium nitride (TiN).   The storage device according to claim 11, wherein the third conductive layer is tungsten (W), titanium nitride (TiN), or copper (Cu). The memory device according to claim 11, wherein the first variable resistance layer between the first conductive layer and the insulating layer is amorphous.