JP2018163729A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device in which power supply noise from other adjacent banks is reduced.SOLUTION: In a semiconductor storage device, a bank BK0 is provided so as to be adjacent to a power supply pad PDV for supplying a predetermined voltage in a D2 direction. The bank BK0 is sandwiched between the power supply pad PDV and a bank BK1 in the D2 direction. That is, the bank BK0 is provided near the power supply pad PDV, and the bank BK1 is provided far from the power supply pad PDV. The power supply pad PDV supplies the predetermined voltage to a sense amplifier/write driver 20b via power supply wiring VDL0.SELECTED DRAWING: Figure 6

Description

  Embodiments described herein relate generally to a semiconductor memory device.

  MRAM (Magnetic Random Access Memory) is a memory device that uses a magnetic element having a magnetoresistive effect in a memory cell that stores information, and is a next-generation memory characterized by high-speed operation, large capacity, and non-volatility. It is attracting attention as a device. In addition, research and development of MRAM are underway as a replacement for volatile memories such as DRAM and SRAM. In this case, it is desirable to operate the MRAM with the same specifications as the DRAM and the SRAM in order to reduce the development cost and perform the replacement smoothly.

JP 2010-33631 A

  A high-quality semiconductor memory device is provided.

  The semiconductor memory device according to the embodiment is connected to the power supply pad, the first bank including a plurality of memory cells, the power supply pad, and the first bank, the second bank including the plurality of memory cells, and the power supply pad. A first wiring that supplies power to the second bank, and a second wiring that is connected to the power supply pad, passes over the second bank, does not supply power to the second bank, and supplies power to the first bank And comprising.

FIG. 1 is a block diagram showing the semiconductor memory device according to the first embodiment. FIG. 2 is a block diagram showing a bank of the semiconductor memory device according to the first embodiment. FIG. 3 is a block diagram showing the memory cell MC of the semiconductor memory device according to the first embodiment. FIG. 4 is a block diagram showing a sense circuit of the semiconductor memory device according to the first embodiment. FIG. 5 is a block diagram showing a sense circuit of the semiconductor memory device according to the first embodiment. FIG. 6 is a layout diagram showing wiring of power supply lines of the semiconductor memory device according to the first embodiment. FIG. 7 is a cross-sectional view taken along line AA in FIG. 8 is a cross-sectional view taken along line BB in FIG. FIG. 9 is a flowchart showing a read operation of the semiconductor memory device according to the first embodiment. FIG. 10 is a waveform diagram showing voltage waveforms during a read operation of the semiconductor memory device according to the first embodiment. FIG. 11 is a layout diagram showing wiring of the power supply lines of the semiconductor memory device according to the comparative example of the first embodiment. FIG. 12 is a diagram showing a read operation of the semiconductor memory device according to the first embodiment. FIG. 13 is a waveform diagram showing voltage waveforms during a read operation of the semiconductor memory device according to the comparative example of the first embodiment. FIG. 14 is a waveform diagram showing voltage waveforms during a read operation of the semiconductor memory device according to the comparative example of the first embodiment. FIG. 15 is a layout diagram illustrating the wiring of the power supply lines of the semiconductor memory device according to the first modification of the first embodiment. FIG. 16 is a layout diagram showing wiring of power supply lines of the semiconductor memory device according to the second modification of the first embodiment. FIG. 17 is a layout diagram showing wiring of the power supply lines of the semiconductor memory device according to the third modification of the first embodiment. FIG. 18 is a layout diagram showing the wiring of the power supply lines of the semiconductor memory device according to Modification 4 of the first embodiment. FIG. 19 is a layout diagram showing wiring of the power supply lines of the semiconductor memory device according to Modification 5 of the first embodiment. FIG. 20 is a layout diagram showing wiring of power supply lines of the semiconductor memory device according to the second embodiment. FIG. 21 is a cross-sectional view taken along the line CC of FIG. FIG. 22 is a cross-sectional view taken along the line DD of FIG. FIG. 23 is a layout diagram showing wiring of the power supply lines of the semiconductor memory device according to the first modification of the second embodiment. FIG. 24 is a layout diagram showing wiring of power supply lines of a semiconductor memory device according to Modification 2 of the second embodiment. FIG. 25 is a layout diagram showing wiring of power supply lines of a semiconductor memory device according to Modification 3 of the second embodiment. FIG. 26 is a layout diagram illustrating wiring of power supply lines of a semiconductor memory device according to Modification 4 of the second embodiment. FIG. 27 is a layout diagram showing wiring of power supply lines of a semiconductor memory device according to Modification 5 of the second embodiment. FIG. 28 is a block diagram showing a controller of the semiconductor memory device according to the third embodiment. FIG. 29 is a waveform diagram showing a waveform of a read operation (normal time) of the semiconductor memory device according to the third embodiment. FIG. 30 is a waveform diagram showing a waveform of a read operation (at the momentary power failure) of the semiconductor memory device according to the third embodiment. FIG. 31 is a block diagram showing a sense amplifier / write driver of the semiconductor memory device according to the fourth embodiment. FIG. 32 is a circuit diagram showing the relationship between the memory array and the write driver of the semiconductor memory device according to the fourth embodiment. FIG. 33 is a circuit diagram showing a write driver of the semiconductor memory device according to the fourth embodiment. FIG. 34 is a waveform diagram showing waveforms in the write operation of the semiconductor memory device according to the fourth embodiment. FIG. 35 is a circuit diagram showing a write driver of the semiconductor memory device according to the comparative example of the fourth embodiment. FIG. 36 is a waveform diagram showing waveforms in the write operation of the semiconductor memory device according to the comparative example of the fourth embodiment. FIG. 37 is a circuit diagram showing a write driver of a semiconductor memory device according to a modification of the fourth embodiment. FIG. 38 is a waveform diagram showing waveforms in the write operation of the semiconductor memory device according to the modification of the fourth embodiment. FIG. 39 is a waveform diagram showing waveforms in the case where the voltages of the bit line BL and the source line SL related to the fourth embodiment are floated while the write operation and the read operation are not performed. FIG. 40 is a waveform diagram showing waveforms when the voltages of the bit line BL and the source line SL related to the fourth embodiment are floated while the write operation and the read operation are not performed. FIG. 41 is a waveform diagram showing waveforms when the voltages of the bit line BL and the source line SL related to the fourth embodiment are floated while the write operation and the read operation are not performed.

  Hereinafter, configured embodiments will be described with reference to the drawings. In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. The “_number” after the numerals constituting the reference numerals is used to distinguish between elements that are referred to by the reference numerals including the same numerals and have the same structure. If it is not necessary to distinguish between elements indicated by reference signs containing the same numbers, these elements are referenced by reference signs containing only the numerals. For example, when it is not necessary to distinguish the elements denoted by reference numerals 10_1 and 10_2, these elements are collectively referred to as the reference numeral 10.

  It should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  In this specification, for convenience of explanation, an XYZ orthogonal coordinate system is introduced. In this coordinate system, two directions that are parallel to the upper surface of the semiconductor substrate and are orthogonal to each other are defined as an X direction (D1) and a Y direction (D2), and are orthogonal to both the X direction and the Y direction. That is, the stacking direction of each layer is defined as the Z direction (D3).

<1> First Embodiment <1-1> Configuration <1-1-1> Semiconductor Memory Device First, a basic configuration of a semiconductor memory device according to the first embodiment will be schematically described with reference to FIG. To do.

  The semiconductor memory device 1 according to the first embodiment includes a core circuit 10a and a peripheral circuit 10b.

  The core circuit 10a includes a memory area 11, a column decoder 12, a word line driver 13, and a row decoder 14. The memory area 11 includes a plurality of banks BK (two banks BK0 and Bk1 in the example of FIG. 1). For example, these banks BK0 and BK1 can be activated independently. When the banks BK0 and BK1 are not distinguished from each other, they are simply referred to as banks BK. Details of the bank BK will be described later.

  The column decoder 12 recognizes the command or address by the command address signal CA based on the external control signal, and controls the selection of the bit line BL and the source line SL.

  The word line driver 13 is disposed along at least one side of the bank BK. The word line driver 13 is configured to apply a voltage to the selected word line WL via the main word line MWL at the time of data reading or data writing.

  The row decoder 14 decodes the address of the command address signal CA supplied from the command address input circuit 15. More specifically, the row decoder 14 supplies the decoded row address to the word line driver 13. Thereby, the word line driver 13 can apply a voltage to the selected word line WL.

  The peripheral circuit 10 b includes a command address input circuit 15, a controller 16, and an IO circuit 17.

  The command address input circuit 15 receives various external control signals such as a chip select signal CS, a clock signal CK, a clock enable signal CKE, and a command address signal CA from a memory controller (also referred to as a host device) 2. Is done. The command address input circuit 15 transfers the command address signal CA to the controller 16.

  The controller 16 identifies a command and an address. The controller 16 controls the semiconductor memory device 1.

  The IO circuit 17 temporarily stores the input data input from the memory controller 2 via the data line DQ or the output data read from the selected bank. Input data is written into the memory cell of the selected bank.

<1-1-2> Bank BK
The basic configuration of the bank BK of the semiconductor memory device according to the first embodiment will be schematically described with reference to FIG.

  The bank BK includes a memory array 20a, a sense amplifier / write driver (SA / WD) 20b, and a page buffer 20c.

  The memory array 20a includes a plurality of memory cells MC arranged in a matrix. The memory array 20a includes a plurality of word lines WL0 to WLi-1 (i is an integer of 2 or more), a plurality of bit lines BL0 to BLj-1 (j is an integer of 2 or more), and a plurality of source lines SL0 to SLj. -1 is arranged. One row of the memory array 20a is connected to one word line WL, and one column of the memory array 20a is connected to a pair of one bit line BL and one source line SL.

  The memory cell MC includes a magnetoresistive effect element (MTJ (Magnetic Tunnel Junction) element) 30 and a selection transistor 31. The selection transistor 31 is composed of, for example, an N channel MOSFET.

  One end of the MTJ element 30 is connected to the bit line BL, and the other end is connected to the drain (source) of the selection transistor 31. The gate of the selection transistor 31 is connected to the word line WL, and the source (drain) is connected to the source line SL.

  The sense amplifier / write driver 20b is arranged in the bit line direction of the memory array 20a. The sense amplifier / write driver 20b includes a sense amplifier and a write driver. Data stored in the memory cell is read by detecting a current flowing in the memory cell MC connected to the bit line BL via the global bit line GBL and connected to the selected word line WL via the main word line MWL. . The write driver is connected to the bit line BL via the global bit line GBL or to the memory cell MC connected to the source line SL via the global source line GSL and to the selected word line WL via the main word line MWL. Data is written by passing current. The sense amplifier / write driver 20b controls the bit line BL and the source line SL based on a control signal from the controller 16. Data exchange between the sense amplifier / write driver 20 b and the data line DQ is performed via the IO circuit 17.

  The page buffer 20c temporarily holds data read from the memory array 20a or write data received from the memory controller 2. Data is written to the memory array 20a in units of a plurality of memory cells (page units). A unit written in the memory array 20a in this way is called a “page”. Further, the page buffer 20c according to the present embodiment is provided for each bank BK, and has a storage capacity enough to temporarily store data of all pages of the bank BK.

  The configuration of the bank BK described above is an example, and the bank BK may have a configuration other than this.

<1-1-3> Memory cell MC
Subsequently, the configuration of the memory cell MC of the semiconductor memory device according to the first embodiment will be schematically described with reference to FIG. As shown in FIG. 3, one end of the MTJ element 30 of the memory cell MC according to the first embodiment is connected to the bit line BL, and the other end is connected to one end of the selection transistor 31. The other end of the selection transistor 31 is connected to the source line SL. The MTJ element 30 utilizing the TMR (tunneling magnetoresistive) effect has a laminated structure composed of two ferromagnetic layers F and P and a nonmagnetic layer (tunnel insulating film) B sandwiched between them, and spin polarization. Digital data is stored by the change in magnetoresistance due to the tunnel effect. The MTJ element 30 can take a low resistance state and a high resistance state by the magnetization arrangement of the two ferromagnetic layers F and P. For example, if the low resistance state is defined as data “0” and the high resistance state is defined as data “1”, 1-bit data can be recorded in the MTJ element 30. Of course, the low resistance state may be defined as data “1”, and the high resistance state may be defined as data “0”.

For example, the MTJ element 30 is configured by sequentially laminating a fixed layer (pinned layer) P, a tunnel barrier layer B, and a recording layer (free layer) F. The pinned layer P and the free layer F are made of a ferromagnetic material, and the tunnel barrier layer B is made of an insulating film (for example, Al ₂ O ₃ , MgO). The pinned layer P is a layer in which the orientation of the magnetization arrangement is fixed, and the free layer F has a variable orientation of the magnetization arrangement, and stores data according to the magnetization orientation.

  When a current is passed in the direction of arrow A1 at the time of writing, the free layer F is in an anti-parallel state (AP state) with respect to the magnetization direction of the pinned layer P, and is in a high resistance state (data “1”). When a current is passed in the direction of the arrow A2 at the time of writing, the magnetization directions of the pinned layer P and the free layer F are in a parallel state (P state), and are in a low resistance state (data “0”). As described above, the TMJ element can write different data depending on the direction of current flow.

<1-1-4> Sense Amplifier / Write Driver The sense amplifier / write driver 20b of the semiconductor memory device according to the first embodiment will be described with reference to FIG.

  As shown in FIG. 4, the sense amplifier / write driver 20 b includes a plurality of sense circuits 200. A plurality of sense circuits 200 are provided for each global bit line. Each of the plurality of sense circuits 200 includes a preamplifier 210 and a sense amplifier (SA) 220.

  The preamplifier 210 supplies a current (cell current) to the memory cell MC via the global bit line and the bit line, and generates voltages V1st and V2nd based on the cell current.

  The sense amplifier 220 determines data (DO, DOB) based on the voltages V1st and V2nd generated by the preamplifier 210.

  Note that the preamplifier 210 and the sense amplifier 220 operate based on voltages VDD and VSS applied via pads (not shown).

  A more specific example of the sense amplifier / write driver 20b of the semiconductor memory device according to the first embodiment will be described with reference to FIG. The configuration of the sense amplifier / write driver 20b is not limited to this.

  As shown in FIG. 5, in the sense amplifier / write driver 20b, a write driver (WD) 230 is connected to a bit line and a source line (BL and SL are collectively referred to as Cell path).

  The sense circuit 200 includes, for example, transistors 221 and 223, a first sample and hold circuit 222, and a second sample and hold circuit 224. The sense amplifier 220 in FIG. 4 corresponds to the second sense amplifier 225.

  The first sample hold circuit 222 holds the voltage acquired by the preamplifier 210 during the first read operation (details will be described later).

  The second sample hold circuit 224 holds the voltage acquired by the preamplifier 210 during the second read operation (details will be described later).

  The second sense amplifier 225 outputs data DO based on the output voltage V1st from the first sample hold circuit 222 and the output voltage V2nd from the first sample hold circuit 224. As will be described later, the second sense amplifier 225 determines data based on the first read operation and the second read operation. The second sense amplifier 225 can determine “0” data correctly when reading “0” data during the first read operation and when reading “0” data during the second read operation. Judgment is made with an offset.

<1-1-5> Layout <1-1-5-1> Wiring Layout The power supply wiring layout of the semiconductor memory device according to the first embodiment will be described with reference to FIG. Here, for the sake of simplicity, a pad for supplying the voltage VDD, a wiring for supplying the voltage VDD, a memory array 20a, and a sense amplifier / write driver 20b are shown.

  As shown in FIG. 6, a bank BK0 is provided adjacent to the power supply pad PDV that supplies the voltage VDD in the direction D2. The bank BK0 is sandwiched between the power supply pad PDV and the bank BK1 in the direction D2. That is, the bank BK0 is provided near the power supply pad PDV, and the bank BK1 is provided far from the power supply pad PDV.

  The power supply pad PDV supplies the voltage VDD to the sense amplifier / write driver 20b through the power supply wiring VDL.

  The power supply wiring VDL connected to the sense amplifier / write driver 20b of the bank BK0 will be described.

  Power supply pad PDV is connected to power supply wiring VDL0 through contact C0.

  The power supply wiring VDL0 extends in the D1 direction. The power supply wiring VDL0 is connected to the power supply wiring VDL1_0 to VDL1_x via contacts C1_0 to C1_x (x is an integer), respectively.

  The power supply wirings VDL1_0 to VDL1_x extend in the D2 direction. The power supply wirings VDL1_0 to VDL1_x are connected to the power supply wiring VDL3 through the contacts C3_0 to C3_x.

  The power supply wiring VDL3 extends in the D1 direction. The power supply wiring VDL3 is connected to the sense amplifier / write driver 20b of the bank BK0 through a contact (not shown).

  The power supply wiring VDL connected to the sense amplifier / write driver 20b of the bank BK1 will be described.

  The power supply wiring VDL0 is connected to the power supply wirings VDL2_0 to VDL2_x through contacts C2_0 to C2_x, respectively.

  The power supply lines VDL2_0 to VDL2_x are not connected to the bank BK0 but extend in the D2 direction so as to be connected to the sense amplifier / write driver 20b of the bank BK1. The power supply wirings VDL2_0 to VDL2_x are connected to the power supply wiring VDL6 through the contacts C7_0 to C7_x.

  The power supply wiring VDL6 extends in the D1 direction. The power supply wiring VDL6 is connected to the sense amplifier / write driver 20b of the bank BK1 through a contact (not shown).

  The power supply wirings VDL2_0 to VDL2_x are connected to the power supply wirings VDL4_0 to VDL4_x through contacts C4_0 to C4_x, respectively.

  The power supply wirings VDL4_0 to VDL4_x extend in the D1 direction. The power supply wirings VDL4_0 to VDL4_x are connected to the power supply wirings VDL5_0 to VDL5_x through the contacts C5_0 to C5_x, respectively.

  The power supply wirings VDL5_0 to VDL5_x extend in the D2 direction. The power supply wirings VDL5_0 to VDL5_x are connected to the power supply wiring VDL6 through the contacts C6_0 to C6_x.

<1-1-5-2> AA Cross Section The AA cross section of FIG. 6 will be described with reference to FIG. Here, for simplicity, an insulating layer covering each wiring is not shown. Further, in the AA cross section, a configuration that is not originally illustrated is indicated by a broken line.

  First, the memory array 20a of the bank BK0 will be described. As described above, the memory array 20a of the bank BK0 includes a plurality of memory cells. Here, for the sake of simplicity, only one memory cell provided in the memory array 20a of the bank BK0 is shown.

  Specifically, impurity regions 101a and 101b are provided in the surface region of the semiconductor substrate 100a. A channel region (not shown) is provided in a surface region of the semiconductor substrate 100a and a region sandwiched between the impurity regions 101a and 101b. An insulating film 102 is provided above the channel region, and a control gate electrode 103 (word line WL) is provided on the insulating film 102. As described above, the selection transistor 31 includes the impurity regions 101a and 101b, the channel region, the insulating film 102, and the control gate electrode 103.

  Note that a layer in which the word line WL is provided is referred to as a first wiring layer (1st ML).

  A contact 104 made of a conductor is provided on the impurity region 101 a, and the MTJ element 30 is provided on the contact 104. A contact 105 made of a conductor is provided on the MTJ element 30, and a wiring layer 106 (bit line BL) made of a conductor extending in the D2 direction is provided on the contact 105. A contact 107 made of a conductor is provided on the impurity region 101b, and a wiring layer (source line SL) made of a conductor extending in the D2 direction is provided on the contact 107. As described above, the memory cell MC includes the selection transistor 31, the contact 104, the MTJ element 30, the contact 105, and the contact 107.

  Note that a layer in which the bit line BL and the source line BL are provided is referred to as a second wiring layer (2nd ML). The second wiring layer is positioned higher in the D3 direction than the first wiring layer.

  Above the wiring layer 106, a wiring layer 108 (main word line MWL) extending in the direction D1 is provided.

  Note that a layer in which the main word line MWL is provided is referred to as a third wiring layer (3rd ML). The third wiring layer is positioned higher in the D3 direction than the second wiring layer.

  Here, for simplicity, one memory cell MC has been described. However, the memory array 20a of the bank BK0 is provided with a plurality of memory cells MC as described above.

  Next, the sense amplifier / write driver 20b in the bank BK0 will be described. Here, for simplicity, only one transistor provided in the sense amplifier / write driver 20b of the bank BK0 is shown.

  Specifically, impurity regions 101c and 101d are provided in the surface region of the semiconductor substrate 100a. A channel region (not shown) is provided in a surface region of the semiconductor substrate 100a and a region sandwiched between the impurity regions 101c and 101d. An insulating film 109 is provided above the channel region, and a control gate electrode 110 is provided on the insulating film 109. As described above, the transistor includes the impurity regions 101c and 101d, the channel region, the insulating film 109, and the control gate electrode 110.

  A contact 111 made of a conductor is provided on the impurity region 101c, and a wiring layer 112 made of a conductor is provided on the contact 111. The wiring layer 112 is located in the second wiring layer. A contact 113 made of a conductor is provided on the wiring layer 112, and a wiring layer 114 made of a conductor is provided on the contact 113. The wiring layer 114 is located in the third wiring layer. A contact 115 made of a conductor is provided on the wiring layer 114, and a wiring layer 116 (power supply wiring VDL1) made of a conductor extending in the D2 direction is provided on the contact 115.

  The layer provided with the power supply wiring VDL1 is referred to as a fourth wiring layer (4th ML). The fourth wiring layer is positioned higher in the D3 direction than the third wiring layer.

  In the above, the memory array 20a and the sense amplifier / write driver 20b of the bank BK0 have been described.

  The memory array 20a and the sense amplifier / write driver 20b in the bank BK1 have the same configuration.

  If the semiconductor substrate 100a in the above description is replaced with the semiconductor substrate 100b and the wiring layer 116 (power supply wiring VDL1) is replaced with the wiring layer 116 (power supply wiring VDL5), the description of the memory array 20a and the sense amplifier / write driver 20b in the bank BK1 Become.

  As shown in FIGS. 6 and 7, the power supply wiring VDL1 and the power supply wiring VDL5 are electrically connected in the power supply wiring VDL0, but are not directly connected.

<1-1-5-3> BB Section The BB section of FIG. 6 will be described with reference to FIG. Here, for simplicity, an insulating layer covering each wiring is not shown. In the BB cross section, a configuration that is not originally illustrated is indicated by a broken line.

  The basic description of the banks BK0 and BK1 is almost the same as that described with reference to FIG. The difference between FIG. 7 and FIG. 8 is that wiring layer 116 (power supply wiring VDL2) passes above bank BK0 but is not directly connected to bank BK0.

  As shown in FIGS. 6 to 8, the power supply wiring connected to the bank BK0 and the power supply wiring connected to the bank BK1 are connected in the vicinity of the power supply pad PDV. Therefore, noise generated in the sense amplifier / write driver 20b in the bank BK0 is absorbed by the power supply pad PDV and does not affect the sense amplifier / write driver 20b in the bank BK1. Similarly, noise generated in the sense amplifier / write driver 20b in the bank BK1 is absorbed by the power supply pad PDV and does not affect the sense amplifier / write driver 20b in the bank BK0.

  Further, the bank BK1 is farther away from the power supply pad PDV than the bank BK0. Therefore, the number of power supply wirings connected to the bank BK1 is twice the number of power supply wirings connected to the bank BK0 so that the voltage supplied to the bank BK1 is not lower than the voltage supplied to the bank BK0. It is. In the first embodiment, for simplicity, the number of power supply wirings connected to the bank BK1 is twice the number of power supply wirings connected to the bank BK0. However, it is only necessary that the number of power supply lines connected to the bank BK1 is larger than the number of power supply lines connected to the bank BK0.

<1-2> Operation As described above, the MTJ element of the semiconductor memory device according to the first embodiment stores data using a change in resistance value. When reading information stored in such an MTJ element, the semiconductor memory device passes a read current (also referred to as a cell current) to the MTJ element. The semiconductor memory device can determine the resistance state by converting the resistance value of the MTJ element into a current value or a voltage value and comparing it with a reference value.

  However, as the resistance variation of the MTJ element increases, the interval between the resistance value distributions in the “0” state and the “1” state may become narrower. For this reason, in a read method in which a reference value is set between the resistance value distributions and the state of the MTJ element is determined based on the magnitude of the reference value, the read margin is significantly reduced.

  Therefore, for such an event, as one reading method, there is a self-reference reading method in which a reference signal is generated by rewriting its own data and data is read based on the generated signal.

  In the following embodiments, a read operation of a semiconductor memory device when a self-reference read method is used as a read method will be described.

<1-2-1> Overview of Read Operation An overview of the read operation of the memory system according to the first embodiment will be described with reference to FIG. In this description, FIGS. 4 and 5 are referred to.

[Step S1001]
The memory controller 2 issues an active command and a read command to the semiconductor memory device 1.

  When the semiconductor memory device 1 receives an active command and a read command from the memory controller 2, the semiconductor memory device 1 performs a first read operation (1st READ) on the memory cell to be read. The sense circuit 200 stores the resistance state of the memory cell to be read as voltage information (signal voltage) V1st by the first read operation.

[Step S1002]
The semiconductor memory device 1 performs a “0” write operation (WRITE “0”) on the memory cell that is the target of the first read operation. As a result, the memory cell targeted for the first read operation is overwritten with the “0” data. In this operation, the memory cell is brought into a reference state (here, “0”) in order to generate V2nd described later. That is, this writing operation may be described as a standardization operation.

[Step S1003]
The semiconductor memory device 1 performs a second read operation (2nd READ) on the memory cell that is the target of the first read operation. The sense circuit 200 generates voltage information (signal voltage) V2nd by the second read operation.

[Step S1004]
The sense circuit 200 determines the result of V1st generated in step S1001 based on V2nd generated in step S1003. Specifically, the sense circuit 200 determines data stored in the memory cell by comparing V1st and V2nd.

  The controller 16 determines the data stored in the memory cell and then writes the data back to the memory cell. Thereby, the data originally stored in the memory cell can be returned to the memory cell.

<1-2-2> Voltage Waveform A voltage waveform during a read operation will be described with reference to FIG.

  As shown in FIG. 10, when the semiconductor memory device 1 performs the first read operation, the first read result is stored in the first sample hold circuit 222, and the voltage of V1st is increased (time T0 to time T1). ).

  The semiconductor memory device 1 performs a “0” write operation after the first read operation (time T1 to time T2).

  In the semiconductor memory device 1, the second read result is stored in the second sample and hold circuit 224, and the voltage V2nd is increased (time T2 to time T3).

  The second sense amplifier 225 determines data based on the voltages V1st and V2nd (time T4).

  As described above, in the read operation of the memory system according to the first embodiment, data is determined by performing the read operation twice.

<1-3> Effect According to the embodiment described above, the power supply wiring connected to the bank BK0 and the power supply wiring connected to the bank BK1 are connected in the vicinity of the power supply pad PDV. Therefore, the noise generated in the sense amplifier / write driver 20b in the bank BK0 or the bank BK1 is absorbed by the power supply pad PDV and does not affect the sense amplifier / write driver 20b in the other bank BK.

  Here, a comparative example will be described in order to facilitate understanding of the effects of the first embodiment.

  A power supply wiring layout of the semiconductor memory device according to the comparative example will be described with reference to FIG. Here, for the sake of simplicity, a pad that supplies the voltage VDD, a wiring that supplies the voltage VDD, a memory array, and the sense amplifier / write driver 20b are shown.

  As shown in FIG. 11, the power supply wirings VDL7_0 to VDL7_x extend in the D2 direction. The power supply wirings VDL7_0 to VDL7_x are connected to the power supply wiring VDL3 through the contacts C3_0 to C3_x. The power supply wirings VDL7_0 to VDL7_x are connected to the power supply wiring VDL6 via the contacts C6_0 to C6_x.

  Thus, in the semiconductor memory device according to the comparative example, the power supply wiring connected to the bank BK0 and the power supply wiring connected to the bank BK1 are common.

  By the way, in the semiconductor memory device, different banks BK may be operated simultaneously.

  For example, as shown in FIG. 12, the timing of the second read operation for the bank BK0 and the first read operation for the bank BK1 may overlap.

  In this case, noise may occur in the bank BK1 during the operation of the bank BK0. Similarly, noise may occur in the bank BK0 during the operation of the bank BK1.

  Here, a waveform when noise from an adjacent bank is received during a read operation will be described.

  FIG. 13 shows waveforms when adjacent banks are activated during the first read operation.

  As shown in FIG. 13, when the adjacent bank is activated during the first read operation, the voltage value is stored in the sample hold circuit 222 while V1st is lowered as surrounded by the broken line in the figure. Sometimes. In this case, there is a possibility that the second sense amplifier 225 cannot appropriately determine data.

  FIG. 14 shows waveforms when adjacent banks are activated during the second read operation.

  As shown in FIG. 14, when the adjacent bank is activated during the second read operation, the voltage value is stored in the sample hold circuit 224 while V2nd is lowered as surrounded by the broken line in the figure. Sometimes. In this case, there is a possibility that the second sense amplifier 225 cannot appropriately determine data.

  As described above, in the semiconductor memory device according to the comparative example, there is a possibility that data cannot be correctly determined due to the influence of adjacent banks.

  As described above, the semiconductor memory device performs two read operations in order to read data from the memory cell. Therefore, it is desirable that the first read operation and the second read operation operate in the same operating environment.

  However, if only one of the first read operation and the second read operation is affected by noise generated in another adjacent bank, there is a possibility that data cannot be read appropriately.

  Therefore, in the semiconductor memory device according to the above-described embodiment, the power supply wiring connected to the bank BK0 and the power supply wiring connected to the bank BK1 are connected in the vicinity of the power supply pad PDV. Since the power supply pad PDV can absorb noise, the power supply noise generated in the bank BK does not affect other adjacent banks BK. Therefore, even when the operation shown in FIG. 12 is performed, the read operation can be performed satisfactorily.

<1-4> Modification <1-4-1> Modification 1
A power supply wiring layout of the semiconductor memory device according to the first modification of the first embodiment will be described with reference to FIG.

  The difference between the power supply wiring layout of the semiconductor memory device according to the first modification of the first embodiment and the power supply wiring layout of the semiconductor memory device according to the first embodiment is that a power supply circuit 300 is further added.

  Specifically, as shown in FIG. 15, a power supply circuit 300a is provided between the power supply wiring VDL0 and the power supply wiring VDL1. A power supply circuit 300b is provided between the power supply wiring VDL0 and the power supply wiring VDL2.

  The power supply circuit 300a may have any configuration as long as the power supply voltage can be transferred from the power supply wiring VDL0 to the power supply wiring VDL1. Similarly, the power supply circuit 300b may have any configuration as long as the power supply voltage can be transferred from the power supply wiring VDL0 to the power supply wiring VDL2.

<1-4-2> Modification 2
A power supply wiring layout of the semiconductor memory device according to the second modification of the first embodiment will be described with reference to FIG.

  A layout as shown in FIG. 16 may be used. In FIG. 15, one power supply wiring VDL1 is connected to one power supply circuit 300a. However, as shown in FIG. 16, a plurality of power supply lines VDL1 may be connected to one power supply circuit 300a. Similarly, as shown in FIG. 16, a plurality of power supply wirings VDL2 may be connected to one power supply circuit 300b.

<1-4-3> Modification 3
A power supply wiring layout of the semiconductor memory device according to the third modification of the first embodiment will be described with reference to FIG.

  The difference between the power supply wiring layout of the semiconductor memory device according to the third modification of the first embodiment and the power supply wiring layout of the semiconductor memory device according to the first embodiment is that a power supply pad for the bank BK0 and a power supply wiring for the bank BK1 are used. The power pad is electrically separated.

  As shown in FIG. 17, the first power supply pad PDV1 supplies the voltage VDD to the sense amplifier / write driver 20b of the bank BK0 via the power supply wiring VDL.

  First power supply pad PDV1 is connected to power supply line VDL0_0 through contact C0_0.

  The power supply wiring VDL0_0 extends in the D1 direction. The power supply wiring VDL0_0 is connected to the power supply wirings VDL1_0 to VDL1_x through contacts C10_0 to C10_x, respectively.

  As shown in FIG. 17, the second power supply pad PDV2 supplies the voltage VDD to the sense amplifier / write driver 20b of the bank BK1 through the power supply wiring VDL.

  Second power supply pad PDV2 is connected to power supply line VDL0_1 via contact C0_1.

  The power supply wiring VDL0_1 extends in the D1 direction. The power supply wiring VDL0_1 is connected to the power supply wirings VDL2_0 to VDL2_x through contacts C11_0 to C11_x, respectively.

<1-4-4> Modification 4
The power supply wiring layout of the semiconductor memory device according to the modification 4 of the first embodiment will be described with reference to FIG.

  As a difference between the power supply wiring layout of the semiconductor memory device according to the fourth modification of the first embodiment and the power supply wiring layout of the semiconductor memory device according to the third modification of the first embodiment, a power supply circuit 300 is further added. Is a point.

  Specifically, as illustrated in FIG. 18, a power supply circuit 300a is provided between the power supply wiring VDL0_0 and the power supply wiring VDL1. A power supply circuit 300b is provided between the power supply wiring VDL0_1 and the power supply wiring VDL2.

  The power supply circuit 300a may have any configuration as long as the power supply voltage can be transferred from the power supply wiring VDL0_0 to the power supply wiring VDL1. Similarly, the power supply circuit 300b may have any configuration as long as the power supply voltage can be transferred from the power supply wiring VDL0_1 to the power supply wiring VDL2.

<1-4-5> Modification 5
A power supply wiring layout of the semiconductor memory device according to Modification 5 of the first embodiment will be described with reference to FIG.

  A layout as shown in FIG. 19 may be used. In FIG. 18, one power supply wiring VDL1 is connected to one power supply circuit 300a. However, as shown in FIG. 19, a plurality of power supply wirings VDL1 may be connected to one power supply circuit 300a. Similarly, as shown in FIG. 19, a plurality of power supply wirings VDL2 may be connected to one power supply circuit 300b.

<2> Second Embodiment A second embodiment will be described. In the second embodiment, another example of the power supply wiring layout of the semiconductor memory device will be described. The basic configuration and basic operation of the semiconductor memory device according to the second embodiment are the same as those of the semiconductor memory device according to the first embodiment described above. Therefore, the description about the matter demonstrated by 1st Embodiment mentioned above and the matter which can be easily guessed from 1st Embodiment mentioned above is abbreviate | omitted.

<2-1> Layout <2-1-1> Wiring Layout A power supply wiring layout of the semiconductor memory device according to the second embodiment will be described with reference to FIG. Here, for the sake of simplicity, a pad for supplying the voltage VDD, a wiring for supplying the voltage VDD, a memory array 20a, and a sense amplifier / write driver 20b are shown.

  As shown in FIG. 20, a bank BK0 is provided adjacent to the power supply pad PDV that supplies the voltage VDD in the direction D2. The bank BK0 is sandwiched between the power supply pad PDV and the bank BK1 in the direction D1. That is, the bank BK0 is provided near the power supply pad PDV, and the bank BK1 is provided far from the power supply pad PDV.

  The power supply pad PDV supplies the voltage VDD to the sense amplifier / write driver 20b through the power supply wiring VDL.

  The power supply wiring VDL connected to the sense amplifier / write driver 20b of the bank BK0 will be described.

  Power supply pad PDV is connected to power supply wiring VDL20 via contact C20.

  The power supply wiring VDL20 extends in the D2 direction. The power supply wiring VDL20 is connected to the power supply wiring VDL21_0 to VDL21_y via contacts C21_0 to C21_y (y is an integer), respectively.

  The power supply wirings VDL21_0 to VDL21_y extend in the D1 direction. The power supply wiring VDL21_0 is connected to the power supply wiring VDL25_0 to VDL25_z through contacts C23_0-0 to C23_0-z (z is an integer). Similarly, the power supply wiring VDL21_y is connected to the power supply wiring VDL25_0 to VDL25_z through the contacts C23_y-0 to C23_yz. In addition, at least one of the power supply wirings VDL21_0 to VDL21_y is preferably provided on the sense amplifier / write driver 20b. In this example, the power supply wiring VDL21_y is provided on the sense amplifier / write driver 20b.

  The power supply wirings VDL25_0 to VDL25_z extend in the D2 direction. The power supply wirings VDL25_0 to VDL25_z are connected to the power supply wiring VDL26 through contacts C28_0 to C28_z.

  The power supply wiring VDL 26 extends in the D1 direction. The power supply wiring VDL26 is connected to the sense amplifier / write driver 20b of the bank BK0 through a contact (not shown).

  The power supply wiring VDL connected to the sense amplifier / write driver 20b of the bank BK1 will be described.

  The power supply wiring VDL20 is connected to the power supply wirings VDL22_0 to VDL22_y through contacts C22_0 to C22_y, respectively.

  The power supply lines VDL22_0 to VDL22_y are not connected to the bank BK0 but extend in the D1 direction so as to be connected to the bank BK1. The power supply wiring VDL22_0 is connected to the power supply wiring VDL27_0 to VDL27_z through contacts C27_0-0 to C27_0-z. Similarly, the power supply wiring VDL22_y is connected to the power supply wiring VDL27_0 to VDL27_z through the contacts C27_y-0 to C27_yz. In addition, at least one of the power supply wirings VDL22_0 to VDL22_y is preferably provided on the sense amplifier / write driver 20b. In this example, the power supply wiring VDL22_y is provided on the sense amplifier / write driver 20b.

  The power supply wirings VDL27_0 to VDL27_z extend in the D2 direction. The power supply wirings VDL27_0 to VDL27_z are connected to the power supply wiring VDL28 through contacts C29_0 to C29_z.

  The power supply wiring VDL 28 extends in the D1 direction. The power supply wiring VDL 28 is connected to the sense amplifier / write driver 20b of the bank BK1 through a contact (not shown).

  The power supply wirings VDL22_0 to VDL22_y are connected to the power supply wirings VDL23_0 to VDL23_y through contacts C24_0 to C24_y.

  The power supply wirings VDL23_0 to VDL23_y extend in the D2 direction. The power supply wiring VDL23_0 is connected to the power supply wirings VDL24_0 to VDL24_y through contacts C25_0 to C25_0.

  The power supply wirings VDL24_0 to VDL24_y extend in the D1 direction. The power supply wiring VDL24_0 is connected to the power supply wiring VDL27_0 to VDL27_z through contacts C26_0-0 to C26_0-z. Similarly, the power supply wiring VDL24_y is connected to the power supply wiring VDL27_0 to VDL27_z through the contacts C26_y-0 to C26_yz. In addition, at least one of the power supply wirings VDL24_0 to VDL24_y is preferably provided on the sense amplifier / write driver 20b. In this example, the power supply wiring VDL24_y is provided on the sense amplifier / write driver 20b.

<2-1-2> CC cross section The CC cross section of FIG. 20 is demonstrated using FIG. Here, for simplicity, an insulating layer covering each wiring is not shown. In addition, in the CC cross section, a configuration that is not originally illustrated is indicated by a broken line.

  The basic description of the bank BK0 is almost the same as that described in FIG. The difference between FIG. 7 and FIG. 21 is that power supply wiring and main word line MWL are alternately provided in the third wiring layer.

<2-1-3> DD cross section The DD cross section of FIG. 20 is demonstrated using FIG. Here, for simplicity, an insulating layer covering each wiring is not shown. In the DD cross section, a configuration that is not originally illustrated is indicated by a broken line.

  In FIG. 21, only the power supply wiring VDL21 is connected to the power supply wiring VDL25. However, in FIG. 22, two lines of power supply wirings VDL22 and VDL24 are connected to the power supply wiring VDL27.

<2-2> Effect As shown in FIGS. 20 to 22, the power supply wiring connected to the bank BK0 and the power supply wiring connected to the bank BK1 are connected in the vicinity of the power supply pad PDV. Further, the number of power supply lines connected to the bank BK1 is twice the number of power supply lines connected to the bank BK0 so that the voltage supplied to the bank BK1 is not lower than the voltage supplied to the bank BK0. It is. In the first embodiment, for simplicity, the number of power supply wirings connected to the bank BK1 is twice the number of power supply wirings connected to the bank BK0. However, it is only necessary that the number of power supply lines connected to the bank BK1 is larger than the number of power supply lines connected to the bank BK0.

  Therefore, the same effect as the first embodiment described above can be obtained.

<2-3> Modification <2-3-1> Modification 1
A power supply wiring layout of the semiconductor memory device according to the first modification of the second embodiment will be described with reference to FIG.

  The difference between the power supply wiring layout of the semiconductor memory device according to the first modification of the second embodiment and the power supply wiring layout of the semiconductor memory device according to the second embodiment is that a power supply circuit 300 is further added.

  Specifically, as shown in FIG. 23, a power supply circuit 300a is provided between the power supply wiring VDL20 and the power supply wiring VDL21. A power supply circuit 300b is provided between the power supply wiring VDL20 and the power supply wiring VDL22.

  The power supply circuit 300a may have any configuration as long as the power supply voltage can be transferred from the power supply wiring VDL20 to the power supply wiring VDL21. Similarly, the power supply circuit 300b may have any configuration as long as the power supply voltage can be transferred from the power supply wiring VDL20 to the power supply wiring VDL22.

<2-3-2> Modification 2
A power supply wiring layout of the semiconductor memory device according to the second modification of the second embodiment will be described with reference to FIG.

  A layout as shown in FIG. 24 may be used. In FIG. 23, one power supply wiring VDL21 is connected to one power supply circuit 300a. However, as shown in FIG. 24, a plurality of power supply wirings VDL21 may be connected to one power supply circuit 300a. Similarly, as shown in FIG. 24, a plurality of power supply wirings VDL22 may be connected to one power supply circuit 300b.

<2-3-3> Modification 3
The power supply wiring layout of the semiconductor memory device according to the third modification of the second embodiment will be described with reference to FIG.

  The difference between the power supply wiring layout of the semiconductor memory device according to the third modification of the second embodiment and the power supply wiring layout of the semiconductor memory device according to the second embodiment is that the power supply pad for the bank BK0 and the power supply wiring for the bank BK1 The power pad is electrically separated.

  As shown in FIG. 25, the first power supply pad PDV1 supplies the voltage VDD to the sense amplifier / write driver 20b of the bank BK0 via the power supply wiring VDL.

  First power supply pad PDV1 is connected to power supply line VDL20_0 through contact C20_0.

  The power supply wiring VDL20_0 extends in the D2 direction. The power supply wiring VDL20_0 is connected to the power supply wirings VDL21_0 to VDL21_y through contacts C21_0 to C21_y, respectively.

  Second power supply pad PDV2 is connected to power supply line VDL20_1 through contact C20_1.

  The power supply wiring VDL20_1 extends in the D2 direction. The power supply wiring VDL20_1 is connected to the power supply wirings VDL22_0 to VDL22_y through contacts C22_0 to C22_y, respectively.

<2-3-4> Modification 4
A power supply wiring layout of the semiconductor memory device according to the modification 4 of the second embodiment will be described with reference to FIG.

  As a difference between the power supply wiring layout of the semiconductor memory device according to the fourth modification of the second embodiment and the power supply wiring layout of the semiconductor memory device according to the third modification of the second embodiment, a power supply circuit 300 is further added. Is a point.

  Specifically, as illustrated in FIG. 26, a power supply circuit 300a is provided between the power supply wiring VDL20_0 and the power supply wiring VDL21. A power supply circuit 300b is provided between the power supply wiring VDL20_1 and the power supply wiring VDL22.

  The power supply circuit 300a may have any configuration as long as the power supply voltage can be transferred from the power supply wiring VDL20_0 to the power supply wiring VDL21. Similarly, the power supply circuit 300b may have any configuration as long as the power supply voltage can be transferred from the power supply wiring VDL20_1 to the power supply wiring VDL22.

<2-3-5> Modification 5
With reference to FIG. 27, a power supply wiring layout of a semiconductor memory device according to Modification 5 of the second embodiment will be described.

  A layout as shown in FIG. 27 may be used. In FIG. 26, one power supply wiring VDL21 is connected to one power supply circuit 300a. However, as shown in FIG. 27, a plurality of power supply wirings VDL21 may be connected to one power supply circuit 300a. Similarly, as shown in FIG. 27, a plurality of power supply wirings VDL22 may be connected to one power supply circuit 300b.

<3> Third Embodiment A third embodiment will be described. In the third embodiment, a controller will be described. The basic configuration and basic operation of the semiconductor memory device according to the third embodiment are the same as those of the semiconductor memory device according to the first embodiment described above. Therefore, the description about the matter demonstrated by 1st Embodiment mentioned above and the matter which can be easily guessed from 1st Embodiment mentioned above is abbreviate | omitted.

<3-1> Controller A controller of the semiconductor memory device according to the third embodiment will be described with reference to FIG.

  Here, at the momentary power failure of the memory controller, the current path of the internal (semiconductor memory device) and external (memory controller) power supply is cut, and the operation is performed up to an appropriate time regardless of the external power supply voltage. The controller 16 that properly ends the operation will be described.

  FIG. 28 shows a part of the controller 16. As shown in FIG. 28, the controller 16 includes a potential drop detector 40, a potential generation circuit 41, a command system circuit 42, and a stabilization capacitor 43.

  When determining that “internal voltage VDD * int <external voltage VDD * ext”, the potential drop detector 40 determines that the external voltage has not dropped. On the other hand, when the potential drop detector 40 determines that “external voltage VDD * ext <internal voltage VDD * int”, it determines that the external voltage has dropped. The potential drop detector 40 supplies an “H” level potential drop detection signal to the potential generation circuit 41 and the command system circuit 42 when determining that the external voltage is dropping. The internal voltage VDD * int is a voltage generated by the stabilization capacitor 43. The external voltage VDD * ext is a voltage supplied from the memory controller 2. The external voltage VDD * ext is input to the non-inverting input terminal of the potential drop detector 40 via the resistance element R1 and the node N1. The internal voltage VDD * int is input to the inverting input terminal of the potential drop detector 40 via the resistance element R3 and the node N2.

  The potential generation circuit 41 generates various voltages (internal voltage VDD * int) based on the external voltage VDD * ext. When the potential generation circuit 41 receives the H ″ level potential drop detection signal from the potential drop detector 40, the potential generation circuit 41 blocks the current path for receiving the external voltage VDD * ext. * Int can be prevented from flowing back to the power supply pad that supplies the external voltage VDD * ext.

  The stabilization capacitor 43 can store an electric charge that can perform, for example, one read operation (first read operation, write operation, second read operation, and determination operation) even if the external voltage VDD * ext is not supplied. The capacity is as large as possible.

  The command system circuit 42 generates a signal for operating the sense circuit 200 or the write driver. When the command system circuit 42 receives the H ″ level potential drop detection signal from the potential drop detector 40, the command system circuit 42 operates the semiconductor memory device 1 to the point where the sharpness is good. After the semiconductor memory device 1 is operated, it operates so as not to accept a command.

<3-2> Operation <3-2-1> Normal Operation The normal operation of the controller of the semiconductor memory device according to the third embodiment will be described with reference to FIG. In FIG. 29, the external voltage VDD * ext, the internal voltage VDD * int, the active (ACT) command and the write (Write) command supplied from the memory controller 2, the potential drop detection signal, and the sense circuit 200 are operated. A signal SA Act and a signal WD Act for operating the write driver are shown. A case where the external voltage VDD * ext does not drop will be described.

  When receiving an active command from the memory controller 2, the controller 16 sets the signal SA Act to the “H” level and operates the sense circuit 200 (time T20 to time T21). Although not shown, the controller 16 performs a first read operation by receiving a read command from the memory controller 2.

  Subsequently, when receiving an active command from the memory controller 2, the controller 16 sets the signal SA Act to the “H” level and operates the sense circuit 200 (time T22 to time T23). When receiving a write command from the memory controller 2, the controller 16 sets the signal WD Act to the “H” level and operates the write driver (time T23 to T25). As a result, the controller 16 performs a “0” write operation.

  Although not shown, the controller 16 completes the read operation by performing a second read operation thereafter.

<3-2-2> Operation during Instantaneous Power Failure Next, with reference to FIG. 30, an operation during a momentary power failure of the controller of the semiconductor memory device according to the third embodiment will be described.

  When receiving an active command from the memory controller 2, the controller 16 sets the signal SA Act to the “H” level and operates the sense circuit 200 (time T30 to time T31). Although not shown, the controller 16 performs a first read operation by receiving a read command from the memory controller 2.

  At time T31, a momentary power failure occurs and the external voltage VDD * ext drops. As a result, at time T32, the potential drop detector 40 detects a drop in the external voltage VDD * ext and sets the potential drop detection signal to the “H” level. When the command system circuit 42 receives the H ”level potential drop detection signal from the potential drop detector 40, the command circuit 42 operates the semiconductor memory device 1 to the point where it is clear. At time T32, the next operation is“ The “0” write operation is an operation that overwrites the data in the memory cell MC and destroys the data stored in the memory cell.Therefore, the external voltage VDD * ext is applied to the semiconductor memory device. In the situation where the internal voltage VDD * int cannot be generated without being supplied to 1, the “0” write operation may occur and the data originally stored in the memory cell may be lost. The command from the memory controller 2 is not accepted, so that the controller 16 can prevent the data stored in the memory cell from being damaged. Although not shown here, for example, when the external voltage VDD * ext drops after the “0” write operation, the command system circuit 42 controls to perform the data write back operation. The controller 16 can prevent corruption of data stored in the memory cell.

<3-3> Effect According to the embodiment described above, the controller determines a momentary power failure of the memory controller, cuts the current path between the semiconductor memory device and the memory controller, and regardless of the power supply voltage from the memory controller, Appropriately configured to terminate operation.

  Therefore, even in a semiconductor memory device that performs a self-referencing read operation, data corruption can be suppressed.

<4> Fourth Embodiment A fourth embodiment will be described. In the fourth embodiment, a write driver will be described. The basic configuration and basic operation of the semiconductor memory device according to the fourth embodiment are the same as those of the semiconductor memory device according to the first to third embodiments described above. Therefore, the description about the matter demonstrated in the 1st-3rd embodiment mentioned above and the matter which can be easily guessed from the 1st-3rd embodiment mentioned above is abbreviate | omitted.

<4-1> Configuration <4-1-1> Sense Amplifier / Write Driver A sense amplifier / write driver 20b of the semiconductor memory device according to the fourth embodiment will be described with reference to FIG.

  As shown in FIG. 31, the sense amplifier / write driver 20b includes a sense circuit 200 and a write driver 230 for each set of global bit lines and global source lines. The write driver 230 is connected to the global bit line and the global source line, and is supplied with the same voltage as the power supply voltage VDD supplied to the preamplifier 210 and the sense amplifier 220.

<4-1-2> Memory Array and Write Driver The memory array 20a described in the first embodiment will be described in more detail.

  As shown in FIG. 32, the memory array 20a includes a plurality of sub memory areas (not shown). The sub memory area includes a memory cell array 20d, a first column selection circuit 20e, a second column selection circuit 20f, and a read current sink 20g. Here, for simplicity, a set of memory cell array 20d, first column selection circuit 20e, second column selection circuit 20f, and read current sink 20g will be described.

  The configuration of the memory cell array 20d is the same as that of the memory array 20a described with reference to FIG.

  The first column selection circuit 20e is connected to the memory cell array 20d via a plurality of bit lines BL_0 to BL_j-1. Then, the bit line BL is selected based on the first column selection signals CSL1_0 to CSL1_j−1 received from the column decoder 12. When the first column selection signals CSL1_0 to CSL1_j-1 are not distinguished, they are simply referred to as the first column selection signal CSL1.

  The first column selection circuit 20e includes a transistor 21 having one end connected to each bit line BL. A global bit line GBL is connected to the other end of the transistor 21, and column selection signals CSL1_0 to CSL1_j-1 are connected to the gate electrodes, respectively.

  The second column selection circuit 20f is connected to the memory cell array 20d via a plurality of source lines SL_0 to SL_j-1. Then, the source line SL is selected based on the second column selection signals CSL2_0 to CSL2_j−1 received from the column decoder 12. When the second column selection signals CSL2_0 to CSL2_j-1 are not distinguished, they are simply referred to as the second column selection signal CSL2.

  The second column selection circuit 20f includes a transistor 22 having one end connected to each source line SL. The global source line GSL is connected to the other end of the transistor 22, and column selection signals CSL2_0 to CSL2_j-1 are connected to the gate electrodes, respectively.

  The read current sink 20g is connected to the second column selection circuit 20f via the global source line GSL. The read current sink 20g sets the voltage of an arbitrary source line SL to VSS based on the control signal RDS received from the controller 16 and the column decoder 12.

  The write driver 230 is connected to the first column selection circuit 20e via the global bit line GBL. The write driver 230 is connected to the second column selection circuit 20f through the global source line GSL. The write driver 230 writes data by passing a current through the memory cell MC connected to the selected word line WL based on the control signal received from the controller 16 and the write data received via the IO circuit 17. .

<4-1-3> Write Driver A write driver 230 of the semiconductor memory device according to the fourth embodiment will be described with reference to FIG.

  As shown in FIG. 33, the write driver 230 includes NAND operation circuits 23a, 23b, 23c, 23f, 23g, and 23h, a NOR operation circuit 23d, an inverter 23e, PMOS transistors 23j, 23k, 23m, and 23n. NMOS transistors 23i, 23l, 23o, and 23p.

  The NAND operation circuit 23a receives the signal WEN_1 (first write enable signal) at the first input terminal, receives the signal WDATA (write data) at the second input terminal, and outputs the NAND operation result of the signal WEN_1 and the signal WDATA to the node. Output to N11. The signal WEN_1 is supplied from the controller 16. The signal WDATA is supplied from the IO circuit 17.

  The NAND operation circuit 23b receives the signal WEN_2 (second write enable signal) at the first input terminal, receives the signal WDATA at the second input terminal, and outputs the NAND operation result of the signal WEN_2 and the signal WDATA to the node N12. . The signal WEN_2 is supplied from the controller 16.

  The NAND operation circuit 23c receives the output signal of the NAND operation circuit 23a at the first input terminal, receives the output signal of the NAND operation circuit 23b at the second input terminal, and outputs the NAND operation result of the received signal to the node N13. .

  The NOR operation circuit 23d receives the signal WEN_1 at the first input terminal, receives the signal WEN_2 at the second input terminal, receives the signal PCHGOFF (precharge off signal) at the third input terminal, and receives the signal WEN_1 and the signal WEN_2. And the NOR operation result of the signal PCHGOFF is output to the node N16.

  Inverter 23e outputs a signal BWDATA obtained by inverting signal WDATA to node N17.

  The NAND operation circuit 23f receives the signal WEN_1 at the first input terminal, receives the signal BWDATA at the second input terminal, and outputs the NAND operation result of the signal WEN_1 and the signal BWDATA to the node N18.

  The NAND operation circuit 23g receives the signal WEN_2 at the first input terminal, receives the signal BWDATA at the second input terminal, and outputs the NAND operation result of the signal WEN_2 and the signal BWDATA to the node N19.

  The NAND operation circuit 23h receives the output signal of the NAND operation circuit 23f at the first input terminal, receives the output signal of the NAND operation circuit 23g at the second input terminal, and outputs the NAND operation result of the received signal to the node N20. .

  The PMOS transistor 23j supplies the voltage Vwrt1 to the node N21 (global bit line GBL) based on the output signal of the NAND operation circuit 23a. The voltage Vwrt1 is the voltage VDD used also in the sense circuit 200, and can be applied to the power supply wiring layout described in the first embodiment or the second embodiment. The PMOS transistor 23j is used as a transistor for charging the global bit line GBL.

  The PMOS transistor 23k supplies the voltage Vwrt2 to the node N21 based on the output signal of the NAND operation circuit 23b. The voltage Vwrt2 is a voltage dedicated to the write driver 230, for example. The voltage Vwrt2 has a higher impedance from the power supply pad than the voltage Vwrt1. Here, the level of the voltage value between the voltage Vwrt1 and the voltage Vwrt2 is not defined. However, regardless of the magnitude relationship between the voltage values of the voltage Vwrt1 and the voltage Vwrt2, the following effects can be achieved.

  The NMOS transistor 23l discharges the node N21 based on the output signal of the NAND operation circuit 23h.

  The NMOS transistor 23o discharges the node N21 based on the output signal of the NOR operation circuit 23d.

  The PMOS transistor 23m supplies the voltage Vwrt1 to the node N22 (global source line GSL) based on the output signal of the NAND operation circuit 23f. The PMOS transistor 23m is used as a transistor for charging the global source line GSL.

  The PMOS transistor 23n supplies the voltage Vwrt2 to the node N22 based on the output signal of the NAND operation circuit 23g.

  The NMOS transistor 23i discharges the node N22 based on the output signal of the NAND operation circuit 23c.

  The NMOS transistor 23p discharges the node N22 based on the output signal of the NOR operation circuit 23d.

<4-2> Operation Next, waveforms during a write operation of the semiconductor memory device according to the fourth embodiment will be described with reference to FIG. The write operation described here is not a write operation performed during the read operation described above but a general write operation. Of course, the present invention can also be applied to the write operation performed during the read operation described above. Further, the case where the voltages of the bit line BL and the source line SL are set to VSS while the cell writing operation and the reading operation are not performed will be described.

[Time T40] to [Time T41]
The row decoder 14 sets the voltage of the word line WL to the “L” level. Further, the column decoder 12 sets the voltages of the signals CSL1 and CSL2 to the “L” level. Further, the controller 16 sets the voltages of the signals WEN1 and WEN2 to the “L” level and sets the signal PCHGOFF (not shown) to the “L” level.

  Here, the operation of the write driver 230 will be described with reference to FIG.

  The NAND operation circuit 23a supplies an “H” level signal based on the received signal. Similarly, the NAND operation circuit 23b supplies an “H” level signal based on the received signal. The NAND operation circuit 23c supplies an “H” level signal based on the received signal. The NOR operation circuit 23d supplies an “H” level signal based on the received signal. The NAND operation circuit 23f supplies an “H” level signal based on the received signal. Similarly, the NAND operation circuit 23g supplies an “H” level signal based on the received signal. The NAND operation circuit 23h supplies an “L” level signal based on the received signal.

  As a result, the PMOS transistors 23j, 23k, 23m, and 23n and the NMOS transistors 23i and 23l are turned off, and the NMOS transistors 23o and 23p are turned on. As a result, the global bit line GBL and the global source line GSL are discharged.

[Time T41] to [Time T42]
The row decoder 14 sets the voltage of the selected word line WL to the “H” level according to the row address. Further, the column decoder 12 sets the voltages of the selection signal CSL1 and the selection signal CSL2 to the “H” level according to the column address.

[Time T42] to [Time T43]
The controller 16 sets the voltage of the signal WEN1 to the “H” level. At this time, the signal WDATA is also input. Note that when “1” data is written to the memory cell MC, the signal WDATA goes to the “H” level. In addition, when “0” data is written in the memory cell MC, the signal WDATA becomes “L” level.

  Here, the operation of the write driver 230 when the signal WDATA is at “H” level (when WDATA = 1) will be described.

  As shown in FIG. 33, the NAND operation circuit 23a supplies an “L” level signal based on the received signal. The NAND operation circuit 23b supplies an “H” level signal based on the received signal. The NAND operation circuit 23c supplies an “H” level signal based on the received signal. The NOR operation circuit 23d supplies an “L” level signal based on the received signal. The NAND operation circuit 23f supplies an “H” level signal based on the received signal. Similarly, the NAND operation circuit 23g supplies an “H” level signal based on the received signal. The NAND operation circuit 23h supplies an “L” level signal based on the received signal.

  As a result, the PMOS transistor 23j and the NMOS transistor 23i are turned on. As a result, the global bit line GBL is applied with the voltage Vwrt1, and the global source line GSL is discharged.

  Thereby, as shown in FIG. 34, the selected bit line BL is charged to the “H” level, and the source line SL is set to the “L” level.

  Since the voltage Vwrt1 is a voltage having a lower impedance from the power supply pad than the voltage Vwrt2, the selected bit line BL is charged at high speed.

  The operation of the write driver 230 when the signal WDATA is at the “L” level (when WDATA = 0) will be described.

  As shown in FIG. 33, the NAND operation circuit 23a supplies an “H” level signal based on the received signal. The NAND operation circuit 23b supplies an “H” level signal based on the received signal. The NAND operation circuit 23c supplies an “L” level signal based on the received signal. The NOR operation circuit 23d supplies an “L” level signal based on the received signal. The NAND operation circuit 23f supplies an “L” level signal based on the received signal. The NAND operation circuit 23g supplies an “H” level signal based on the received signal. The NAND operation circuit 23h supplies an “H” level signal based on the received signal.

  As a result, the PMOS transistor 23m and the NMOS transistor 23l are turned on. As a result, the voltage Vwrt1 is applied to the global source line GSL, and the global bit line GBL is discharged.

  Thereby, as shown in FIG. 34, the selected source line SL is charged to the “H” level, and the bit line BL is set to the “L” level.

  Note that the voltage Vwrt1 is a voltage whose impedance from the power supply pad is lower than that of the voltage Vwrt2, so that the selected source line SL is charged at high speed.

[Time T43] to [Time T44]
The controller 16 sets the voltage of the signal WEN1 to “L” level and the voltage of the signal WEN2 to “H” level.

  Here, the operation of the write driver 230 when the signal WDATA is at “H” level (when WDATA = 1) will be described.

  As shown in FIG. 33, the NAND operation circuit 23a supplies an “H” level signal based on the received signal. The NAND operation circuit 23b supplies an “L” level signal based on the received signal. The NAND operation circuit 23c supplies an “H” level signal based on the received signal. The NOR operation circuit 23d supplies an “L” level signal based on the received signal. The NAND operation circuit 23f supplies an “H” level signal based on the received signal. Similarly, the NAND operation circuit 23g supplies an “H” level signal based on the received signal. The NAND operation circuit 23h supplies an “L” level signal based on the received signal.

  As a result, the PMOS transistor 23k and the NMOS transistor 23i are turned on. As a result, the global bit line GBL is applied with the voltage Vwrt2, and the global source line GSL is discharged.

  Thereby, as shown in FIG. 34, the selected bit line BL is maintained at the “H” level, and the source line SL is set at the “L” level.

  The voltage Vwrt2 has a higher impedance from the power supply pad than the voltage Vwrt1, but the selected bit line BL has already been charged from time T42 to time T43. Therefore, even when the impedance from the power supply pad is switched to a voltage having a high impedance from time T43 to time T44, a voltage drop due to charging of the global source line GSL and the source line SL does not occur.

  The operation of the write driver 230 when the signal WDATA is at the “L” level (when WDATA = 0) will be described.

  As shown in FIG. 33, the NAND operation circuit 23a supplies an “H” level signal based on the received signal. The NAND operation circuit 23b supplies an “H” level signal based on the received signal. The NAND operation circuit 23c supplies an “L” level signal based on the received signal. The NOR operation circuit 23d supplies an “L” level signal based on the received signal. The NAND operation circuit 23f supplies an “H” level signal based on the received signal. The NAND operation circuit 23g supplies an “L” level signal based on the received signal. The NAND operation circuit 23h supplies an “H” level signal based on the received signal.

  As a result, the PMOS transistor 23n and the NMOS transistor 23l are turned on. As a result, the global source line GSL is applied with the voltage Vwrt2, and the global bit line GBL is discharged.

  Accordingly, as shown in FIG. 34, the selected source line SL is maintained at the “H” level, and the bit line BL is set at the “L” level.

  The voltage Vwrt2 is a voltage having a higher impedance from the power supply pad than the voltage Vwrt1, but the selected source line SL has already been charged from time T42 to time T43. Therefore, even when the impedance from the power supply pad is switched to a voltage having a high impedance from time T43 to time T44, a voltage drop due to charging of the global source line GSL and the source line SL does not occur.

[Time T44] to [Time T45]
The controller 16 ends the write operation by setting the voltage of the signal WEN2 to the “L” level. The NOR operation circuit 23d supplies an “L” level signal based on the received signal. As a result, the NMOS transistors 23o and 23p are turned on. As a result, the global bit line GBL and the global source line GSL are discharged.

<4-3> Effects <4-3-1> Overview According to the above-described embodiment, the first impedance of the power supply pad is relatively low in the first period in which the global bit line GBL or the global source line GSL is charged. Charging with power supply. Then, after charging the global bit line GBL or the global source line GSL, and during the write operation period, the potential of the global bit line GBL or the global source line GSL is maintained by the second power supply having a higher impedance from the power supply pad than the first power supply. To do. Thereby, the write operation can be performed appropriately.

<4-3-2> Comparative Example Here, a comparative example will be described in order to facilitate understanding of the effects of the above-described embodiment.

<4-3-2-1> Write Driver The write driver 230 of the semiconductor memory device according to the comparative example of the fourth embodiment will be described with reference to FIG.

  As shown in FIG. 35, the write driver 230 includes NAND operation circuits 24a and 24f, a NOR operation circuit 24d, inverters 24c, 24e, and 24h, PMOS transistors 24b and 24g, NMOS transistors 24i, 24j, 24k and 24l.

  The NAND operation circuit 24a receives the signal WEN (write enable signal) at the first input terminal, receives the signal WDATA at the second input terminal, and outputs the NAND operation result of the signal WEN and the signal WDATA to the node N32.

  The inverter 24c outputs a signal obtained by inverting the output signal of the NAND operation circuit 24a.

  The NOR operation circuit 24d receives the signal WEN at the first input terminal, receives the signal PCHGOFF at the second input terminal, and outputs the NOR operation result of the signal WEN and the signal PCHGOFF to the node N33.

  The inverter 24e outputs a signal BWDATA obtained by inverting the signal WDATA.

  The NAND operation circuit 24f receives the signal WEN at the first input terminal, receives the signal BWDATA at the second input terminal, and outputs the NAND operation result of the signal WEN and the signal BWDATA to the node N34.

  The inverter 24h outputs a signal obtained by inverting the output signal of the NAND operation circuit 24f.

  The PMOS transistor 24b supplies the voltage Vwrt to the node N35 (global bit line GBL) based on the output signal of the NAND operation circuit 24a. The voltage Vwrt corresponds to the voltage Vwrt2 in the above embodiment.

  The NMOS transistor 24i discharges the node N35 based on the output signal of the inverter 24h.

  The NMOS transistor 24k discharges the node N35 based on the output signal of the NOR operation circuit 24d.

  The PMOS transistor 24g supplies the voltage Vwrt to the node N36 (global source line GSL) based on the output signal of the NAND operation circuit 24f.

  The NMOS transistor 24j discharges the node N36 based on the output signal of the inverter 24c.

  The NMOS transistor 24l discharges the node N36 based on the output signal of the NOR operation circuit 24d.

<4-3-2-2> Operation Here, with reference to FIG. 36, a waveform during a write operation of the semiconductor memory device according to the comparative example of the fourth embodiment will be described. The case where the voltages of the bit line BL and the source line SL are set to VSS while the writing operation and the reading operation to the cell are not performed is described.

[Time T50] to [Time T51]
The row decoder 14 sets the voltage of the word line WL to the “L” level. Further, the column decoder 12 sets the voltages of the signals CSL1 and CSL2 to the “L” level. Further, the controller 16 sets the voltage of the signal WEN to the “L” level and sets the signal PCHGOFF (not shown) to the “L” level.

  Here, the operation of the write driver 230 will be described with reference to FIG.

  The NAND operation circuit 24a supplies an “H” level signal based on the received signal. The NOR operation circuit 24d supplies an “H” level signal based on the received signal. The NAND operation circuit 24f supplies an “H” level signal based on the received signal.

  As a result, the PMOS transistors 24b and 24g and the NMOS transistors 24i and 24j are turned off, and the NMOS transistors 24k and 24l are turned on.

  As a result, the global bit line GBL and the global source line GSL are discharged.

[Time T51] to [Time T52]
The row decoder 14 sets the voltage of the selected word line WL to the “H” level according to the row address. Further, the column decoder 12 sets the voltages of the selection signal CSL1 and the selection signal CSL2 to the “H” level according to the column address.

[Time T52] to [Time T53]
The controller 16 sets the voltage of the signal WEN to the “H” level. At this time, the signal WDATA is also input.

  Here, the operation of the write driver 230 when the signal WDATA is at “H” level (when WDATA = 1) will be described.

  As shown in FIG. 35, the NAND operation circuit 24a supplies an “L” level signal based on the received signal. The NOR operation circuit 24d supplies an “L” level signal based on the received signal. The NAND operation circuit 24f supplies an “H” level signal based on the received signal.

  As a result, the PMOS transistor 24b and the NMOS transistor 24j are turned on. As a result, the global bit line GBL is applied with the voltage Vwrt, and the global source line GSL is discharged.

  Incidentally, the global bit line GBL has a long wiring length and a large capacitance. Therefore, when the global bit line GBL is charged with the voltage Vwrt having the same impedance from the power supply pad as the voltage Vwrt2 described above, a voltage drop of the voltage Vwrt may occur due to a current peak. As a result, as shown in FIG. 36, there is a possibility that the charging time of the global bit line GBL becomes long. In that case, an effective write time to the memory cell MC is reduced, and a write failure may occur.

  The operation of the write driver 230 when the signal WDATA is at the “L” level (when WDATA = 0) will be described.

  As shown in FIG. 35, the NAND operation circuit 24a supplies an “H” level signal based on the received signal. The NOR operation circuit 24d supplies an “L” level signal based on the received signal. The NAND operation circuit 24f supplies an “L” level signal based on the received signal.

  As a result, the PMOS transistor 24g and the NMOS transistor 24i are turned on. As a result, the global source line GSL is applied with the voltage Vwrt, and the global bit line GBL is discharged.

  Even when the signal WDATA is at "L" level, the same problem as described above may occur.

<4-3-3> Summary However, according to the above-described embodiment, charging is performed using a voltage with low impedance from the power supply pad in the first period in which the global bit line GBL or the global source line GSL is charged. A power supply having a low impedance from the power supply pad is not affected by the voltage drop due to the charging current peak as described above in the first period. Therefore, the global bit line GBL or the global source line GSL can be charged at high speed. As a result, an increase in the write failure rate due to the voltage drop can be suppressed. Furthermore, as described in the first to third embodiments, power supply noise is not easily propagated to different banks. For this reason, it is possible to suppress malfunctions caused by power supply noise in other banks.

<4-4> Modified Example <4-4-1> Write Driver A write driver 230 of a semiconductor memory device according to a modified example of the fourth embodiment will be described with reference to FIG.

  As shown in FIG. 37, the write driver 230 includes NAND operation circuits 25a and 25f, a NOR operation circuit 25d, inverters 25c, 25e, and 25h, PMOS transistors 25b, 25g, 25m, and 25n, and an NMOS transistor. 25i, 25j, 25k, and 25l.

  The NAND operation circuit 25a receives the signal WEN at the first input terminal, receives the signal WDATA at the second input terminal, and outputs the NAND operation result of the signal WEN and the signal WDATA to the node N42. The signal WEN is supplied from the controller 16.

  The inverter 25c outputs a signal obtained by inverting the output signal of the NAND operation circuit 25a.

  The NOR operation circuit 25d receives the signal WEN at the first input terminal, receives the signal PCHGOFF at the second input terminal, and outputs the NOR operation result of the signal WEN and the signal PCHGOFF to the node N43.

  The inverter 25e outputs a signal BWDATA obtained by inverting the signal WDATA.

  The NAND operation circuit 25f receives the signal WEN at the first input terminal, receives the signal BWDATA at the second input terminal, and outputs the NAND operation result of the signal WEN and the signal BWDATA to the node N44.

  The inverter 25h outputs a signal obtained by inverting the output signal of the NAND operation circuit 25f.

  The PMOS transistor 25m supplies the voltage Vwrt1 to the node N47 based on the signal EN_1.

  The PMOS transistor 25n supplies the voltage Vwrt2 to the node N47 based on the signal EN_2.

  The PMOS transistor 25b supplies the voltage Vwrt1 or Vwrt2 to the node N45 (global bit line GBL) based on the output signal of the NAND operation circuit 25a.

  The NMOS transistor 25i discharges the node N45 based on the output signal of the inverter 25h.

  The NMOS transistor 25k discharges the node N45 based on the output signal of the NOR operation circuit 25d.

  The PMOS transistor 25g supplies the voltage Vwrt1 or Vwrt2 to the node N46 (global source line GSL) based on the output signal of the NAND operation circuit 25f.

  The NMOS transistor 25j discharges the node N46 based on the output signal of the inverter 25c.

  The NMOS transistor 25l discharges the node N46 based on the output signal of the NOR operation circuit 25d.

<4-4-2> Operation Here, with reference to FIG. 38, waveforms during a write operation of the semiconductor memory device according to the modification of the fourth embodiment will be described.

[Time T60] to [Time T61]
The row decoder 14 sets the voltage of the word line WL to the “L” level. Further, the column decoder 12 sets the voltages of the signals CSL1 and CSL2 to the “L” level. Further, the controller 16 sets the voltage of the signal WEN and PCHGOFF (not shown) to the “L” level, and sets the signals EN_1 and EN_2 to the “H” level.

  Here, the operation of the write driver 230 will be described with reference to FIG. A case will be described where the voltages of the bit line BL and the source line SL are set to VSS while the writing operation and the reading operation to the cell are not performed.

  The NAND operation circuit 25a supplies an “H” level signal based on the received signal. The NOR operation circuit 25d supplies an “H” level signal based on the received signal. The NAND operation circuit 25f supplies an “H” level signal based on the received signal.

  As a result, the PMOS transistors 25b, 25g, 25m, and 25n and the NMOS transistors 25i and 25j are turned off, and the NMOS transistors 25k and 25l are turned on. As a result, the global bit line GBL and the global source line GSL are discharged.

[Time T61] to [Time T62]
The row decoder 14 sets the voltage of the selected word line WL to the “H” level according to the row address. Further, the column decoder 12 sets the voltages of the selection signal CSL1 and the selection signal CSL2 to the “H” level according to the column address.

[Time T62] to [Time T63]
The controller 16 sets the voltage of the signal WEN to the “H” level and sets the signal EN_1 to the “L” level. At this time, the signal WDATA is also input.

  Here, the operation of the write driver 230 when the signal WDATA is at “H” level (when WDATA = 1) will be described.

  As shown in FIG. 37, the NAND operation circuit 25a supplies an “L” level signal based on the received signal. The NOR operation circuit 25d supplies an “L” level signal based on the received signal. The NAND operation circuit 25f supplies an “H” level signal based on the received signal.

  As a result, the PMOS transistors 25b and 25m and the NMOS transistor 25j are turned on. As a result, the global bit line GBL is applied with the voltage Vwrt1, and the global source line GSL is discharged.

  As a result, the global bit line GBL is charged at high speed as in the first embodiment.

  Further, the operation of the write driver 230 when the signal WDATA is “L” level (WDATA = 0) will be described.

  As shown in FIG. 37, the NAND operation circuit 25a supplies an “H” level signal based on the received signal. The NOR operation circuit 25d supplies an “L” level signal based on the received signal. The NAND operation circuit 25f supplies an “L” level signal based on the received signal.

  As a result, the PMOS transistors 25g and 25m and the NMOS transistor 25i are turned on. As a result, the voltage Vwrt1 is applied to the global source line GSL, and the global bit line GBL is discharged.

  As a result, the global source line GSL is charged at high speed as in the first embodiment.

[Time T62] to [Time T63]
The controller 16 sets the signal EN_1 to the “H” level and the signal EN_2 to the “L” level.

  Here, the operation of the write driver 230 when the signal WDATA is at “H” level (when WDATA = 1) will be described.

  As shown in FIG. 37, the NAND operation circuit 25a supplies an “L” level signal based on the received signal. The NOR operation circuit 25d supplies an “L” level signal based on the received signal. The NAND operation circuit 25f supplies an “H” level signal based on the received signal.

  As a result, the PMOS transistors 25b and 25n and the NMOS transistor 25j are turned on. As a result, the global bit line GBL is applied with the voltage Vwrt2, and the global source line GSL is discharged.

  As a result, the potential of the global bit line GBL is maintained as in the first embodiment.

  Further, the operation of the write driver 230 when the signal WDATA is “L” level (WDATA = 0) will be described.

  As shown in FIG. 37, the NAND operation circuit 25a supplies an “H” level signal based on the received signal. The NOR operation circuit 25d supplies an “L” level signal based on the received signal. The NAND operation circuit 25f supplies an “L” level signal based on the received signal.

  As a result, the PMOS transistors 25g and 25n and the NMOS transistor 25i are turned on. As a result, the global source line GSL is applied with the voltage Vwrt2, and the global bit line GBL is discharged.

  Thereby, the potential of the global source line GSL is maintained as in the first embodiment.

<4-4-3> Effect As described above, also in the write driver shown in FIG. 37, the same effect as in the fourth embodiment can be obtained.

  In the above-described embodiment, the case where the voltage of the bit line BL and the source line SL is set to VSS while the cell writing operation and the reading operation are not performed is described. The same effect can be obtained even when the SL voltage is floated.

  When the voltages of the bit line BL and the source line SL are floated, for example, a waveform diagram corresponding to FIG. 34 of the fourth embodiment is expressed as shown in FIG.

  That is, as shown in FIG. 39, after time T44, the voltages of the bit line BL of WDATA = "1" and the source line SL approach each other, and the values between the respective voltage levels from time T43 to time T44 are maintained. In addition, after time T44, the voltages of the bit line BL and the source line SL of WDATA = "0" are close to each other, and the values between the respective voltage levels from time T43 to time T44 are maintained.

  Similarly, also in FIG. 36 of the comparative example of the fourth embodiment, when the voltages of the bit line BL and the source line SL are floated, the bit line BL and the source of WDATA = “1” after time T54 as shown in FIG. The voltage of the line SL approaches and maintains the value between the respective voltage levels from time T53 to time T54. Further, after time T54, the voltages of the bit line BL and the source line SL of WDATA = “0” approach each other and maintain values between the respective voltage levels.

  Similarly, in FIG. 38 of the comparative example of the fourth embodiment, when the voltages of the bit line BL and the source line SL are floated, the bit line BL and the source of WDATA = “1” after time T64 as shown in FIG. The voltage of the line SL approaches and maintains a value between the respective voltage levels from time T63 to time T64. Further, after time T64, the voltages of the bit line BL and the source line SL of WDATA = “0” approach each other and maintain values between the respective voltage levels from time T63 to time T64.

<5> Others Note that the term to be connected in each of the above embodiments includes a state in which they are indirectly connected with something else such as a transistor or a resistor in between.

  Here, the MRAM that stores data using a magnetoresistive effect element (Magnetic Tunnel Junction (MTJ) element) as the variable resistance element has been described as an example. However, the present invention is not limited to this.

  For example, the present invention can also be applied to a semiconductor memory device having an element for storing data using resistance change, such as a resistance change type memory similar to MRAM, such as ReRAM and PCRAM.

  Regardless of whether it is a volatile memory or a non-volatile memory, data is stored by resistance change accompanying application of current or voltage, or data stored by converting resistance difference accompanying resistance change into current difference or voltage difference The present invention can be applied to a semiconductor memory device having an element that can read the data.

  In each of the embodiments described above, the bit line pair is referred to as a bit line BL and a source line SL for convenience, but is not limited thereto, and is referred to as, for example, a first bit line and a second bit line. May be.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining the disclosed constituent elements. For example, even if several constituent requirements are deleted from the disclosed constituent requirements, the invention can be extracted as long as a predetermined effect can be obtained.

DESCRIPTION OF SYMBOLS 1 ... Memory device 2 ... Memory controller 10a ... Core circuit 10b ... Peripheral circuit 11 ... Memory area 12 ... Column decoder 13 ... Word line driver 14 ... Row decoder 15 ... Command address input circuit 16 ... Controller 17 ... IO circuit 20a ... Memory array 20b ... sense amplifier / write driver 20c ... page buffer 20d ... memory cell array 20e ... first column selection circuit 20f ... second column selection circuit 20g ... read current sink 30 ... MTJ element 31 ... selection transistor 100a ... semiconductor substrate 100b ... Semiconductor substrate 101a ... impurity region 101b ... impurity region 101c ... impurity region 101d ... impurity region 102 ... insulating film 103 ... gate electrode 104 ... contact plug 105 ... contact plug 106 ... wiring layer 107 ... contact layer 108 ... wiring layer 109 ... insulating film 110 ... gate electrode 111 ... contact plug 112 ... wiring layer 113 ... contact plug 114 ... wiring layer 115 ... contact plug 116 ... wiring layer 200 ... sense circuit 210 ... preamplifier 220 ... sense amplifier 230 ... Write driver 300a ... Power supply circuit 300b ... Power supply circuit

Claims (5)

A power pad;
A first bank comprising a plurality of memory cells;
A second bank sandwiched between the power supply pad and the first bank and comprising a plurality of memory cells;
A first wiring connected to the power supply pad and supplying power to the second bank;
A second wiring connected to the power supply pad, passing over the second bank, supplying power to the first bank without supplying power to the second bank;
A semiconductor memory device. The semiconductor memory device according to claim 1, wherein the number of the second wirings is greater than the number of the first wirings. A first power supply circuit provided between the power pad and the first wiring;
A second power supply circuit provided between the power pad and the second wiring;
The semiconductor memory device according to claim 1, further comprising: A first power pad;
A second power pad;
A first bank comprising a plurality of memory cells;
A second bank sandwiched between the first and second power supply pads and the first bank and comprising a plurality of memory cells;
A first wiring connected to the first power supply pad and supplying power to the second bank;
A second wiring connected to the second power supply pad, passing over the second bank, supplying power to the first bank without supplying power to the second bank;
A semiconductor memory device. The semiconductor memory device according to claim 4, wherein the number of the second wirings is larger than the number of the first wirings.