JP2018157190A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and manufacturing method therefor, capable of achieving high controllability of a charging speed of a gate voltage by a gate resistance even at a low on-voltage.SOLUTION: The semiconductor device includes a first semiconductor layer 1, a second semiconductor layer 12, a third semiconductor layer 5, a fourth semiconductor layer 11, a trench 6, a fifth semiconductor layer 17, a sixth semiconductor layer 2, an emitter electrode 10, a collector electrode 14 and a gate electrode 8. The fifth semiconductor layer 17 is provided between the trenches 6 not provided with the second semiconductor layer 12. The plurality of fifth semiconductor layer 17 is provided, being spaced from the trench 6.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  In power converters for various uses such as industrial or electric vehicles, there is a great expectation for low power consumption of power semiconductor devices that play a central role. Among power semiconductor devices, IGBTs (Insulated Gate Bipolar Transistors) can achieve a low on-voltage due to the conductivity modulation effect, and can be easily controlled by voltage-driven gate control. It has been firmly established. In particular, a trench gate type IGBT in which a gate electrode is formed in a trench provided on the surface of a silicon (Si) wafer can increase the density (total channel length) of an inversion layer (channel) of electrons, so that the on-voltage is reduced. can do.

Conventionally, in a semiconductor device having a plurality of trench gates, a trench gate type IGBT having a floating p-type region is known (see, for example, Patent Documents 1 and 2). FIG. 21 is a cross-sectional view showing the structure of a conventional semiconductor device having a floating p-type region. As shown in FIG. 21, n ^- type on one surface layer of the silicon substrate with a drift layer 1 p ^- -type layer 4 is provided, n ⁺ -type buffer layer 3 is provided on the other surface layer, n ⁺ -type A p ⁺ type collector region 2 is provided on the surface layer of the buffer layer 3 (hereinafter, the side on which the p ⁻ type layer 4 is provided is the front surface of the silicon substrate, and the p ⁺ type collector region 2 is provided. The defined side is defined as the back side of the silicon substrate). From the front surface side of the silicon substrate, a plurality of trenches 6 penetrating the p ⁻ -type layer 4 in the depth direction and reaching the n ⁻ -type drift layer 1 are provided.

The p ⁻ type layer 4 is divided into a p ⁻ type base region 12 and a p ⁻ type floating region 13 by the trench 6. The p ⁻ -type base region 12 and the p ⁻ -type floating region 13 are repeatedly arranged, for example, alternately in the lateral direction in which the trenches 6 are arranged, and are linearly parallel to the trench 6 in the longitudinal direction perpendicular to the lateral direction. It extends. An n ⁺ emitter region 5 is selectively provided inside the p ⁻ type base region 12. Further, a p ⁺ type base region 11 is selectively provided adjacent to the n ⁺ emitter region 5 inside the p ⁻ type base region 12. An n-type inversion layer serving as a current path for the main current in the on state is formed in a portion of the p ⁻ -type base region 12 along the sidewall of the trench 6.

Emitter electrode 10 is conductively connected to p ⁺ -type base region 11 and n ⁺ emitter region 5 through a contact hole provided in interlayer insulating film 9. The collector electrode 14 is conductively connected to the p ⁺ collector layer 2 on the back side of the silicon substrate. The gate electrode 8 is provided inside the trench 6 via the gate insulating film 7.

In such a structure, since the p ⁻ type floating region 13 is not connected to the emitter electrode 10, holes injected into the n ⁻ type drift layer 1 from the p ⁺ collector layer 2 side in the on state are formed in the emitter electrode 10. It can be less discharged. As a result, holes are accumulated in the p ⁻ type floating region 13, the carrier concentration distribution of the n ⁻ type drift layer 1 is increased on the emitter side, and the ON voltage can be lowered without increasing the turn-off loss.

Further, in order to reduce the on-resistance of the IGBT, the n + emitter region is not formed in the semiconductor region 213b, the n hole barrier region 211 is joined in the p body region 203b, and the gate insulating film 205 and the n hole barrier region are joined. There is a technique for forming a p + emitter region 203b between the second and second electrodes 211 (see, for example, Patent Document 3). Further, in order to reduce the on-resistance of the IGBT, the float layer 18 of the base layer 11 has an N spaced apart from the one surface 10a of the semiconductor substrate 10 at a predetermined depth with respect to the one surface 10a of the semiconductor substrate 10. There is a technique for forming a mold hole stopper layer 19 (see, for example, Patent Document 4). In addition, there is a technique in which a floating p region is not disposed between adjacent trench gates where the N ⁺ -type emitter layer 9 is not disposed (see, for example, Patent Document 5). Further, in the trench IGBT, an N ⁺ emitter region 4 in which the P-type base region 3 is arranged in a staggered lattice pattern in order to reduce a switching loss, improve a turn-on characteristic, and obtain a high breakdown voltage while maintaining a low on-voltage. There is a technique in which a P-type base region is not disposed between trench gates (see, for example, Patent Document 6).

JP-A-5-243561 JP 2001-308327 A JP 2004-221370 A JP 2014-197702 A JP 2007-329270 A JP 2006-210547 A

M. Yamaguchi, 7 others, IEGT Design Criterion For Reducing EMI Noise (IEGT Design Criterion for Reducing EMI Noise) Proceedings of 2004 International Symposium on Power Semiconductors Power Semiconductor Devices & ICs), May 2004, p. 115-118 Y. Onozawa, 5 others, Development of the next generation 1200-- Trench-gate FS-IGBT featuring lower EMI noise and lower switching loss (Development of the next generation generation and lower switching loss), Proceedings of the 19th International Symposium on Power Semiconductor Devices and ICs (Proceedings of the 19th International Symposium on Power) r Semiconductor Devices & ICs), (Jeju Island), May 27, 2007 - 30 days, p. 13-16

Here, in the structure using the conventional p ⁻ type floating region 13, it is known that it is difficult to adjust the charging speed of the gate electrode 8 by the gate resistance, which makes it difficult to adjust the turn-off speed (for example, Non-patent documents 1 and 2).

In the structure not using the p ⁻ type floating region 13, the gate electrode 8 is charged by a current flowing through the gate resistance. Therefore, the gate voltage increase rate dVg / dt can be controlled by changing the gate resistance. it can.

However, in the structure using the mesa portion where the channel is not formed (the region of the adjacent trench 6) such as the p ⁻ type floating region 13, the holes are gathered in the mesa portion where the channel is not formed. When the displacement current flows to the gate electrode at the potential increase rate dV / dt, the gate electrode 8 is charged. For this reason, even if the gate resistance is increased, it is difficult to reduce the charging speed of the gate current.

  An object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device, which have good controllability of the charging speed of the gate voltage due to the gate resistance while the on-voltage is low, in order to eliminate the above-described problems caused by the prior art. And

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following characteristics. A second conductive type second semiconductor layer is selectively provided on one surface layer of the first conductive type first semiconductor layer. A third semiconductor layer of the first conductivity type is selectively provided inside the second semiconductor layer. A second conductive type fourth semiconductor layer connected to the second semiconductor layer is selectively provided adjacent to the third semiconductor layer inside the second semiconductor layer. A trench reaching the first semiconductor layer through the third semiconductor layer and the second semiconductor layer is provided. A first conductive type fifth semiconductor layer is selectively provided on one surface layer of the first semiconductor layer. A second conductive type sixth semiconductor layer is provided on the other surface layer of the first semiconductor layer. An emitter electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer and electrically insulated from the fifth semiconductor layer is provided. A collector electrode electrically connected to the sixth semiconductor layer is provided. A gate electrode is provided inside the trench via a gate insulating film. The fifth semiconductor layer is provided between the trenches where the second semiconductor layer is not provided.

  In the semiconductor device according to the present invention, a plurality of the fifth semiconductor layers are provided between the trenches that are separated from the trenches and are not provided with the second semiconductor layer.

  In the semiconductor device according to the present invention, in the above-described invention, the second semiconductor layer is separated from the trench in a region between the trenches not provided with the second semiconductor layer and is sandwiched by the fifth semiconductor layer. A conductive seventh semiconductor layer is provided.

  In the semiconductor device according to the present invention as set forth in the invention described above, the fifth semiconductor layer is provided over the entire one surface layer of the first semiconductor layer between the trenches where the second semiconductor layer is not provided. It has been.

  In the semiconductor device according to the present invention, in the above-described invention, the second semiconductor layer is separated from the trench between the trenches not provided with the second semiconductor layer, and one surface is in contact with the fifth semiconductor layer. A conductive seventh semiconductor layer is provided.

  In the semiconductor device according to the present invention, in the above-described invention, one fifth semiconductor layer is provided between the trenches separated from the trench and not provided with the second semiconductor layer.

  Moreover, in the semiconductor device according to the present invention, in the above-described invention, the trench is not provided with the second semiconductor layer, and is separated from the trench, and one surface is in contact with the fifth semiconductor layer, A seventh conductivity type seventh semiconductor layer having a narrower width than the fifth semiconductor layer is provided.

  In the semiconductor device according to the present invention, a plurality of the fifth semiconductor layers are provided between the trenches that are connected to the trenches and are not provided with the second semiconductor layer.

  In the semiconductor device according to the present invention, in the above-described invention, the second semiconductor layer is separated from the trench between the trenches not provided with the second semiconductor layer, and the second semiconductor layer is sandwiched between the fifth semiconductor layers. A conductive seventh semiconductor layer is provided.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device manufacturing method according to the present invention has the following characteristics. First, a first step of selectively forming a second semiconductor layer of the second conductivity type on one surface layer of the first semiconductor layer of the first conductivity type is performed. Next, a second step of selectively forming a third semiconductor layer of the first conductivity type inside the second semiconductor layer is performed. Next, a third step of selectively forming a second conductive type fourth semiconductor layer connected to the second semiconductor layer in the second semiconductor layer adjacent to the third semiconductor layer is performed. . Next, a fourth step of selectively forming a first conductivity type fifth semiconductor layer on one surface layer of the first semiconductor layer is performed. Next, a fifth step of forming a trench that reaches the first semiconductor layer through the third semiconductor layer and the second semiconductor layer is performed. Next, a sixth step of forming a second conductivity type sixth semiconductor layer on the other surface layer of the first semiconductor layer is performed. Next, a seventh step of forming an emitter electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer and electrically insulated from the fifth semiconductor layer is performed. Next, an eighth step of forming a collector electrode electrically connected to the sixth semiconductor layer is performed. Next, a ninth step of forming a gate electrode inside the trench through a gate insulating film is performed. In the fourth step, the fifth semiconductor layer is formed between the trenches not provided with the second semiconductor layer.

  In the semiconductor device according to the present invention as set forth in the invention described above, the fifth semiconductor layer is separated from the trench by a distance of 2 μm or more and 6 μm or less.

  In the semiconductor device according to the present invention, the distance between the trench and the seventh semiconductor layer is 1 μm or more larger than the distance between the trench and the fifth semiconductor layer.

  The semiconductor device according to the present invention is characterized in that, in the above-described invention, the seventh semiconductor layer is separated from the trench by a distance of 2 μm or more and 4 μm or less.

  In the semiconductor device according to the present invention as set forth in the invention described above, the width of the fifth semiconductor layer is 2 μm or more.

According to the above-described invention, the n ⁺ type floating region (first conductivity type fifth semiconductor layer) is provided in the mesa portion where the channel is not provided. As a result, the potential of the hole accumulation layer in the mesa portion where the channel is not provided becomes high, and the potential becomes high before the channel is formed. Therefore, when the channel is formed, holes are less likely to gather, the potential increase rate dV / dt is reduced, and the gate electrode is not charged, thereby improving the turn-on controllability.

  According to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, there is an effect that the controllability of the charging speed of the gate voltage by the gate resistance is good while the on-voltage is low.

1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment; FIG. 3 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment (part 1); FIG. 3 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment (part 2); FIG. 3 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment (part 3); FIG. 6 is a sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment (part 4); 6 is a cross-sectional view showing a structure of a semiconductor device according to a second embodiment; FIG. FIG. 6 is a cross-sectional view illustrating a structure of a semiconductor device according to a third embodiment. FIG. 6 is a sectional view showing a structure of a semiconductor device according to a fourth embodiment. FIG. 9 is a cross-sectional view showing a structure of a semiconductor device according to a fifth embodiment. FIG. 9 is a cross-sectional view showing a structure of a semiconductor device according to a sixth embodiment. FIG. 9 is a cross-sectional view illustrating a structure of a semiconductor device according to a seventh embodiment. FIG. 10 is a sectional view showing a structure of a semiconductor device according to an eighth embodiment; It is a graph which shows the gate resistance dependence of the turn-on waveform of the conventional semiconductor device. 3 is a graph showing the gate resistance dependence of the turn-on waveform of the semiconductor device according to the first embodiment; 6 is a graph showing the gate resistance dependence of turn-on dI / dt of the semiconductor device according to the first embodiment and the conventional semiconductor device. 6 is a graph showing a relationship between a distance d1 of the semiconductor device according to the first embodiment, dI / dt, and BVces. 4 is a graph showing a relationship between an n ⁺ type floating region w1 of the semiconductor device according to the first embodiment and dI / dt. 12 is a graph showing the relationship between the distance d1, the distance d2 and dI / dt of the semiconductor device according to the second embodiment (part 1); It is the graph which shows the relationship between distance d1, distance d2, and BVces of the semiconductor device concerning Embodiment 2 (the 1). 11 is a graph showing a relationship between distance d1, distance d2 and dI / dt of the semiconductor device according to the second embodiment (part 2); 12 is a graph showing the relationship between the distance d1 and distance d2 of the semiconductor device according to the second embodiment and BVces (part 2); 14 is a graph showing the relationship between the distance d2 of the semiconductor device according to the fourth embodiment, dI / dt, and BVces. 24 is a graph showing the relationship between the distance d5 of the semiconductor device according to the eighth embodiment and dI / dt. 19 is a graph showing a relationship between a distance d5 of a semiconductor device according to an eighth embodiment and BVces. It is sectional drawing which shows the structure of the semiconductor device which has the conventional floating p-type area | region.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. When the notations of n and p including + and − are the same, it indicates that the concentrations are close to each other, and the concentrations are not necessarily equal. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment 1)
The semiconductor device according to the present invention will be described by taking an IGBT having a floating p-type region as an example. FIG. 1 is a cross-sectional view illustrating the structure of the semiconductor device according to the first embodiment. FIG. 1 shows only two unit cells (functional units of the element), and other unit cells adjacent to these are omitted. The IGBT shown in FIG. 1 has a MOS (Metal Oxide Semiconductor) on the front surface (surface on the p ⁺ -type base layer 11 side) side of a semiconductor substrate (silicon substrate: semiconductor chip) made of silicon that becomes the n ⁻ -type drift region 1. ) IGBT with a gate.

As shown in FIG. 1, the semiconductor device according to the first embodiment has a p ⁻ type on the surface layer of the main surface (front surface) of an n ⁻ type drift region (first semiconductor layer of the first conductivity type) 1. A base region (second conductivity type second semiconductor layer) 12 is selectively provided. An n ⁺ type buffer layer 3 is provided on the back surface side of the n ⁻ type drift region 1, and a p ⁺ type collector region (second conductivity type sixth semiconductor layer) 2 is provided on the surface of the n ⁺ type buffer layer 3. Yes.

A p ⁺ type base region (second conductivity type fourth semiconductor layer) 11 and an n ⁺ type emitter region (first conductivity type third semiconductor layer) 5 are selectively provided in the p ⁻ type base region 12. Provided. n ⁺ -type emitter region 5 is disposed on the outer periphery of the p ⁺ -type base region 11, p ⁺ -type base region 11 may be deeper than the n ⁺ -type emitter region 5. In a region adjacent to the n ⁺ -type emitter region 5, a trench 6 that reaches the n ⁻ -type drift region 1 through the p ⁻ -type base region 12 in the depth direction (collector electrode 14 side) is provided. For example, a gate electrode 8 made of polysilicon is buried in the trench 6 through a gate insulating film 7 which is a thermal oxide film.

An interlayer insulating film 9 for insulating from the emitter electrode 10 is provided on the gate electrode 8. Emitter electrode 10 is electrically connected to n ⁺ -type emitter region 5, p ⁺ -type base region 11 and p ⁻ -type base region 12 through a contact hole provided in interlayer insulating film 9. The emitter electrode 10 may be grounded or a negative voltage may be applied. A collector electrode 14 is provided on the back side of the semiconductor device. A positive voltage is applied to the collector electrode 14.

A plurality of trenches 6 are provided on the front surface side of the n ⁻ -type drift region to form a mesa portion 15 provided with a channel and a mesa portion 16 provided with no channel. In the mesa portion 15 where the channel is provided, a p ⁻ type base region 12, a p ⁺ type base region 11 and an n ⁺ type emitter region 5 having a higher impurity concentration than the p ⁻ type base region 12 are provided. Therefore, a channel is formed in p ⁻ type base region 12 when the semiconductor device is in the on state.

An n ⁺ -type floating region (first conductivity type fifth semiconductor layer) 17 is provided in the mesa portion 16 where no channel is provided. The n ⁺ type floating region 17 is in an electrically floating state. Specifically, n ⁺ type floating region 17 is electrically insulated from emitter electrode 10 by gate insulating film 7 and interlayer insulating film 9 covering the surface. Further, n ⁺ -type floating region 17 the n ^- by the pn junction between the type drift layer 1 n ^- -type drift layer 1 and electrically insulated.

A plurality of n ⁺ -type floating regions 17 are provided apart from each other in the mesa portion 16 where no channel is provided (two in the example of FIG. 1). The n ⁺ type floating region 17 is provided at a distance d1 from the side wall of the trench 6 and is preferably closer to the trench 6 and smaller in the distance d1. The impurity concentration, depth, and width of the n ⁺ type floating region 17 may be the same as those of the n ⁺ type emitter region 5.

  FIG. 16 is a graph showing the relationship between the distance d1 of the semiconductor device according to the first embodiment, dI / dt, and BVces. In FIG. 16, the horizontal axis indicates the distance d1, and the unit is μm. The left vertical axis indicates turn-on dI / dt, the unit is A / μs, the right vertical axis indicates BVces, and the unit is V. BVces (Collector-Emitter Breakdown Voltage) indicates the breakdown voltage of the semiconductor device.

As shown in FIG. 16, when the distance d1 is 4 μm, the turn-on dI / dt is minimum, and when the distance d1 is 2 μm or more and 6 μm or less (region S1 in FIG. 16), the turn-on dI / dt is 700 A with a breakdown voltage of 650 V or more. / Μs or less. For this reason, it is preferable that the n ⁺ -type floating region 17 is provided 2 μm or more and 6 μm or less away from the sidewall of the trench 6.

FIG. 17 is a graph showing the relationship between the width w1 of the n ⁺ type floating region of the semiconductor device according to the first embodiment and dI / dt. In FIG. 17, the horizontal axis indicates the width w1 (see FIG. 1) of the n ⁺ type floating region 17, and the unit is μm. The vertical axis indicates turn-on dI / dt, and the unit is A / μs. As shown in FIG. 17, the larger the width w1, the lower the dI / dt. For this reason, the larger the width w1, the better. Specifically, the width w1 is preferably 2 μm or more (region S2 in FIG. 17).

Here, as described above, holes injected into the n ⁻ -type drift layer 1 from the collector electrode 14 side in the on state accumulate in the mesa portion 16 where no channel is provided. That is, holes injected into the n ⁻ type drift layer 1 from the collector electrode 14 side are not easily discharged to the emitter electrode 10. Thereby, the carrier concentration distribution of the n ⁻ type drift layer 1 is increased. In the present invention, the n ⁺ type floating region 17 electrically disconnects the surface of the mesa portion 16 where no channel is provided and the hole accumulation layer on the sidewall of the trench 6. As a result, the potential of the hole accumulation layer of the mesa portion 16 where no channel is provided is high, and the potential is high before the channel is formed. For this reason, when a channel is formed, holes are less likely to gather, the rate of potential increase dV / dt is reduced, and the turn-on controllability is improved.

In the first embodiment, the p ⁻ type floating region is not provided in the mesa portion 16 where no channel is provided. When the interval between the trenches 6 is sufficiently narrow, the electric field distribution becomes flat and the electric field concentration at the bottom of the trench 6 is relaxed, so that a predetermined breakdown voltage can be obtained even without the p ⁻ type floating region.

(Method for Manufacturing Semiconductor Device According to First Embodiment)
Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. 2-5 is sectional drawing which shows the state in the middle of manufacture of IGBT concerning Embodiment. First, an n ⁻ type semiconductor substrate to be the n ⁻ type drift layer 1 is prepared. The material of the n ⁻ type semiconductor substrate may be silicon or silicon carbide (SiC). The n ⁻ type semiconductor substrate may be an n ⁻ type semiconductor layer obtained by epitaxially growing an n ⁻ type semiconductor layer on the front surface of the n type semiconductor substrate. Hereinafter, a case where the n ⁻ type semiconductor substrate is a silicon wafer will be described as an example.

Next, the p ⁻ type base region 12 is selectively formed on the front surface side of the n ⁻ type drift layer 1 by photolithography and ion implantation. Next, the p ⁺ type base region 11 is selectively formed on the surface of the p ⁻ type base region 12 by photolithography and ion implantation. Next, n ⁺ -type emitter region 5 is selectively formed on the surface of p ⁺ -type base region 11 by photolithography and ion implantation, and the front surface side of n ⁻ -type drift layer 1, p ⁻ -type base region is formed. An n ⁺ type floating region 17 is selectively formed in a region where 12 is not formed. The state so far is described in FIG.

Next, the front surface of n ⁻ type drift layer 1 is thermally oxidized to form a field oxide film that covers the front surface of n ⁻ type drift layer 1. Next, a trench 6 that reaches the n ⁻ type drift region 1 through the n ⁺ type emitter region 5 and the p ⁻ type base region 12 is formed by photolithography and etching. The trench 6 is, for example, a striped layout extending in a direction (depth direction in FIG. 1) perpendicular to the direction in which the trenches 6 are arranged (lateral direction in FIG. 1) when viewed from the front surface of the n ⁻ type drift layer 1. Is arranged.

Next, the gate insulating film 7 is formed along the front surface of the n ⁻ type drift layer 1 and the inner wall of the trench 6 by, for example, thermal oxidation. Next, a polysilicon (poly-Si) layer is formed on the front surface of the n ⁻ -type drift layer 1 so as to fill the inside of the trench 6. Next, the polysilicon layer is etched back, for example, to leave a portion to be the gate electrode 8 in the trench 6.

These p ⁻ type base region 12, n ⁺ type emitter region 5, p ⁺ type base region 11, trench 6, gate insulating film 7 and gate electrode 8 constitute a trench gate structure MOS gate. After the formation of the gate electrode 8, the p ⁻ type base region 12, the n ⁺ type emitter region 5, the p ⁺ type base region 11, and the n ⁺ type floating region 17 may be formed. The state so far is described in FIG.

Next, an interlayer insulating film 9 is formed on the front surface of the n ⁻ -type drift layer 1 so as to cover the gate electrode 8. Next, the interlayer insulating film 9 is patterned to form a plurality of contact holes that penetrate the interlayer insulating film 9 in the depth direction. The depth direction is a direction from the front surface to the back surface of the n ⁻ -type drift layer 1. In the contact hole, the n ⁺ type emitter region 5 and the p ⁺ type base region 11 are exposed.

Next, an emitter electrode 10 is formed on the interlayer insulating film 9 so as to fill the contact hole. Emitter electrode 10 is electrically connected to p ⁻ type base region 12, n ⁺ type emitter region 5 and p ⁺ type base region 11. The state so far is described in FIG.

Next, the n ⁻ -type drift layer 1 is ground from the back side (back grinding), and is ground to the position of the product thickness used as a semiconductor device. Next, the n ⁺ type buffer layer 3 is formed on the back surface side of the n ⁻ type drift layer 1 by photolithography and ion implantation. Next, p ⁺ type collector region 2 is formed on the surface of n ⁺ type buffer layer 3 by photolithography and ion implantation. The state so far is described in FIG.

Next, the collector electrode 14 is formed on the entire surface of the p ⁺ -type collector region 2. Thereafter, the semiconductor wafer is cut (diced) into chips and separated into individual pieces, whereby the IGBT chip (semiconductor chip) shown in FIG. 1 is completed.

As described above, according to the semiconductor device according to the first embodiment, the n ⁺ type floating region is provided in the mesa portion where the channel is not provided. As a result, the potential of the hole accumulation layer in the mesa portion where the channel is not provided becomes high, and the potential becomes high before the channel is formed. Therefore, when the channel is formed, holes are less likely to gather, the potential increase rate dV / dt is reduced, and the gate electrode is not charged, thereby improving the turn-on controllability.

  In addition, according to the semiconductor device according to the first embodiment, since the mesa portion without the channel is formed, the on-voltage can be lowered without increasing the turn-off loss so much.

(Embodiment 2)
FIG. 6 is a cross-sectional view illustrating the structure of the semiconductor device according to the second embodiment. As shown in FIG. 6, the semiconductor device according to the second embodiment has a structure in which a p ⁻ -type floating region (second conductivity type seventh semiconductor layer) 13 is added to the semiconductor device according to the first embodiment. is there.

The p ⁻ type floating region 13 is provided in the mesa portion 16 where no channel is provided. The p ⁻ type floating region 13 is in an electrically floating state. Specifically, p ⁻ type floating region 13 is electrically insulated from emitter electrode 10 by gate insulating film 7 and interlayer insulating film 9 covering the surface. Further, p ^- -type floating region 13 the n ^- by the pn junction between the type drift layer 1 n ^- -type drift layer 1 and electrically insulated. The p ⁻ type base region 12 and the p ⁻ type floating region 13 are combined to form the p ⁻ type layer 4. The impurity concentration and depth of the p ⁻ type floating region 13 may be the same as that of the p ⁻ type base region 12.

The p ⁻ type floating region 13 is disposed between the center of the mesa portion 16 and the n ⁺ type floating region 17 and is separated from the sidewall of the trench 6 by a distance d2. The interface between the p ⁻ type floating region 13 and the n ⁻ type drift layer 1 in the lateral direction (the direction in which the trenches 6 are arranged) is closer to the trench 6 than the lateral interface between the n ⁺ type floating region 17 and the n ⁻ type drift layer 1. It is preferable that d2> d1. That is, it is preferable that the n ⁺ type floating region 17 is not provided inside the p ⁻ type floating region 13. When the n ⁺ type floating region 17 is provided inside the p ⁻ type floating region 13, the n ⁺ type floating region 17 electrically connects the surface of the mesa portion 16 where no channel is provided and the hole accumulation layer on the side wall of the trench 6. This is because the potential of the hole accumulation layer of the mesa portion 16 where the channel cannot be provided cannot be increased.

18A and 18C are graphs showing the relationship between the distance d1 and the distance d2 of the semiconductor device according to the second embodiment and dI / dt. 18A and 18C, the horizontal axis indicates the distance d2, and the unit is μm. The vertical axis indicates turn-on dI / dt, and the unit is A / μs. FIG. 18A shows the case where the distance d1 = 2 μm, and FIG. 18C shows the case where the distance d1 = 4 μm. 18A shows the case where the width w1 of the n ⁺ type floating region 17 is 1 μm, 3 μm, 5 μm and 9 μm, and FIG. 18C shows the case where the width w1 of the n ⁺ type floating region 17 is 1 μm, 3 μm and 9 μm. Show.

18B and 18D are graphs showing the relationship between the distance d1 and the distance d2 of the semiconductor device according to the second embodiment and BVces. 18B and 18D, the horizontal axis indicates the distance d2, and the unit is μm. The vertical axis indicates BVces, and the unit is V. FIG. 18B shows the case where the distance d1 = 2 μm, and FIG. 18D shows the case where the distance d1 = 4 μm. 18B shows the case where the width w1 of the n ⁺ type floating region 17 is 1 μm, 3 μm, 5 μm, and 9 μm, and FIG. 18D shows the case where the width w1 of the n ⁺ type floating region 17 is 1 μm, 3 μm, and 9 μm. Show.

As shown in FIGS. 18A and 18C, when the distance d2 is larger than the distance d1 (d2> 2 μm in FIG. 18A, d2> 4 μm in FIG. 18C), the turn-on dI / dt is smaller than when the distance d2 is equal to or less than the distance d1. It is low. On the other hand, as shown in FIGS. 18B and 18D, the breakdown voltage decreases as the distance d2 increases. Therefore, in order to achieve both low turn-on dI / dt and breakdown voltage, the distance d2 is about 1 μm larger than the distance d1 (regions S3, S4, S5, and S6 in FIGS. 18A, 18B, 18C, and 18D), that is, The distance d2 between the trench 6 and the p ⁻ type floating region 13 is preferably about 1 μm larger than the distance d1 between the trench 6 and the n ⁺ type floating region 17.

(Method for Manufacturing Semiconductor Device According to Second Embodiment)
Next, a method for manufacturing the semiconductor device according to the second embodiment will be described. In the second embodiment, in FIG. 2 of the first embodiment, the p ⁻ type base region 12 is selectively formed on the front surface side of the n ⁻ type drift layer 1 by photolithography and ion implantation. , P ⁻ type floating region 13 is selectively formed. The other steps are the same as those in Embodiment Mode 1 to complete the semiconductor device shown in FIG.

As described above, according to the second embodiment, as in the first embodiment, dV / dt is reduced and the controllability of turn-on is improved. Further, p ^- by providing the type floating region, near the bottom of the trench, p ^- can form a pn junction between the type drift layer ^- type floating region and n. Thus, by forming the pn junction, it is possible to prevent a high electric field from being applied to the gate insulating film at the bottom of the trench. For this reason, the withstand voltage of the semiconductor device can be increased.

(Embodiment 3)
FIG. 7 is a cross-sectional view illustrating the structure of the semiconductor device according to the third embodiment. As shown in FIG. 7, the semiconductor device according to the third embodiment has a structure in which the width of the n ⁺ -type floating region 17 is wider than that of the semiconductor device according to the first embodiment.

The n ⁺ type floating region 17 is provided on the entire front surface of the n ⁻ type drift layer 1 of the mesa portion 16 where no channel is provided. Therefore, the n ⁺ type floating region 17 is in contact with the sidewall of the trench 6. The impurity concentration and depth of the n ⁺ type floating region 17 may be the same as in the first embodiment.

(Method for Manufacturing Semiconductor Device According to Third Embodiment)
Next, a method for manufacturing the semiconductor device according to the third embodiment will be described. In Figure 2 of the first embodiment in the third embodiment, by photolithography and ion implantation, n ^- the front surface side of the type drift layer 1, when forming the n ⁺ -type floating region 17, n ⁺ -type floating Region 17 is formed on the entire front surface of n ⁻ type drift layer 1 of mesa portion 16. The other steps are the same as those in Embodiment Mode 1 to complete the semiconductor device shown in FIG.

As described above, according to the third embodiment, as in the first embodiment, dV / dt is reduced and the controllability of turn-on is improved. As described above, the characteristics are better when the n ⁺ type floating region and the trench are spaced apart. For this reason, although dV / dt becomes smaller in the third embodiment than in the conventional structure, dV / dt becomes larger than that in the first embodiment.

(Embodiment 4)
FIG. 8 is a sectional view showing the structure of the semiconductor device according to the fourth embodiment. As shown in FIG. 8, the semiconductor device according to the fourth embodiment has a structure in which a p ⁻ type floating region 13 is added to the semiconductor device according to the third embodiment.

The p ⁻ type floating region 13 is provided in the mesa portion 16 where no channel is provided, as in the second embodiment. The p ⁻ type floating region 13 is disposed below the n ⁺ type floating region 17 in the depth direction, and the upper surface is in contact with the n ⁺ type floating region 17. The impurity concentration, depth, and width of the p ⁻ type floating region 13 may be the same as that of the p ⁻ type base region 12.

The p ⁻ type floating region 13 is provided at a distance d2 from the side wall of the trench 6. When the p ⁻ type floating region 13 is in contact with the side wall of the trench 6, the n ⁺ type floating region 17 cannot electrically cut the surface of the mesa portion 16 where no channel is provided and the hole accumulation layer on the side wall of the trench 6, This is because the potential of the hole accumulation layer of the mesa portion 16 where no channel is provided cannot be increased.

  FIG. 19 is a graph showing the relationship between the distance d2 of the semiconductor device according to the fourth embodiment, dI / dt, and BVdss. In FIG. 19, the horizontal axis indicates the distance d2, and the unit is μm. The left vertical axis indicates turn-on dI / dt, the unit is A / μs, the right vertical axis indicates BVces, and the unit is V. BVces (Collector-Emitter Breakdown Voltage) indicates the breakdown voltage of the semiconductor device.

As shown in FIG. 19, the smaller the distance d2, the lower the turn-on dI / dt. When the distance d2 is 2 μm or more and 4 μm or less, the turn-on dI / dt is 900 A with a breakdown voltage of 1000 V or more (region S7 in FIG. 19). / Μs or less (region S8 in FIG. 19). For this reason, the p ⁻ type floating region 13 is preferably provided 2 μm or more and 4 μm or less away from the sidewall of the trench 6.

(Method for Manufacturing Semiconductor Device According to Fourth Embodiment)
Next, a method for manufacturing the semiconductor device according to the fourth embodiment will be described. In the fourth embodiment, when the p ⁻ type base region 12 is selectively formed on the front surface side of the n ⁻ type drift layer 1 by photolithography and ion implantation in FIG. 2 of the first embodiment, , P ⁻ type floating region 13 is formed. Thereafter, in the same manner as in the third embodiment, n ⁺ type floating region 17 is formed on n ⁻ type drift layer 1 of mesa portion 16 on the front surface side of n ⁻ type drift layer 1 by photolithography and ion implantation. It is formed on the entire front surface. The other steps are the same as those in Embodiment Mode 1 to complete the semiconductor device shown in FIG.

As described above, according to the fourth embodiment, as in the first embodiment, dV / dt is reduced and the controllability of turn-on is improved. Since the n ⁺ type floating region is in contact with the trench, dV / dt is the same as in the third embodiment. Further, since the p ⁻ type floating region is provided, it is possible to prevent a high electric field from being applied to the gate insulating film at the bottom of the trench as in the second embodiment.

(Embodiment 5)
FIG. 9 is a cross-sectional view illustrating the structure of the semiconductor device according to the fifth embodiment. As shown in FIG. 9, the semiconductor device according to the fifth embodiment is different from the semiconductor device according to the first embodiment in that one n ⁺ -type floating region 17 is provided in the mesa portion 16 where no channel is provided. In this structure, the width of the n ⁺ type floating region 17 is widened.

The n ⁺ -type floating region 17 is provided on the front surface of the n ⁻ -type drift layer 1 of the mesa portion 16 where no channel is provided, and is separated from the side wall of the trench 6 by a distance d3. In order to divide a wide area of the front surface of the n ⁻ type drift layer 1 between the trenches 6 with one n ⁺ type floating region 17, a certain amount of area is required. It is wider than the n ⁺ type floating region 17. The impurity concentration and depth of the n ⁺ type floating region 17 may be the same as those in the first embodiment.

The relationship between the distance d3 of the semiconductor device according to the fifth embodiment and dI / dt and BVces is the same as the relationship between the distance d1 of the semiconductor device according to the first embodiment and dI / dt and BVces. . For this reason, also in the fifth embodiment, the n ⁺ -type floating region 17 is preferably provided 2 μm or more and 6 μm or less away from the sidewall of the trench 6, as in the first embodiment.

(Method for Manufacturing Semiconductor Device According to Embodiment 5)
Next, a method for manufacturing the semiconductor device according to the fifth embodiment will be described. In Figure 2 of the first embodiment in the fifth embodiment, by photolithography and ion implantation, n ^- the front surface side of the type drift layer 1, when forming the n ⁺ -type floating region 17, n ⁺ -type floating One region 17 is formed on the front surface of the n ⁻ -type drift layer 1 of the mesa portion 16 so as not to contact the sidewall of the trench 6. Other processes are the same as those in Embodiment Mode 1, so that the semiconductor device shown in FIG. 9 is completed.

As described above, according to the fifth embodiment, as in the first embodiment, dV / dt is reduced and the controllability of turn-on is improved. In the fifth embodiment, since there is a gap between the n ⁺ type floating region and the trench, dV / dt is approximately the same as in the first embodiment.

(Embodiment 6)
FIG. 10 is a cross-sectional view illustrating the structure of the semiconductor device according to the sixth embodiment. As shown in FIG. 10, the semiconductor device according to the sixth embodiment has a structure in which a p ⁻ type floating region 13 is added to the semiconductor device according to the fifth embodiment.

The p ⁻ type floating region 13 is provided in the mesa portion 16 where no channel is provided, as in the second embodiment. The impurity concentration and depth of the p ⁻ type floating region 13 may be the same as that of the p ⁻ type base region 12.

The p ⁻ type floating region 13 is provided at a distance d4 from the side wall of the trench 6, and is provided with a width narrower than the n ⁺ type floating region 17 from the center of the mesa portion 16. p ^- it is separated from the side wall of the trench 6 than the interface lateral -type drift layer 1 ^- lateral n type floating region 13 ^- an interface between the type drift layer 1, n of the n ⁺ -type floating region 17 , D4> d3 is preferable. This is to prevent the potential of the hole accumulation layer of the mesa portion 16 where no channel is provided from becoming high, as in the second embodiment.

The relationship between the distance d3 and distance d4 of the semiconductor device according to the sixth embodiment and dI / dt is the same as the relationship between the distance d1 and distance d2 of the semiconductor device according to the second embodiment and dI / dt. become. Furthermore, the relationship between the distance d3 and distance d4 of the semiconductor device according to the sixth embodiment and BVces is the same as the relationship between the distance d1 and distance d2 of the semiconductor device according to the second embodiment and BVces. Therefore, also in the sixth embodiment, as in the second embodiment, the distance d4 between the trench 6 and the p ⁻ type floating region 13 is about 1 μm larger than the distance d3 between the trench 6 and the n ⁺ type floating region 17. It is preferable.

(Method for Manufacturing Semiconductor Device According to Sixth Embodiment)
Next, a method for manufacturing the semiconductor device according to the sixth embodiment will be described. In the sixth embodiment, in FIG. 2 of the first embodiment, when the p ⁻ type base region 12 is selectively formed on the front surface side of the n ⁻ type drift layer 1 by photolithography and ion implantation, , P ⁻ type floating region 13 is formed. Thereafter, similarly to the fifth embodiment, one n ⁺ type floating region 17 is formed on the front surface of the n ⁻ type drift layer 1 of the mesa portion 16 so as not to contact the sidewall of the trench 6. Other steps are the same as those in Embodiment Mode 1, whereby the semiconductor device shown in FIG. 10 is completed.

As described above, according to the sixth embodiment, as in the first embodiment, dV / dt is reduced and the controllability of turn-on is improved. Further, similarly to the second embodiment, by providing the p ⁻ type floating region, it is possible to prevent a high electric field from being applied to the gate insulating film at the bottom of the trench.

(Embodiment 7)
FIG. 11 is a cross-sectional view illustrating the structure of the semiconductor device according to the seventh embodiment. As shown in FIG. 11, the semiconductor device according to the seventh embodiment has a structure in which the position of the n ⁺ -type floating region 17 is changed with respect to the semiconductor device according to the first embodiment.

A plurality (two in the example of FIG. 11) of n ⁺ type floating regions 17 are provided apart from each other on the front surface of the n ⁻ type drift layer 1 of the mesa portion 16 where no channel is provided. The n ⁺ type floating region 17 in the vicinity of the trench 6 is provided so that one side surface is in contact with the trench 6. The width, impurity concentration, and depth of the n ⁺ type floating region 17 may be the same as those in the first embodiment.

(Method for Manufacturing Semiconductor Device According to Seventh Embodiment)
Next, a method for manufacturing the semiconductor device according to the seventh embodiment will be described. In Figure 2 of the first embodiment In the seventh embodiment, by photolithography and ion implantation, n ^- the front surface side of the type drift layer 1, when forming the n ⁺ -type floating region 17, n ⁺ -type floating A plurality of regions 17 are formed on the front surface of the n ⁻ type drift layer 1 of the mesa portion 16. At this time, the n ⁺ type floating region 17 in the vicinity of the trench 6 is formed so that one side surface thereof is in contact with the trench 6. Other steps are the same as those in Embodiment Mode 1, so that the semiconductor device shown in FIG. 11 is completed.

As described above, according to the seventh embodiment, as in the first embodiment, dV / dt is reduced and the controllability of turn-on is improved. As described above, the characteristics are better when the n ⁺ type floating region and the trench are spaced apart. Therefore, dV / dt is smaller in the seventh embodiment than in the conventional structure, but dV / dt is larger than that in the first embodiment.

(Embodiment 8)
FIG. 12 is a cross-sectional view illustrating the structure of the semiconductor device according to the eighth embodiment. As shown in FIG. 12, the semiconductor device according to the eighth embodiment has a structure in which a p ⁻ type floating region 13 is added to the semiconductor device according to the seventh embodiment.

The p ⁻ type floating region 13 is provided in the mesa portion 16 where no channel is provided, as in the second embodiment. The impurity concentration, depth, and width of the p ⁻ type floating region 13 may be the same as that of the p ⁻ type base region 12.

Further, the p ⁻ type floating region 13 is arranged between the center of the mesa portion 16 and the n ⁺ type floating region 17 as in the second embodiment, and is separated from the side wall of the trench 6 by a distance d5 in the eighth embodiment. Is done. p ^- that is closer than the lateral interface between the type drift layer 1 on the side walls of the trench 6 ^- -type lateral n of the floating region 13 ^- an interface between the type drift layer 1, n of the n ⁺ -type floating region 17 , D6> d5 is preferable. That is, the p ⁻ type floating region 13 and the n ⁺ type floating region 17 are preferably in contact with each other. When the p ⁻ -type floating region 13 and the n ⁺ -type floating region 17 are separated, the n ⁺ -type floating region 17 cannot electrically cut the hole accumulation layer on the surface of the mesa portion 16 where the channel is not provided and the sidewall of the trench 6. This is because the potential of the hole accumulation layer of the mesa portion 16 where no channel is provided cannot be increased.

FIG. 20A is a graph illustrating a relationship between the distance d5 of the semiconductor device according to the eighth embodiment and dI / dt. In FIG. 20A, the horizontal axis indicates the distance d5, and the unit is μm. The vertical axis indicates turn-on dI / dt, and the unit is A / μs. FIG. 20B is a graph illustrating a relationship between the distance d5 of the semiconductor device according to the eighth embodiment and BVces. In FIG. 20B, the horizontal axis indicates the distance d5, and the unit is μm. The vertical axis indicates BVces, and the unit is V. 20A shows the case where the width w1 of the n ⁺ type floating region 17 is 1 μm, 3 μm, 5 μm, 7 μm, and 9 μm. In FIG. 20B, the width w1 of the n ⁺ type floating region 17 is 1 μm, 3 μm, 5 μm, The case of 9 μm is shown.

As shown in FIGS. 20A and 20B, when the distance d5 is 2 μm or more and 4 μm or less (region S9 in FIG. 20A, region S10 in FIG. 20B), when the width w1 is 5 μm or more, the turn-on dI / The dt is as low as 900 A / μs or less. For this reason, it is preferable that the n ⁺ -type floating region 17 is provided 2 μm or more and 4 μm or less away from the sidewall of the trench 6. Further, when the distance d5 is about 3 μm, both turn-on dI / dt and breakdown voltage can be achieved, which is more preferable.

(Method for Manufacturing Semiconductor Device According to Eighth Embodiment)
Next, a method for manufacturing the semiconductor device according to the eighth embodiment will be described. In the eighth embodiment, in FIG. 2 of the first embodiment, the p ⁻ type base region 12 is selectively formed on the front surface side of the n ⁻ type drift layer 1 by photolithography and ion implantation. , P ⁻ type floating region 13 is formed. Thereafter, n ⁺ type floating region 17 is formed in the same manner as in the seventh embodiment. Other steps are the same as those in Embodiment Mode 1, so that the semiconductor device shown in FIG. 12 is completed.

As described above, according to the eighth embodiment, as in the first embodiment, dV / dt is reduced and the controllability of turn-on is improved. As in the seventh embodiment, dV / dt is smaller than that in the conventional structure, but dV / dt is larger than that in the first embodiment. Further, by providing the p ⁻ type floating region, it is possible to prevent a high electric field from being applied to the gate insulating film at the bottom of the trench. For this reason, the withstand voltage of the silicon carbide semiconductor device can be increased.

  The effects of the present invention over the conventional example will be described below based on the measurement results of the turn-on waveform and the collector current at turn-on. FIG. 13 is a graph showing the gate resistance dependence of the turn-on waveform of a conventional semiconductor device. FIG. 14 is a graph showing the gate resistance dependence of the turn-on waveform of the semiconductor device according to the first embodiment.

  13 and 14, the left vertical axis indicates the gate voltage, and the unit is V. The right vertical axis represents the collector current, and the unit is A. The horizontal axis indicates time, and the unit is seconds. In FIGS. 13 and 14, a line surrounded by an ellipse indicated by symbol A is a collector current, and a line surrounded by an ellipse indicated by symbol B is a gate voltage. In each ellipse, five lines indicate the case where the gate resistance Rg is 10, 20, 30, 40, 50Ω from the left.

  Compared to the conventional example of FIG. 13, in the first embodiment of FIG. 14, it can be seen that the time variation of the gate voltage and the collector current is small and converges quickly in the case of all the gate resistances Rg. As described above, in the first embodiment, the increase rate dV / dt of the gate potential is small, and the controllability of the charge rate of the gate voltage by the gate resistance is improved.

FIG. 15 is a graph showing the gate resistance dependence of the turn-on dI / dt of the semiconductor device according to the first embodiment and the conventional semiconductor device. In FIG. 15, the vertical axis represents dI / dt, and the unit is A / μs. The horizontal axis represents the gate resistance Rg, and the unit is Ω. As shown in FIG. 15, in the first embodiment, when the gate resistance Rg is increased to 50Ω, it can be seen that dI / dt is reduced to half of the conventional value. Although not shown, in the form in which the n ⁺ type floating region 17 is in contact with the sidewall of the trench 6, for example, the seventh embodiment, dI / dt is slightly increased, but dI / dt is lower than the conventional one.

  As described above, the present invention can be variously modified without departing from the gist of the present invention, and in each of the above-described embodiments, for example, the dimensions and impurity concentrations of each part are variously set according to required specifications. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, in the present invention, the first conductivity type is p-type and the second conductivity type is n-type. It holds.

  As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for a high voltage semiconductor device used for a power conversion device and a power supply device such as various industrial machines.

1 n ⁻ type drift layer 2 p ⁺ type collector region 3 n ⁺ type buffer layer 4 p ⁻ type layer 5 n ⁺ type emitter region 6 trench 7 gate insulating film 8 gate electrode 9 interlayer insulating film 10 emitter electrode 11 p ⁺ type base Region 12 p ⁻ type base region 13 p ⁻ type floating region 14 Collector electrode 15 Mesa portion 16 provided with channel Mesa portion 17 provided with no channel 17 n ⁺ type floating region

Claims (14)

A first semiconductor layer of a first conductivity type;
A second semiconductor layer of a second conductivity type selectively provided on one surface layer of the first semiconductor layer;
A third semiconductor layer of a first conductivity type selectively provided inside the second semiconductor layer;
A second conductive type fourth semiconductor layer selectively provided adjacent to the third semiconductor layer in the second semiconductor layer and connected to the second semiconductor layer;
A trench in contact with the third semiconductor layer and the second semiconductor layer and reaching the first semiconductor layer;
A fifth semiconductor layer of a first conductivity type selectively provided on one surface layer of the first semiconductor layer;
A sixth semiconductor layer of a second conductivity type provided on the other surface layer of the first semiconductor layer;
An emitter electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer and electrically insulated from the fifth semiconductor layer;
A collector electrode electrically connected to the sixth semiconductor layer;
A gate electrode provided inside the trench via a gate insulating film;
With
The fifth semiconductor layer is provided between the trenches not in contact with the second semiconductor layer.   2. The semiconductor device according to claim 1, wherein a plurality of the fifth semiconductor layers are provided between the trenches apart from the trenches and not provided with the second semiconductor layer.   A seventh semiconductor layer of a second conductivity type is provided in a region between the trenches not provided with the second semiconductor layer and sandwiched between the fifth semiconductor layers and spaced apart from the trenches. The semiconductor device according to claim 2.   2. The semiconductor according to claim 1, wherein the fifth semiconductor layer is provided on one entire surface layer of the first semiconductor layer between the trenches not provided with the second semiconductor layer. apparatus.   A seventh semiconductor layer of a second conductivity type is provided between the trenches not provided with the second semiconductor layer, spaced apart from the trench and having one surface in contact with the fifth semiconductor layer. The semiconductor device according to claim 4.   2. The semiconductor device according to claim 1, wherein one fifth semiconductor layer is provided between the trenches apart from the trench and not provided with the second semiconductor layer.   Between the trenches not provided with the second semiconductor layer, spaced apart from the trenches, one surface is in contact with the fifth semiconductor layer, and the second conductivity type seventh narrower than the fifth semiconductor layer. The semiconductor device according to claim 6, further comprising a semiconductor layer.   The semiconductor device according to claim 1, wherein a plurality of the fifth semiconductor layers are provided between the trenches connected to the trenches and not provided with the second semiconductor layer.   A seventh semiconductor layer of a second conductivity type is provided between the trenches not provided with the second semiconductor layer, in a region sandwiched between the fifth semiconductor layers and spaced apart from the trench. The semiconductor device according to claim 8. A first step of selectively forming a second semiconductor layer of the second conductivity type on one surface layer of the first semiconductor layer of the first conductivity type;
A second step of selectively forming a third semiconductor layer of a first conductivity type inside the second semiconductor layer;
Forming a second conductive type fourth semiconductor layer connected to the second semiconductor layer adjacent to the third semiconductor layer in the second semiconductor layer; and
A fourth step of selectively forming a fifth semiconductor layer of the first conductivity type on one surface layer of the first semiconductor layer;
A fifth step of forming a trench reaching the first semiconductor layer through the third semiconductor layer and the second semiconductor layer;
A sixth step of forming a second conductive type sixth semiconductor layer on the other surface layer of the first semiconductor layer;
A seventh step of forming an emitter electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer and electrically insulated from the fifth semiconductor layer;
An eighth step of forming a collector electrode electrically connected to the sixth semiconductor layer;
A ninth step of forming a gate electrode inside the trench through a gate insulating film;
Including
In the fourth step, the fifth semiconductor layer is formed between the trenches not provided with the second semiconductor layer.   The semiconductor device according to claim 2, wherein the fifth semiconductor layer is separated from the trench by a distance of 2 μm to 6 μm.   The semiconductor device according to claim 3, wherein a distance between the trench and the seventh semiconductor layer is 1 μm or more greater than a distance between the trench and the fifth semiconductor layer.   The semiconductor device according to claim 5, wherein the seventh semiconductor layer is separated from the trench by a distance of 2 μm to 4 μm.   The semiconductor device according to claim 1, wherein a width of the fifth semiconductor layer is 2 μm or more.

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