JP2018151921A - Electronic control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic control device capable of detecting abnormality of communication early and re-synchronizing at an early stage even when communication fails.SOLUTION: An electronic control device 1, in which a microcomputer 11 transmits a command signal to a microcomputer 12 via a data communication line L4 and the microcomputer 12 performs predetermined processing based on a command presented by the command signal, includes a DMA transfer counter 121 that counts the number of times the microcomputer 12 has received the command signal from the microcomputer 11 and a communication trigger line L1 via which a trigger signal presenting a trigger corresponding to termination of the transmission of the command signal from the microcomputer 11 to the microcomputer 12 is transmitted from the microcomputer 11 to the microcomputer 12. The microcomputer 12 determines that the data communication having received the command signal is abnormal when the value of the number of times the DMA transfer counter 121 counted at the trigger timing does not match a predetermined value.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an electronic control device, and more particularly to an electronic control device that includes a plurality of microcomputers and communicates between the microcomputers.

  2. Description of the Related Art Conventionally, an electronic control device that performs continuous communication by connecting a plurality of microcomputers (hereinafter referred to as “microcomputers”) via communication lines is known. In such an electronic control device, continuous communication is performed by a DMA (Direct Memory Access) method or the like without using a CPU.

  Under such circumstances, Patent Document 1 discloses a serial communication device configured to perform serial communication between two microcomputers. In such a serial communication device, the master side microcomputer controls main engine control such as ignition timing control and fuel injection control, and the slave side microcomputer performs A / D conversion of sensing data by various sensors necessary for engine control, load calculation, and others. Provide auxiliary control.

  Conventionally, the master-side microcomputer executes processing for storing various commands in the RAM at a constant cycle, and transmits a command signal for causing the slave-side microcomputer to execute each command stored in the RAM a predetermined number of times. To do. The slave side microcomputer executes a predetermined process in accordance with each command of the command signal received from the master side microcomputer.

  Conventionally, the master side microcomputer counts the number of times the command signal is transmitted by the DMA transfer counter, and resets the DMA transfer counter after completion of the predetermined number of command signal transmissions. The slave microcomputer counts the number of times the command signal is received by the DMA transfer counter, starts the interrupt process after receiving the command signal a predetermined number of times, and resets the DMA transfer counter. Thus, the master side microcomputer and the slave side microcomputer communicate with each other using the DMA transfer counter in synchronization.

JP 2002-183082 A

  However, according to the study of the present inventor, when communication fails due to the influence of noise or the like during continuous communication by the DMA method or the like, the number of times of transmitting the command signal counted by the DMA transfer counter of the master side microcomputer, If there is a difference between the number of times the command signal counted by the DMA transfer counter of the side microcomputer is received and normal communication cannot be performed, it is necessary to perform resynchronization by performing handshake communication or the like. In addition, since resynchronization is performed after detecting an abnormality and performing handshake communication or the like, it takes time to return to a normal state after detecting the abnormality.

  The present invention has been made after the above examination, and even when communication fails, an electronic control device that can detect communication abnormality early and can perform resynchronization early The purpose is to provide.

  In order to achieve the above object, according to the first aspect of the present invention, in the first aspect, the present invention includes a first microcomputer and a second microcomputer that cooperate with each other to control the control target device group, and data from the first microcomputer In an electronic control device that transmits a command signal to the second microcomputer via a communication line, and the second microcomputer performs a predetermined process based on a command presented by the command signal, the second microcomputer A counter that counts the number of times the command signal is received from the first microcomputer; and a trigger signal that exhibits a trigger corresponding to the end of transmission of the command signal from the first microcomputer to the second microcomputer. A communication trigger line that flows from one microcomputer to the second microcomputer, and the second microcomputer has the counter at the trigger timing. When the value of the number of times of the number does not match the predetermined value, the data communication that has received the command signal is determined electronic control unit is abnormal.

  An electronic control device according to a first aspect of the present invention includes a first microcomputer and a second microcomputer that cooperate with each other to control a device group to be controlled, and are connected from the first microcomputer via a data communication line. The second microcomputer receives a command signal from the first microcomputer in an electronic control device that transmits a command signal to the second microcomputer and the second microcomputer performs a predetermined process based on the command presented by the command signal. A counter that counts the number of times of transmission, and a trigger signal that triggers a trigger corresponding to the end of transmission of the command signal from the first microcomputer to the second microcomputer, and a communication trigger line that flows from the first microcomputer to the second microcomputer; The second microcomputer receives a command signal when the value counted by the counter at the trigger timing does not match the predetermined value. By determining data communication is abnormal, even if the communication fails, it is possible to detect the abnormality of communication at an early stage, it is possible to perform resynchronization promptly.

FIG. 1 is a block diagram showing a configuration of an electronic control device according to an embodiment of the present invention. FIG. 2 is a timing chart for explaining the flow of data communication processing executed by the electronic control unit according to this embodiment.

  Hereinafter, an electronic device according to an embodiment of the present invention will be described in detail with reference to the drawings as appropriate.

<Configuration of electronic control device>
With reference to FIG. 1, the structure of the electronic control apparatus in this embodiment is demonstrated.

  FIG. 1 is a block diagram showing a configuration of an electronic control device according to an embodiment of the present invention.

  The electronic control device 1 in this embodiment is typically mounted on a vehicle such as a motorcycle.

  The electronic control device 1 includes a microcomputer 11 and a microcomputer 12. The microcomputer 11 and the microcomputer 12 transmit a communication trigger line L1 for transmitting a trigger signal, a signal line L2 for transmitting a chip selector signal, a signal line L3 for transmitting a clock signal, and a command signal. Are connected to each other by a data communication line L4 for transmitting data and a data communication line L5 for transmitting transfer data, and cooperate with each other to control a device group to be controlled such as a fuel injection device.

  The microcomputer 11 and the microcomputer 12 perform data communication processing and perform predetermined data communication. Data communication processing is executed at regular intervals. Further, the predetermined data communication is typically communication by an SPI (Serial Peripheral Interface) method using a DMA function.

  The microcomputer 11 performs control to transmit a chip select signal to the microcomputer 12 through the signal line L2 and control to transmit a clock signal to the microcomputer 12 through the signal line L3.

  The microcomputer 11 executes a periodic processing for storing various commands in a RAM (not shown), and sends a command signal for causing the microcomputer 12 to execute each command stored in the RAM to the microcomputer 12 through the data communication line L4. Control to send the number of times. The microcomputer 11 includes a DMA transfer counter 111 that counts the number of times the command signal is transmitted.

  The microcomputer 11 controls to transmit a trigger signal indicating a trigger corresponding to the end of transmission of the command signal to the microcomputer 12 via the communication trigger line L1 while presenting a trigger corresponding to the start of transmission of the command signal. The microcomputer 11 is typically a master side microcomputer.

  The microcomputer 12 receives the chip select signal transmitted from the microcomputer 11 via the signal line L2, and receives the clock signal transmitted from the microcomputer 11 via the signal line L3.

  The microcomputer 12 receives the command signal transmitted from the microcomputer 11 via the data communication line L4, and performs a predetermined process based on the command presented by the received command signal. The predetermined process is an auxiliary process of the process executed by the microcomputer 11 and is typically A / D conversion or signal output of sensing data.

  The microcomputer 12 includes a DMA transfer counter 121 that counts the number of times the command signal is received from the microcomputer 11. The microcomputer 12 executes interrupt processing at the trigger timing corresponding to the end of transmission of the command signal in the trigger signal received via the communication trigger line L1, and the value of the number of times counted by the DMA transfer counter 121 matches the predetermined value. If not, it is determined that the data communication that received the command signal is abnormal. The microcomputer 12 is typically a slave-side microcomputer.

  The number of times that the microcomputer 11 transmits the command signal and the number of times that the microcomputer 12 receives the command signal are set in advance.

  The electronic control device 1 having the above configuration performs the data communication process shown below.

<Data communication processing>
With reference to FIG. 2, the specific flow of the data communication processing in this embodiment will be described in detail.

  FIG. 2 is a timing chart for explaining the flow of data communication processing executed by the electronic control unit according to this embodiment.

  The data communication process in the present embodiment starts at the timing when power is supplied to the electronic control device 1 and the electronic control device 1 is activated. Such data communication processing is repeatedly executed at regular intervals while the electronic control device 1 is activated.

  First, a case where communication is successful in the data communication process will be described.

  First, the microcomputer 11 executes a periodic process S1 for storing a command for causing the microcomputer 12 to execute a desired process in a RAM (not shown) (FIG. 2A).

  The microcomputer 11 transmits a trigger signal that exhibits a trigger corresponding to the start of transmission of the command signal through the trigger communication line L1 during the periodic processing S1 (FIG. 2C). The microcomputer 11 typically sets the trigger corresponding to the start of transmission of the command signal by inverting the level of the trigger signal from low level to high level (logic inversion).

  The microcomputer 11 inverts the chip select signal from the high level to the low level in synchronization with the trigger timing of the trigger signal corresponding to the start of transmission of the command signal (FIG. 2D). When the chip select signal is at a low level, it indicates that communication is in progress, and when it is at a high level, it indicates that communication is stopped, and is transmitted through the signal line L2. Further, the microcomputer 11 starts transmission of the clock signal in synchronization with the trigger timing of the trigger signal corresponding to the start of transmission of the command signal (FIG. 2 (e)). Such a clock signal indicates the number of bits of data to be transmitted, and is transmitted through the signal line L3. Further, the microcomputer 11 starts transmission of the first command signal in synchronization with the trigger timing of the trigger signal corresponding to the start of transmission of the command signal (FIG. 2 (f)). Such a command signal is transmitted through the data communication line L4. The number of times the command signal is transmitted is typically five.

  Next, the microcomputer 12 receives the trigger signal shown in FIG. 2C via the trigger communication line L1, and recognizes the start of data communication by detecting the rising edge of the received trigger signal.

  The microcomputer 12 recognizes that communication is in progress by receiving a low-level chip select signal via the signal line L2, and transmits what bit data by receiving the clock signal via the signal line L3. Recognize what was done. The microcomputer 12 receives a command signal via the data communication line L4, stores the received command signal in a RAM (not shown), and decrements the preset count value 5 of the DMA transfer counter 121. The count value is 4 (FIG. 2 (h)). The number of times the command signal is received is typically five.

  The microcomputer 12 executes a predetermined process indicated by the command of the first command signal stored in the RAM in the previous data communication process, and transmits the first transfer data via the data communication line L5 (FIG. 2 ( g)).

  Next, the microcomputer 11 and the microcomputer 12 repeat the above processing until the set number of times is reached. Thereby, the command signal is sequentially transmitted from the microcomputer 11 through the data communication line L4 and is sequentially received by the microcomputer 12, and the transfer data is sequentially transmitted from the microcomputer 12 through the data communication line L5 and is sequentially transmitted by the microcomputer 11. Received. The count value of the DMA transfer counter 111 is sequentially decremented to 4, 3, 2, 1 every time the transmission of the command signal is finished (FIG. 2B). Further, the count value of the DMA transfer counter 121 is decremented sequentially every time a command signal is received, and becomes 4, 3, 2, 1, 0 (FIG. 2 (h)).

  Then, after completing the transmission of the last command signal, the microcomputer 11 resets the DMA transfer counter 111 to set the count value to “0”, and generates a trigger signal indicating a trigger corresponding to the end of the transmission of the command signal. Transmission is performed by the trigger communication line L1 (FIG. 2C). The microcomputer 11 typically sets the trigger corresponding to the end of transmission of the command signal by inverting the level of the trigger signal from the high level to the low level.

  When the microcomputer 12 detects the falling edge of the trigger signal, it executes the interrupt processing S11 (FIG. 2 (i)), and resets the count value of the DMA transfer counter 121 to 5 (FIG. 2 (FIG. 2). h)). In the interrupt process S11, the microcomputer 12 detects that the falling edge of the trigger signal is detected, and the count value of the DMA transfer counter 121 matches 0 as a predetermined value. Therefore, the data communication that has received the command signal is normal. Judge that there is.

  Next, a case where communication fails in the data communication process will be described.

  If the microcomputer 11 starts executing the periodic processing S2 and noise is generated in the process of transmitting the low-level chip select signal for the third time during data communication according to the same procedure as described above, the microcomputer 12 Receives a high-level chip select signal with noise and recognizes that communication is stopped. For this reason, the microcomputer 12 cannot normally receive the command signal transmitted from the microcomputer 11 for the third time, and does not decrement the count value of the DMA transfer counter 121. In this case, the count value of the DMA transfer counter 121 remains 3.

  Then, the microcomputer 11 continues to transmit the command signal without noticing the occurrence of noise, and sequentially decrements the count value of the DMA transfer counter 111 every time the transmission of the command signal is completed.

  Further, the microcomputer 12 sequentially decrements the count value of the DMA transfer counter 121 every time a command signal is received. Thereby, when the data communication process is completed, the count value of the DMA transfer counter 121 becomes 1. That is, the count value of the DMA transfer count 121 becomes the value of the number of times deficient once.

  When the microcomputer 12 detects the falling edge of the trigger signal while the count value of the DMA transfer counter 121 is 1, the microcomputer 12 executes the interrupt processing S12 and resets the count value of the DMA transfer counter 121 to 5. . In the interrupt processing S12, the microcomputer 12 detects the falling edge of the trigger signal, and the count value of the DMA transfer counter 121 does not coincide with 0 as the predetermined value. Therefore, the data communication that received the command signal is abnormal. Judge that there is.

  If the microcomputer 12 determines that the data communication is abnormal, it can take a fail-safe action. The fail-safe action is typically execution of processing for holding the previously received command signal, or execution of processing for replacing the received command signal with an alternative signal.

  Incidentally, in the data communication processing by the conventional DMA method or the like, when the data communication fails, the count value of the DMA transfer counter of the slave microcomputer is the value when the communication next to the communication that failed in the data communication is started. The predetermined value is 0. As a result, the microcomputer on the slave side executes interrupt processing. Therefore, in the conventional data communication process, detection of an abnormal communication is delayed and resynchronization is delayed as compared with the present embodiment.

  In FIG. 2, it is determined that the data communication is abnormal when noise is added to the chip select signal. However, even when noise is added to the clock signal, the microcomputer 12 cannot correctly receive the command signal and perform DMA transfer. Since the count value of the counter 121 cannot be decremented, it can be determined that the data communication is abnormal.

  In the electronic control device in the present embodiment described above, the DMA transfer counter 121 that counts the number of times that the microcomputer 12 receives the command signal from the microcomputer 11 and the trigger corresponding to the end of transmission of the command signal from the microcomputer 11 to the microcomputer 12 are provided. When the present trigger signal has the communication trigger line L1 transmitted from the microcomputer 11 to the microcomputer 12, and the value of the number of times counted by the DMA transfer counter 121 at the trigger timing does not match the predetermined value, the command signal is received. By determining that the data communication is abnormal, even if the communication fails, the communication abnormality can be detected early and resynchronization can be performed early.

  In the present invention, the type, shape, arrangement, number, etc. of the members are not limited to the above-described embodiments, and the constituent elements thereof are appropriately replaced with those having the same operational effects, etc. Of course, it can be changed as appropriate within range 2.

  Specifically, in this embodiment, data communication by the DMA method or the SPI method is performed, but continuous communication may be performed between the microcomputers by a method other than the DMA method and the SPI method.

  In this embodiment, it is determined that the communication is performed less than the set number using the count values counted by the DMA transfer counter 111 and the DMA transfer counter 121. The count value to be set may be set to a value that can count the number of times greater than the set number of times, and it may be determined that the number of times of communication greater than the set number of times has been performed.

  In this embodiment, the DMA transfer counter 111 and the DMA transfer counter 121 are decremented, but may be incremented, and the count value for starting the count can be set to an arbitrary value.

  As described above, according to the present invention, it is possible to provide an electronic control device capable of detecting a communication abnormality early and performing resynchronization early even if communication fails. It is expected that it can be widely applied to electronic control devices such as motorcycles because of its universality.

DESCRIPTION OF SYMBOLS 1 ... Electronic control unit 11 ... Microcomputer 12 ... Microcomputer 111 ... DMA transfer counter 121 ... DMA transfer counter L1 ... Communication trigger line L2 ... Signal line L3 ... Signal line L4 ... Data communication line L5 ... Data communication line

Claims (1)

A first microcomputer and a second microcomputer that control the control target device group in cooperation with each other, transmit a command signal from the first microcomputer to the second microcomputer via a data communication line, and The second microcomputer is an electronic control device that performs predetermined processing based on a command presented by the command signal.
A counter for counting the number of times the second microcomputer has received the command signal from the first microcomputer;
A communication trigger line that transmits a trigger signal corresponding to the end of transmission of the command signal from the first microcomputer to the second microcomputer, and is transmitted from the first microcomputer to the second microcomputer;
Further comprising
The second microcomputer is
When the number of times counted by the counter at the timing of the trigger does not match a predetermined value, it is determined that the data communication that has received the command signal is abnormal.
An electronic control device characterized by that.

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