JP2018146729A - Method for manufacturing semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor element capable of reducing stress.SOLUTION: A method for manufacturing a semiconductor element comprises the steps of: forming a first mesa on a semiconductor substrate; forming a first insulating film on a side surface of the first mesa; forming a first resin layer embedded with the first mesa after the step of forming the first insulating film; forming a resist mask including a first opening through which an upper surface of the first mesa is exposed and a second opening adjacent to the first opening on the semiconductor substrate and an upper surface of the first resin layer; and forming a first metal layer in the first opening and a second metal layer in the second opening.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a method for manufacturing a semiconductor element.

  A technique is known in which a mesa formed in a semiconductor layer is embedded with benzocyclobutene (BCB) and an electrode is formed on the mesa by a lift-off method (see, for example, Patent Document 1).

JP 2009-206177 A

  A protective film for protecting the mesa is provided on the side surface of the mesa. However, the protective film may be peeled off due to the stress generated from the resist used in the lift-off method or the like.

  An object of the present invention is to provide a method for manufacturing a semiconductor element capable of reducing stress.

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming a first mesa on a semiconductor substrate, a step of forming a first insulating film on a side surface of the first mesa, and a step of forming the first insulating film. A step of forming a first resin layer for embedding the first mesa, a first opening in which an upper surface of the first mesa is exposed on the upper surface of the semiconductor substrate and the first resin layer, and the first opening Forming a resist mask having a second opening adjacent to the first opening, and forming a first metal layer in the first opening and a second metal layer in the second opening.

  According to the above invention, it is possible to reduce stress.

FIG. 1 is a plan view of an optical waveguide portion of the multilevel modulator according to the first embodiment. FIG. 2 is a plan view of the multilevel modulator according to the first embodiment. FIG. 3A is a cross-sectional view taken along line AA in FIG. FIG. 3B is a cross-sectional view taken along line BB in FIG. FIGS. 4A to 4D are cross-sectional views illustrating a method for manufacturing a multilevel modulator. FIG. 5A, FIG. 5C, and FIG. 5D are cross-sectional views illustrating a method for manufacturing a multilevel modulator. FIG. 5B is a plan view illustrating a method for manufacturing the multilevel modulator. FIG. 6A to FIG. 6C are cross-sectional views illustrating a method for manufacturing a multilevel modulator. FIG. 7A and FIG. 7B are cross-sectional views illustrating a method for manufacturing a multilevel modulator. FIG. 8A and FIG. 8B are cross-sectional views illustrating a method for manufacturing a multilevel modulator. FIG. 9 is a cross-sectional view illustrating a multilevel modulator according to the second embodiment. FIG. 10A and FIG. 10B are cross-sectional views illustrating a method for manufacturing a multilevel modulator. FIG. 10C is a plan view illustrating a method for manufacturing the multilevel modulator. FIG. 11A is a plan view illustrating the method for manufacturing the multilevel modulator according to the third embodiment. FIG. 11B is a plan view illustrating the method for manufacturing the multilevel modulator according to the variation of the third embodiment.

[Description of Embodiment of Present Invention]
First, the contents of the embodiments of the present invention will be listed and described.

According to one aspect of the present invention, (1) a step of forming a first mesa on a semiconductor substrate, a step of forming a first insulating film on a side surface of the first mesa, and a step of forming the first insulating film A step of forming a first resin layer for embedding the first mesa; a first opening in which an upper surface of the first mesa is exposed; and a first opening on the upper surface of the semiconductor substrate and the first resin layer. A method for manufacturing a semiconductor device, comprising: forming a resist mask having adjacent second openings; and forming a first metal layer in the first opening and a second metal layer in the second opening. According to this configuration, the volume of the resist mask that contributes to the stress is reduced, and the stress can be reduced.
(2) The first opening and the second opening may extend along the extending direction of the first mesa. According to this configuration, stress can be reduced in each portion of the mesa to be stretched, and peeling of the protective film can be suppressed.
(3) Two first mesas are formed on the semiconductor substrate, the resist mask has two first openings corresponding to the two first mesas, and the second opening has the two You may locate between a 1st opening and the edge part of the said semiconductor substrate. According to this configuration, the volume of the resist mask that contributes to the stress is reduced, and the stress can be reduced.
(4) forming the second insulating film on the first mesa and the first resin layer, and etching the first resist and the second opening by etching using the resist mask; A step of removing the second insulating film, and a step of forming the second metal layer after the step of removing the second insulating film. According to this configuration, the volume of the resist mask that contributes to stress is reduced. Therefore, stress can be reduced even if the resist mask contracts during the etching and formation of the second metal layer.
(5) The distance between the first opening and the second opening may be 50 μm or less. Thereby, stress can be reduced effectively.
(6) An upper surface of the first resin layer is exposed from the second opening, the second metal layer is formed on the first resin layer, and a second layer is formed on the second metal layer and the first resin layer. You may have the process of forming a resin layer. According to this configuration, the first metal layer and the second metal layer are insulated.
(7) forming a second mesa on the semiconductor substrate, the upper surface of the second mesa is exposed from the second opening, and the second metal layer is formed on the upper surface of the second mesa. Also good. According to this configuration, since the adhesion between the second metal layer and the second mesa is high, peeling of the second metal layer is suppressed.
(8) The resist mask may include a plurality of the second openings arranged along the extending direction of the first mesa. According to this configuration, stress can be suppressed.
(9) The first mesa may be an optical waveguide mesa, and the first metal layer may be included in a modulation electrode that modulates light propagating through the optical waveguide mesa. According to this configuration, stress can be reduced in the optical waveguide mesa and peeling of the protective film can be suppressed.

[Details of the embodiment of the present invention]
A specific example of a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. In addition, this invention is not limited to these illustrations, is shown by the claim, and intends that all the changes within the meaning and range equivalent to a claim are included.

  FIG. 1 is a plan view of an optical waveguide portion of a multilevel modulator 100 (semiconductor element) according to the first embodiment. As shown in FIG. 1, an input waveguide 12, an output waveguide 14, optical couplers 16 a and 16 b, and a plurality of Mach-Zehnder modulators 20 are provided on a substrate 10. The input waveguide 12, the output waveguide 14, and the optical couplers 16a and 16b are formed of mesa-shaped optical waveguides. The optical couplers 16a and 16b are MMI (Multimode Interferometer) type optical couplers. The plurality of Mach-Zehnder modulators 20 are configured by combining paths of mesa-shaped optical waveguides. The light input from the input waveguide 12 is branched by the optical coupler 16 a, passes through the Mach-Zehnder modulator 20, is multiplexed by the optical coupler 16 b, and is output to the output waveguide 14. The size of the multilevel modulator 100 is, for example, 10 mm × 4 mm.

  The Mach-Zehnder modulator 20 includes, on the substrate 10, two optical couplers 22a and 22b, and two arm waveguides 24a and 24b connected between the two optical couplers 22a and 22b. The optical couplers 22a and 22b and the arm waveguides 24a and 24b are formed of mesa-shaped optical waveguides. The optical coupler 22a branches the light input from the input waveguide 12. The two arm waveguides 24a and 24b propagate the light branched by the optical coupler 22a. The optical coupler 22b multiplexes the light propagated through the two arm waveguides 24a and 24b. The optical couplers 22a and 22b are MMI type optical couplers.

  FIG. 2 is a plan view of the multilevel modulator 100 according to the first embodiment. In FIG. 2, the optical waveguide portion described in FIG. 1 is illustrated by a thin dotted line. As shown in FIG. 2, the mesa-shaped optical waveguide is embedded with a resin layer 30 of BCB (benzocyclobutene). The wiring pattern includes a modulation electrode 32, a ground electrode 34, and a phase adjustment electrode 36. The modulation electrode 32 is provided on the arm waveguides 24 a and 24 b of the Mach-Zehnder modulator 20 and is connected to the signal electrode pad 38. The ground electrode 34 is provided between the arm waveguide 24 a and the arm waveguide 24 b and is connected to the ground electrode pad 40. The phase adjustment electrode 36 is provided on the arm waveguides 24 a and 24 b of the Mach-Zehnder modulator 20 at a position different from the modulation electrode 32 and is connected to the DC electrode pad 42.

  When a high frequency electrical signal is supplied from the signal electrode pad 38 to the modulation electrode 32, a high frequency (for example, about 20 GHz) electrical signal flows between the modulation electrode 32 and the ground electrode 34. As a result, the refractive indexes of the arm waveguides 24a and 24b change, and the phase of light propagating through the arm waveguides 24a and 24b changes. Thereby, the light propagating through the arm waveguides 24a and 24b undergoes phase modulation, and is output to the output waveguide 14 as a modulated optical signal.

  When a DC voltage is supplied from the DC electrode pad 42 to the phase adjustment electrode 36, the refractive indexes of the arm waveguides 24a and 24b shift by a certain value. The magnitude of the direct current voltage is set to a value (optimum value) such that the light propagating through the arm waveguides 24a and 24b is favorably modulated by the electric signal supplied to the modulation electrode 32. That is, the phase of the light propagating through the arm waveguides 24a and 24b is adjusted by the phase adjustment electrode 36 so that the light propagating through the arm waveguides 24a and 24b is favorably modulated.

  The optimum value of the DC voltage supplied to the phase adjustment electrode 36 depends on the optical path length difference between the arm waveguides 24a and 24b. The optical path length difference between the arm waveguides 24a and 24b varies depending on, for example, the wavelength of light propagating through the arm waveguides 24a and 24b. In the multilevel modulator 100, for example, in the wavelength range of 1530 nm to 1570 nm, light of the first wavelength is incident at the first moment, and the wavelength is switched at another second moment, and the wavelength of the second wavelength is changed. Light is incident. For this reason, a relationship table between the wavelength of incident light and the value of the supplied DC voltage is prepared in advance, and the value of the DC voltage is determined based on this relationship table during operation. Further, the optical path length difference between the arm waveguides 24a and 24b also changes depending on the temperature difference between the arm waveguides 24a and 24b. For this reason, the multi-level modulator 100 is mounted on a TEC (Thermo-electric Cooler) and used at a constant temperature (for example, 70 ° C.).

  FIG. 3A is a cross-sectional view taken along line AA in FIG. The substrate 10 is a semiconductor substrate formed of semi-insulating indium phosphide (InP). As shown in FIG. 3A, a lower clad layer 51 of n-type InP (for example, InP doped with Si) is provided on a substrate 10. A core layer 52 having a multiple quantum well structure including an AlGaInAs well layer and an AlInAs barrier layer is provided on the lower cladding layer 51. An upper clad layer 54 of p-type InP (for example, InP doped with Zn) is provided on the core layer 52, and a p-type InGaAs contact layer 55 is provided on the upper clad layer 54. The lower cladding layer 51, the core layer 52, the upper cladding layer 54, and the contact layer 55 form a mesa 50 (first mesa). That is, on the substrate 10, arm waveguides 24 a and 24 b made of a mesa-shaped optical waveguide and electrically connected to each other with the lower cladding layer 51 in common are formed.

  The height of the mesas of the arm waveguides 24a and 24b is 3 μm, for example, and the width of the mesa is 1.5 μm, for example. The two arm waveguides 24a and 24b extend in parallel, and the distance between them is about 50 μm. The interval between the plurality of Mach-Zehnder modulators is 250 μm. Here, the interval is, for example, the distance between the arm waveguide 24 b of one Mach-Zehnder modulator 20 and the arm waveguide 24 a of another Mach-Zehnder modulator 20.

A protective film 56 (first insulating film) made of an inorganic insulating film such as silicon oxide (SiO ₂ ) is provided on the substrate 10 so as to cover the arm waveguides 24a and 24b. A resin layer 30 is provided on the protective film 56. The resin layer 30 is made of, for example, BCB (benzocyclobutene) resin, and includes a first resin layer 30a and a second resin layer 30b. The first resin layer 30a is provided on the side surfaces of the arm waveguides 24a and 24b, and embeds the arm waveguides 24a and 24b. The first resin layer 30a is provided on the entire side surface of the mesa 50 of the arm waveguides 24a and 24b, for example.

  A protective film 60 (second insulating film) made of an inorganic insulating film such as a silicon oxynitride (SiON) film is provided on the upper surface of the first resin layer 30a. The protective film 60 has an opening 60a at a position overlapping the arm waveguides 24a and 24b, and also has an opening 60b adjacent to the opening 60a. A second resin layer 30 b is provided on the protective film 60. Protective films 64 and 66 such as SiON are provided on the upper surface of the second resin layer 30b.

  The modulation electrode 32 is provided on the upper surface of the contact layer 55 of the arm waveguides 24a and 24b. The modulation electrode 32 is formed by laminating an ohmic layer 32a (first metal layer), a base layer 32b, an Au layer 32c, a base layer 32d, and an Au layer 32e in order from the side closer to the contact layer 55. The ohmic layer 32a is provided in the opening 60a of the protective film 60 and is, for example, a laminate of titanium (Ti), platinum (Pt), and Au. The foundation layer 32b and the foundation layer 32d are made of TiW. A protective film 66 that covers the Au layer 32e is provided on the protective film 66 and the Au layer 32e. The protective film 66 is, for example, a stacked body of a SiON film and a silicon nitride (SiN) film.

  A ground electrode 34 is provided between the arm waveguides 24 a and 24 b and on the upper surface of the lower cladding layer 51. The ground electrode 34 is formed by laminating an n-electrode layer 34 a, a base layer 34 b, and a gold (Au) layer 34 c in order from the side closer to the lower cladding layer 51. The n-electrode layer 34a is a laminate (AuGeNi / Au) of a gold germanium nickel alloy and gold. The underlayer 34b is formed of a titanium tungsten alloy (TiW). The ground electrode 34 is covered with the second resin layer 30b.

  A metal layer 62 (second metal layer) is provided in the opening 60 b of the protective film 60. The metal layer 62 is a laminated body of Ti, Pt, and Au, for example, and is formed of the same metal layer as the ohmic layer 32a. The metal layer 62 is located on the opposite side of the mesa 50 from the ground electrode 34 side, and the two metal layers 62 sandwich the arm waveguides 24a and 24b.

  FIG. 3B is a cross-sectional view taken along line BB in FIG. As shown in FIG. 3B, the signal electrode pad 38 is formed by laminating a base layer 38b, an Au layer 38c, a base layer 38d, and an Au layer 38e, and each layer is a layer corresponding to the modulation electrode 32. The same metal layer. The surface of the signal electrode pad 38 is exposed from the opening 66 a of the protective film 66. The signal electrode pad 38 is electrically connected to the modulation electrode 32. The ground electrode pad 40 and the DC electrode pad 42 have the same configuration as the signal electrode pad 38.

(Semiconductor element manufacturing method)
4 (a) to 5 (a) and FIGS. 5 (c) to 8 (b) are cross-sectional views illustrating a method for manufacturing a multilevel modulator, and correspond to line AA in FIG. A cross section is shown. FIG. 5B is a cross-sectional view illustrating a method for manufacturing a multi-level modulator, and shows the same state as FIG.

  As shown in FIG. 4A, a lower clad layer 51, a core layer 52, an upper clad layer 54, and a contact layer 55 are grown on a substrate 10 by metal organic vapor phase epitaxy (MOVPE method). By photolithography and dry etching, arm waveguides 24a and 24b extending in a stripe shape when viewed from above and having a mesa shape when viewed from a cross section are formed. The two mesas 50 extend in parallel. The distance between the two mesas 50 is, for example, 50 μm. Further, by photolithography and dry etching, processing is performed to remove the lower cladding layer 51 in other portions while leaving the lower cladding layer 51 between the arm waveguides 24a to 24b. A protective film 56 that covers the substrate 10, the arm waveguides 24a and 24b, and the lower cladding layer 51 is formed by thermal CVD (chemical vapor deposition).

  As shown in FIG. 4B, a resist mask 70 having an opening 70 a is formed on the protective film 56. The protective film 56 exposed to the opening 70a is removed by wet etching using buffered hydrofluoric acid (BHF). An n-electrode layer 34a made of AuGeNi / Au is formed on the lower cladding layer 51 by metal vapor deposition. Thereafter, the resist mask 70 and the n-electrode layer 34a deposited thereon are also removed (lifted off) together with the resist mask using a solvent. The n-electrode layer 34a deposited on the lower cladding layer 51 remains without being removed. The n-electrode layer 34a is sandwiched between the two arm waveguides 24a and 24b, and extends on the lower cladding layer 51 in parallel with the arm waveguides 24a and 24b. The width of the n electrode layer 34a is 15 μm.

  As shown in FIG. 4C, a BCB resin precursor to be the first resin layer 30a is spin-coated. The spin coating speed is adjusted so that the protective film 56 on the top of the mesa 50 is exposed at the time of coating. After spin coating, the precursor is thermoset to form the first resin layer 30a. Alternatively, after forming the first resin layer 30a thicker than the mesa 50, the BCB may be etched back by dry etching to expose the protective film 56. As shown in FIG. 4D, a protective film 60 is deposited on the first resin layer 30a by a CVD method or the like.

  As shown in FIG. 5A, a resist mask 72 is formed on the protective film 60 by photolithography. The thickness of the resist mask 72 is 1.5 μm. The resist mask 72 has an opening 72 a having a width of 0.8 μm on the mesa 50. Further, the resist mask has an opening 72b having a width of 0.8 μm adjacent to the opening 72a and extending in a stripe shape. FIG. 5B is a plan view showing a state corresponding to FIG. As shown in FIG. 5B, the mesa 50 and the openings 72a and 74b extend parallel to each other.

  For example, the first resin layer 30 a and the protective film 56 on the mesa are removed by dry etching using the resist mask 72. Dry etching is performed until the protective film 60 is removed. Thereby, an opening continuous with the opening 72a is formed in the protective film 60, and an opening continuous with the opening 72b is formed. As shown in FIG. 5A, after dry etching, the contact layer 55 is exposed from the opening 72a, and the first resin layer 30a is exposed from the opening 72b. Since there is no protective film 60 in the opening 72b, the first resin layer 30a exposed to the opening 72b is slightly etched and slightly depressed.

  During dry etching, the resist mask 72 slightly shrinks. Due to this shrinkage, the resist mask 72 exerts stress on the region near the lower end of the openings 72a and 72b. The end of the opening 72a is close to the boundary between the mesa 50 and the protective film 56 that covers the side surface of the mesa. For this reason, the stress from the resist mask 72 acts on the protective film 56 in the direction of peeling from the mesa 50. The magnitude of the stress is proportional to the volume of the resist mask 72.

  In this embodiment, the distance between adjacent Mach-Zehnder modulators is 250 μm, and the distance between the opening 72a and the opening 72b (the distance between the mesa 50 and the opening 72b) is, for example, 50 μm or less. The volume of the resist mask 72 outside the two arm waveguides 24a and 24b is limited not by the distance between adjacent Mach-Zehnder modulators but by the distance from the opening 72a to the opening 72b. The stress in the direction in which the protective film 56 is peeled is determined by the volume of the resist mask 72 in a region sandwiched between the opening 72a and the opening 72b. According to the first embodiment, by providing the opening 72b, the volume of the resist mask 74 from the mesa 50 to the opening 74b can be reduced, and the stress applied to the protective film 56 can be reduced. This makes it difficult for the protective film 56 to peel from the mesa 50.

  As shown in FIG. 5C, while leaving the resist mask 72, Ti / Ti, for example, is deposited on the contact layer 55 in the opening 72a, on the first resin layer 30a in the opening 72b, and on the resist mask 72 by evaporation. A metal layer 73 of Pt / Au is formed. Of the metal layer 73, the one deposited on the contact layer 55 becomes the ohmic layer 32a. The metal layer 62 is deposited on the first resin layer 30a in the opening 72b. In the vapor deposition process, the resist mask 72 contracts, and stress is applied to the position where the ends of the openings 72a and 72b are in contact. The end of the opening 72 a is close to the boundary between the mesa 50 and the protective film 56. For this reason, the stress from the resist mask 72 acts on the protective film 56 in the direction in which the protective film 56 is peeled off from the mesa 50. The magnitude of the stress is proportional to the volume of the resist mask 72.

  As described above, the volume of the resist mask 72 outside the two arm waveguides 24a and 24b is limited by the distance from the arm waveguides 24a and 24b to the opening 72b. For this reason, the volume of the resist mask 72 is reduced, and the stress can be reduced. Therefore, peeling of the protective film 56 from the mesa is less likely to occur. Further, between the arm waveguides 24a and 24b, the volume of the resist mask 72 is determined by the distance between the two openings 72a (for example, 50 μm). Since the volume of the resist mask 72 is small between the arm waveguides 24a to 24b, the stress acting on the protective film 56 is small, and the protective film 56 is difficult to peel off.

  As shown in FIG. 5D, the resist mask 72 is removed with a solvent, and the metal layer 73 on the resist mask 72 is also removed (lifted off). The ohmic layer 32a is located in the opening 60a of the protective film 60, and the metal layer 62 is located in the opening 60b. The ohmic layer 32a and the metal layer 62 are separated from each other, and the distance between them is 50 μm or less. The ohmic layer 32a and the metal layer 62 extend parallel to each other.

  As shown in FIG. 6A, a resist mask 74 is formed on the first resin layer 30a by photolithography. The resist mask 74 has a stripe-shaped opening 74a above the n-electrode layer 34a. The width of the opening 74a is larger than the width of the n-electrode layer 34a. The protective film 60 in the opening 74a is removed by dry etching to expose the first resin layer 30a above the n-electrode layer 34a. After the dry etching, the resist mask 74 is removed.

  As shown in FIG. 6B, another resist mask 76 is formed on the protective film 60 by photolithography. The resist mask 76 has a stripe-shaped opening 76a on the n-electrode layer 34a. The width of the opening 76a is larger than the width of the n-electrode layer 34a. The first resin layer 30a in the opening 76a is removed by dry etching to expose the upper surface of the n-electrode layer 34a. After the dry etching, the resist mask 76 is removed.

  As shown in FIG. 6C, the base layer 32b is formed on the protective film 60 and the ohmic layer 32a, for example, by sputtering, and the base layer 34b is formed on the n-electrode layer 34a. By plating using a mask (not shown), the Au layer 32c is formed on the base layer 32b, and the Au layer 34c layer is formed on the base layer 34b. Further, the base layer 38b and the Au layer 38c shown in FIG. 3B are also formed.

  As shown in FIG. 7A, the second resin layer 30b is formed on the first resin layer 30a. First, a BCB resin precursor is spin-coated. The BCB resin precursor is of a viscosity that fills the opening 60b and flattens the top surface of the resin after coating. Further, the number of rotations of spin coating is adjusted so that the thickness from the upper surface of the ohmic layer 32a to the upper surface of the second resin layer 30b is 1.3 μm. The precursor is thermally cured to form the second resin layer 30b. A protective film 64 is formed on the upper surface of the second resin layer 30b by a CVD method or the like.

  As shown in FIG. 7B, the protective film 64 and the second resin layer 30b are dry-etched, for example, to form an opening 30c through which the Au layer 32c on the arm waveguides 24a and 24b is exposed. A resist mask (not shown) used for dry etching is removed after dry etching.

  As shown in FIG. 8A, the base layer 32d is formed on the protective film 64 from the Au layer 32c by, for example, sputtering. Further, an Au layer 32e is formed on the base layer 32d by plating using a mask (not shown). Thereby, the modulation electrode 32 is formed. Further, the base layer 38d and the Au layer 38e shown in FIG. 3B are also formed.

  As shown in FIG. 8B, a protective film 66 that covers the Au layer 32e and the protective film 64 is formed by, eg, CVD. As shown in FIG. 3B, the protective film 66 on the pad is removed by photolithography and etching. Thereby, a semiconductor element is formed.

  According to the first embodiment, as shown in FIGS. 5A and 5B, the resist mask 72 has the opening 72a on the mesa 50 of the arm waveguides 24a and 24b. Adjacent openings 72b are provided. The volume of the resist mask 72 from the opening 72a to the opening 72b is small. For this reason, for example, even when the resist mask 72 contracts during etching or vapor deposition, the stress applied to the protective film 56 is reduced, and peeling of the protective film 56 is suppressed.

  As shown in FIG. 5B, the opening 72a and the opening 72b extend along the extending direction of the mesa (the left-right direction in FIG. 5B). For this reason, stress can be reduced in each part in the extending direction, and peeling of the protective film 56 can be effectively suppressed.

  Two mesas 50 are formed on the substrate 10, and the resist mask 72 has two openings 72 a corresponding to the mesas 50. As shown in FIGS. 5A and 5B, the opening 72 b is located between the opening 72 a and the end of the substrate 10. For this reason, the volume of the resist mask 72 contributing to the stress is reduced, and the stress is reduced. Further, since the volume of the resist mask 72 between the two mesas 50 is small, the stress is reduced. Thereby, peeling of the protective film 56 in the Mach-Zehnder modulator 20 can be suppressed.

  As shown in FIG. 5A, the protective film 60 exposed from each of the openings 72a and 72b is removed by etching using the resist mask 72. Thereafter, the ohmic layer 32a and the metal layer 62 are formed by vapor deposition, for example. The resist mask 72 may shrink during etching and vapor deposition. Since the volume of the resist mask 72 contributing to the stress is small, the stress can be reduced.

  The distance between the opening 72a and the opening 72b is preferably 50 μm or less. Thereby, stress can be reduced effectively. The distance may be 60 μm or less, 40 μm or less, for example.

  The upper surface of the first resin layer 30a is exposed from the opening 72b, the metal layer 62 is formed on the first resin layer 30a, and the second resin layer 30b is formed on the metal layer 62 and the first resin layer 30a. The arm waveguides 24a and 24b are protected by the resin layer 30, and the metal layer 62 and the modulation electrode 32 are insulated.

  The mesa 50 forms arm waveguides 24 a and 24 b that are optical waveguides, and the ohmic layer 32 a is included in the modulation electrode 32. Thereby, stress can be reduced in the mesa 50 of the optical waveguide, and peeling of the protective film 56 can be suppressed.

(Semiconductor element)
FIG. 9 is a cross-sectional view illustrating a multilevel modulator 200 according to the second embodiment. The description of the same configuration as that of the first embodiment is omitted. As shown in FIG. 9, two mesas 80 (second mesas) are formed, and the metal layer 62 is formed on the upper surface of the mesa 80. The mesa 80 is formed by the lower clad layer 51, the core layer 52, the upper clad layer 54, and the contact layer 55 like the mesa 50. The lower cladding layer 51 of the mesa 50 and the lower cladding layer 51 of the mesa 80 are separated, and the mesa 50 and the mesa 80 are not connected. The side surface of the mesa 80 is covered with a protective film 60. The mesa 50 and the mesa 80 extend in parallel.

(Semiconductor element manufacturing method)
FIG. 10A and FIG. 10B are cross-sectional views illustrating a method for manufacturing the multilevel modulator 200. FIG. 10C is a plan view illustrating a method for manufacturing the multi-level modulator 200, and shows the same state as FIG. As shown in FIG. 10A, a mesa 80 is formed together with the mesa 50. As shown in FIGS. 10B and 10C, the resist mask 72 has an opening 72 b at a position overlapping the mesa 80. The metal layer 62 is formed on the upper surface of the mesa 80. Other steps are the same as those in Example 1.

  According to the second embodiment, peeling of the protective film 60 from the mesas 50 and 80 can be suppressed. Further, the adhesion between the metal layer 62 and the contact layer 55 of the mesa 80 is higher than the adhesion between the metal layer 62 and the first resin layer 30a. For this reason, peeling of the metal layer 62 is suppressed.

  FIG. 11A is a plan view illustrating the method for manufacturing the multilevel modulator according to the third embodiment, and shows a state corresponding to FIG. The description of the same configuration as that of the first embodiment is omitted. As shown in FIG. 11A, the resist mask 72 has an opening 72a and a plurality of openings 72b. The plurality of openings 72b extend in the same direction as the opening 72a and are parallel to the opening 72a. The plurality of openings 72b are periodically arranged in the extending direction. A metal layer 62 is provided in the opening 72b. Therefore, a plurality of metal layers 62 parallel to the ohmic layer 32a are formed.

  According to the third embodiment, as in the first embodiment, the stress generated from the resist mask 72 can be reduced and the peeling of the protective film 56 can be suppressed. In order to reduce stress uniformly and suppress stress concentration, it is preferable that the plurality of openings 72b be periodically arranged in the extending direction.

(Modification)
FIG. 11B is a plan view illustrating the method for manufacturing the multilevel modulator according to the modification of the third embodiment, and shows a state corresponding to FIG. Mesa 80 and opening 72b are provided periodically. Other configurations are the same as those of the third embodiment.

  In the first to third embodiments, the case of a multi-level modulator is shown as an example. However, if the optical semiconductor element has a configuration in which the optical waveguide of the Mach-Zehnder modulator is embedded with a BCB resin film, other semiconductor elements are used. It may be the case.

DESCRIPTION OF SYMBOLS 10 Board | substrate 12 Input waveguide 14 Output waveguide 16a, 16b Optical coupler 20 Mach-Zehnder modulator 22a, 22b Optical coupler 24a, 24b Arm waveguide 30 Resin layer 30a 1st resin layer 30b 2nd resin layer 30c, 60a, 60b, 66a , 70a, 72a, 72b, 74a, 74b, 76a Opening 32 Modulating electrode 32a Ohmic layer 32b, 32d, 34b, 38b, 38d Underlayer 32c, 32e, 34c, 38e Au layer 34 Ground electrode 34a n electrode layer 36 Phase adjustment Electrode 38 Signal electrode pad 40 Ground electrode pad 42 DC electrode pad 50, 80 Mesa 51 Lower cladding layer 52 Core layer 54 Upper cladding layer 55 Contact layer 56, 60, 64, 66 Protective film 62 Metal layer 70, 72, 74, 76 resist mask 1 00, 200 Multilevel modulator

Claims (9)

Forming a first mesa on the semiconductor substrate;
Forming a first insulating film on a side surface of the first mesa;
After the step of forming the first insulating film, forming a first resin layer in which the first mesa is embedded;
Forming a resist mask having a first opening in which an upper surface of the first mesa is exposed and a second opening adjacent to the first opening on the upper surfaces of the semiconductor substrate and the first resin layer;
Forming a first metal layer in the first opening and a second metal layer in the second opening.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first opening and the second opening extend along a direction in which the first mesa extends. Two first mesas are formed on the semiconductor substrate;
The resist mask has two first openings corresponding to the two first mesas,
3. The method of manufacturing a semiconductor device according to claim 1, wherein the second opening is located between the two first openings and an end portion of the semiconductor substrate. Forming a second insulating film on the first mesa and the first resin layer;
Removing the second insulating film exposed from each of the first opening and the second opening by etching using the resist mask,
4. The method of manufacturing a semiconductor element according to claim 1, wherein a step of forming the second metal layer is performed after the step of removing the second insulating film. 5.   The method for manufacturing a semiconductor element according to claim 1, wherein a distance between the first opening and the second opening is 50 μm or less. An upper surface of the first resin layer is exposed from the second opening,
The second metal layer is formed on the first resin layer;
6. The method of manufacturing a semiconductor element according to claim 1, further comprising a step of forming a second resin layer on the second metal layer and the first resin layer. Forming a second mesa on the semiconductor substrate;
An upper surface of the second mesa is exposed from the second opening;
The method of manufacturing a semiconductor device according to claim 1, wherein the second metal layer is formed on an upper surface of the second mesa.   8. The method of manufacturing a semiconductor device according to claim 1, wherein the resist mask has a plurality of the second openings arranged along the extending direction of the first mesa. 9. The first mesa is an optical waveguide mesa;
9. The method of manufacturing a semiconductor device according to claim 1, wherein the first metal layer is included in a modulation electrode that modulates light propagating through the optical waveguide mesa. 10.

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