JP2018142800A - Headset jack circuit and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a headset jack circuit capable of reducing crosstalk when using a headset of different rating.SOLUTION: A headset jack circuit includes a jack for loading a headset plug, a first line for connection with 3 poles of the headset plug via the jack, a second line for connection with 4 poles of the headset plug via the jack, first switch means for changing over the connection destination of a microphone amplifier and the GND to the first line or the second line, according to the signal levels of the first and second lines, and second switch means for connecting the first line or the second line to the GND, according to the signal levels of the first and second lines.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a headset jack circuit and an electronic device.

  For example, headsets are used in various electronic devices. Headset plug standards include the OMTP standard (Open Mobile Terminal Platform) and the CTIA standard (Cellular Telecommunications Internet Association). For example, the OMTP standard is used in Apple (registered trademark), and the CTIA standard is used in Nokia (registered trademark). In the CTIA standard and the OMTP standard, four poles are formed from the tip side to the back part. In the OTMP standard, the left audio, the right audio, GND, and the microphone correspond to the poles in order from the pole at the tip. In the CMTP standard, the third and fourth poles from the tip are opposite to the OMTP standard.

  When both OMTP standard and CTIA standard headset plugs are used with one headset jack, it is necessary to detect whether the headset plug is an OMTP standard or a CTIA standard. Also, crosstalk needs to be considered when using headset plugs of different standards.

Special table 2017-504284

  The present invention has been made in view of the above, and an object of the present invention is to provide a headset jack circuit and an electronic apparatus that can reduce crosstalk when using headsets of different standards.

  In order to solve the above-described problems and achieve the object, the present invention includes a jack for mounting a headset plug, and a first line connected to the three poles of the headset plug via the jack. , The second line connected to the four poles of the headset plug via the jack, and the connection destination of the microphone amplifier and GND according to the signal level of the first line and the second line, First switch means for switching to the first line or the second line, and the GND of the first line or the second line according to the signal level of the first line and the second line And a second switch means for connecting to.

  According to a preferred aspect of the present invention, when an OMTP standard headset plug is attached to the jack, the first switch means connects the microphone amplifier to the second line. Preferably, the connection to the GND is switched to the first line, and the second switch means connects the second line to the GND.

  According to a preferred aspect of the present invention, when a CTIA standard headset plug is attached to the jack, the first switch means switches the input destination of the microphone amplifier to the first line. It is preferable that the connection to the GND is switched to the second line, and the second switch means connects the first line to the GND.

  According to a preferred aspect of the present invention, it is desirable that the second switching means includes an Nch type MOS transistor.

  According to a preferred aspect of the present invention, it is desirable that the second switching means further includes a NAND circuit and an Ex-NOR circuit.

  According to the present invention, it is possible to reduce crosstalk when using headsets of different standards.

FIG. 1 is a diagram showing a schematic configuration of a notebook PC according to the present embodiment. FIG. 2 is a diagram for explaining a four-pole type headset plug. FIG. 3 is a schematic diagram of a configuration for detecting a headset plug of the headset jack circuit. FIG. 4 is a diagram showing a state where an OMTP standard headset is attached to the headset jack of the headset jack circuit of FIG. FIG. 5-A is a schematic diagram of FIG. 4 for explaining crosstalk caused by the sleeve of FIG. FIG. 5-B is a schematic diagram showing lines between the CODEC and the headset jack. FIG. 6 is a diagram showing a configuration in which measures for reducing crosstalk are applied to the headset jack circuit of FIG. FIG. 7 is a diagram showing a more specific configuration of the headset jack circuit of FIG. FIG. 8 is a diagram illustrating another configuration example of the headset jack circuit. FIG. 9 is a diagram showing an operation table of the headset jack circuit of FIG.

  Hereinafter, embodiments of the headset jack circuit and the electronic device according to the present embodiment will be described. Although the components of the present invention are generally illustrated in the drawings herein, it can be readily understood that they may be arranged and designed in a wide variety of configurations with various configurations. Accordingly, the following more detailed description of embodiments of the apparatus, method, and embodiments of the present invention is not intended to limit the scope of the invention as set forth in the claims, but is merely illustrative of selected embodiments of the invention. It is intended as an example, and is merely illustrative of selected embodiments of the apparatus, system and method consistent with the present invention as set forth in the claims herein. Those skilled in the art will appreciate that the present invention may be implemented without one or more of the specific details or with other methods, components, and materials.

(Embodiment)
An applied electronic apparatus to which the headset jack circuit according to the present embodiment is applied will be described. The electronic device is, for example, a notebook PC, a desktop PC, a smartphone, a mobile phone terminal, a TV device, an audio device, or the like. In the following example, a notebook PC will be described as an example of an electronic device.

  FIG. 1 is a diagram showing a schematic configuration of a notebook PC according to the present embodiment. As shown in FIG. 1, in a notebook PC 1, a display side housing 2 and a main body side housing 3 are connected via a pair of hinges 4 so as to be opened and closed.

  The display-side casing 2 houses an LCD (liquid crystal display) 8. The main body side housing 3 has various electrical components including a headset jack circuit (see FIG. 2) mounted therein, and a keyboard device 6 and a touch pad device 7 mounted on the surface thereof. In this specification, “headset” includes a combination of a microphone and a headphone or a headset, a single headphone, and a single earphone.

  A headset jack 20 of a headset jack circuit is provided on the side surface of the main body side housing 3. The headset jack circuit 10 is compatible with both 4-pole type OMTP standard and CTIA standard headset plugs.

  The headset 100 includes a 4-pole type headset plug 101 and a microphone 102. 2A and 2B are diagrams for explaining a four-pole type headset plug 101. FIG. 2A shows the OMTP standard and FIG. 2B shows the CTIA standard.

  In FIG. 2, a four-pole headset plug 101 includes four poles and is referred to as Tip, Ring1, Ring2, and Sleeve from the tip. An insulating ring is provided between each pole.

  As shown in FIG. 2A, in the OMTP standard, Tip = left audio (L), Ring1 = right audio (R), Ring2 = GND (G), and Sleep = microphone (M). Further, as shown in FIG. 2B, in the CTIA standard, Tip = left audio (L), Ring1 = right audio (R), Ring2 = microphone (M), and Sleep = GND (G). In the OMTP standard and the OMTP standard, Ring2 and Sleeve microphones and GND are reversed.

  FIG. 3 is a schematic diagram of a configuration for detecting a headset plug of the headset jack circuit 10. FIG. 3 schematically shows only a part necessary for detecting the headset jack. FIG. 4 is a diagram showing a state where the headset 100 of the OMTP standard is attached to the headset jack 20 of the headset jack circuit 10 of FIG.

  In FIG. 3, the headset jack circuit 10 includes a headset jack 20 and a CODEC 30. Headset jack 20 is connected to lines 41 to 44 that connect to Tip, Ring1, Ring2, and Sleeve of headset plug 101 when headset plug 101 is attached.

  The CODEC 30 includes switch means 31 and 32, a left signal amplifier 33, a right signal amplifier 34, a microphone amplifier 35, and a level detection means 36. The switch means 31 and 32 and the level detection means 36 constitute a first switching means.

  The left signal amplifier 33 amplifies the left audio signal and outputs it to the Tip of the headset plug 101 via the line 41. The right signal amplifier 34 amplifies the right audio signal and outputs it to the Ring 1 of the headset plug 101 via the line 42.

  The switch means 31 has an input side terminal connected to the line 43 (Ring2: first line) of the headset plug 101, an output side A terminal connected to AGND, and an output side B terminal connected to the microphone amplifier 35. It is connected. The switch unit 31 switches the connection to the A terminal or the B terminal according to the instruction of the level detection unit 36.

  The switch means 32 has an input-side terminal connected to a line 44 (Sleeve: second line), an output-side A terminal connected to the microphone amplifier 35, and an output-side B terminal connected to AGND. The switch unit 32 switches the connection to the A terminal or the B terminal according to the instruction of the level detection unit 36.

  The microphone amplifier 35 amplifies the microphone signal input via the switch means 31 and 32. The level detection means 36 switches the connection of the switch means 31 and 32 according to the signal levels of the line 43 (Ring 2) and the line 44 (Sleeve).

  The level detection means 36 compares the signal level (voltage level) of the line 43 (Ring 2) and the line 44 (Sleeve), and if the line 44 (Sleeve) is greater, the level detection means 36 determines the output destination of the switch means 31 and 32. Switch to the A terminal. As shown in FIG. 4, when the headset plug 101 of the OMTP standard is attached to the headset jack 20, the signal level of the line 44 (Sleeve) becomes higher than the signal level (voltage level) of the line 43 (Ring2). . Thereby, the line 44 (Sleeve) is connected to the microphone amplifier 35, and the line 43 (Ring2) is connected to AGND. Thus, the headset plug 101 of the OMTP standard can be detected and used.

  On the other hand, when the line 43 (Ring 2) is larger, the level detection means 36 switches the output destination of the switch means 31 and 32 to the B terminal. When the CTIA standard headset plug 101 is attached to the headset jack 20, the signal level of the line 43 (Ring2) becomes higher than the signal level (voltage level) of the line 44 (Sleeve). Thereby, the line 43 (Ring 2) is connected to the microphone amplifier 35, and the line 44 (Sleeve) is connected to AGND. In this manner, the CTIA standard headset plug 101 can be detected and used.

  As described above, according to the above configuration, the first switching means connects the connection destination of the microphone amplifier 35 and the GND to the line 43 according to the signal level of the line 43 (Ring2) and the line 44 (Sleeve). Since switching to (Ring 2) or line 44 (Sleeve), it becomes possible to detect the headset plug 101 of the OMTP standard and the CTIA standard with a simple configuration.

  FIG. 5-A is a schematic diagram of FIG. 4 for explaining crosstalk caused by the line 44 (Sleeve) in FIG. FIG. 5-B is a schematic diagram showing lines between the CODEC 20 and the headset 100.

  In FIG. 4, the GND line of the headset 100 is connected to the sleeve of the headset plug 101. As shown in FIG. 5B, the line 44 (Sleeve) is a line connected to the GND line of the headset 100. However, as the path becomes longer, the DC resistance DCR increases and crosstalk occurs.

Specifically, as shown in FIG. 5-A, when only the left audio signal is activated when the connection of the switch means 31 and 32 is the A terminal, the current I is observed on the line 41 (Tip). When the return signal flows through the line 44 (Sleeve) and the DC resistance of the line 44 (Sleeve) is DCR, V _LCH = V _OUT -DCR × (current I) of the line 41 (Tip). In this case, an inverted amplitude due to DCR × I is observed in the line 42 (Ring 1) which is not activated. V _RCH of the line 42 (Ring1) = DCR × (−current I). In this way, crosstalk occurs and left audio leaks to the right.

  In order to reduce the crosstalk, the DC resistance DCR of the line 44 (Sleeve) may be reduced, and the length of the line 44 (Sleeve) may be shortened or thickened. There are also many.

  Therefore, in the present embodiment, the second switch means for selectively connecting the line 44 (Sleeve) and the line 43 (Ring2) to AGND having a low resistance value is provided to reduce crosstalk.

  FIG. 6 is a diagram showing a configuration in which measures for reducing crosstalk are taken in the headset jack circuit 10 of FIG. In FIG. 6, the switch means 50 has an input side connected to a line 44 (Sleeve) and a line 43 (Ring 2), and an output side connected to AGND. The switch unit 50 switches the connection destination of AGND between the line 44 (Sleeve) and the line 43 (Ring 2) in accordance with an instruction from the level detection unit 36. The switch means 50 and the level detection means 36 constitute a second switch means.

  The level detection means 36 compares the signal level (voltage level) between the line 43 (Ring 2) and the line 44 (Sleeve), and the connection destination to the AGND is connected to the switch means 50 by the line 44 (Sleeve) or the line 43 ( Switch to Ring2).

  When the signal level of the line 44 (Sleeve) is higher than the line 43 (Ring 2), the level detecting unit 36 causes the switch unit 50 to connect the line 44 (Sleeve) to AGND. As a result, the DC resistance DCR of the line 44 (Sleeve) can be reduced, and crosstalk can be reduced.

  On the other hand, when the signal level of the line 43 (Ring2) is higher than the line 44 (Sleeve), the level detecting unit 36 causes the switch unit 50 to connect the line 43 (Ring2) to AGND.

  According to the above configuration, the second switch means connects the line 43 (Ring2) or the line 44 (Sleeve) to the GND according to the signal level of the line 43 (Ring2) and the line 44 (Sleeve). Therefore, it is possible to reduce crosstalk due to the line 44 (Sleeve).

  FIG. 7 is a diagram showing a more specific circuit of the headset jack circuit 10 of FIG. In the circuit shown in FIG. 7, it is a schematic diagram showing an outline of a configuration example in the case where an Nch-MOS type transistor is used as the switch means.

  The Nch-MOS transistor Tr1 has its gate G connected to the switch control means 60, its drain D connected to the line 44 (Sleeve), and its source S connected to AGND. The Nch-MOS transistor Tr2 has its gate G connected to the switching control means 60, its drain D connected to the line 43 (Ring2), and its source S connected to AGND. The transistors Tr1 and Tr2 and the switch control means 60 constitute second switch means. Although an Nch-MOS type transistor is used here, a Pch-MOS type transistor may be used.

  The switch control means 60 turns on / off the transistors Tr1 and Tr2 based on the output of the level detection means 36.

  When the signal level of the line 44 (Sleeve) is higher than the line 43 (Ring2), the switch control unit 60 turns on the transistor Tr1 to connect the line 44 (Sleeve) to AGND. Thereby, the direct current resistance DCR of the line 44 (Sleeve) can be reduced, and the crosstalk caused by the line 44 (Sleeve) can be reduced.

  On the other hand, when the signal level of the line 43 (Ring2) is higher than the line 44 (Sleeve), the switch control means 60 turns on the transistor Tr2 to connect the line 43 (Ring2) to AGND.

  FIG. 8 is a diagram showing another configuration example of the headset jack circuit 10 of FIG. FIG. 9 is a diagram showing an operation table of the headset jack circuit 10 of FIG.

  The transistor Tr1 has its gate G connected to one terminal side of the switch means S1, its drain D connected to the line 44 (Sleeve), and its source S connected to AGND. The transistor Tr2 has its gate G connected to one terminal side of the switch means S2, its drain D connected to the line 43 (Ring2), and its source S connected to AGND.

  The switch means S1 has one terminal side connected to the gate G of the transistor Tr1, the two terminal side A terminal connected to the NAND circuit 80, and the B terminal connected to the line 44 (Sleeve). The connection of the switch means S1 is switched by the output of the EX NOR circuit 70.

  The switch means S2 has one terminal connected to the gate of the transistor Tr2, the output A terminal connected to the line 43 (Ring2), and the B terminal connected to the NAND circuit 80. The connection of the switch means S2 is switched by the output of the EX NOR circuit 70.

  The NAND circuit 80 has an input side connected to the line 43 (Ring 2) and a line 44 (Sleeve), and an output side connected to the A terminal of the switch means S1 and the B terminal of the switch means S2.

  The EX NOR circuit 70 has an input side connected to a line 43 (Ring2) and a line 44 (Sleeve), and an output side connected to the input terminals of the switch means S1 and the switch means S2.

  In the above configuration, the transistors Tr1 and Tr2, the switch means S1 and S2, the EX NOR circuit 70, and the NAND circuit 80 constitute second switch means.

  As shown in FIG. 9, when nothing is attached to the headset jack 20 (Open), the line 43 (Ring2) is High, the line 44 (Sleeve) is High, and the switch means S1 and S2 are on the A terminal side. The transistors Tr1 and Tr2 are turned off.

  When a three-pole headset is attached to the headset jack 20, the line 43 (Ring2) is Low, the line 44 (Sleeve) is Low, the switch means S1 and S2 are connected to the A terminal side, the transistors Tr1 and Tr2 is turned ON.

  When an OMTP standard headset is attached to the headset jack 20, the line 43 (Ring2) is Low, the line 44 (Sleeve) is High, the switch means S1 and S2 are connected to the B terminal side, and the transistor Tr1 is ON, transistor Tr2 is OFF. As a result, the line 44 (Sleeve) is connected to AGND, the DC resistance of the line 44 (Sleeve) can be reduced, and crosstalk can be reduced.

  When a headset of CTIA standard is connected to the headset jack 20, the line 43 (Ring2) is High, the line 44 (Sleeve) is Low, the switch means S1 and S2 are connected to the B terminal side, and the transistor Tr1 is OFF, transistor Tr2 is turned ON. Thereby, the line 43 (Ring 2) is connected to AGND.

  According to the circuit configuration of FIG. 8, in addition to a 4-pole OMTP standard and CTIA standard headset jack, a 3-pole headset jack can also be used.

1 Notebook PC
2 Display-side housing 3 Body-side housing 4 Hinge 6 Keyboard device 7 Touchpad device 8 LCD (Liquid Crystal Display)
10 Headset jack circuit 20 Headset jack 30 CODEC
31, 32 Switch means 33 Left signal amplifier 34 Right signal amplifier 35 Microphone amplifier 36 Level detection means 41-44 Line 50 Switch means 60 Switch control means 70 EX NOR circuit 80 NAND circuit 100 Headset 101 Headset plug 102 Microphone Tr1, Tr2 Transistor S1, S2 switch means

Claims (6)

A jack to attach the headset plug,
A first line connected to the three poles of the headset plug via the jack;
A second line connected to the four poles of the headset plug via the jack;
First switch means for switching the connection destination of the microphone amplifier and GND to the first line or the second line according to the signal levels of the first line and the second line;
Second switch means for connecting the first line or the second line to GND in accordance with signal levels of the first line and the second line;
A headset jack circuit characterized by comprising: When an OMTP standard headset plug is attached to the jack, the first switch means connects the microphone amplifier to the second line and connects to the GND to the first line. switching,
2. The headset jack circuit according to claim 1, wherein the second switch means connects the second line to GND. When a CTIA standard headset plug is attached to the jack, the first switch means switches the input destination of the microphone amplifier to the first line, and connects the GND to the second line. Switch to
2. The headset jack circuit according to claim 1, wherein the second switch means connects the first line to GND.   The headset jack circuit according to claim 1, wherein the second switching unit includes an Nch type MOS transistor.   The headset jack circuit according to claim 4, wherein the second switching unit further includes a NAND circuit and an Ex-NOR circuit.   An electronic apparatus comprising the headset jack circuit according to any one of claims 1 to 5.

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