JP2018137522A - High frequency module and communication device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high frequency module suitable for shortening the start time of an amplification circuit.SOLUTION: A high frequency module 10 comprises a plurality of amplifiers 41 to 43 and a control unit 47. The plurality of amplifiers stop when a first control voltage is applied, and operate when a second control voltage higher than the first control voltage is applied. The control unit receives serial data SDATA containing first information and second information following the first information. When the first information is information for specifying the plurality of amplifiers 41 to 43, the control unit applies a third control voltage higher than the first control voltage to the plurality of amplifiers 41 to 43. When the second information is information for instructing the stop or operation of each of the plurality of amplifiers 41 to 43, the control unit applies the first control voltage to the amplifier for which stop was instructed and applies the second control voltage to the amplifier for which operation was instructed.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a high frequency module and a communication device.

  Conventionally, high-frequency modules that amplify high-frequency signals are used in various communication devices such as wireless terminal devices. For example, as represented by a multiband high-frequency module in which an amplifier circuit is provided for each frequency band, there is also a high-frequency module that has a plurality of amplifier circuits and operates only an amplifier circuit that actually performs transmission and reception operations.

  In a high-frequency module that operates individual amplifier circuits only in a timely manner, it is desirable that the startup time of the amplifier circuits (that is, the transition time from the stop state to the operation state) is short. In order to shorten the startup time of the amplifier circuit, a switch is provided in the bias voltage supply path to the amplifier element, and the switch is switched when the amplifier circuit is started to temporarily reduce the resistance value of the bias voltage supply path. There is technology (Patent Document 1). According to the amplifier circuit of Patent Document 1, the startup time of the amplifier circuit is shortened by increasing the precharge of the bias voltage.

JP 2010-183473 A

  However, according to the conventional amplifier circuit, since the switch is provided in the supply path of the bias voltage to the amplifier element, the switch becomes a noise generation source, which is disadvantageous in terms of miniaturization.

  In general, the operation of the high-frequency module is controlled by serial data. When serial data is used to control the stop and operation of the amplifier circuit included in the high-frequency module, the serial data transmission time is added as a delay factor for starting the amplifier circuit.

  Therefore, an object of the present invention is to provide a high-frequency module suitable for shortening the startup time of an amplifier circuit and a communication device using the high-frequency module.

  In order to achieve the above object, the high-frequency module according to one aspect of the present invention stops when a first control voltage is applied, and when a second control voltage higher than the first control voltage is applied. Receive serial data including a plurality of operating amplifiers, first information, and second information subsequent to the first information, wherein the first information is information designating the plurality of amplifiers. For example, when a third control voltage higher than the first control voltage is applied to the plurality of amplifiers, and then the second information is information instructing to stop or operate each of the plurality of amplifiers, A control unit that applies the first control voltage to the amplifier instructed to stop and applies the second control voltage to the amplifier instructed to operate.

  According to this configuration, when a plurality of amplifiers are designated by the first information, the control voltage is thereafter set regardless of whether or not each amplifier is instructed to stop or operate by the second information. The third voltage can be higher than the first voltage. Therefore, when the amplifier is actually operated, the control voltage may be increased from the third voltage to the second voltage, and the control voltage is increased from the first voltage to the second voltage in full width. Compared to the case, the startup time of the amplifier is shortened.

  Further, after the application of the third control voltage, if the second information is not information instructing the stop or operation of each of the plurality of amplifiers after the application of the third control voltage, The same control voltage as that applied before the application of the third control voltage may be applied.

  According to this configuration, when the stop or operation of each amplifier is not instructed by the second information, each amplifier can be returned to the original stop or operation state.

  Further, the third voltage may be an upper limit voltage at which the amplifier does not operate.

  According to this configuration, it is possible to avoid a malfunction in which an amplifier that should not be operated is operated by the third voltage.

  The controller may continue to apply the second control voltage to the operating amplifier when applying the third control voltage to the plurality of amplifiers.

  According to this configuration, it can be avoided that the control voltage of the amplifier that should continue to operate decreases from the second voltage to the third voltage and the operation becomes unstable.

  The high-frequency module may include a plurality of low-noise amplifier circuit blocks, and the serial data may specify the plurality of low-noise amplifier circuit blocks with first information.

  According to this configuration, when the operations of the plurality of low-noise amplifier circuit blocks of the high-frequency module are controlled by serial data, the startup time of the amplifier circuit in the low-noise amplifier circuit block can be shortened.

  In addition, the communication device according to an aspect of the present invention transmits the serial data to the high-frequency module and the high-frequency module, transmits a high-frequency transmission signal to the high-frequency module, and receives a high-frequency reception signal from the high-frequency module. An RF signal processing circuit.

  According to this configuration, it is possible to obtain a multiband communication apparatus capable of switching frequency bands at high speed, for example, by taking advantage of the characteristics of the high frequency module that the startup time of the amplifier circuit is short.

  According to the high frequency module and the communication device of the present invention, a high frequency module suitable for shortening the startup time of the amplifier circuit and a communication device using the high frequency module can be obtained.

It is a block diagram which shows an example of a functional structure of the communication apparatus containing the high frequency module which concerns on embodiment. It is a figure which shows an example of the format of the serial data which concerns on embodiment. It is a block diagram which shows an example of a functional structure of the LNA circuit which concerns on embodiment. 6 is a timing chart showing an operation example of the LNA circuit according to the embodiment. It is a block diagram which shows an example of a functional structure of the communication apparatus containing the high frequency module which concerns on a modification.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. It should be noted that each of the embodiments described below shows a comprehensive or specific example. Numerical values, shapes, materials, constituent elements, arrangement of constituent elements, connection forms, and the like shown in the following embodiments are merely examples, and are not intended to limit the present invention. Among the constituent elements in the following embodiments, constituent elements not described in the independent claims are described as optional constituent elements. In addition, the size or size ratio of the components shown in the drawings is not necessarily strict.

(Embodiment)
A high-frequency module according to an embodiment and a communication device using the high-frequency module in a front-end circuit will be described. Below, the outline | summary of a communication apparatus is demonstrated first, and the detail of a high frequency module is demonstrated after that.

  FIG. 1 is a block diagram illustrating an example of a functional configuration of a communication device according to an embodiment.

  As shown in FIG. 1, the communication device 1 includes a front end circuit 10, an RF signal processing circuit 20, and a baseband signal processing circuit 30. The front end circuit 10 includes a radio frequency (RF) module having a low noise amplification (LNA) circuit 40, a power amplification (PA) circuit 50, a switch (SW) circuit 60, and a duplexer 70.

  The front end circuit 10 amplifies the transmission RF signal generated by the RF signal processing circuit 20 by the PA circuit 50 and supplies the amplified signal to the antenna 80 via the SW circuit 60 and the duplexer 70. Also, the received RF signal received by the antenna 80 is amplified by the LNA circuit 40 via the duplexer 70 and the SW circuit 60 and supplied to the RF signal processing circuit 20.

  The RF signal processing circuit 20 converts the transmission signal generated by the baseband signal processing circuit 30 into a transmission RF signal and supplies it to the front end circuit 10. Such conversion may include modulation and up-conversion of the signal. Further, the reception RF signal received from the front end circuit 10 is converted into a reception signal and supplied to the baseband signal processing circuit 30. The conversion may include signal demodulation and down-conversion. The RF signal processing circuit 20 may be composed of a high frequency integrated circuit (RFIC) chip.

  The baseband signal processing circuit 30 converts transmission data generated by the application device / application software into a transmission signal and supplies the transmission signal to the RF signal processing circuit 20. The conversion may include data compression, multiplexing, and error correction code addition. Also, the received signal received from the RF signal processing circuit 20 is converted into received data and supplied to the application device / application software. Such conversion may include data decompression, demultiplexing, and error correction. The baseband signal processing circuit 30 may be configured with a baseband integrated circuit (BBIC) chip.

  The application device / application software performs application operations such as voice call and image display using the transmission data and the reception data.

  Next, the RF module constituting the front end circuit 10 will be described. Hereinafter, for convenience, the RF module is not distinguished from the front end circuit 10 and is referred to by the same reference numeral.

  The RF module 10 is a composite part that processes high-frequency signals in a plurality of frequency bands, and includes a plurality of circuit blocks formed on a single substrate. The plurality of circuit blocks may include, for example, the LNA circuit 40, the PA circuit 50, the SW circuit 60, and the duplexer 70.

  The LNA circuit 40 includes low noise amplifiers (LNA) 41 to 43, filters 44 to 46, and an LNA control unit 47.

  The LNAs 41 to 43 and the filters 44 to 46 are provided in a plurality of signal paths corresponding to different frequency bands. Among the LNAs 41 to 43, the LNA provided in the signal path of the frequency band during the reception operation is activated, and the other LNAs are stopped. The stop and operation of the LNAs 41 to 43 are controlled by the LNA control unit 47. The stopped state of the LNA may be referred to as a disabled state or a power saving mode.

  The PA circuit 50 includes power amplifiers (PA) 51 to 53, filters 54 to 56, and a PA control unit 57.

  The PAs 51 to 53 and the filters 54 to 56 are provided in signal paths corresponding to different frequency bands. Among the PAs 51 to 53, PAs provided in the signal path of the frequency band during the transmission operation are activated, and the other PAs are stopped. The stop and operation of the PAs 51 to 53 are controlled by the PA control unit 57. The stop state of the PA may be referred to as a disabled state or a power saving mode.

  The SW circuit 60 includes switches (SW) 61 and 62 and an SW control unit 63.

  The SW 61 connects the signal path of the frequency band during the reception operation in the LNA circuit 40 to the duplexer 70. The SW 62 connects the signal path of the frequency band during the transmission operation in the PA circuit 50 to the duplexer 70. Switching of the connections of the SWs 61 and 62 is controlled by the SW control unit 63.

  The RF signal processing circuit 20 manages in which frequency band the transmission operation and the reception operation are performed.

  The RF signal processing circuit 20 instructs the LNA circuit 40 and the PA circuit 50 to stop or operate the LNAs 41 to 43 and PAs 51 to 53 in accordance with the frequency band for performing the transmission operation and the reception operation, and the SW circuit 60. To instruct the connection in the SWs 61 and 62.

  The instruction may be performed using serial data. In that case, the RF signal processing circuit 20 sends serial data instructing stop or operation of the LNAs 41 to 43 and PAs 51 to 53 and connection in the SWs 61 and 62 to the signal line BL. The LNA circuit 40, the PA circuit 50, and the SW circuit 60 acquire the serial data from the signal line BL, and switch or stop the LNAs 41 to 43 and PAs 51 to 53, and the connections of the SWs 61 and 62.

  In the following, the control of the circuit block by serial data, in particular, the shortening of the startup time of the amplifier will be described with an example of the LNA circuit 40.

  FIG. 2 is a diagram illustrating an example of a format of serial data. The serial data in FIG. 2 includes a clock SCLK and serial data SDATA. Following the start bit S, the serial data SDATA includes slave addresses SA3 to SA0, a bit string 0b010 representing a register write command, register addresses RA4 to RA0, and data D7 to D0.

  Slave addresses SA3 to SA0 specify a circuit block (for example, LNA circuit 40). The register addresses RA4 to RA0 designate registers to which data is written (for example, registers provided in the LNA control unit 47 for recording the power mode, details will be described later). Data D7 to D0 represent data (for example, data instructing stop or operation of the LNAs 41 to 43) to be written in the registers.

  Here, the slave addresses SA3 to SA0 are an example of the first information. The bit string 0b010 representing the register write command, the register addresses RA4 to RA0, and the data D7 to D0 are an example of the second information subsequent to the first information.

  FIG. 3 is a block diagram showing an example of a functional configuration of the LNA circuit 40, and details of the LNA control unit 47 are shown. As illustrated in FIG. 3, the LNA control unit 47 includes a receiver 471, a register unit 472, a comparator 475, a timing generator 476, and a voltage generator 477.

  The receiver 471 receives serial data SDATA from the signal line BL in synchronization with the clock SCLK, and controls writing of the received serial data SDATA to the register unit 472. Specifically, at the end of the serial data SDATA, the write enable signal WE is output while supplying the register addresses RA4 to RA0 and the data D7 to D0 included in the serial data SDATA to the register unit 472. Also, the slave addresses SA3 to SA0 included in the serial data SDATA are output before receiving the subsequent portion of the serial data.

  The register unit 472 includes a plurality of registers specified by register addresses RA4 to RA0. The plurality of registers include a USID (unique slave ID) register 473 and a PM (power mode) register 474.

  The USID register 473 holds in advance a unique slave address value USID for designating the LNA circuit 40.

  The PM register 474 holds power mode data PM instructing to stop or operate the LNAs 41 to 43. Each bit of the power mode data PM corresponds to one LNA, and instructs to stop or operate the corresponding LNA. For example, the bit values 0 or 1 of the bits PM7, PM1, and PM0 of the power mode data PM may indicate the stop or operation of the LNAs 41, 42, and 43, respectively.

  In the PM register 474, data D7 to D0 in the register write command having the slave addresses SA3 to SA0 of the LNA circuit 40 and the register addresses RA4 to RA0 of the PM register 474 are written as power mode data PM.

  The comparator 475 compares the slave addresses SA3 to SA0 output from the receiver 471 with the USID held in the USID register 473, and outputs a match signal Match if they match.

  The timing generator 476 outputs the pre-drive signal PreDrive during the period from the output of the match signal Match to the end of the serial data SDATA. For example, the timing generator 476 may output the pre-drive signal PreDrive by counting the clock SCLK until the end of the serial data SDATA after outputting the match signal Match.

  The voltage generator 477 generates variable control voltages V7 to V0 for controlling stop or operation for each LNA according to the power mode data PM and the pre-drive signal PreDrive, and applies the generated control voltages V7 to V0 to the LNAs 41 to 43. For example, the control voltages V7, V1, and V0 may control the stop and operation of the LNAs 41, 42, and 43, respectively.

  The control voltages V7 to 0 are, for example, bias voltages that determine the operating points of the transistor elements constituting the corresponding LNAs 41 to 43, and the LNAs 41 to 43 amplify the high-frequency signal superimposed on the bias voltage with the transistor elements. Configured. In such a configuration, the LNAs 41 to 43 stop the amplification operation when a control voltage equal to or lower than the threshold voltage of the transistor element is applied, and when a control voltage higher than the threshold voltage is applied. Operate.

  The control voltages V7 to 0 are not limited to the bias voltage to the transistor elements, but may be the power supply voltage itself supplied to the LNAs 41 to 43.

  FIG. 4 is a timing chart showing an operation example of the LNA circuit 40 configured as described above. FIG. 4 shows an example in which the LNA 43 is stopped and the LNA 42 is started according to the serial data SDATA.

  In FIG. 4, a voltage Vdis is a control voltage for stopping the LNA, and is output when the stop of the corresponding LNA is instructed by the power mode data PM and the pre-drive signal PreDrive is not output.

  The voltage Vena is a control voltage that operates the LNA, and is output to the LNA that is instructed to operate by the power mode data PM.

  The voltage Vpre is a control voltage newly provided to speed up the start of the LNA, and is output only while the pre-drive signal PreDrive is being output to the LNA instructed to stop by the power mode data PM. The The voltage Vpre is higher than the voltage Vdis and may be an upper limit voltage at which the LNA does not operate (for example, a threshold voltage of a transistor constituting the LNA).

  Here, the voltage Vdis, the voltage Vena, and the voltage Vpre are examples of the first voltage, the second voltage, and the third voltage, respectively.

  At time T0, reception of serial data SDATA is started. At this time, the PM register 474 holds the power mode data PM having values instructing the stop of the LNAs 41 and 42 and the operation of the LNA 43. The voltage generator 477 generates the voltage Vena as the control voltage V0 according to the power mode data PM, and generates the voltage Vdis as the control voltages V1 and V7.

  At time T1, reception of the slave addresses SA3 to SA0 in the serial data SDATA is completed. The comparator 475 outputs a match signal Match when the received slave addresses SA3 to SA0 match the USID held in the USID register 473, and the timing generator 476 outputs the pre-drive signal PreDrive. Start.

  When the pre-drive signal PreDrive is output, the voltage generator 477 generates the voltage Vpre as the control voltages V1 and V7 for the stopped LNAs 42 and 41 according to the power mode data PM. The control voltages V1 and V7 actually increase from the voltage Vdis to the voltage Vpre with a time constant determined according to the signal line and the capacitance component (gate capacitance of the transistor elements) of the LNAs 41 and 42 (thick solid line). On the other hand, the voltage generator 477 continues to generate the voltage Vena as the control voltage V0 for the operating LNA 43 (dotted line).

  At time T2, reception of serial data SDATA is completed. The receiver 471 outputs a write enable signal WE, and the power mode data PM is updated to a value that instructs the LNAs 41 and 43 to stop and the LNA 42 to operate. The timing generator 476 stops the pre-drive signal PreDrive.

  When the pre-drive signal PreDrive is stopped, the voltage generator 477 generates the voltage Vdis as the control voltages V0 and V7 according to the updated power mode data PM, and generates the voltage Vena as the control voltage V1.

  The control voltage V0 drops from the voltage Vena to the voltage Vdis, and the LNA 43 is stopped (dotted line). The control voltage V1 rises from the voltage Vpre to the voltage Vena, and the LNA 42 is in a stable operating state by the time T3 (thick solid line). The control voltage V7 drops from the voltage Vpre to the voltage Vdis, and the LNA 41 returns to the stopped state without being activated (thick broken line).

  For comparison, FIG. 4 shows the control voltage V1 when the voltage Vpre is not used (thin line). Since the control voltage V1 of the comparative example needs to rise in full width from the voltage Vdis to the voltage Vena after time T2, according to the control voltage V1 of the comparative example, the time T4 when the LNA 42 is in a stable operating state is , Later than time T3.

  From this comparison, it can be seen that the startup time of the LNA 42 can be shortened by providing the control voltage V1 with the voltage Vpre. Note that the effect of reducing the startup time of the LNA by providing the voltage Vpre is not limited to the control voltage V1, and can be obtained in any of the control voltages V7 to V0.

  According to the RF module 10 described above, when the LNA circuit 40 is designated by the slave addresses SA3 to SA0, the control voltage for the stopped LNA among the LNAs 41 to 43 is set to the voltage Vpre higher than the voltage Vdis. Therefore, when the LNA is actually operated, the control voltage may be increased from the voltage Vpre to the voltage Vena. As a result, the startup time of the LNA is shortened as compared with the case where the control voltage is increased from the voltage Vdis to the voltage Vena in full width.

  Note that when the serial data SDATA is not a register write command, or when a register other than the PM register 474 is designated by the register addresses RA4 to RA0, the power mode data PM is not updated. In this case, the control voltage for the stopped LNA once rises to the voltage Vpre in accordance with the pre-drive signal PreDrive, but again drops to the original voltage Vdis after the pre-drive signal PreDrive is stopped.

  For such an operation, when the voltage Vpre is set to an upper limit voltage at which the LNA does not operate (for example, a threshold voltage of a transistor constituting the LNA), the stopped LNA is activated by the application of the voltage Vpre. Malfunctions can be avoided.

  In addition, the LNA in operation continues to apply the control voltage of the voltage Vena even during the output of the pre-drive signal PreDrive. Thereby, it can be avoided that the control voltage of the LNA which should continue to operate is lowered from the voltage Vena to the voltage Vdis and the operation becomes unstable.

  Although the RF module and the communication device according to the embodiments of the present invention have been described above, the present invention is not limited to the individual embodiments. Unless it deviates from the gist of the present invention, one or more of the present invention may be applied to various modifications that can be conceived by those skilled in the art, or forms constructed by combining components in different embodiments. It may be included within the scope of the embodiments.

  For example, in the above description, the startup time of the LNAs 41 to 43 has been shortened using the example of the LNA circuit 40, but the same idea can be applied to the PA circuit 50. That is, by configuring the PA control unit 57 in the same way as the LNA control unit 47, the PA 51-53 activation time can be shortened.

  In the above description, the example of the communication device 1 in which the front end circuit is configured by one RF module 10 has been described. However, the front end circuit is not necessarily configured by a single RF module.

  FIG. 5 is a block diagram illustrating an example of a functional configuration of a communication device according to a modification.

  As illustrated in FIG. 5, the communication device 1 a includes two RF modules 10 a and 10 b and a diplexer 75 as compared with the communication device 1 of FIG. 1, and the RF signal processing circuit 20 a is changed. The front end circuit of the communication device 1a includes two RF modules 10a and 10b.

  The RF modules 10a and 10b are all configured in the same manner as the RF module 10, and simultaneously process high-frequency signals in different frequency bands. For example, the RF module 10a processes a high-frequency signal in a frequency band belonging to a first band group (low band), and the RF module 10b is a second band group (middle band) having a higher frequency than the first band group. A high frequency signal in a frequency band belonging to may be processed.

  The diplexer 75 is connected to the antenna 80 and the duplexers 70a and 70b in the RF modules 10a and 10b, and mixes and separates the high frequency signal of the first band group and the high frequency signal of the second band group.

  The RF signal processing circuit 20a has LNAs 41a to 43a and PAs 51a to 53a connected to the LNA circuit 40a (LNA control unit 47a) and the PA circuit 50a (PA control unit 57a) according to the frequency band for performing the transmission operation and the reception operation. Instruct to stop or operate. Further, the LNA circuit 40b (LNA control unit 47b) and the PA circuit 50b (PA control unit 57b) are instructed to stop or operate the LNAs 41b to 43b and PAs 51b to 53b. In addition, the SW circuit 60a (SW control unit 63a) is instructed to connect in the SWs 61a and 62a, and the SW circuit 60b (SW control unit 63b) is instructed to connect in the SWs 61b and 62b.

  Thereby, in the communication device 1a, the carrier aggregation operation using at least two frequency bands becomes possible by simultaneously operating the RF modules 10a and 10b.

  Similar to the RF signal processing circuit 20, the RF signal processing circuit 20a transmits serial data specifying a single circuit block (for example, one of the LNA circuits 40a and 40b). Thereby, the RF signal processing circuit 20a can individually control the stop or operation of the LNAs 41a to 43a in the LNA circuit 40a and the stop or operation of the LNAs 41b to 43b in the LNA circuit 40b.

  Further, the RF signal processing circuit 20a may transmit serial data designating a plurality of circuit blocks (for example, both the LNA circuits 40a and 40b). For example, the same group ID is assigned to the LNA control units 47a and 47b separately from the unique slave address, and the group ID is designated in the first information of the serial data. The group ID may be recorded in each specific register of the LNA control units 47a and 47b.

  When serial data designating both the LNA circuits 40a and 40b is transmitted from the RF signal processing circuit 20a, the LNA circuits 40a and 40b simultaneously execute the operations described in FIG. Switch. By using the group ID, the RF signal processing circuit 20a controls the stop or operation of the LNAs 41a to 43a in the LNA circuit 40a and the stop or operation of the LNAs 41b to 43b in the LNA circuit 40b with a single serial data. be able to. This makes it possible to further shorten the startup time of the LNA.

  The present invention can be widely used for various communication devices as a high-frequency module.

1, 1a Communication device 10, 10a, 10b Front-end circuit (RF module)
20, 20a RF signal processing circuit 30 Baseband signal processing circuit 40, 40a, 40b LNA circuit 41-43, 41a-43a, 41b-43b LNA circuit
44-46 Filter 47, 47a, 47b LNA control unit 50, 50a, 50b PA circuit 51-53, 51a-53a, 51b-53b PA
54 to 56 Filters 57, 57a, 57b PA control unit 60, 60a, 60b SW circuit 61, 61a, 61b, 62, 62a, 62b SW
63, 63a, 63b SW control unit 70, 70a, 70b Duplexer 75 Diplexer 80 Antenna 471 Receiver 472 Register unit 473 USID register 474 PM register 475 Comparator 476 Timing generator 477 Voltage generator

Claims (6)

A plurality of amplifiers that are stopped when a first control voltage is applied and that are activated when a second control voltage higher than the first control voltage is applied;
If serial data including first information and second information subsequent to the first information is received, and the first information is information specifying the plurality of amplifiers, the plurality of amplifiers If a third control voltage higher than the first control voltage is applied, and then the second information is information instructing to stop or operate each of the plurality of amplifiers, the amplifier instructed to stop is supplied to the amplifier A controller that applies the first control voltage and applies the second control voltage to an amplifier instructed to operate;
High frequency module comprising. If the second information is not information indicating stop or operation of each of the plurality of amplifiers after application of the third control voltage, the control unit applies the third amplifier to each of the plurality of amplifiers. Apply the same control voltage that was applied before the control voltage of
The high frequency module according to claim 1. The third voltage is an upper limit voltage at which the amplifier does not operate.
The high frequency module according to claim 1 or 2. When the controller applies the third control voltage to the plurality of amplifiers, the controller continues to apply the second control voltage to an operating amplifier.
The high-frequency module according to any one of claims 1 to 3. The high-frequency module has a plurality of low-noise amplifier circuit blocks,
The serial data designates the plurality of low noise amplifier circuit blocks with the first information.
The high frequency module of any one of Claim 1 to 4. The high-frequency module according to any one of claims 1 to 5,
An RF signal processing circuit that transmits the serial data to the high-frequency module, transmits a high-frequency transmission signal to the high-frequency module, and receives a high-frequency reception signal from the high-frequency module;
A communication device comprising:

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