JP2018133659A - Optical communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique that provides an optical communication system leveling time stamp drift.SOLUTION: An optical communication system of an embodiment includes a plurality of subscriber side devices and an accommodation station side device communicatively connected with the subscriber side devices. At least one of the subscriber side devices and the accommodation station side device includes a delay processing unit for generating delay corresponding to differential value between a pre-specified prescribed value and a time of digital signal processing.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an optical communication system.

  Due to increasing needs for high-speed access services, FTTH (Fiber To The Home) is spreading worldwide. Most of the FTTH services are provided by the economical PON (Passive Optical Network) system. In the PON system, one accommodating station side device (OLT: Optical Line Terminal) accommodates a plurality of subscriber side devices (ONU: Optical Network Unit) by time division multiplexing (TDM).

  The current main system in Japan is a GE-PON (Gigabit Ethernet PON) whose transmission speed is a gigabit class. GE-PON is one of the standards IEEE 802.3ah standardized by the IEEE (American Institute of Electrical and Electronics Engineers) 802 committee for the purpose of applying Ethernet (registered trademark) communication to an access network.

  In order to multiplex the upstream signal of each ONU by the PON system, it is necessary to synchronize the time between the OLT and each ONU. In order to achieve this time synchronization, the OLT transmits the current value of the local station master counter to the ONU as a time stamp. The ONU employs a method of updating its own master counter value based on the received time stamp. By using this method, the ONU operates in an independent synchronization method, and a high-precision PLL (Phase Lock Loop) necessary for the cascade synchronization device is not required. Therefore, the configuration can contribute to cost reduction. The time stamp is multiplexed with a downstream signal from the OLT to the ONU in a MAC (Media Access Control) control sublayer included in the OLT. The time stamp is embedded in a Gate frame that is issued by the OLT to permit transmission to the ONU.

  On the other hand, as the demand for user traffic increases, the capacity and economy of optical access networks are increasing. To realize this, a DSP-PON system in which a digital signal processing (DSP) technology is applied to a PON system has attracted attention, and research and development / practical use has been activated.

  Further, when the DSP-PON system is used, the digital signal processed digital signal is converted into an analog signal and input to the transmitter in the PHY (PHYsical sublayer) of the OLT. In the ONU-PHY, the analog signal output from the receiver is converted into a digital signal, and then digital signal processing is performed.

IEEE Standard 802.3ah

  In the DSP-PON system in which the DSP technology is applied to the PON system, there is a concern that the processing time of the DSP varies. For example, when an OFDM (Orthogonal Frequency-Division Multiplexing) technique is used, since the OFDM signal is transmitted at intervals of the symbol length T, the processing delay varies by the OFDM symbol length. In addition, when traffic is input in bursts, it cannot be sent in one cycle, but is sent in several cycles. Therefore, a delay several times as long as the OFDM symbol length T is generated, and only several times as long as the OFDM symbol length is processed. Delay varies.

  However, the time stamp used to synchronize the time between the OLT and each ONU is embedded in the Gate frame transmitted from the OLT to the ONU. If the delay due to digital signal processing varies, the time stamp is observed by the OLT and the ONU. Increased time stamp drift. Under such conditions with a large time stamp drift, there are problems that a time stamp drift error is detected and ONU registration is canceled, and that burst optical signal collisions from multiple ONUs occur in upstream burst optical transmission. It was.

  In view of the above circumstances, an object of the present invention is to provide an optical communication system in which time stamp drift is further reduced.

  One aspect of the present invention is an optical communication system including a plurality of subscriber-side devices and a receiving station-side device that is communicably connected to the subscriber-side device, the subscriber-side device and the receiving station An optical communication system, comprising: a delay processing unit that generates a delay corresponding to a difference value between a predetermined value specified in advance and a digital signal processing time in at least one of the side devices.

  One aspect of the present invention is the optical communication system described above, wherein the delay processing unit included in at least one of the subscriber side device and the accommodating station side device has a processing time in the delay processing unit. A digital signal processing counter unit for measuring, a digital signal processing unit for performing digital signal processing, a buffer for temporarily storing data, and a frame extraction for acquiring a frame from the buffer when the processing time is equal to the predetermined value A section.

  One aspect of the present invention is the optical communication system described above, wherein the delay processing unit included in the accommodation station side device includes a digital signal processing unit that performs digital signal processing, a buffer that temporarily stores data, and the accommodation When the difference value between the local station master counter value of the station side device and the time stamp value added to the Gate signal issued for transmission permission is equal to the maximum value of the MAC / PHY processing delay, the frame is acquired from the buffer. And a frame take-out part.

  According to the present invention, time stamp drift can be further reduced.

It is a figure showing an example of composition of DSP-PON system 1 of a 1st embodiment. It is a functional block diagram showing the functional structure of the time synchronous process of DSP-PON system 1 of 1st Embodiment. It is a figure showing the content of the time synchronous process of the delay process part 126 in 1st Embodiment. It is a functional block diagram which shows the structure of the delay process part 126 in the accommodation station side apparatus 100 of 2nd Embodiment. It is a flowchart which shows the flow of a process of the delay process part 126 in the accommodation station side apparatus 100 of 2nd Embodiment. It is a functional block diagram which shows the structure of the delay process part 126a in the accommodation station side apparatus 100 of 3rd Embodiment. It is a flowchart which shows the flow of a process of the delay process part 126a in the accommodation station side apparatus 100 of 3rd Embodiment.

(First embodiment)
FIG. 1 is a diagram illustrating a configuration example of a DSP-PON system 1 according to the first embodiment. The DSP-PON system 1 includes an accommodation station side device 100, a plurality of subscriber side devices 200-1 to 200-n (n is an arbitrary integer), and an optical multiplexing / demultiplexing device 300. Hereinafter, when it is not distinguished which subscriber-side device, it will be simply referred to as the subscriber-side device 200. The accommodation station side device 100 and the subscriber side device 200 are connected to each other via the optical multiplexing / demultiplexing device 300 so as to communicate with each other. The DSP-PON system is an aspect of an optical communication system.

  The accommodation station side device 100 is a device that realizes communication with another communication device by an optical signal passing through a communication network. The accommodating station side apparatus accommodates a plurality of subscriber side apparatuses 200 by time division multiplexing. The communication network to which the accommodation station side device 100 is connected is, for example, an optical fiber network such as PON. The accommodation station side apparatus 100 is installed in a station building for providing communication services, for example. The accommodation station side device 100 is configured by a data link sublayer called MAC 110 and a physical layer called PHY 120. The PHY includes a DSP 127 that performs digital signal processing. The accommodation station side device 100 is, for example, an OLT.

  The subscriber-side device 200 is a device that realizes communication with another communication device by an optical signal passing through a communication network. The communication network to which the subscriber side device 200 is connected is an optical fiber network such as PON. The subscriber side device 200 is installed, for example, in the home of a user who receives a communication service. The subscriber side device 200 is composed of a MAC 210 and a PHY 220. The PHY 220 includes a DSP 227. The subscriber side device 200 is, for example, an ONU.

  The optical multiplexing / demultiplexing device 300 aggregates the signals transmitted from the subscriber side device 200 and transmits them to the accommodating station side device 100. The optical multiplexing / demultiplexing device 300 distributes the signal transmitted from the accommodating station side device 100 or the transmitted signal to the subscriber side device 200. The optical multiplexing / demultiplexing device 300 is, for example, an optical splitter.

  FIG. 2 is a functional block diagram illustrating a functional configuration of a time synchronization process of the DSP-PON system 1 according to the first embodiment. The accommodation station side device 100 includes a MAC 110 and a PHY 120. The MAC 110 includes a MAC control sublayer 111, which is an optional sublayer of the MAC 110, and a MAC sublayer 112 that performs MAC framing of data and medium access.

  The MAC control sublayer 111 performs real-time control and operation of the MAC sublayer 112. The MAC control sublayer 111 includes a Discovery process 113, a Reporting process 114, Data 115, and a Control multiplexer 116. The control multiplexer 116 outputs the signals received from the discovery process 113, the reporting process 114, and the data 115 to the MAC sublayer 112 as one signal. The control multiplexer 116 has a time stamp embedded in the Gate frame. The Gate frame is a frame issued for permitting transmission from the accommodation station side device 100 to the subscriber side device 200. The Gate frame includes a transmission start time and a transmission amount so that each subscriber apparatus 200 can transmit without colliding.

  The MAC sublayer 112 performs MAC frame conversion based on the output signal. In MAC frame conversion, data included in a signal is framed, a MAC address is added to the frame, and frame error detection is performed. The MAC sublayer 112 performs medium access such as MAC frame collision detection and postponement processing for MAC frame transmission / reception timing.

  The PHY 120 includes an RS (Reconciliation sublayer) 121, a GMII (Gigabit media independent interface) 122, a PCS (Physical Coding Sublayer) 123, a PMA 124, and a PMD (Physical Medium Dependent) 125. The RS 121 and the GMII 122 connect the MAC 110 and the PHY 120. The PCS 123 encodes data. A PMA (Physical Medium Attachment) 124 serializes data. The PCS 123 and PMD 125 are connected by a PMA 124.

  The PMD 125 includes a delay processing unit 126, a DAC (Digital to Analog Converter) 128, and a Tx (Transceiver) 129. The delay processing unit 126 includes a DSP 127. The DSP 127 performs digital signal processing (hereinafter referred to as “DSP processing”). The delay processing unit 126 stores in advance a maximum DSP processing time that is a maximum value of delay due to the DSP processing. The delay processing unit 126 generates a time delay corresponding to the difference between the maximum DSP processing time and the actual DSP processing delay. As a result, the DSP processing delay time becomes constant. The DAC 128 converts the digital signal processed by the DSP 127 into an analog signal. The DAC 128 inputs the converted analog signal to Tx129. The Tx 129 transmits the received analog signal to the subscriber apparatus 200.

  The subscriber side device 200 includes a MAC 210 and a PHY 220. The MAC 210 includes a MAC control sublayer 211 that is a sublayer of the MAC 210 and a MAC sublayer 212 that performs data MAC frame conversion and medium access.

  The PHY 220 includes RS 221, GMII 222, PCS 223, PMA 224, and PMD 225. The RS 221 and the GMII 222 connect the MAC 210 and the PHY 220. The PCS 223 encodes data. The PMA 224 serializes data. PMD 225 is connected by PMA 224.

  The PMD 225 includes a delay processing unit 226, an ADC (Analog to Digital Converter) 228, and an Rx (Receiver) 229. The delay processing unit 226 includes a DSP 227. The Rx 229 outputs the received analog signal to the ADC 228. The ADC 228 converts the received analog signal into a digital signal. The DSP 227 performs DSP processing on the converted digital signal. The delay processing unit 226 stores in advance a maximum DSP processing time that is a maximum value of delay due to the DSP processing. The delay processing unit 226 generates a time delay corresponding to the difference between the maximum DSP processing time and the actual DSP processing delay. As a result, the DSP processing delay time becomes constant.

  The MAC sublayer 212 acquires a Gate frame based on the received digital signal. The MAC sublayer 212 sets the time stamp acquired from the Gate frame in the subscriber side device 200. The MAC control sublayer 211 performs real-time control and operation of the MAC sublayer 212. The MAC control sublayer 211 includes a Discovery process 213, a Reporting process 214, Data 215, and a Control multiplexer 216. The control multiplexer 216 outputs the signals received from the MAC sublayer 212 as three signals to the discovery process 213, the reporting process 214, and the data 215, respectively.

  In the present embodiment, both the accommodation station side device 100 and the subscriber side device 200 are provided with DSPs. However, at least one of the accommodation station side device 100 and the subscriber side device 200 may be provided with a DSP. .

  FIG. 3 is a diagram illustrating the contents of the time synchronization processing of the delay processing unit 126 in the first embodiment. The MAC 110 of the accommodation station side device 100 outputs the Gate frame in which the time stamp t0 is embedded to the DSP 127 of the accommodation station side device 100 (step S101). The DSP 127 performs digital signal processing on the Gate frame. Even after the digital signal processing is completed, the DSP 127 holds the Gate frame until the maximum DSP processing time is reached (step S102). When the maximum DSP processing time has elapsed, the DSP 127 transmits a Gate frame to the subscriber apparatus 200 (step S103). The DSP 227 of the subscriber side device 200 performs digital signal processing on the received Gate frame. Even after the digital signal processing is completed, the DSP 227 holds the Gate frame until the maximum DSP processing time is reached (step S104). The DSP 227 outputs a Gate frame to the MAC 210 (step S105). The MAC 210 acquires the time stamp t0 from the Gate frame and sets it in the subscriber apparatus 200 (step S106).

As described above, the DSP-PON system 1 configured as described above includes the DSP 127 and the DSP 227 so that the Gate frame transmission is waited until the maximum DSP processing time regardless of the length of the DSP processing time, and there is an error in the DSP processing time. Absorbed and the DSP processing time is leveled to the maximum DSP processing time. Therefore, the time stamp drift becomes smaller and the time stamp drift error can be eliminated.

(Second Embodiment)
FIG. 4 is a functional block diagram illustrating a configuration of the delay processing unit 126 in the accommodating station side device 100 according to the second embodiment. The delay processing unit 126 includes a DSP counter unit 130, a DSP processing unit 131, a buffer 132, and a frame extraction unit 133. The delay processing unit 226 in the subscriber side device 200 has the same configuration.

  The DSP counter unit 130 measures the processing time in the delay processing unit 126. Specifically, the DSP counter unit 130 starts the DSP counter when a frame is input. When the DSP counter is started, the DSP counter unit 130 adds the DSP counter value as time elapses. The DSP counter unit 130 outputs the DSP counter value to the frame extraction unit 133. The DSP counter unit 130 is an aspect of the digital signal processing counter unit.

  The DSP processing unit 131 performs DSP processing. The DSP processing unit 131 temporarily stores the DSP-processed digital signal in the buffer 132. The buffer 132 temporarily stores the digital signal. The frame extraction unit 133 acquires a frame from the buffer 132 at a timing when the received DSP counter value becomes equal to the maximum DSP processing time. The acquired frame is deleted from the buffer 132. The frame extraction unit 133 outputs the acquired digital signal to the DAC 128. The maximum DSP processing time is stored in the frame extraction unit 133 in advance. The DSP processing unit is an aspect of the digital signal processing unit.

  FIG. 5 is a flowchart illustrating a processing flow of the delay processing unit 126 in the accommodation station side device 100 according to the second embodiment. The DSP counter unit 130 starts the DSP counter when a frame is input (step S201). The DSP processing unit 131 performs DSP processing (step S202). The buffer 132 temporarily stores the DSP-processed digital signal (step S203). The frame extraction unit 133 determines whether the DSP counter value is equal to the maximum DSP processing time (step S204). When the DSP counter value is equal to the maximum DSP processing time (step S204: YES), the frame extraction unit 133 acquires a frame from the buffer 132 (step S205). When the DSP counter value is not equal to the maximum DSP processing time (step S204: NO), the frame extraction unit 133 proceeds to step S204.

  Thus, in the configured DSP-PON system 1, the DSP processing delay time is measured by using the DSP counter, and the DSP processing delay is always equal to the maximum DSP processing time regardless of the actual DSP processing delay time. As such, the signal can be digital signal processed. Therefore, the time stamp drift error can be eliminated.

(Third embodiment)
FIG. 6 is a functional block diagram illustrating a configuration of the delay processing unit 126a in the accommodation station side device 100 according to the third embodiment. The delay processing unit 126a is different from the delay processing unit 126 in that it includes a frame extraction unit 133a instead of the frame extraction unit 133 and does not include the DSP counter unit 130, but the other configurations are the same. Hereinafter, differences from the delay processing unit 126 will be described.

  The frame extraction unit 133a acquires the frame from the buffer 132 at a timing when the difference value between the own station master counter value of the accommodation station side device 100 and the time stamp value becomes equal to the maximum value of the MAC / PHY processing delay. For example, the time stamp value is a value registered when adding a time stamp to the Gate frame in the MAC control sublayer 111. The maximum MAC / PHY processing delay is the sum of the MAC processing, RS121, GMII122, PCS123, PMA124 processing delay, and DSP processing delay maximum.

  FIG. 7 is a flowchart illustrating a processing flow of the delay processing unit 126a in the accommodation station side device 100 according to the third embodiment. The DSP processing unit 131 performs DSP processing (step S301). The buffer 132 temporarily stores the DSP-processed digital signal (step S302). The frame extraction unit 133a acquires the local station master counter value and the time stamp value (step S303). The frame extraction unit 133a calculates a difference value between the local station master counter value and the time stamp value (step S304). The frame extraction unit 133a determines whether or not the difference value is equal to the maximum value of the MAC / PHY processing delay (step S305). When the difference value is equal to the maximum value of the MAC / PHY processing delay (step S305: YES), the frame extraction unit 133a acquires a frame from the buffer 132 (step S306). When the difference value is not equal to the maximum value of the MAC / PHY processing delay (step S305: NO), the frame extraction unit 133a transits to step S303.

  As described above, in the configured DSP-PON system 1, the frame extraction unit 133a uses the master counter value and the time stamp value to measure the MAC / PHY processing delay, regardless of the actual DSP processing delay time. The signal can be digital signal processed so that the DSP processing delay is always equal to the maximum value. Therefore, the time stamp drift error can be eliminated.

  You may make it implement | achieve the accommodating station side apparatus 100 and the subscriber side apparatus 200 in embodiment mentioned above with a computer. In that case, a program for realizing this function may be recorded on a computer-readable recording medium, and the program recorded on this recording medium may be read into a computer system and executed. Here, the “computer system” includes an OS and hardware such as peripheral devices. The “computer-readable recording medium” refers to a storage device such as a flexible medium, a magneto-optical disk, a portable medium such as a ROM and a CD-ROM, and a hard disk incorporated in a computer system. Furthermore, the “computer-readable recording medium” dynamically holds a program for a short time like a communication line when transmitting a program via a network such as the Internet or a communication line such as a telephone line. In this case, a volatile memory inside a computer system serving as a server or a client in that case may be included and a program held for a certain period of time. Further, the program may be a program for realizing a part of the above-described functions, and may be a program capable of realizing the functions described above in combination with a program already recorded in a computer system. You may implement | achieve using programmable logic devices, such as FPGA (Field Programmable Gate Array).

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes designs and the like that do not depart from the gist of the present invention.

  The present invention is applicable to a DSP-PON system in which DSP processing is used.

DESCRIPTION OF SYMBOLS 1 ... DSP-PON system, 100 ... Accommodating station side device, 110 ... MAC, 111 ... MAC control sublayer, 112 ... MAC sublayer, 113 ... Discovery process, 114 ... Reporting process, 115 ... Data, 120 ... PHY, 121 ... RS, 122 ... GMII, 123 ... PCS, 124 ... PMA, 125 ... PMD, 126 ... Delay processing section, 127 ... DSP, 128 ... DAC, 129 ... Tx, 130 ... DSP counter section, 131 ... DSP processing section, 132 ... buffer, 133 ... frame extraction unit, 126a ... delay processing unit, 133a ... frame extraction unit, 200 ... subscriber side device, 210 ... MAC, 211 ... MAC control sublayer, 212 ... MAC sublayer, 213 ... Discovery process, 214 ... Reporting process, 215 ... Data, 220 ... PHY, 22 ... RS, 222 ... GMII, 223 ... PCS, 224 ... PMA, 225 ... PMD, 226 ... delay processing section, 227 ... DSP, 228 ... ADC, 229 ... Rx

Claims (3)

An optical communication system comprising a plurality of subscriber-side devices and a receiving station-side device that is communicably connected to the subscriber-side device,
A delay processing unit that generates a delay corresponding to a difference value between a predetermined value specified in advance and a time of digital signal processing in at least one of the subscriber side device and the accommodation station side device;
Comprising
Optical communication system. The delay processing unit included in at least one of the subscriber side device and the accommodation station side device is:
A digital signal processing counter unit for measuring processing time in the delay processing unit;
A digital signal processor for performing digital signal processing;
A buffer to temporarily store data;
When the processing time becomes equal to the predetermined value, a frame extraction unit that acquires a frame from the buffer;
Comprising
The optical communication system according to claim 1. The delay processing unit provided in the accommodation station side device,
A digital signal processor for performing digital signal processing;
A buffer to temporarily store data;
When the difference value between the local station master counter value of the accommodation station side device and the time stamp value added to the Gate signal issued for transmission permission becomes equal to the maximum value of the MAC / PHY processing delay, the frame is stored in the buffer. A frame extraction unit acquired from
Comprising
The optical communication system according to claim 1 or 2.

Images