JP2018129461A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the same capable of improving the sensitivity while suppressing variation in saturation charge amount of a photodiode.SOLUTION: A semiconductor device includes a first device that comprises: a first N-type impurity diffusion layer 31 formed in a semiconductor substrate; a first P-type impurity diffusion layer 32 formed above the first N-type impurity diffusion layer 31 in the semiconductor substrate; and a second N-type impurity diffusion layer 33 formed above the first N-type impurity diffusion layer 31 in the semiconductor substrate, and at least a part of which overlaps with the first P-type impurity diffusion layer 32. A potential well to electrons of the second N-type impurity diffusion layer 33 is deeper than a potential well to electrons of the first N-type impurity diffusion layer 31.SELECTED DRAWING: Figure 1B

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  As characteristics of a photodiode (PD) of a CMOS image sensor, sensitivity, saturation charge amount and dark current are important. Visible light from green to red enters the silicon substrate while being attenuated to a depth of 2 μm or more. Therefore, in order to obtain signal charges from the visible light, an impurity diffusion layer for PD having a depth of 2 μm or more may be formed in the silicon substrate. When such an impurity diffusion layer is formed, ion implantation with high energy using a thick resist pattern is performed.

  However, the thicker the resist pattern, the more easily the shape of the opening varies. Variation in the shape of the opening leads to variation in the area of the impurity diffusion layer, and variation in the area of the impurity diffusion layer leads to variation in the saturation charge amount. For this reason, conventionally, it is difficult to improve the sensitivity while suppressing variations in the saturation charge amount.

JP 2004-134790 A JP 2008-235753 A JP 2003-248293 A JP 2004-103721 A JP 2003-282858 A Japanese Patent Laid-Open No. 10-189936 JP 2009-71049 A

  An object of the present invention is to provide a semiconductor device capable of improving sensitivity while suppressing variation in saturation charge amount of a photodiode, and a manufacturing method thereof.

  In one aspect of the semiconductor device, a first N-type impurity diffusion layer formed on a semiconductor substrate and a first P-type impurity diffusion formed on the semiconductor substrate above the first N-type impurity diffusion layer. And a second N-type impurity diffusion layer formed above the first N-type impurity diffusion layer of the semiconductor substrate and at least partially overlapping the first P-type impurity diffusion layer. The potential well for electrons in the second N-type impurity diffusion layer includes a first device deeper than the potential well for electrons in the first N-type impurity diffusion layer.

  In one embodiment of a method for manufacturing a semiconductor device, a first N-type impurity diffusion layer is formed in a semiconductor substrate by ion implantation of a first N-type impurity using a first resist pattern having a first thickness as a mask. A P-type impurity diffusion layer is formed above the first N-type impurity diffusion layer of the semiconductor substrate by ion implantation of P-type impurities using the first resist pattern as a mask. By ion implantation of the second N-type impurity using the second resist pattern having a thin second thickness as a mask, at least a part of the P-type impurity is diffused above the first N-type impurity diffusion layer of the semiconductor substrate. A second N-type impurity diffusion layer overlapping the type impurity diffusion layer is formed. The potential well for electrons in the second N-type impurity diffusion layer is deeper than the potential well for electrons in the first N-type impurity diffusion layer.

  According to the semiconductor device or the like, since an appropriate P-type impurity diffusion layer is included, the sensitivity can be improved while suppressing variations in the saturation charge amount of the photodiode.

1 is a diagram illustrating a semiconductor device according to a first embodiment. 1 is a diagram illustrating a semiconductor device according to a first embodiment. It is a figure which shows the electronic transfer path | route. It is a figure which shows the energy of the movement path | route of an electron. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. FIG. 4B is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 4A. FIG. 4B is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 4B. FIG. 4D is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 4C. FIG. 4D is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 4D. FIG. 4E is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 4E. It is a figure which shows a potential well in case a P-type impurity diffusion layer is deeper than a shallow N-type impurity diffusion layer. It is a figure which shows a potential well in case a P-type impurity diffusion layer is shallower than a shallow N-type impurity diffusion layer. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. FIG. 7B is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 7A. FIG. 7B is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 7B. It is a figure which shows the positional relationship in planar view of the N type impurity diffused layer at the time of performing oblique ion implantation from 4 directions, and a P type impurity diffused layer. It is a figure which shows the positional relationship in planar view of the N type impurity diffusion layer at the time of performing oblique ion implantation from 2 directions, and a P type impurity diffusion layer. It is a figure which shows the geometric relationship of the various dimensions in 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. FIG. 11B is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 11A. FIG. 11B is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 11B. FIG. 11D is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 11C. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 4th Embodiment. FIG. 12B is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 12A. FIG. 12B is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 12B. FIG. 12C is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 12C. It is sectional drawing which shows the semiconductor device which concerns on 5th Embodiment.

  Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

(First embodiment)
First, the first embodiment will be described. The first embodiment relates to a semiconductor device suitable for a CMOS image sensor and a manufacturing method thereof. 1A and 1B are diagrams illustrating a semiconductor device according to the first embodiment. 1A (a) is a diagram showing an arrangement of pixels, FIG. 1A (b) is a circuit diagram showing a configuration in the pixel, FIG. 1B (c) is a diagram showing a layout in the pixel, and FIG. (D) is sectional drawing which followed the II line | wire in FIG.1B (c).

  As shown in FIG. 1A (a), the semiconductor device 10 according to the first embodiment includes a pixel array 12 including a plurality of pixels 11. The pixel pitch is about 1 μm to 3 μm. As shown in FIGS. 1A (b) and 1B (c), each pixel 11 includes a photodiode (PD) 21, a transfer gate (TG) 22, and a floating diffusion (FD) 23. Each pixel 11 also includes N-type impurity diffusion layers 24, 26, 28 and 20. A reset gate (RG) 25 is provided between the N-type impurity diffusion layer 24 and the N-type impurity diffusion layer 26, and a selection gate (SG) 29 is provided between the N-type impurity diffusion layer 28 and the N-type impurity diffusion layer 20. And a gate 27 that constitutes a source follower together with the N-type impurity diffusion layer 26 and the N-type impurity diffusion layer 28. A power supply potential Vdd is applied to the N-type impurity diffusion layer 26.

  As shown in FIG. 1B (d), the PD 21 includes an N-type impurity diffusion layer 31 formed in the P-well 30, a P-type impurity diffusion layer 32 formed above the N-type impurity diffusion layer 31, and an N-type impurity. An N-type impurity diffusion layer 33 formed above the impurity diffusion layer 31 and at least partially overlapping the P-type impurity diffusion layer 32 is included. The FD 23 includes an N-type impurity diffusion layer formed on the surface of the P well 30. The TG 22 is formed on the P well 30 via a gate insulating film, and the N-type impurity diffusion layer 33, the FD 23, and the TG 22 are included in one field effect transistor. The potential well for electrons becomes deeper in the order of the N-type impurity diffusion layer 31, the N-type impurity diffusion layer 33, and the FD23.

  Next, an outline of the reading operation in the pixel 11 will be described. FIG. 2 is a diagram illustrating an electron transfer path, and FIG. 3 is a diagram illustrating energy of an electron movement path.

  As shown in FIGS. 3A and 3B, the potential well for the electrons of the PD 21 is shallow in the N-type impurity diffusion layer 31 and deep in the N-type impurity diffusion layer 33. When the TG 22 is off, as shown in FIG. 3A, a high potential barrier exists in the channel, and electrons cannot move between the N-type impurity diffusion layer 33 and the FD 23. As shown in FIG. 2, when light enters the N-type impurity diffusion layer 31, electron-hole pairs are generated in the N-type impurity diffusion layer 31, and electrons are accumulated from a deep portion to a shallow portion of the potential well. Go. When the TG 22 is turned on, the potential barrier disappears and the accumulated electrons move to the FD 23 as shown in FIG.

  At the time of reading, the RG 25 is turned on / off to reset the FD 23 connected to the N-type impurity diffusion layer 24 to the power supply voltage Vdd. The gate 27 is connected to the FD 23. When electrons move to the FD 23, the potential of the gate 27 changes, and the source voltage changes accordingly. This change in the source voltage is read from the N-type impurity diffusion layer 20 to the peripheral circuit via the selection gate 29.

  Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. 4A to 4F are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the first embodiment in the order of steps. 4A to 4F show the pixel 1 in which the size of the opening of the resist pattern did not deviate from the design value and the pixel 2 in which the size of the opening has deviated.

First, as shown in FIG. 4A, a P well 108 is formed on a silicon substrate 100, and an insulating film 109 is formed on the silicon substrate 100 as a through film for ion implantation. As the insulating film 109, for example, a silicon oxide film having a thickness of about 10 nm to 50 nm is formed. Next, a resist pattern 111 is formed on the insulating film 109. In the formation of the resist pattern 111, a thick resist film having a thickness of 3 μm or more is formed, and an opening 111a is formed by a photolithography technique at a location where a photodiode (photo diode: PD) of the pixel array is formed. At this time, in the pixel 1, the opening area of the opening 111a is as designed (S (μm ² )), and in the pixel 2, the opening area of the opening 111a is shifted by ΔS (μm ² ).

Thereafter, as shown in FIG. 4B, ion implantation of N-type impurities is performed using the resist pattern 111 as a mask to form a deep N-type impurity diffusion layer 101 in the P well 108. For example, the position of the N-type impurity diffusion layer 101 is in the range of 0.5 μm to 3 μm from the surface of the silicon substrate 100. In the formation of the N-type impurity diffusion layer 101, for example, phosphorus (P) is used as the N-type impurity, the implantation energy is 400 keV or more, and the dose (DN (cm ⁻² )) is 1 × 10 ¹¹ cm ⁻² to 1. × 10 ¹³ cm ^-2 The N-type impurity diffusion layer 101 may be formed by a plurality of ion implantations.

Subsequently, as shown in FIG. 4B, P-type impurity ions are implanted using the resist pattern 111 as a mask to form a P-type impurity diffusion layer 102 shallower than the N-type impurity diffusion layer 101 in the P well 108. For example, the position of the P-type impurity diffusion layer 102 is in the range of 0.1 μm to 0.4 μm from the surface of the silicon substrate 100. In the formation of the P-type impurity diffusion layer 102, for example, boron (B) is used as the P-type impurity, the implantation energy is several tens of keV to 130 keV, and the dose (P ₁ (cm ⁻² )) is 1 × 10 ¹¹ cm ^{−. 2} to 1 × 10 ¹³ cm ⁻² .

Next, as illustrated in FIG. 4C, the resist pattern 111 is removed, and a resist pattern 112 is formed over the insulating film 109. In the formation of the resist pattern 112, a thin resist film having a thickness of 500 nm to 1 μm is formed, and an opening 112a is formed by a photolithography technique at a position where the PD of the pixel array is formed. At this time, in both the pixel 1 and the pixel 2, the opening area of the opening 112a is assumed to be as designed (SA (μm ² )).

4C, N-type impurity ions are implanted using the resist pattern 112 as a mask, and the N-type impurity diffusion layer 103 is shallower than the N-type impurity diffusion layer 101 so as to overlap the P-type impurity diffusion layer 102. Are formed in the P-well 108. For example, the position of the N-type impurity diffusion layer 103 is in the range of 0.1 μm to 0.4 μm from the surface of the silicon substrate 100. In the formation of the N-type impurity diffusion layer 103, for example, P is used as the N-type impurity, the implantation energy is 80 keV to 300 keV, and the dose (SN (cm ⁻² )) is 1 × 10 ¹¹ cm ^{−2 to} 5 × 10. ¹³ cm- ² . At this time, the concentration of P forming the N-type impurity diffusion layer 103 is set higher than the concentration of P forming the N-type impurity diffusion layer 101, and the potential well for electrons is shallow in the N-type impurity diffusion layer 101, The diffusion layer 103 is made deep. When forming the N-type impurity diffusion layer 103, oblique ion implantation with a tilt angle of 7 ° or less may be performed.

  Subsequently, as shown in FIG. 4D, the resist pattern 112 is removed, and a gate insulating film 121, a transfer gate (TG) 122, and a floating diffusion (FD) 123 are formed in each pixel. The gate insulating film 121 can be formed by thermal oxidation. The TG 122 can be formed by depositing and patterning a polycrystalline silicon film. The FD 123 can be formed by ion implantation of N-type impurities using a resist pattern as a mask. The polycrystalline silicon film can be patterned by a photolithography technique and an etching technique.

  Next, as shown in FIG. 4E, an insulating film 131 is formed as a contact interlayer insulating film on the silicon substrate 100, a contact hole is formed in the insulating film 131, and a conductive plug 132 is formed in the contact hole. Thereafter, an insulating film 133 is formed on the insulating film 131, a wiring groove is formed in the insulating film 133, and a wiring 134 is formed in the wiring groove. Subsequently, an insulating film 135 is formed on the insulating film 133, a via hole and a wiring groove are formed in the insulating film 135, a conductive plug 136a is formed in the via hole, and a wiring 136b is formed in the wiring groove. Next, an insulating film 137 is formed over the insulating film 135, a via hole and a wiring groove are formed in the insulating film 137, a conductive plug 138a is formed in the via hole, and a wiring 138b is formed in the wiring groove. After that, an insulating film 139 is formed over the insulating film 137. In the formation of the insulating film 131, for example, a silicon nitride film, a silicon oxide film, and a silicon oxide film are planarized by chemical mechanical polishing (CMP). For example, a tungsten (W) plug is formed as the conductive plug 132. As the insulating films 133 and 139, a silicon oxide film is formed by, for example, a plasma chemical vapor deposition (CVD) method. For example, a Cu wiring is formed as the wiring 134. Contact holes, via holes, and wiring trenches can be formed by photolithography and etching techniques. The wiring 134 can be formed by a single damascene method. The conductive plug 136a and the wiring 136b can be formed by a dual damascene method. The conductive plug 138a and the wiring 138b can also be formed by a dual damascene method. The number of wiring layers is not limited.

  After that, as illustrated in FIG. 4F, a supporting substrate 161 is attached to the insulating film 139 using an adhesive. Subsequently, the silicon substrate 100 is polished from the back surface side so that the distance between the deepest portion of the N-type impurity diffusion layer 101 and the back surface of the silicon substrate 100 is within 0.5 μm. Subsequently, an antireflection film 162, a metal light shielding film 163, a color filter 164, and a microlens 165 are formed on the back surface of the silicon substrate 100.

  In this way, the semiconductor device 10 according to the first embodiment can be manufactured.

  Next, effects of the first embodiment will be described in comparison with a reference example in which the P-type impurity diffusion layer 102 is not formed. Here, the variation of the saturation charge amount is compared. Table 1 shows parameters used for calculation of the saturation charge amount in the first embodiment and the reference example.

In the first embodiment, the saturation charge amount Q1 of the pixel 1 is “α · DN · S−β · P ₁ · S + γ · SN · SA”, and the saturation charge amount Q2 of the pixel 2 is “α · DN · ( S−ΔS) −β · P ₁ · (S−ΔS) + γ · SN · SA ”. Therefore, the difference ΔQ in the saturation charge amount between the pixel 1 and the pixel 2 is “(α · DN−β · P ₁ ) · ΔS”. That is, by reducing the value of “α · DN−β · P ₁ ”, it is possible to reduce the variation in the saturation charge amount due to the variation in the shape of the opening 111a, and the dose amount P ₁ is α · DN. If it is about / β, the variation in the saturation charge amount does not substantially occur.

  On the other hand, in the reference example, the saturation charge amount Q1 of the pixel 1 is “α · DN · S + γ · SN · SA”, and the saturation charge amount Q2 of the pixel 2 is “α · DN · (S−ΔS) + γ · SN · SA”. SA ". Therefore, the difference ΔQ in the saturation charge amount between the pixel 1 and the pixel 2 is “α · DN · ΔS”. Since there is a limit in reducing the dose DN from the viewpoint of sensitivity, there is a limit in reducing the variation in the saturation charge amount due to the variation in the shape of the opening.

  In the first embodiment, the saturation charge amount is slightly reduced due to the P-type impurity diffusion layer 102, but can be compensated by the shallow N-type impurity diffusion layer 103.

  In the first embodiment, the design value SA of the opening area of the opening 112a is equal to the design value S of the opening area of the opening 111a, but a larger saturation charge amount is obtained as the area of the impurity diffusion layer is larger. The design value SA is preferably larger than the design value S because 112a can be formed more stably than the opening 111a. In this case, the N-type impurity diffusion layer 103 is formed with a larger area than the N-type impurity diffusion layer 101.

  Note that an afterimage tends to occur when the P-type impurity diffusion layer 32 does not overlap the N-type impurity diffusion layer 33. FIG. 5 is a diagram showing a potential well when the P-type impurity diffusion layer 32 is deeper than the N-type impurity diffusion layer 33. FIG. 6 shows the P-type impurity diffusion layer 32 shallower than the N-type impurity diffusion layer 33. It is a figure which shows the potential well in a case.

  When the P-type impurity diffusion layer 32 is deeper than the N-type impurity diffusion layer 33, a potential barrier exists between the N-type impurity diffusion layer 31 and the N-type impurity diffusion layer 33 as shown in FIG. . This potential barrier hinders the movement of electrons from the N-type impurity diffusion layer 31 to the N-type impurity diffusion layer 33, and an afterimage may occur accompanying this.

  When the P-type impurity diffusion layer 32 is shallower than the N-type impurity diffusion layer 33, as shown in FIG. 6, a potential barrier exists between the N-type impurity diffusion layer 33 and the FD 23 when the TG 22 is turned on. . This potential barrier hinders the movement of electrons from the N-type impurity diffusion layer 33 to the FD 23, and an afterimage may occur accompanying this.

  Therefore, it is preferable that the P-type impurity diffusion layer 32 overlaps with the N-type impurity diffusion layer 33.

(Second Embodiment)
Next, a second embodiment will be described. The second embodiment relates to a semiconductor device suitable for a CMOS image sensor and a manufacturing method thereof. For convenience of explanation, the structure of the semiconductor device will be described together with its manufacturing method. 7A to 7C are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the second embodiment in the order of steps. 7A to 7C illustrate a pixel 1 in which the size of the opening of the resist pattern has not shifted from the design value and a pixel 2 in which the size of the opening has shifted.

First, as shown in FIG. 7A, processing up to the formation of the deep N-type impurity diffusion layer 101 is performed as in the first embodiment. Next, oblique ion implantation of P-type impurities is performed using the resist pattern 111 as a mask to form a P-type impurity diffusion layer 202 having a circular planar shape shallower than the N-type impurity diffusion layer 101 in the P well 108. For example, the position of the P-type impurity diffusion layer 202 is in the range of 0.1 μm to 0.4 μm from the surface of the silicon substrate 100. In the formation of the P-type impurity diffusion layer 202, for example, B is used as the P-type impurity, the implantation energy is several tens of keV to 130 keV, and the dose (P ₂ (cm ⁻² )) is 1 × 10 ¹¹ cm ⁻² to 1. × and 10 ¹³ cm ^-2, the tilt angle is set to 2 ° to 40 °.

  FIG. 8 is a diagram showing a positional relationship in plan view between the N-type impurity diffusion layer 101 and the P-type impurity diffusion layer 202 when oblique ion implantation is performed from four directions. FIG. FIG. 8B shows the pixel 2. As shown in FIGS. 8A and 8B, in the pixel 2, the N-type impurity diffusion layer 101 is narrower and the P-type impurity diffusion layer 202 is thinner than the pixel 1. In this example, oblique ion implantation is performed from four directions, but oblique ion implantation may be performed from two directions. FIG. 9 shows a positional relationship in plan view between the N-type impurity diffusion layer 101 and the P-type impurity diffusion layer 202 when oblique ion implantation is performed from two directions.

Next, as illustrated in FIG. 7B, the resist pattern 111 is removed, and a resist pattern 112 is formed over the insulating film 109. In the formation of the resist pattern 112, a thin resist film having a thickness of 500 nm to 1 μm is formed, and an opening 112a is formed by a photolithography technique at a position where the PD of the pixel array is formed. At this time, in both the pixel 1 and the pixel 2, the opening area of the opening 112a is assumed to be as designed (SA (μm ² )).

7B, N-type impurity ions are implanted using the resist pattern 112 as a mask so as to overlap the P-type impurity diffusion layer 202 above the N-type impurity diffusion layer 101. An N-type impurity diffusion layer 103 shallower than 101 is formed in the P well 108. For example, the position of the N-type impurity diffusion layer 103 is in the range of 0.1 μm to 0.4 μm from the surface of the silicon substrate 100. In the formation of the N-type impurity diffusion layer 103, for example, P is used as the N-type impurity, the implantation energy is 80 keV to 300 keV, and the dose (SN (cm ⁻² )) is 1 × 10 ¹¹ cm ^{−2 to} 5 × 10. ¹³ cm- ² . When forming the N-type impurity diffusion layer 103, oblique ion implantation with a tilt angle of 7 ° or less may be performed.

  Subsequently, as shown in FIG. 7C, similarly to the first embodiment, the processes from the removal of the resist pattern 112 to the formation of the microlens 165 are performed.

  In this way, the semiconductor device according to the second embodiment can be manufactured.

  Next, effects of the second embodiment will be described. Table 2 shows parameters used for the calculation of the saturation charge amount in the second embodiment. The planar shape of the opening 111a is a square having a width of R (μm). FIG. 10 is a diagram showing geometric relationships of various dimensions in the second embodiment.

In the second embodiment, the area of the P well 108 into which the P-type impurity is implanted is “(R + 2Rp · tan δ) ² − (2 (T + Rp) · tan δ−R) ² = (4T + 8Rp) R · tan δ−4T”. (T + 2Rp) (tan δ) ² ”. Accordingly, the saturation charge amount Q (R) of the pixel 1 is “α · DN · R ² −β · P ₂ · [(4T + 8Rp) R · tan δ−4T (T + 2Rp) (tan δ) ² ] + γ · SN · SA”. is there. The change in the saturation charge amount Q (R) when the width R varies by ΔR (μm) is “dQ (R) / dR · ΔR”. Accordingly, the difference ΔQ in the saturation charge amount between the pixel 1 and the pixel 2 is “2 (α · DN · R−β · P ₂ · (2T + 4Rp) tan δ) · ΔR”. That is, by reducing the value of “2 (α · DN · R−β · P ₂ · (2T + 4Rp) tan δ)”, it is possible to reduce the variation in the saturation charge due to the variation in the shape of the opening 111a. If the dose amount P ₂ is about α · DN · R / (β · (2T + 4Rp) tan δ), the variation of the saturation charge amount does not substantially occur.

  Thus, in the second embodiment, oblique ion implantation is performed to form the P-type impurity diffusion layer 202. Therefore, when the width R of the opening 112a is larger than the design value, the width of the P-type impurity diffusion layer 202 is larger than the design value, and when the width R is smaller than the design value, the width of the P-type impurity diffusion layer 202 is designed. Smaller than the value. Therefore, variation in the amount of net N-type impurity in the N-type impurity diffusion layer 101 due to variation in width R is compensated, and variation in saturation charge amount is suppressed.

  In the second embodiment, the saturation charge amount is slightly reduced due to the P-type impurity diffusion layer 202, but can be compensated by the shallow N-type impurity diffusion layer 103.

  In the second embodiment, as shown in FIG. 7B, the P-type impurity diffusion layer 202 is not formed in the central portion of the N-type impurity diffusion layer 103. Therefore, the N-type impurity diffusion layer 103 and the P-type impurity diffusion layer 202 are not formed. 5 is not formed in the path through which electrons pass through the central portion of the N-type impurity diffusion layer 103, and therefore, It is possible to reduce the occurrence of afterimages accompanying the movement hindrance.

(Third embodiment)
Next, a third embodiment will be described. The third embodiment relates to a semiconductor device suitable for a CMOS image sensor and a method for manufacturing the same. For convenience of explanation, the structure of the semiconductor device will be described together with its manufacturing method. FIG. 11A to FIG. 11D are cross-sectional views showing the method of manufacturing the semiconductor device according to the third embodiment in the order of steps. 11A to 11D show a pixel 1 in which the size of the opening of the resist pattern did not deviate from the design value, and a pixel 2 in which the size of the opening has deviated.

  First, as shown in FIG. 11A, processing up to the formation of the P-type impurity diffusion layer 102 is performed as in the first embodiment. Next, as shown in FIG. 11B, as in the second embodiment, oblique ion implantation of P-type impurities is performed using the resist pattern 111 as a mask to form a P-type impurity diffusion layer 202.

  Thereafter, as shown in FIG. 11C, processing from the removal of the resist pattern 111 to the formation of the N-type impurity diffusion layer 103 is performed. Subsequently, as shown in FIG. 11D, processing from the removal of the resist pattern 112 to the formation of the microlens 165 is performed.

  In this way, the semiconductor device according to the third embodiment can be manufactured.

In the third embodiment, the saturation charge amount Q1 of the pixel 1 is “(α · DN−β · P ₁ ) · R ² −β · P ₂ · [(4T + 8Rp) R · tan δ−4T (T + 2Rp) (tan δ). ² ] + γ · SN · SA ”, and the saturation charge amount Q2 of the pixel 2 is“ (α · DN−β · P ₁ ) · (R−ΔR) ² −β · P ₂ · [(4T + 8Rp) (R− ΔR) · tan δ−4T (T + 2Rp) (tan δ) ² ] + γ · SN · SA ”. Accordingly, the difference ΔQ in the saturation charge amount between the pixel 1 and the pixel 2 is substantially “2 (α · DN · R−β · P ₁ −2β · P ₂ · (T + 2Rp) tan δ) · ΔR”. . That is, by reducing the value of “α · DN · R−β · P ₁ −2β · P ₂ · (T + 2Rp) tan δ”, the variation in the saturation charge due to the variation in the shape of the opening 111a is reduced. In addition, by adjusting the doses P ₁ and P ₂ , it is possible to substantially prevent the variation in the saturation charge amount.

(Fourth embodiment)
Next, a fourth embodiment will be described. The fourth embodiment relates to a semiconductor device suitable for a CMOS image sensor and a manufacturing method thereof. For convenience of explanation, the structure of the semiconductor device will be described together with its manufacturing method. 12A to 12D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the fourth embodiment in the order of steps. 12A to 12D show the pixel 1 in which the size of the opening of the resist pattern did not deviate from the design value, and the pixel 2 in which the size of the opening has deviated.

  First, as shown in FIG. 12A, processing up to the formation of the P-type impurity diffusion layer 102 is performed as in the first embodiment. However, the N-type impurity diffusion layer 101 is formed deeper than in the first embodiment, and the P-type impurity diffusion layer 102 is formed shallower than in the first embodiment. For example, the position of the N-type impurity diffusion layer 101 is in the range of 1 μm to 3 μm from the surface of the silicon substrate 100, and the position of the P-type impurity diffusion layer 102 is in the range of 0.1 μm to 0.3 μm from the surface of the silicon substrate 100. And

  Next, as illustrated in FIG. 12B, the resist pattern 111 is removed, and a resist pattern 113 is formed over the insulating film 109. In the formation of the resist pattern 113, a thin resist film having a thickness of 1 μm to 2 μm is formed, and an opening 113a is formed by a photolithography technique at a position where the PD of the pixel array is formed.

Thereafter, as shown in FIG. 12B, N-type impurities and P-type impurities are ion-implanted using the resist pattern 113 as a mask, and an N-type impurity is interposed between the N-type impurity diffusion layer 101 and the P-type impurity diffusion layer 102. A diffusion layer 501 and a P-type impurity diffusion layer 502 having a circular planar shape are formed. For example, the position of the N-type impurity diffusion layer 501 is in the range of 0.5 μm to 1 μm from the surface of the silicon substrate 100. In the formation of the N-type impurity diffusion layer 501, for example, P is used as the N-type impurity, the implantation energy is 300 keV to 800 keV, and the dose is 1 × 10 ¹¹ cm ⁻² to 1 × 10 ¹³ cm ⁻² . When the N-type impurity diffusion layer 501 is formed, oblique ion implantation with a tilt angle of 7 ° or less may be performed. For example, the position of the P-type impurity diffusion layer 502 is in the range of 0.5 μm to 1 μm from the surface of the silicon substrate 100. In the formation of the P-type impurity diffusion layer 502, for example, B is used as the P-type impurity, the implantation energy is 150 keV to 400 keV, the dose is 1 × 10 ¹¹ cm ⁻² to 1 × 10 ¹³ cm ⁻² , and the tilt angle Is 10 ° to 30 °. The peak depths of the N-type impurity diffusion layer 501 and the P-type impurity diffusion layer 502 are approximately the same. Also in this example, oblique ion implantation is performed from four directions, but oblique ion implantation may be performed from two directions.

  Subsequently, as shown in FIG. 12C, the resist pattern 113 is removed, and processing from the formation of the resist pattern 113 to the formation of the N-type impurity diffusion layer 103 is performed in the same manner as in the first embodiment. However, the N-type impurity diffusion layer 103 is formed deeper than in the first embodiment. For example, the position of the N-type impurity diffusion layer 103 is in the range of 0.1 μm to 0.4 μm from the surface of the silicon substrate 100.

  Next, as shown in FIG. 12D, similarly to the first embodiment, processing from the removal of the resist pattern 112 to the formation of the microlens 165 is performed.

  In this way, the semiconductor device according to the fourth embodiment can be manufactured.

  In the fourth embodiment, even if a deviation occurs in the shape of the opening 111a, the variation of the saturation charge amount can be reduced by the action of the P-type impurity diffusion layer 102, as in the first embodiment. Even if the shape of the opening 113a is deviated, the variation of the saturation charge amount can be reduced by the action of the P-type impurity diffusion layer 502 as in the second embodiment.

(Fifth embodiment)
Next, a fifth embodiment will be described. The fifth embodiment relates to a semiconductor device suitable for a CMOS image sensor and a manufacturing method thereof. FIG. 13 is a cross-sectional view showing a semiconductor device according to the fifth embodiment.

  The semiconductor device 50 according to the fifth embodiment includes a pixel array including a plurality of pixels 51 as in the first embodiment. The pixel pitch is about 1 μm to 3 μm. Unlike the first embodiment, each pixel 51 includes two PDs 61 and 62 as shown in FIG. The size of the PDs 61 and 62 depends on the position in the pixel array. As the pixel 51 is closer to the periphery of the pixel array, the areas of the N-type impurity diffusion layers 101 included in the PDs 61 and 62 in the pixel 51 are greatly different. In FIG. 13, PD 62 is closer to the center of the pixel array than PD 61, and the area of N-type impurity diffusion layer 101 included in PD 62 is smaller than the area of N-type impurity diffusion layer 101 included in PD 61.

  In the semiconductor device 50 configured as described above, as shown in FIG. 13, the light 71 incident from substantially the front of the pixel 51 is incident on the PD 62 from a direction nearly perpendicular to the rear surface of the silicon substrate 100. On the other hand, the light 72 incident from the center side of the pixel array enters the PD 61 from a direction nearly parallel to the back surface of the silicon substrate 100. In such a case, if the size of the N-type impurity diffusion layer 101 is approximately the same, the sensitivity of the PD 62 is higher than the sensitivity of the PD 61. In this embodiment, the area of the N-type impurity diffusion layer 101 of the PD 61 is N-type of the PD 62. Since it is larger than the area of the impurity diffusion layer 101, the sensitivity between the PDs 61 and 62 is comparable.

  Further, when the size of the N-type impurity diffusion layer 101 is different, a difference in saturation charge amount may occur between the PDs 61 and 62. However, in the present embodiment, a size corresponding to the size of the N-type impurity diffusion layer 101 is generated. A P-type impurity diffusion layer 102 is included in the PDs 61 and 62. Accordingly, the saturation charge amount is approximately the same on the same principle as in the first embodiment.

  The pixel 51 having such a configuration is, for example, a low-noise and high-sensitivity CMOS image sensor that achieves both image plane phase difference AF and imaging in the document “Video Information Media Society Technical Report VOL.39, NO.35”. And the phase difference autofocus described in International Publication No. 2014/097884.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1)
A first N-type impurity diffusion layer formed on the semiconductor substrate;
A first P-type impurity diffusion layer formed above the first N-type impurity diffusion layer of the semiconductor substrate;
A second N-type impurity diffusion layer formed above the first N-type impurity diffusion layer of the semiconductor substrate and at least partially overlapping the first P-type impurity diffusion layer;
Have
The semiconductor device characterized in that the potential well for electrons in the second N-type impurity diffusion layer includes a first device deeper than the potential well for electrons in the first N-type impurity diffusion layer.

(Appendix 2)
2. The semiconductor device according to appendix 1, wherein the first P-type impurity diffusion layer overlaps the entire first N-type impurity diffusion layer in plan view.

(Appendix 3)
2. The semiconductor device according to appendix 1, wherein the first P-type impurity diffusion layer overlaps a part of the first N-type impurity diffusion layer in plan view.

(Appendix 4)
The semiconductor device according to appendix 3, wherein the planar shape of the first P-type impurity diffusion layer is annular.

(Appendix 5)
The semiconductor device according to any one of appendices 1 to 4, wherein the second N-type impurity layer is formed in a larger area than the first N-type impurity diffusion layer.

(Appendix 6)
A third N-type impurity diffusion layer formed on the surface of the semiconductor substrate;
A gate electrode formed between the second N-type impurity diffusion layer and the third N-type impurity diffusion layer in plan view on the semiconductor substrate;
Have
6. The semiconductor device according to claim 1, wherein a potential well for electrons in the third N-type impurity diffusion layer is deeper than a potential well for electrons in the second N-type impurity diffusion layer. .

(Appendix 7)
A fourth N-type impurity diffusion layer formed on the semiconductor substrate;
A second P-type impurity diffusion layer formed above the fourth N-type impurity diffusion layer of the semiconductor substrate;
A fifth N-type impurity diffusion layer formed above the fourth N-type impurity diffusion layer of the semiconductor substrate and at least partially overlapping the second P-type impurity diffusion layer;
Have
A potential well for electrons of the fifth N-type impurity diffusion layer is deeper than a potential well for electrons of the fourth N-type impurity diffusion layer;
In plan view, the area of the fourth N-type impurity diffusion layer is larger than the area of the first N-type impurity diffusion layer, and the area of the second P-type impurity diffusion layer is the first P-type impurity diffusion layer. The semiconductor device according to appendix 1, further comprising a second device larger than the area of the first device.

(Appendix 8)
Forming a first N-type impurity diffusion layer in a semiconductor substrate by ion implantation of a first N-type impurity using a first resist pattern having a first thickness as a mask;
Forming a P-type impurity diffusion layer above the first N-type impurity diffusion layer of the semiconductor substrate by ion implantation of P-type impurities using the first resist pattern as a mask;
By ion implantation of a second N-type impurity using a second resist pattern having a second thickness smaller than the first thickness as a mask, above the first N-type impurity diffusion layer of the semiconductor substrate, Forming a second N-type impurity diffusion layer at least partially overlapping the P-type impurity diffusion layer;
Have
A method of manufacturing a semiconductor device, wherein a potential well for electrons of the second N-type impurity diffusion layer is deeper than a potential well for electrons of the first N-type impurity diffusion layer.

(Appendix 9)
9. The method of manufacturing a semiconductor device according to appendix 8, wherein the P-type impurity diffusion layer is formed so as to overlap the entire first N-type impurity diffusion layer in plan view.

(Appendix 10)
9. The semiconductor device according to appendix 8, wherein the P-type impurity diffusion layer is formed so as to overlap a part of the first N-type impurity diffusion layer in plan view by oblique ion implantation of the P-type impurity. Manufacturing method.

(Appendix 11)
11. The method of manufacturing a semiconductor device according to appendix 10, wherein the planar shape of the P-type impurity diffusion layer is annular.

(Appendix 12)
12. The method of manufacturing a semiconductor device according to any one of appendices 8 to 11, wherein the second N-type impurity diffusion layer is formed with a larger area than the first N-type impurity diffusion layer.

(Appendix 13)
Forming a third N-type impurity diffusion layer on the surface of the semiconductor substrate;
Forming a gate electrode between the second N-type impurity diffusion layer and the third impurity diffusion layer in plan view on the semiconductor substrate;
Have
13. The semiconductor device according to any one of appendices 8 to 12, wherein a potential well for electrons in the third N-type impurity diffusion layer is deeper than a potential well for electrons in the second N-type impurity diffusion layer. Manufacturing method.

21: Photodiode 30: P well 31: Deep N type impurity diffusion layer 32: P type impurity diffusion layer 33: Shallow N type impurity diffusion layer 100: Silicon substrate 108: P well 101: Deep N type impurity diffusion layer 102, 202 : P-type impurity diffusion layer 103: Shallow N-type impurity diffusion layer 111: Thick resist pattern 112: Thin resist pattern

Claims (10)

A first N-type impurity diffusion layer formed on the semiconductor substrate;
A first P-type impurity diffusion layer formed above the first N-type impurity diffusion layer of the semiconductor substrate;
A second N-type impurity diffusion layer formed above the first N-type impurity diffusion layer of the semiconductor substrate and at least partially overlapping the first P-type impurity diffusion layer;
Have
The semiconductor device characterized in that the potential well for electrons in the second N-type impurity diffusion layer includes a first device deeper than the potential well for electrons in the first N-type impurity diffusion layer.   2. The semiconductor device according to claim 1, wherein the first P-type impurity diffusion layer overlaps the entire first N-type impurity diffusion layer in plan view.   2. The semiconductor device according to claim 1, wherein the first P-type impurity diffusion layer overlaps with a part of the first N-type impurity diffusion layer in plan view.   4. The semiconductor device according to claim 3, wherein the planar shape of the first P-type impurity diffusion layer is annular.   5. The semiconductor device according to claim 1, wherein the second N-type impurity layer has a larger area than the first N-type impurity diffusion layer. 6. A fourth N-type impurity diffusion layer formed on the semiconductor substrate;
A second P-type impurity diffusion layer formed above the fourth N-type impurity diffusion layer of the semiconductor substrate;
A fifth N-type impurity diffusion layer formed above the fourth N-type impurity diffusion layer of the semiconductor substrate and at least partially overlapping the second P-type impurity diffusion layer;
Have
A potential well for electrons of the fifth N-type impurity diffusion layer is deeper than a potential well for electrons of the fourth N-type impurity diffusion layer;
In plan view, the area of the fourth N-type impurity diffusion layer is larger than the area of the first N-type impurity diffusion layer, and the area of the second P-type impurity diffusion layer is the first P-type impurity diffusion layer. The semiconductor device according to claim 1, further comprising a second device having a larger area. Forming a first N-type impurity diffusion layer in a semiconductor substrate by ion implantation of a first N-type impurity using a first resist pattern having a first thickness as a mask;
Forming a P-type impurity diffusion layer above the first N-type impurity diffusion layer of the semiconductor substrate by ion implantation of P-type impurities using the first resist pattern as a mask;
By ion implantation of a second N-type impurity using a second resist pattern having a second thickness smaller than the first thickness as a mask, above the first N-type impurity diffusion layer of the semiconductor substrate, Forming a second N-type impurity diffusion layer at least partially overlapping the P-type impurity diffusion layer;
Have
A method of manufacturing a semiconductor device, wherein a potential well for electrons of the second N-type impurity diffusion layer is deeper than a potential well for electrons of the first N-type impurity diffusion layer.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the P-type impurity diffusion layer is formed to overlap the entire first N-type impurity diffusion layer in plan view.   8. The semiconductor according to claim 7, wherein the P-type impurity diffusion layer is formed so as to overlap a part of the first N-type impurity diffusion layer in a plan view by oblique ion implantation of the P-type impurity. Device manufacturing method.   The method of manufacturing a semiconductor device according to claim 9, wherein the planar shape of the P-type impurity diffusion layer is annular.

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