JP2018121325A - Solid-state imaging device, imaging system, and mobile body - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging device capable of outputting a signal for abnormality detection with higher accuracy.SOLUTION: The solid-state imaging device includes: a pixel that outputs a pixel signal that is an analog signal; a readout unit for converting a pixel signal into a digital signal to generate a digital pixel signal; a storage unit for storing the digital pixel signal; and a first inspection signal output unit that outputs a first inspection signal to the storage unit and stores it in the storage unit. The first inspection signal stored in the storage unit is output from the storage unit after the output of the digital pixel signal of a certain frame is finished and during the period before starting the output of the digital pixel signal of the next frame.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a solid-state imaging device, an imaging system, and a moving body.

  In recent years, there has been a demand for improved solid-state imaging devices and improved reliability. In particular, in applications such as in-vehicle use, the use environment is severe and safety measures are extremely important, and an imaging system having a failure detection function is required as a function safety measure. Accordingly, it is necessary to incorporate a failure detection mechanism in the solid-state imaging device.

  Patent Document 1 discloses an image sensor having dark pixels in a pixel array. The image sensor disclosed in Patent Document 1 describes that abnormality detection can be performed by comparing an output when a predetermined verification voltage is applied to a dark pixel with an output expected when there is no abnormality. .

  In Patent Document 2, in a solid-state imaging device having a function of converting a pixel signal from an analog signal to a digital signal, a test signal is written to and read from a column memory that holds the pixel signal converted into a digital signal. Describes a technique for inspecting column memory.

US Patent Application Publication No. 2013/0027565 JP, 2015-201879, A

  Since the output signal from the dark pixel is an analog signal, noise of the readout circuit may be included in the signal during readout. Therefore, when the output signal from the readout circuit is converted from analog to digital and the converted digital value is held in the memory, the value in the lower digit of the value held in the memory is expected to be expected due to the influence of noise. May be different. That is, an error due to noise may occur in the abnormality detection signal. Therefore, if the lower digit of the value held in the memory is different from the expected value, it may be difficult to determine whether it is caused by an abnormality in the reading circuit or noise. . For the above reasons, it may be difficult to determine the presence or absence of abnormality in abnormality detection using output from dark pixels.

  SUMMARY An advantage of some aspects of the invention is that it provides a solid-state imaging device capable of outputting a more accurate abnormality detection signal.

  According to an aspect of the present invention, a pixel that outputs a pixel signal that is an analog signal, a reading unit that converts the pixel signal into a digital signal and generates a digital pixel signal, and a storage unit that stores the digital pixel signal And a first inspection signal output unit that outputs the first inspection signal to the storage unit and stores the first inspection signal in the storage unit, and the first inspection signal stored in the storage unit There is provided a solid-state imaging device that outputs from the storage unit in a period after the output of the digital pixel signal is finished and before the output of the digital pixel signal of the next frame is started.

  According to another aspect of the present invention, a pixel that outputs a pixel signal that is an analog signal, a reading unit that converts the pixel signal into a digital signal and generates a digital pixel signal, and the digital pixel signal A storage unit for storing, and a first inspection signal output unit for outputting the first inspection signal to the storage unit and storing the first inspection signal in the storage unit, wherein the first inspection signal stored in the storage unit is A solid-state imaging device that is output from the storage unit in a period after the output of the digital pixel signal of a certain frame is finished and before the output of the digital pixel signal of the next frame is started, and the solid-state imaging device There is provided an imaging system including a signal processing unit that processes a signal output from the computer.

  According to still another aspect of the present invention, a pixel that outputs a pixel signal that is an analog signal and a reading unit that generates the digital pixel signal by converting the pixel signal into a digital signal. And a storage unit that stores the digital pixel signal, and a first inspection signal output unit that outputs the first inspection signal to the storage unit and stores the first inspection signal in the storage unit, and is stored in the storage unit The first inspection signal is output from the storage unit after the output of the digital pixel signal of a certain frame is finished and before the output of the digital pixel signal of the next frame is started. Apparatus, distance information acquisition means for acquiring distance information to an object from a parallax image based on the pixel signal output from the pixel of the solid-state imaging device, and controlling the moving body based on the distance information Moving body is provided with a that control means.

  According to still another aspect of the present invention, a plurality of pixels arranged so as to form a matrix including a plurality of columns and a plurality of rows are provided corresponding to the plurality of columns. A plurality of memories each holding as a digital value information based on signals output from the pixels arranged in a column; an inspection information supply unit for supplying inspection information for fault inspection to the plurality of memories; An output circuit for outputting information held by the memory, wherein the output circuit outputs information based on signals output from the plurality of pixels in units of rows, and the output circuit includes the plurality of memories. The inspection information held in a part of the plurality of memories is output in a first period corresponding to an output period for one row, and the inspection information held in another part of the plurality of memories is output in the first period It is separate from the period of In the first period and the second period, output operation of pixel information of one row by the output circuit and pixel information of another row by the output circuit are performed in the corresponding second period, respectively. A solid-state imaging device is provided which is a period between the output operations.

  According to the present invention, it is possible to provide a solid-state imaging device capable of outputting a more accurate abnormality detection signal.

It is a block diagram of the solid-state imaging device concerning a 1st embodiment. FIG. 3 is an equivalent circuit diagram of a pixel according to the first embodiment. It is a schematic diagram which shows the read-out operation | movement for 1 line of the solid-state imaging device which concerns on 1st Embodiment. It is a schematic diagram which shows the vertical scanning method of the solid-state imaging device which concerns on 1st Embodiment. It is a schematic diagram of the image data output from the solid-state imaging device which concerns on 1st Embodiment. It is a flowchart which shows operation | movement of the imaging system carrying the solid-state imaging device concerning 1st Embodiment. It is a block diagram of the solid-state imaging device concerning a 2nd embodiment. It is a schematic diagram of the image data output from the solid-state imaging device which concerns on 2nd Embodiment. It is a flowchart which shows operation | movement of the imaging system carrying the solid-state imaging device concerning 2nd Embodiment. It is a block diagram of the solid-state imaging device concerning a 3rd embodiment. It is a block diagram of the input selection circuit concerning a 3rd embodiment. It is a schematic diagram of the image data output from the solid-state imaging device which concerns on 3rd Embodiment. It is a flowchart which shows operation | movement of the imaging system carrying the solid-state imaging device which concerns on 3rd Embodiment. It is a block diagram of the solid-state imaging device concerning a 4th embodiment. It is a schematic diagram of the image data output from the solid-state imaging device which concerns on 4th Embodiment. It is a flowchart which shows operation | movement of the imaging system carrying the solid-state imaging device which concerns on 4th Embodiment. It is a block diagram which shows schematic structure of the solid-state imaging device which concerns on 5th Embodiment. It is a circuit diagram which shows the structural example of the pixel in the solid-state imaging device which concerns on 5th Embodiment. It is a block diagram (the 1) which shows the structural example of the memory part in the solid-state imaging device which concerns on 5th Embodiment, a horizontal scanning circuit, and a horizontal transfer circuit. It is a block diagram (the 2) which shows the structural example of the memory part in the solid-state imaging device which concerns on 5th Embodiment, a horizontal scanning circuit, and a horizontal transfer circuit. It is a block diagram (the 3) which shows the structural example of the memory part in the solid-state imaging device which concerns on 5th Embodiment, a horizontal scanning circuit, and a horizontal transfer circuit. It is the schematic explaining the read-out operation | movement of 1 line in the solid-state imaging device which concerns on 5th Embodiment. It is the schematic which shows the drive method of the solid-state imaging device which concerns on 5th Embodiment. It is a schematic diagram which shows the structural example of the data in the signal processing apparatus outside a solid-state imaging device. It is a flowchart which shows the failure detection method of the solid-state imaging device which concerns on 5th Embodiment. It is a block diagram (the 1) which shows the structural example of the memory part in the solid-state imaging device which concerns on 6th Embodiment, a horizontal scanning circuit, and a horizontal transfer circuit. It is a block diagram (the 2) which shows the structural example of the memory part in the solid-state imaging device which concerns on 6th Embodiment, a horizontal scanning circuit, and a horizontal transfer circuit. It is a timing chart which shows the drive method of the solid-state imaging device concerning a 6th embodiment. It is a schematic diagram which shows the structural example of the data in the signal processing apparatus outside a solid-state imaging device. It is a block diagram which shows schematic structure of the solid-state imaging device which concerns on 7th Embodiment. It is a block diagram (the 1) which shows the structural example of the memory part in the solid-state imaging device which concerns on 7th Embodiment, a horizontal scanning circuit, and a horizontal transfer circuit. It is a block diagram (the 2) which shows the structural example of the memory part in the solid-state imaging device which concerns on 7th Embodiment, a horizontal scanning circuit, and a horizontal transfer circuit. It is a timing chart which shows the drive method of the solid-state imaging device concerning a 7th embodiment. It is a timing chart which shows the drive method of the solid-state imaging device concerning 8th Embodiment of this invention. It is a schematic diagram which shows the structure of the moving body which concerns on 9th Embodiment of this invention. It is a block diagram of the mobile body which concerns on 9th Embodiment of this invention.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. In each figure, the same reference numerals are given to the same components or components corresponding to each other. In each of the following embodiments, the description of overlapping components may be omitted or simplified.

[First Embodiment]
FIG. 1 is a block diagram showing a schematic configuration of a solid-state imaging device 100 according to the first embodiment of the present invention. The solid-state imaging device 100 includes a timing generator 102, a vertical scanning circuit 103, a comparison circuit unit 104, a counter 105, a column memory 106, a horizontal scanning circuit 107, an image output circuit 108, a voltage supply unit 109, and a pixel array 110.

  The pixel array 110 includes a plurality of pixels 101 arranged two-dimensionally over a plurality of rows and a plurality of columns. The vertical scanning circuit 103 supplies a plurality of control signals for driving the plurality of pixels 101 for each row. The vertical scanning circuit 103 can include logic circuits such as a shift register and an address decoder. In the figure, for the sake of simplification, only one control signal line is shown for each row, but actually includes a plurality of control signal lines. The pixels 101 in the row selected by the vertical scanning circuit 103 output pixel signals, which are analog signals, to the comparison circuit unit 104 via vertical output lines provided corresponding to the respective columns of the pixel array 110.

  The comparison circuit unit 104 includes a plurality of sample and hold circuits, a plurality of comparators, a reference signal generation unit, and the like. A sample hold circuit and a comparator are provided corresponding to each column of the pixel array. The counter 105 performs a count operation and outputs a count value. The column memory 106 has a storage area corresponding to each column of the pixel array, and the count value from the counter 105 is input to each storage area.

  The pixel signal input to the comparison circuit unit 104 is held in the sample hold circuit in the corresponding column. The reference signal generation unit generates a reference signal whose voltage changes with time. For example, a ramp signal may be used as the waveform of the reference signal. The comparator compares the pixel signal held in the sample hold circuit with the reference signal output from the reference signal generation unit and the voltage magnitude relationship, and outputs a latch signal when the magnitude relationship is inverted. The counter 105 causes the column memory 106 to store a count value corresponding to the time from the start of the change of the reference signal to the output of the latch signal. This count value corresponds to a pixel signal converted into a digital signal. That is, the comparison circuit unit 104, the counter 105, and the column memory 106 have a function as a reading unit and a storage unit that store pixel signals by analog-digital conversion (hereinafter referred to as AD conversion). In this specification, a pixel signal (digital pixel signal) converted into a digital signal is referred to as image data. One image is composed of a plurality of image data. The column memory 106 has a function as a storage unit that stores image data obtained by AD converting pixel signals. Normally, the column memory 106 holds a multi-bit digital signal. Note that in the above-described reading unit, the reference signal may be input from the outside of the comparison circuit unit 104.

  The horizontal scanning circuit 107 outputs a control signal for sequentially transferring the image data stored in the column memory 106 to the image output circuit 108 for each column. The image output circuit 108 outputs the image data transferred from the column memory 106 to a signal processing unit (not shown) outside the solid-state imaging device 100. The voltage supply unit 109 can set a stored digital value to a desired value by supplying a voltage of a desired level to a storage area corresponding to each bit of each column of the column memory 106. Thereby, the voltage supply unit 109 functions as a first inspection signal output unit that initializes the column memory 106 and further supplies a first inspection signal that is a digital signal to the column memory 106. The voltage supply unit 109 can perform initialization by supplying a voltage (for example, a fixed voltage such as 0 V) that sets the value of each bit of each column of the column memory 106 to “0”. The supply of the first inspection signal will be described later.

  The timing generator 102 supplies timing signals to the vertical scanning circuit 103, the counter 105, the horizontal scanning circuit 107, and the voltage supply unit 109, and controls the operation timing of each unit.

  FIG. 2 is an equivalent circuit diagram of the pixel 101 according to the first embodiment. In FIG. 2, two pixels 101 in the same column in the pixel array 110 are extracted and shown. The pixel 101 includes a photoelectric conversion unit PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4. The photoelectric conversion unit PD is, for example, a photodiode. The photodiode of the photoelectric conversion unit PD has an anode connected to the ground and a cathode connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to the source of the reset transistor M2 and the gate of the amplification transistor M3. A connection node of the drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplification transistor M3 constitutes a floating diffusion FD. The drain of the reset transistor M2 and the drain of the amplification transistor M3 are connected to the power supply voltage terminal VDD. The source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the vertical output line.

  The vertical scanning circuit 103 supplies control signals PTX, PRES, and PSEL to the gate of the transfer transistor M1, the gate of the reset transistor M2, and the gate of the selection transistor M4, respectively. When each transistor is formed of an N-type transistor, the corresponding transistor is turned on when a high-level control signal is supplied from the vertical scanning circuit 103, and the corresponding transistor is turned on when a low-level control signal is supplied from the vertical scanning circuit 103. Transistor is turned off.

  The photoelectric conversion unit PD converts incident light into an amount of charge corresponding to the amount of light (photoelectric conversion) and accumulates the generated charge. When the transfer transistor M1 is turned on, the charge of the photoelectric conversion unit PD is transferred to the floating diffusion FD. The floating diffusion FD becomes a voltage corresponding to the amount of charge transferred from the photoelectric conversion unit PD by charge-voltage conversion by the capacitance. The amplification transistor M3 has a configuration in which a power supply voltage is supplied to the drain and a bias current is supplied to the source from a current source (not shown) via the selection transistor M4, and constitutes a source follower circuit having a gate as an input node. . Thus, the amplification transistor M3 outputs the voltage VLINE based on the voltage of the floating diffusion FD to the vertical output line as a pixel signal via the selection transistor M4. The reset transistor M2 resets the floating diffusion FD to a voltage corresponding to the power supply voltage when turned on.

  Note that the names of the source and the drain of the transistor may differ depending on the conductivity type of the transistor, the function of interest, and the like, and the above-described source and drain may be referred to as opposite names.

  FIG. 3 is a schematic diagram illustrating a reading operation for one row of the solid-state imaging device 100 according to the first embodiment. A reading operation for one row of the solid-state imaging device 100 will be described with reference to FIG. First, in a period T1, pixel signals are read. The pixel 101 in the row outputs a pixel signal to the vertical output line. The pixel signal is input to the comparison circuit unit 104 and held in the sample hold circuit. Next, in the period T 2, AD conversion is performed in the comparison circuit unit 104, the counter 105, and the column memory 106 by the above-described method, and image data of the digital signal obtained thereby is stored in the column memory 106. Next, in a period T3, image data is read from the column memory 106 to the image output circuit 108 in accordance with the scanning of the horizontal scanning circuit 107. Thereafter, in the period T4, the voltage supply unit 109 performs initialization by supplying a voltage (for example, a fixed voltage such as 0V) that sets the value of each bit of each column of the column memory 106 to “0”.

  FIG. 4 is a schematic diagram illustrating a vertical scanning method of the solid-state imaging device 100 according to the first embodiment. The vertical scanning method shown in FIG. 4 shows an outline of scanning for image acquisition during moving image shooting by extracting two frames. In FIG. 4, it is assumed that light is incident on the pixel 101 over the entire period, and light shielding by the mechanical shutter is not considered. The hatched frame in FIG. 4 indicates shutter scanning. The shutter scan is a scan in which an electronic shutter operation for resetting the photoelectric conversion unit PD of the pixel 101 is sequentially performed for each row. More specifically, in the period indicated by the hatched frame, both the transfer transistor M1 and the reset transistor M2 in the pixel 101 in the corresponding row are turned on. Thereby, the electric charge accumulated in the photoelectric conversion unit PD is discharged from the power supply voltage terminal VDD, and the photoelectric conversion unit PD is reset. After this electronic shutter operation, the photoelectric conversion unit PD accumulates charges generated by photoelectrically converting incident light. After a predetermined period has elapsed after the electronic shutter operation, readout scanning is performed in which the readout operation shown in FIG. 3 is sequentially performed for each row. The period from shutter scanning to readout scanning is the accumulation period, and the scanning timing is set so that the length of the accumulation period is the same for each row.

  In the period from the end of the reading scan to the start of the next reading scan, image data is not written to the column memory 106. Therefore, this period is a column memory inspection period for inspecting the abnormality of the column memory 106. When the column memory 106 is initialized, the voltage supply unit 109 inputs a voltage that gives “0” to each bit. In the column memory inspection period, “1” is given to at least some of the bits. A voltage (for example, the same voltage as the power supply voltage of the column memory 106) can also be input. As a result, the voltage supply unit 109 can store the bit arrangement of a predetermined memory test pattern in the column memory 106. Examples of the memory test pattern of the column memory 106 include an example in which “0” is input to each bit of the column memory 106 of all columns, and an example in which 1 is input to each bit of the column memory 106 of all columns. Further, in order to check for a short circuit between adjacent columns, “0101...” Is input to the column memory 106 of a certain column in order from the upper bit, and the column memory 106 of the adjacent column is sequentially input from the upper bit. An example of inputting “1010...” Is also given. In addition, in order to inspect a short circuit in one column, “0101...” Is input to the storage area of one column, and then a value different from “1010. Also mentioned. As described above, the voltage supply unit 109 can supply a voltage using a plurality of memory test patterns having different bit arrangement patterns.

  As described above, the voltage supply unit 109 of the present embodiment can store the first inspection signal including one or more of the plurality of memory inspection patterns for each bit of the column memory 106. it can. When the first test signal includes a plurality of memory test patterns having different values, the voltage supply unit 109 sequentially outputs and stores the plurality of memory test patterns in the column memory 106. Since this signal is supplied as a digital signal without passing through the reading unit, any number of bits is stored in the column memory 106 without being affected by external noise. Therefore, according to the present embodiment, a higher-accuracy inspection signal can be stored in the column memory 106 than in the case where an analog signal such as a signal output from a dark pixel is AD-converted into an inspection signal. It becomes possible. Thereby, it is possible to perform abnormality detection with higher accuracy by collating the memory test pattern input to the column memory 106 with the memory test pattern output from the column memory 106.

  FIG. 5A to FIG. 5D show one or a plurality of frames of image data among a number of frames of image data output from the image output circuit 108 of the solid-state imaging device 100 according to the first embodiment. It is a schematic diagram which shows the structure of these. A region 501 shown in FIG. 5A indicates image data acquired by the solid-state imaging device 100. Areas 502-1 to 502-4 show data of four types of memory test patterns. In this way, as shown in FIG. 5A, the memory test pattern data can be added to the image data of one frame and output. In the example shown in FIG. 5A, the memory test pattern data is added below the image data, that is, output after the memory test pattern data is output. However, this order may be reversed, and the memory test pattern data may be added above the image data as shown in FIG. In other words, the memory test pattern data may be output before the output of the image data. In this specification, in the schematic diagrams showing the frame configurations of FIGS. 5A to 5D, the signals indicated by the rectangular areas are sequentially output from the upper side in the figure. Shall. That is, these schematic diagrams show the order of data output. More specifically, FIG. 5A shows that the memory test pattern is output from the column memory 106 after the output of a certain frame of image data is completed. FIG. 5B shows that the memory test pattern is output from the column memory 106 before the output of a certain frame of image data is started. In addition, before and after the output of the signals shown in FIGS. 5A and 5B, image data of other frames is output. In other words, in FIG. 5 (a) and FIG. 5 (b), the memory test pattern is obtained after the output of image data of a certain frame is finished and before the output of image data of the next frame is started. It is output from the column memory 106 during the period.

  When the column memory inspection period is longer than the time required for inputting and outputting the column memory inspection pattern to the column memory 106, as shown in FIG. 5A or FIG. All the column memory test patterns can be added to the image. When the column memory inspection period is shorter than the above-described required time, it is impossible to secure time for adding data of all memory inspection patterns to one frame image. However, in this case as well, as shown in FIG. 5C or FIG. 5D, the column memory 106 is similarly inspected by dividing and adding a plurality of memory inspection patterns into a plurality of image data. It can be carried out. In the example shown in FIG. 5C, regions 501-1 to 501-4 indicate image data from the first frame to the fourth frame. In FIG. 5C, memory test pattern data is added to the image data of the first to fourth frames one by one. Further, as in the example shown in FIG. 5D, a configuration in which two memory test patterns are added to the image data of the first frame and the second frame may be used. An optimum configuration can be selected as appropriate according to the relationship of the required time.

  FIG. 6 is a flowchart showing the operation of the imaging system including the solid-state imaging device 100 according to the first embodiment. Examples of an imaging system on which the solid-state imaging device 100 is mounted include a digital still camera, a digital camcorder, a surveillance camera, an in-vehicle camera, and the like. Moreover, the imaging system in which the solid-state imaging device 100 is mounted may be included in a moving body such as a vehicle described in an embodiment described later. The operation illustrated in FIG. 6 is mainly performed by the solid-state imaging device 100 and a signal processing unit provided in the imaging system.

  In step S600, the solid-state imaging device 100 performs the operation described with reference to FIGS. 3 and 4 and acquires image data. In step S610, the solid-state imaging device 100 adds a first inspection signal including one or more memory inspection patterns to the image data, and outputs the first inspection signal to the signal processing unit of the imaging system. This operation is performed within the column memory inspection period.

  The image processing unit holds in advance a value of the first inspection signal expected when there is no abnormality in the column memory 106 (hereinafter, a value expected when there is no abnormality is referred to as an expected value). In step S620, the image processing unit collates the first inspection signal included in the image data output from the solid-state imaging device 100 with the expected value, and performs a match determination. If the first inspection signal in the image data matches the expected value (Yes in step S620), the imaging system determines that the column memory 106 is normal (step S630), and proceeds to step S600. Continue acquiring image data. If the first inspection signal in the image data does not match the expected value (No in step S620), the imaging system determines that the column memory 106 is abnormal and issues an alarm indicating the abnormality of the solid-state imaging device 100. An alarm is issued (step S640), and the process proceeds to step S650. This alarm notification may include, for example, causing the user to recognize the occurrence of an abnormality by a method such as displaying an abnormal state on a display device provided in the imaging system. Thereafter, in step S650, the imaging system stops the operation of the solid-state imaging device 100.

  As described above, according to this embodiment, a solid-state imaging device capable of outputting a more accurate abnormality detection signal is provided. By performing abnormality detection using this signal, it is possible to detect abnormality of the solid-state imaging device with higher accuracy.

[Second Embodiment]
FIG. 7 is a block diagram showing a schematic configuration of the solid-state imaging device 100 according to the second embodiment of the present invention. In addition to the configuration of the first embodiment, the solid-state imaging device 100 of the present embodiment is further provided with a first determination unit 701. The first determination unit 701 is a circuit having a function of performing a match determination corresponding to step S620 in the first embodiment and outputting a first determination result that is a match determination result. In order to perform the coincidence determination, the first determination signal output from the voltage supply unit 109 is input to the first determination unit 701. The first inspection signal is used as an expected value that is a comparison target in the coincidence determination. The first determination unit 701 also receives a first inspection signal stored in the column memory 106 and then output from the column memory 106. As a result, the first determination unit 701 can determine whether the first inspection signal output from the column memory 106 matches the expected value.

  FIG. 8A to FIG. 8E are schematic diagrams illustrating the configuration of one frame of image data output from the image output circuit 108 of the solid-state imaging device 100 according to the second embodiment. Regions 801-1 to 801-4 indicate data of the first determination result indicating the determination result of the first determination unit 701 for each memory inspection pattern. As shown in FIG. 8A, the data of the first determination result can be added to one frame of image data and output. In the example shown in FIG. 8A, the data of the first determination result is added below the image data, that is, output after the output of the image data. However, this order may be reversed, and the data of the first determination result may be added above the image data as shown in FIG. In other words, the data of the first determination result may be output before the output of the image data.

  Similarly to the case of the first embodiment, when the column memory inspection period is shorter than the required time, the first determination result for each memory inspection pattern is obtained as shown in FIGS. 8C and 8D. The column memory 106 can be inspected by dividing and adding to a plurality of image data. Note that the number of determination result data may be reduced by setting the first determination result as data indicating whether the determination results for each memory test pattern are all normal or at least one is abnormal. FIG. 8E shows an example in which the first determination result reduced to one in this way is shown as a region 802.

  FIG. 9 is a flowchart illustrating the operation of the imaging system including the solid-state imaging device 100 according to the second embodiment. Description of steps in which operations similar to those in FIG. 6 are performed may be omitted or simplified.

  In step S <b> 910, the voltage supply unit 109 outputs the first inspection signal to the column memory 106 and the first determination unit 701. The column memory 106 stores the first inspection signal, and then outputs the stored first inspection signal to the first determination unit 701. The first inspection signal directly output from the voltage supply unit 109 to the first determination unit 701 is used as an expected value that is a comparison target in the match determination.

  In step S920, the first determination unit 701 compares the first inspection signal output from the column memory 106 with the expected value and performs a match determination. If the first inspection signal output from the column memory 106 matches the expected value (Yes in step S920), the imaging system determines that the column memory 106 is normal (step S930). Thereafter, in step S940, the first determination unit 701 adds the first determination result data indicating that the column memory 106 is normal to the image data, and the image output circuit 108 adds the first determination result data. Output image data. Thereafter, the process proceeds to step S600 and the acquisition of the image data is continued.

  If the first inspection signal output from the column memory 106 does not match the expected value (No in step S920), the imaging system determines that the column memory 106 is abnormal (step S950). Thereafter, in step S960, the first determination unit 701 adds the first determination result data indicating that the column memory 106 is abnormal to the image data, and the image output circuit 108 adds the first determination result data. Output image data. Upon receiving this image data, the imaging system issues an alarm indicating an abnormality of the solid-state imaging device 100, and stops the operation of the solid-state imaging device 100 (step S970). Note that the image output circuit 108 may add the data of the first determination result to the image data.

  As described above, according to the present embodiment, it is possible to detect the abnormality of the solid-state imaging device with high accuracy by performing abnormality detection using a more accurate abnormality detection signal.

[Third Embodiment]
FIG. 10 is a block diagram showing a schematic configuration of a solid-state imaging apparatus 100 according to the third embodiment of the present invention. The solid-state imaging device 100 of this embodiment includes an input selection circuit 1001 that selects a signal to be read and a column amplification circuit that amplifies the input pixel signal for each column as an analog signal, in addition to the imaging device of the first embodiment. It further has 1002 (amplification part).

  FIG. 11 is a block diagram of an input selection circuit 1001 according to the third embodiment. In the clip circuit, the input selection circuit 1001 includes a voltage source 1101 and a selector 1102 provided corresponding to each column. The voltage source 1101 outputs a predetermined fixed voltage to each selector 1102 as a second inspection signal. That is, the voltage source 1101 functions as a second inspection signal output unit that supplies a second inspection signal that is an analog signal. A pixel signal is input to one input terminal of each selector 1102 via a vertical output line. A second inspection signal from the voltage source 1101 is input to the other input terminal of each selector 1102. Each selector 1102 selectively outputs the second inspection signal or the pixel signal to the column amplifier circuit 1002. The second test signal is a test pattern (column amplifier circuit test pattern) for testing the column amplifier circuit 1002. Each selector 1102 selects and outputs a second inspection signal at the timing of inspecting the column amplifier circuit 1002 and the like.

  The second inspection signal selected and output by the selector 1102 is input to the comparison circuit unit 104, and AD conversion is performed in the same procedure as the pixel signal. The second inspection signal converted into a digital signal by AD conversion is stored in the column memory 106, added to the image data, and output to the outside of the solid-state imaging device 100. In the present embodiment, the column memory 106 described in the first embodiment can also be inspected, but the description is omitted because it is the same as the first embodiment.

  FIG. 12A to FIG. 12E are schematic diagrams illustrating the configuration of one frame of image data output from the image output circuit 108 of the solid-state imaging device 100 according to the third embodiment. A region 1201 indicates data of the second inspection signal after AD conversion. That is, in this embodiment, in addition to the image data and the memory test pattern shown in FIGS. 5A to 5D, a column amplifier circuit test pattern is further added and output. As shown in FIG. 12A, the data of the column amplifier circuit test pattern is added to one frame of image data and output. In the example shown in FIG. 12A, the data of the column amplifier circuit test pattern is added below the image data, that is, output after the output of the image data. However, this order may be reversed, and the data of the column amplifier circuit test pattern may be added above the image data as shown in FIG. In other words, the data of the column amplifier circuit test pattern may be output before the output of the image data. Furthermore, as shown in FIG. 12C, the order of the memory test pattern and the column amplifier circuit test pattern may be opposite to that in FIG. 12A, and this order is not limited.

  When a plurality of memory test patterns are divided and added to a plurality of image data as in the first embodiment, one of the plurality of image data is added as shown in FIG. A column amplifier circuit test pattern may be added. Further, as shown in FIG. 12E, a column amplifier circuit test pattern may be added to image data to which no memory test pattern is added.

  FIG. 13 is a flowchart illustrating an operation of the imaging system including the solid-state imaging device 100 according to the third embodiment. Description of steps in which operations similar to those in FIG. 6 or FIG. 9 are performed may be omitted or simplified.

  In step S1310, the solid-state imaging device 100 adds the second inspection signal AD-converted by the reading unit to the image data. Thereafter, in step S610, as in the first embodiment, the solid-state imaging device 100 adds the first inspection signal to the image data and outputs the image data to the signal processing unit of the imaging system. Note that the order of step S1310 and step S610 may be reversed.

  The image processing unit holds in advance the expected value of the first inspection signal and the expected value of the second inspection signal. In step S1320, the image processing unit matches the first inspection signal included in the image data with the expected value of the first inspection signal, and further includes the second inspection signal and the second inspection signal included in the image data. A match determination is performed by comparing with the expected value.

  If both match (Yes in step S1320), the imaging system determines that the column memory 106 and the column amplifier circuit 1002 are normal (step S1330), and proceeds to step S600 to acquire image data. Continue.

  If at least one does not match in the match determination (No in step S1320), the imaging system determines that the column memory 106 or the column amplifier circuit 1002 is abnormal and issues an alarm indicating an abnormality of the solid-state imaging device 100. (Step S1340). Thereafter, the process proceeds to step S650. In step S650, the imaging system stops the operation of the solid-state imaging device 100.

  As described above, according to the present embodiment, in addition to the effects related to the inspection of the column memory 106 described in the first embodiment, the inspection of the column amplifier circuit 1002 can be performed. Thereby, it is possible to detect the abnormality of the solid-state imaging device with higher accuracy.

  Note that the second inspection signal is output via a reading unit including the comparison circuit unit 104 and the like, and thus may include noise caused by the reading unit. Therefore, in the coincidence determination using the second inspection signal, it is desirable to perform the determination in consideration of an error due to this noise. For example, a determination criterion may be used such that an abnormality is determined when there is a discrepancy with an expected value that exceeds an error due to an assumed noise.

  In addition, the inspection target by the second inspection signal is not limited to the column amplifier circuit 1002, and elements provided in a path through which the pixel signal is transmitted, for example, a vertical signal line, the input selection circuit 1001, and the like may be the inspection target. it can.

[Fourth Embodiment]
FIG. 14 is a block diagram showing a schematic configuration of a solid-state imaging apparatus 100 according to the fourth embodiment of the present invention. In addition to the configuration of the third embodiment, the solid-state imaging device 100 of this embodiment is further provided with a determination circuit 1402. The determination circuit 1402 includes a first determination unit 701 having the same function as the first determination unit 701 of the second embodiment, and a second determination unit 1401.

  The determination circuit 1402 is a circuit having a function of performing coincidence determination corresponding to step S1320 in the third embodiment and outputting the first determination result and the second determination result which are the coincidence determination results. In order to perform the coincidence determination, the first determination signal output from the voltage supply unit 109 is input to the first determination unit 701. In addition, the second determination signal 1401 output from the voltage source 1101 of the input selection circuit 1001 is input to the second determination unit 1401. The first inspection signal and the second inspection signal are used as expected values that are comparison targets in matching determination. The first check signal stored in the column memory 106 and then output from the column memory 106 is also input to the first determination unit 701. As a result, the first determination unit 701 can determine whether the first inspection signal output from the column memory 106 matches the expected value. A second test signal that is stored in the column memory 106 after AD conversion and then output from the column memory 106 is also input to the second determination unit 1401. As a result, the second determination unit 1401 can determine whether the second inspection signal output from the column memory 106 matches the expected value.

  FIGS. 15A to 15F are schematic diagrams illustrating a configuration of one frame of image data output from the image output circuit 108 of the solid-state imaging device 100 according to the fourth embodiment. An area 1501 indicates data of a second determination result indicating a result of determination by the second determination unit 1401. An area 1502 indicates data obtained by combining the first determination result and the second determination result into one determination result. In the present embodiment, in addition to the image data and the first determination result shown in FIGS. 8A to 8E, a second determination result is further added and output. As shown in FIG. 15A, the data of the second determination result is added to one frame of image data and output. In the example shown in FIG. 15A, the data of the second determination result is added below the image data, that is, output after the output of the memory test pattern data. However, this order may be reversed, and the data of the column amplifier circuit test pattern may be added above the image data as shown in FIG. In other words, the data of the column amplifier circuit test pattern may be output before the output of the image data. Furthermore, as shown in FIG. 15C, the order of the first determination result and the second determination result may be opposite to that in FIG. 15A, and this order is not limited.

  Further, when the first determination result is divided and added to a plurality of image data, the second determination result is added to one of the plurality of image data as shown in FIG. Also good. In addition, as shown in FIG. 15E, the second determination result may be added to image data to which the first determination result is not added. As yet another example, the first determination result and the second determination result may be combined and added to the image data as one determination result, as shown as an area 1502 in FIG.

  FIG. 16 is a flowchart illustrating the operation of the imaging system including the solid-state imaging device 100 according to the fourth embodiment. Description of steps in which operations similar to those in FIGS. 6, 9, or 13 are performed may be omitted or simplified.

  In step S1610, the voltage source 1101 of the input selection circuit 1001 outputs the second inspection signal to the column amplifier circuit 1002 and the second determination unit 1401. The column memory 106 stores the second inspection signal converted into a digital signal, and then outputs the stored second inspection signal to the second determination unit 1401. The second inspection signal directly output from the voltage source 1101 to the second determination unit 1401 is used as an expected value that is a comparison target in the match determination. Note that the second inspection signal used as the expected value may be, for example, a signal that has been converted into a digital signal so as to be suitable for matching determination processing in the second determination unit 1401.

  In step S <b> 1620, the first determination unit 701 compares the first inspection signal output from the column memory 106 with the expected value and performs a match determination. In addition, the second determination unit 1401 performs matching determination by comparing the second inspection signal output from the column memory 106 with the expected value.

  If both match (Yes in step S1620), the imaging system determines that the column memory 106 and the column amplifier circuit 1002 are normal (step S1630). Thereafter, in step S1640, the first determination unit 701 adds the data of the first determination result indicating that the column memory 106 is normal to the image data, and the second determination unit 1401 indicates that the column amplification circuit 1002 is normal. The data of the second determination result is added to the image data. Then, the image output circuit 108 outputs the image data to which the data of the first determination result and the second determination result are added. Thereafter, the process proceeds to step S600 and the acquisition of the image data is continued.

  If at least one does not match in the match determination (No in step S1620), the imaging system determines that the column memory 106 or the column amplifier circuit 1002 is abnormal (step S1650). Thereafter, in step S1660, the first determination unit 701 and the second determination unit 1401 add the data of the first determination result and the second determination result to the image data, respectively. The image output circuit 108 outputs image data to which data of the first determination result and the second determination result is added. Upon receiving this image data, the imaging system issues an alarm indicating an abnormality of the solid-state imaging device 100, and stops the operation of the solid-state imaging device 100 (step S970).

  As described above, according to the present embodiment, in addition to the effects related to the inspection of the column memory 106 described in the first embodiment, the inspection of the column amplifier circuit 1002 can be performed. Thereby, it is possible to detect the abnormality of the solid-state imaging device with higher accuracy.

[Fifth Embodiment]
A solid-state imaging device and a failure detection method for the solid-state imaging device according to the fifth embodiment of the present invention will be described with reference to FIGS.
In order to test all the column memories at the same time, an output circuit corresponding to the number of bits constituting the column memory is required. However, the circuit scale of the output circuit needs to be increased depending on the configuration of the column memory. In the present embodiment, a solid-state imaging device capable of realizing a fault inspection of a column memory and a reading unit in real time without increasing the circuit scale of an output circuit is shown.

  FIG. 17 is a block diagram illustrating a schematic configuration of the solid-state imaging apparatus according to the present embodiment. FIG. 18 is a circuit diagram illustrating a configuration example of a pixel in the solid-state imaging device according to the present embodiment. 19 to 21 are block diagrams illustrating configuration examples of the memory unit, the horizontal scanning circuit, and the horizontal transfer circuit in the solid-state imaging device according to the present embodiment. FIG. 22 is a schematic diagram for explaining the readout operation for one row in the solid-state imaging device according to the present embodiment. FIG. 23 is a schematic diagram illustrating a driving method of the solid-state imaging device according to the present embodiment. FIG. 24 is a schematic diagram illustrating a data configuration example in a signal processing device outside the solid-state imaging device. FIG. 25 is a flowchart illustrating a failure detection method for the solid-state imaging device according to the present embodiment.

  As shown in FIG. 17, the solid-state imaging device 100 according to the present embodiment includes a pixel array unit 10, a vertical scanning circuit 20, a comparison circuit unit 40, a memory unit 50, a counter 52, a voltage supply unit 54, a horizontal scanning circuit 60, a horizontal scanning circuit. A transfer circuit 70, an output circuit 80, and a timing generator 90 are included.

  The pixel array unit 10 is provided with a plurality of pixels 12 arranged to form a matrix including a plurality of rows and a plurality of columns. Each row of the pixel array section 10 is provided with a control line 14 extending in the first direction (lateral direction in FIG. 17). The control line 14 is connected to each of the pixels 12 arranged in the first direction, and forms a common signal line for these pixels 12. In the present specification, the first direction in which the control line 14 extends may be referred to as a row direction. Each column of the pixel array unit 10 is provided with an output line 16 extending in a second direction (vertical direction in FIG. 17) intersecting with the first direction. The output lines 16 are respectively connected to the pixels 12 arranged in the second direction, and form a signal line common to these pixels 12. In the present specification, the second direction in which the output line 16 extends may be referred to as a column direction.

  The control line 14 in each row is connected to the vertical scanning circuit 20. The output line 16 of each column is connected to the comparison circuit unit 40. The comparison circuit unit 40 is connected to the memory unit 50. A counter 52, a voltage supply unit 54, and a horizontal scanning circuit 60 are connected to the memory unit 50. The memory unit 50 is also connected to the output circuit 80 via the horizontal transfer circuit 70. A timing generator 90 is connected to the vertical scanning circuit 20, the counter 52, the voltage supply unit 54, and the horizontal scanning circuit 60.

  The vertical scanning circuit 20 is a circuit unit that supplies a control signal for driving a reading circuit in the pixel 12 to the pixel 12 via the control line 14 when reading a pixel signal from the pixel 12.

  The comparison circuit unit 40 includes a sample and hold circuit that samples and holds a pixel signal, a reference signal generation unit that generates a reference signal, and a comparator that compares the reference signal and the pixel signal. A sample hold circuit and a comparator are provided corresponding to each column of the pixel array unit 10. The comparison circuit unit 40 outputs to the memory unit 50 a latch signal corresponding to the result of comparison between the pixel signal and the reference signal by the comparator. The comparison circuit unit 40 constitutes an AD conversion circuit unit together with the counter 52.

  The counter 52 performs a count operation and outputs a count value to the memory unit 50. The memory unit 50 stores the count value at the timing when the latch signal is output from the comparator of each column of the comparison circuit unit 40 in a column memory provided corresponding to each column of the pixel array unit 10. The voltage supply unit 54 supplies a voltage for setting a digital value stored in the column memory to a desired value in a storage area corresponding to each bit of the column memory in each column of the memory unit 50.

  The horizontal scanning circuit 60 is a circuit unit that supplies the memory unit 50 with a control signal for outputting a pixel signal stored in the column memory of each column of the memory unit 50. The horizontal transfer circuit 70 is a circuit unit that transfers the digital value of the pixel signal output from the memory unit 50 to the output circuit 80 in accordance with a control signal from the horizontal scanning circuit 60. The output circuit 80 is a signal processing unit that performs processing such as correlated double sampling (CDS) on the digital value of the pixel signal received from the memory unit 50, or an external device such as LVDS (Low Voltage Differential Signaling). Includes an interface.

  The timing generator 90 supplies timing signals to the vertical scanning circuit 20, the counter 52, the voltage supply unit 54, the horizontal scanning circuit 60, and the like, and controls the operation timing of each unit. At least a part of the timing signal may be supplied from the outside of the solid-state imaging device 100.

  FIG. 18 is a circuit diagram illustrating a configuration example of the pixel 12. FIG. 18 shows two pixels 12 extracted from the output line 16 in the same column. Each pixel 12 includes a photoelectric conversion unit PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4.

  The photoelectric conversion unit PD is, for example, a photodiode, and has an anode connected to the ground voltage terminal and a cathode connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to the source of the reset transistor M2 and the gate of the amplification transistor M3. A connection node between the drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplifying transistor M3 is a so-called floating diffusion FD, and forms a charge-voltage conversion unit including a capacitance component included in the node. The drain of the reset transistor M2 and the drain of the amplification transistor M3 are connected to the power supply voltage terminal (VDD). The source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the output line 16. Note that the names of the source and the drain of the transistor may differ depending on the conductivity type of the transistor, the function of interest, and the like, and the above-described source and drain may be referred to as opposite names.

  In the case of the circuit configuration shown in FIG. 18, the control line 14 in each row includes a transfer gate signal line, a reset signal line, and a selection signal line (all not shown). The transfer gate signal line is connected to the gate of the transfer transistor M1 of the pixel 12 belonging to the corresponding row, and supplies the control signal PTX output from the vertical scanning circuit 20 to the gate of the transfer transistor M1. The reset signal line is connected to the gate of the reset transistor M2 of the pixel 12 belonging to the corresponding row, and supplies the control signal PRES output from the vertical scanning circuit 20 to the gate of the reset transistor M2. The selection signal line is connected to the gate of the selection transistor M4 of the pixel 12 belonging to the corresponding row, and supplies the control signal PSEL output from the vertical scanning circuit 20 to the gate of the selection transistor M4. When each transistor of the pixel 12 is an N-type transistor, when a high level control signal is supplied from the vertical scanning circuit 20, the corresponding transistor is turned on, and a low level control signal is supplied from the vertical scanning circuit 20. Then, the corresponding transistor is turned off.

  FIG. 19 shows a configuration example of the memory unit 50, the horizontal scanning circuit 60, the horizontal transfer circuit 70, and the output circuit 80. Here, it is assumed that the column memory of each column of the memory unit 50 is configured by 12 bits of the storage areas S1 to S12, and the image data output from the output circuit 80 is configured by 10 bits of DATA1 to DATA10. Yes.

  The pixel signal read from the pixel array unit 10 includes a noise component such as a dark current in the pixel array unit 10 as an offset in addition to the optical signal based on the charge generated by the photoelectric conversion unit PD. Therefore, the column memory of each column of the memory unit 50 is configured by a memory capable of storing a digital value having a digit number larger than the 10-bit image data output from the output circuit 80, for example, a 12-bit memory. With this configuration, it is possible to prevent the optical signal from being saturated with noise components, and to ensure a sufficient dynamic range.

  The digital values stored in the storage areas S1 to S12 of the column memory of each column of the memory unit 50 are transferred to the output circuit 80 via the horizontal transfer circuit 70 in accordance with a control signal from the horizontal scanning circuit 60. The output circuit 80 performs arithmetic processing such as noise removal on the transferred digital value, and outputs 10-bit image data of DATA1 to DATA10.

  FIG. 20 shows another configuration example of the memory unit 50, the horizontal scanning circuit 60, the horizontal transfer circuit 70, and the output circuit 80. The configuration example of FIG. 20 is basically the same as the configuration example of FIG. 19 except that the horizontal scanning circuit 60 is divided into a plurality of (N) blocks 60-1, 60-2,. It is. The horizontal scanning circuit 60 may be divided into a plurality of blocks 60-1, 60-2,..., 60-N as shown in FIG.

  FIG. 21 shows another configuration example of the memory unit 50, the horizontal scanning circuit 60, the horizontal transfer circuit 70, and the output circuit 80. In the configuration example shown in FIGS. 19 and 20, the number of channels of the horizontal transfer circuit 70 is one, but the number of channels of the horizontal transfer circuit 70 may be plural. FIG. 21 shows a configuration example of the memory unit 50, the horizontal scanning circuit 60, the horizontal transfer circuit 70, and the output circuit 80 when the number of channels of the horizontal transfer circuit 70 is two. Note that the number of channels of the horizontal transfer circuit 70 may be three or more.

  The horizontal transfer circuit 70 includes a horizontal transfer circuit 70A corresponding to the channel a and a horizontal transfer circuit 70B corresponding to the channel b. The channel a is connected to the column memory of the odd number column of the memory unit 50 and corresponds to the image data (DATA1a to DATA10a) output from the output circuit 80. The channel b is connected to the even-numbered column memory of the memory unit 50 and corresponds to the image data (DATA1b to DATA10b) output from the output circuit 80. The image data of channel a and the image data of channel b can be read out in parallel by using a common control signal supplied from the horizontal scanning circuit 60.

Next, the driving method of the solid-state imaging device according to the present embodiment will be described.
When the optical image of the subject enters the pixel array unit 10, the photoelectric conversion unit PD of each pixel 12 converts the incident light into an amount of charge corresponding to the amount of light (photoelectric conversion) and accumulates the generated charge. When the transfer transistor M1 is turned on, the charge of the photoelectric conversion unit PD is transferred to the floating diffusion FD. The floating diffusion FD becomes a voltage corresponding to the amount of charge transferred from the photoelectric conversion unit PD by charge-voltage conversion by the capacitance component. The amplification transistor M3 has a configuration in which a power supply voltage is supplied to the drain and a bias current is supplied to the source from a current source (not shown) via the selection transistor M4. ). As a result, the amplification transistor M3 outputs a signal based on the voltage of the floating diffusion FD to the output line 16 via the selection transistor M4. When the reset transistor M2 is turned on, the floating diffusion FD is reset to a voltage corresponding to the voltage VDD supplied from the power supply voltage terminal.

  The transfer transistor M1, the reset transistor M2, and the selection transistor M4 of the pixel 12 are controlled in units of rows by control signals PTX, PRES, and PSEL supplied from the vertical scanning circuit 20 under the control of the timing generator 90. The pixel signals of the pixels 12 belonging to the row selected by the control signal PSEL are simultaneously output to the corresponding output line 16 of each pixel 12.

  The pixel signal of each column output to the output line 16 is input to the comparison circuit unit 40 and held in the sample hold circuit of the corresponding column. The reference signal generation unit generates a reference signal whose voltage changes with time. For example, a ramp signal is used as the waveform of the reference signal. The comparator of each column compares the level of the pixel signal held in the sample and hold circuit with the level of the reference signal, and outputs a latch signal to the memory unit 50 when the magnitude relationship between these levels is inverted.

  The counter 52 counts the number of clock signals generated by the timing generator 90 and outputs the count value to the memory unit 50. The memory unit 50 stores the count value corresponding to the time from the start of the change of the reference signal to the output of the latch signal in the column memory (storage areas S1 to S12) as the digital value of the pixel signal. That is, the comparison circuit unit 40, the memory unit 50, and the counter 52 have functions as a reading unit and a storage unit that store pixel signals by analog-digital conversion (hereinafter referred to as AD conversion). In this specification, a pixel signal (digital pixel signal) converted into a digital signal is referred to as image data. One image is composed of a plurality of image data.

  The horizontal scanning circuit 60 sequentially outputs a control signal for each column to the column memory of each column of the memory unit 50 under the control of the timing generator 90. The memory unit 50 that has received the control signal from the horizontal scanning circuit 60 outputs the image data stored in the column memory of the corresponding column to the output circuit 80 via the horizontal transfer circuit 70.

  The output circuit 80 performs predetermined signal processing such as digital CDS on the image data received from the memory unit 50, and then outputs the pixel signal after the signal processing to the outside via the external interface in units of rows. Note that the pixel signal output from the output circuit 80 is, for example, a signal processing unit included in an imaging system including the solid-state imaging device 100. This signal processing unit performs predetermined signal processing on the signal output from the solid-state imaging device 100.

  The readout operation for one row of the pixel array unit 10 will be briefly described as shown in FIG. As shown in FIG. 22, the reading operation for one row includes a period T1 during which pixel signals are read, a period T2 during which AD conversion of pixel signals and writing to the column memory, and reading of image data from the column memory. A period T3 to be performed and a period T4 to initialize the column memory.

  First, in a period T1, pixel signals are read from the pixels 12 in the selected row. The pixel 12 in the row outputs a pixel signal to the output line 16. The pixel signal read from the pixel 12 is input to the comparison circuit unit 40 and held in the sample and hold circuit.

  Next, in the period T2, AD conversion is performed in the comparison circuit unit 40, the memory unit 50, and the counter 52 by the above-described procedure, and the image data of the digital signal obtained thereby is stored in the column memory of each column of the memory unit 50. Is done.

  Next, in a period T <b> 3, image data is read from the memory unit 50 to the output circuit 80 in accordance with the column scanning by the horizontal scanning circuit 60.

  Next, in a period T4, the column memory of each column of the memory unit 50 is initialized. That is, a voltage (for example, a fixed voltage such as 0V) that sets the value of each bit to “0” is supplied from the voltage supply unit 54 to the storage areas S1 to S12 of the column memory of each column of the memory unit 50. The unit 50 is initialized to prepare for reading out the pixel signal of the pixel 12 in the next row.

  The readout operation for one row is sequentially performed on the pixels 12 in each row constituting the pixel array unit 10 to acquire a plurality of image data constituting one image. This operation is vertical scanning.

  FIG. 23 is a schematic diagram for explaining an operation (vertical scanning) when acquiring a plurality of image data constituting one image. In FIG. 23, an outline of scanning for image acquisition at the time of moving image capturing is extracted for two frames. In FIG. 23, it is assumed that light is incident on the pixel 12 over the entire period, and light shielding by the mechanical shutter is not considered.

  In the upper part of FIG. 23, the horizontal axis represents time, and the vertical axis represents a row. Each of the frames subjected to the right-up hatching represents an electronic shutter operation performed on the plurality of pixels 12 belonging to one row. The electronic shutter operation is an operation for resetting the photoelectric conversion unit PD. More specifically, both the transfer transistors M1 and the reset transistors M2 of the pixels 12 in the corresponding row are turned on during the period indicated by the right-hatched frame. Thereby, the electric charge accumulated in the photoelectric conversion unit PD is discharged from the power supply voltage terminal (VDD), and the photoelectric conversion unit PD is reset. After this electronic shutter operation, the photoelectric conversion unit PD starts accumulating charges generated by photoelectrically converting incident light.

  The electronic shutter operation for a plurality of rows is sequentially performed for each row. In FIG. 23, in order to visually indicate that the electronic shutter operation of the pixels 12 in each row is executed in row sequence, the frames are arranged in an oblique direction. A series of operations in which electronic shutter operations of a plurality of rows are sequentially performed for each row is shutter scanning.

  In FIG. 23, each white frame represents a pixel signal readout operation from a plurality of pixels 12 belonging to one row. More specifically, the pixel signals of the pixels 12 belonging to the corresponding row are sequentially read out for each column during the period indicated by the white frame. This operation is horizontal scanning. A period during which reading from a plurality of pixels 12 belonging to one row is performed is one horizontal period (1H).

  The read operation of a plurality of rows is sequentially performed for each row. In FIG. 23, in order to visually indicate that the readout operation of the pixels 12 in each row is executed in row sequence, the frames are arranged in an oblique direction. A series of operations for sequentially performing a plurality of row reading operations for each row is reading scanning. In each row, a period from the end of the electronic shutter operation to the start of the reading operation is an accumulation period. The scanning timing is set so that the length of the accumulation period is the same in all rows.

  In the period from the end of the reading scan in a certain frame to the start of the reading scan in the next frame, image data is not written to the column memory of the memory unit 50. Therefore, in the driving method of the solid-state imaging device according to the present embodiment, real-time failure inspection is realized by using this period as a column memory inspection period for inspecting whether or not the memory unit 50 is operating normally. Yes.

  The failure inspection of the memory unit 50 does not always have to be performed, and may be performed as necessary. For example, a normal readout mode and a memory failure inspection mode are prepared as operation modes of the solid-state imaging device, and the failure inspection of the memory unit 50 is executed only when the memory failure inspection mode is selected. be able to. Even when the memory failure inspection mode is selected, it is not always necessary to execute the failure inspection every frame, and the failure inspection may be executed at predetermined frame intervals.

  In the column memory inspection period, as shown in the lower part of FIG. 23, writing of a memory inspection pattern for failure inspection into the column memory of each column of the memory unit 50 and the data from the column memory of each column of the memory unit 50 are performed. Read. The memory test pattern is written by supplying a voltage corresponding to information to be written from the voltage supply unit 54 to the storage areas S1 to S12 of the column memory of each column of the memory unit 50. Reading from the column memory of each column of the memory unit 50 is performed by horizontal scanning similar to the reading operation of each row in the reading scan. The period necessary for reading from the column memory of each column of the memory unit 50 is one horizontal period (1H) similar to the case of reading the pixel signal.

  When the memory unit 50 is initialized, the voltage supply unit 54 supplies a voltage that gives “0” to each of the storage areas S1 to S12. However, in the column memory inspection period, a voltage that gives “1” to at least some of the storage areas S1 to S12 (for example, the same voltage as the power supply voltage of the memory unit 50) can be input from the voltage supply unit 54. . That is, the voltage supply unit 54 can store a bit arrangement of a predetermined memory test pattern in the memory unit 50. In this sense, the voltage supply unit 54 is also an inspection information supply unit to the memory unit 50.

  The memory test pattern written to the column memory of each column of the memory unit 50 is not particularly limited. For example, an example in which “0” is written in each of the storage areas S1 to S12 of the column memories of all the columns of the memory unit 50 is given. Alternatively, an example in which “1” is written in each of the storage areas S1 to S12 of the column memory of all the columns of the memory unit 50 is given. Alternatively, an example in which “0101...” Is written in order from the most significant bit of the column memory. Alternatively, an example is given in which “1010...” Is input sequentially from the most significant bit of the column memory.

  The memory test pattern can be arbitrarily determined for each column. For example, the memory test pattern may be the same for a plurality of columns or may be different for each column. Further, the memory test patterns of the same column in different column memory test periods may be different. The voltage supply unit 54 can supply a voltage corresponding to an arbitrary memory test pattern to the column memory of each column of the memory unit 50.

  As described above, the voltage supply unit 54 of the solid-state imaging device according to the present embodiment can write a predetermined memory test pattern in the column memory of each column of the memory unit 50. Since the signal to be written in the memory unit 50 is supplied as a digital signal without going through the reading unit, any number of bits is stored in the memory unit 50 without being affected by external noise. Therefore, it is possible to write a more accurate inspection signal in the memory unit 50. Thereby, the abnormality detection by collating the memory test pattern written in the memory unit 50 with the memory test pattern read from the memory unit 50 can be performed with higher accuracy.

  By the way, in the configuration example shown in FIGS. 19 to 21, the bit number of the signal output from one pixel 12 is 10 bits, whereas the bit number of the column memory in each column of the memory unit 50 is 12 bits. It is. Therefore, in the inspection of the memory unit 50, in order to output all the 12-bit information stored in the column memory of each column of the memory unit 50, the output circuit 80 can execute a mode for outputting 12-bit information. It is necessary to configure as follows. However, in order to output image data as 10-bit information and further output column memory inspection data as 12-bit information, it is necessary to provide an extra output system for at least 2 bits. This leads to an increase in configuration.

  From this point of view, in the solid-state imaging device according to the present embodiment, the column memory inspection data is divided into two or more data so that it can be output with the number of bits less than the number of output bits of the image data (10 bits or less). It is configured to output. That is, the information stored in each column memory is divided and output in units of bits so that the number of bits of information output at a time by the output circuit 80 is equal to or less than the number of bits of the signal output from one pixel 12. To do.

  For example, as shown in FIG. 23, after a predetermined memory test pattern is written in the column memory of each column of the memory unit 50, transfer of 12-bit column memory test data from the memory unit 50 to the output circuit 80 is performed twice. The horizontal scanning is performed. In the first horizontal scan, 10-bit information is output from the output circuit 80 from the most significant bit of the column memory of each column of the memory unit 50. In the subsequent second horizontal scan, information of the lower 2 bits of the column memory of each column of the memory unit 50 is output from the output circuit 80. That is, the column memory inspection data is read during a period corresponding to the reading period for two rows. The period of the first horizontal scanning is a period (first period) corresponding to the output period for one row of inspection information held in a part of the column memory of each column. Similarly, the second horizontal scanning period is a period (second period) corresponding to an output period of one row of inspection information held in another part of the column memory of each column. The first period and the second period are periods between the output operation of the pixel information of one row by the output circuit 80 and the output operation of the pixel information of another row by the output circuit 80, respectively.

  In this way, all the information read from the storage areas S1 to S12 of the column memory of each column of the memory unit 50 is used for solid-state imaging using the output circuit 80 in which the number of bits of a signal that can be output is 10 bits. It can be output outside the device.

  In the driving example shown in FIG. 23, after the output of the image data of a certain frame is completed and before the output of the image data of the next frame is started, writing of the memory test pattern and reading of all the column memory test data are performed. Is an example of This driving example can be applied when the column memory inspection period is longer than the time required for writing the column memory inspection pattern and reading from the column memory by two horizontal scans.

  If the column memory test period is shorter than the time required for writing the column memory test pattern and reading from the column memory by two horizontal scans, the two divided column memory test data are transferred to another column memory. You may make it read in an inspection period. For example, after the output of the image data of a certain frame is completed, before the output of the image data of the next frame is started, writing of the column memory test pattern and reading of one of the divided column memory test data are performed. Do. Next, after the output of the image data of the next frame is completed, writing of the column memory test pattern and reading of the other of the divided column memory test data are performed. In this way, all the column memory test data can be output without reducing the frame rate.

  The column memory inspection data output from the solid-state imaging device is compared with an expected value that is data corresponding to the column memory inspection pattern to be written in the memory unit 50 in an external signal processing device. Various failures in the solid-state imaging device can be estimated by the memory test pattern written in the memory unit 50.

  For example, when “0” or “1” is written in the storage areas S1 to S12 of the column memory of all columns of the memory unit 50 as column memory inspection data, a value different from the written value is read. If there is a stored storage area, it can be estimated that there is a failure in the storage area.

  In the configuration example shown in FIGS. 19 and 20, the column memory of the memory unit 50 is sequentially selected for each column by the horizontal scanning circuit 60, and the information stored in the column memory of the selected column is transferred horizontally. The data is sequentially transferred to the output circuit 80 via the circuit 70. In such a case, the expected values written in the column memories of the columns selected by the horizontal scanning circuit 60 at different times are set to different values, so that the selection by the horizontal scanning circuit 60 is performed in the correct order, that is, The horizontal scanning circuit 60 can be inspected. At this time, the expected values to be written to the column memories of the columns selected by the horizontal scanning circuit 60 at different times do not have to be set to different values from each other, and the expected values are set to different values for some columns. By doing so, the horizontal scanning circuit 60 can be simply inspected. As an example of some columns set to different values, an adjacent column or a block unit of the horizontal scanning circuit 60 in the configuration example of FIG. 20 can be considered.

  In the channel a of the configuration example shown in FIG. 21, column memories selected by the horizontal scanning circuit 60 at different times are column memories of columns 1, 3, 5,. The horizontal scanning circuit can be inspected by setting different expected values to be written in the column memories of these columns. Similarly, in the channel b, column memories selected by the horizontal scanning circuit 60 at different times are column memories of columns 2, 4, 6,. The horizontal scanning circuit can be inspected by setting different expected values to be written in the column memories of these columns.

  The column memory inspection data output from the solid-state imaging device can be added to image data of one frame, for example, as shown in FIG. FIG. 24A shows an example in which column memory test data 220A and 220B divided into two are added after the image data 210 of one frame. For example, the present invention can be applied as a data configuration in which all column memory inspection data is output after outputting image data of a certain frame and before outputting image data of the next frame. FIG. 24B is an example in which the column memory inspection data 220A and 220B divided into two are added after the image data 210 and 212 of the image of another frame, respectively. For example, after outputting the image data of a certain frame, one of the column memory inspection data divided before the output of the image data of the next frame is output, and the column memory inspection data divided after the output of the image data of the next frame is output. It can be applied as a data configuration example when outputting the other. The column memory inspection data may be added before the image data.

  FIG. 25 is a flowchart illustrating a failure detection method of the solid-state imaging device in the imaging system equipped with the solid-state imaging device according to the present embodiment. Examples of the imaging system on which the solid-state imaging device is mounted include a digital still camera, a digital camcorder, a surveillance camera, an in-vehicle camera, and the like. In addition, the imaging system on which the solid-state imaging device is mounted may be included in a moving body such as a vehicle described in an embodiment described later. The operation illustrated in FIG. 25 is mainly performed by the solid-state imaging device and the signal processing unit provided in the imaging system.

  Failure detection of the solid-state imaging device in the imaging system is performed, for example, according to the flowchart shown in FIG.

  First, the signal processing unit of the imaging system acquires column memory inspection data output from the solid-state imaging device (step S101). The acquisition of the column memory inspection data is performed according to the procedure described with reference to FIGS.

  Next, the signal processing unit collates the acquired column memory test data with the expected value, and determines whether or not the column memory test data matches the expected value (step S102). The expected value of the column memory test data is the value of the column memory test data expected when there is no abnormality in the solid-state imaging device, and the memory test pattern written in the column memory of each column of the memory unit 50 by the voltage supply unit 54 Corresponds to the information. Note that the expected value of the column memory inspection data is held in advance in the signal processing unit.

  If the column memory inspection data acquired from the solid-state imaging device matches the expected value (Yes), it is determined that the solid-state imaging device is normal (step S103), and imaging is continued.

  If the column memory inspection data acquired from the solid-state imaging device does not match the expected value (No), it is determined that there is an abnormality in the solid-state imaging device, and an alarm notifying the abnormality of the solid-state imaging device is issued ( Step S104). This alerting may include causing the user to recognize the occurrence of an abnormality by another method such as displaying that the display device is in an abnormal state. Thereafter, the imaging system stops the operation of the solid-state imaging device (step S105).

  Since the column memory inspection data can be acquired in a period between frames, a failure of the column memory can be detected in real time during moving image shooting.

  As described above, according to the present embodiment, it is possible to execute a failure inspection of the reading unit such as the memory unit 50 and the horizontal scanning circuit 60 in real time without increasing the circuit scale of the output circuit 80.

[Sixth Embodiment]
A solid-state imaging device and a failure detection method for the solid-state imaging device according to the sixth embodiment of the present invention will be described with reference to FIGS. The same components as those of the solid-state imaging device according to the fifth embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified.

  26 and 27 are block diagrams illustrating configuration examples of the memory unit, the horizontal scanning circuit, and the horizontal transfer circuit in the solid-state imaging device according to the present embodiment. FIG. 28 is a timing chart showing a driving method of the solid-state imaging device according to the present embodiment. FIG. 29 is a schematic diagram illustrating a data configuration example in the signal processing device outside the solid-state imaging device.

  The solid-state imaging device according to the present embodiment is the same as the solid-state imaging device according to the first embodiment except that the configurations of the memory unit 50 and the horizontal transfer circuit 70 are different. That is, in the solid-state imaging device according to the present embodiment, as shown in FIG. 26, the memory unit 50 includes storage areas N1 to N10 in addition to the storage areas S1 to S12 as a column memory of each column. The storage areas S1 to S12 are memories (S memories) that store 12-bit optical signals (S signals). The storage areas N1 to N10 are memories (N memories) that store 10-bit noise signals (N signals). Further, the horizontal transfer circuit 70 transfers the information stored in the storage areas S1 to S12 and the information stored in the storage areas N1 to N10 to the output circuit 80 in accordance with a control signal from the horizontal scanning circuit 60. It is configured. FIG. 27 shows a configuration example in which the horizontal scanning circuit 60 is divided into a plurality (N) of blocks 60-1, 60-2,..., 60-N, as in the case of FIG. .

  FIG. 28 is a timing chart showing a driving method of the solid-state imaging device according to the present embodiment. In FIG. 28, control signals PSEL, PRES, and PTX supplied to the control line 14 of the row to be read from the vertical scanning circuit 20, the pixel signal input to the comparison circuit unit 40, and the reference signal generation unit of the comparison circuit unit 40 The reference signal supplied from FIG.

  At time t1, the vertical scanning circuit 20 controls the control signal PSEL of the row from which the pixel signal is read out from the low level to the high level, and turns on the selection transistor M4 of the pixel 12 belonging to the corresponding row. Thereby, the pixels 12 belonging to the row are selected. At time t1, the control signal PRES is at a high level, and the floating diffusion FD of the pixels 12 belonging to the row is reset to a voltage corresponding to the voltage VDD. The control signal PTX is at a low level.

  Next, at time t2, the vertical scanning circuit 20 controls the control signal PRES of the row from which the pixel signal is read out from the high level to the low level, and cancels the reset of the floating diffusion FD. A noise signal (N signal) corresponding to the reset voltage of the floating diffusion FD is output via the selection transistor M4 and the output line 16, and is held in the sample hold circuit of the comparison circuit unit 40.

  Next, at time t3 after the voltage of the output line 16 has settled, the reference signal generation unit of the comparison circuit unit 40 starts ramping up the reference signal. The counter 52 starts counting the number of clocks of the clock signal generated by the timing generator 90 in response to the start of ramping up of the reference signal, and outputs the count value to the memory unit 50. The comparator of the comparison circuit unit 40 starts a comparison operation between the level of the N signal held in the sample hold circuit and the level of the reference signal.

  When the magnitude relationship between the level of the N signal and the level of the reference signal changes at time t4, the output of the comparator is inverted. The memory unit 50 stores the count value corresponding to the time from the start of the ramp-up of the reference signal until the output of the comparator is inverted in the storage areas N1 to N10 of the corresponding column of the memory unit 50 as the digital value of the N signal. Remember.

  Next, at time t5, the reference signal output by the reference signal generation unit is reset, and AD conversion of the N signal ends.

  Next, during the period from time t6 to time t7, the vertical scanning circuit 20 controls the control signal PTX to high level, and transfers the charge generated and accumulated in the photoelectric conversion unit PD to the floating diffusion FD. As a result, the floating diffusion FD becomes a voltage corresponding to the amount of transferred charge by charge-voltage conversion by the capacitance component. An optical signal (S signal) corresponding to the amount of charge transferred to the floating diffusion FD is output through the selection transistor M4 and the output line 16, and is held in the sample hold circuit of the comparison circuit unit 40.

  Next, at time t8 after the voltage of the output line 16 has settled, the reference signal generation unit of the comparison circuit unit 40 starts ramping up the reference signal. The counter 52 starts counting the number of clocks of the clock signal generated by the timing generator 90 in response to the start of ramping up of the reference signal, and outputs the count value to the memory unit 50. The comparator of the comparison circuit unit 40 starts a comparison operation between the level of the S signal held in the sample hold circuit and the level of the reference signal.

  When the magnitude relationship between the level of the S signal and the level of the reference signal changes at time t9, the output of the comparator is inverted. The memory unit 50 stores the count value corresponding to the time from the start of the ramp-up of the reference signal until the output of the comparator is inverted in the storage areas S1 to S12 of the corresponding column of the memory unit 50 as the digital value of the S signal. Remember.

  Next, at time t10, the reference signal output by the reference signal generation unit is reset, and AD conversion of the S signal ends.

  Next, at time t11, the vertical scanning circuit 20 controls the control signal PSEL from the high level to the low level to cancel the selection of the row, and ends the reading of the pixel signal from the pixels 12 belonging to the row.

  The digital N signal and digital S signal held in the storage areas N1 to N10 and S1 to S12 of each column of the memory unit 50 are in the order of the digital N signal and the digital S signal for each column via the horizontal transfer circuit 70. It is transferred to the output circuit 80. The output circuit 80 performs a process of subtracting the digital value of the N signal from the digital value of the S signal, so-called digital CDS process, calculates 10-bit image data from which noise has been removed, and outputs it to an external device.

  On the other hand, in the column memory inspection, as the column memory inspection data, information of 12 bits corresponding to the storage areas S1 to S12 and information of 10 bits corresponding to the storage areas N1 to N10 is 22 bits in total. is necessary. Therefore, in this embodiment, the column memory test data is divided into three pieces of data having a number of bits less than or equal to the number of output bits of the output circuit 80 (10 bits or less) and output. That is, reading of the column memory inspection data is performed during a period corresponding to a reading period of two or more rows (here, three rows).

  For example, after a predetermined memory test pattern is written in the column memory of each column of the memory unit 50, horizontal scanning for transferring 12-bit column memory test data for S memory test is performed twice, and 10 for N memory test is performed. A horizontal scan for transferring the bit column memory test data is performed once. In the first horizontal scan, 10-bit information is output from the output circuit 80 from the most significant bit of the S memory in each column of the memory unit 50. In the subsequent second horizontal scan, information of the lower 2 bits of the S memory in each column of the memory unit 50 is output from the output circuit 80. In the subsequent third horizontal scan, 10-bit information of the N memories in each column of the memory unit 50 is output from the output circuit 80. The order in which the divided column memory test data is output is not particularly limited.

  In this way, all information read from the storage areas S1 to S12 and N1 to N10 of the column memory of each column of the memory unit 50 is output from the output circuit 80 in which the number of bits of a signal that can be output is 10 bits. And output to the outside of the solid-state imaging device.

  The column memory inspection data output from the solid-state imaging device can be added to image data of one frame as shown in FIG. 29, for example. As described in the fifth embodiment, the mode of adding the column memory inspection data can be changed according to the length of the column memory inspection period. FIG. 29A is an example in which column memory test data 220A, 220B, and 220C divided into three are added after the image data 210 of one frame. FIG. 29B shows an example in which the column memory test data 220A, 220B, and 220C divided into three are added after the image data 210, 212, and 214 of another frame, respectively. FIG. 29C shows an example in which the column memory test data 220A and 220B are added after the frame image data 210 and the column memory test data 220C are added after the frame image data 212, respectively. The column memory inspection data may be added before the image data.

  As described above, according to the present embodiment, it is possible to execute a failure inspection of the reading unit such as the memory unit 50 and the horizontal scanning circuit 60 in real time without increasing the circuit scale of the output circuit 80.

[Seventh Embodiment]
A solid-state imaging device and a failure detection method for the solid-state imaging device according to the seventh embodiment of the present invention will be described with reference to FIGS. 30 to 33. The same components as those of the solid-state imaging device according to the fifth and sixth embodiments are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 30 is a block diagram illustrating a schematic configuration of the solid-state imaging device according to the present embodiment. 31 and 32 are block diagrams illustrating configuration examples of the memory unit, the horizontal scanning circuit, and the horizontal transfer circuit in the solid-state imaging device according to the present embodiment. FIG. 33 is a timing chart illustrating a method for driving the solid-state imaging device according to the present embodiment.

  The solid-state imaging device 100 according to the present embodiment has fifth and sixth embodiments in that it further includes an amplifier circuit unit 30 provided between the pixel array unit 10 and the comparison circuit unit 40, as shown in FIG. This is different from the solid-state image pickup device. The output lines 16 in each column arranged in the pixel array unit 10 are connected to the amplifier circuit unit 30. The amplifier circuit unit 30 includes a plurality of column amplifier circuits (not shown) provided corresponding to the columns of the pixel array unit 10. The column amplification circuit of each column amplifies the analog pixel signal output from the output line 16 of the pixel array unit 10 with a predetermined amplification factor and outputs the amplified signal to the comparison circuit unit 40. The column amplifier circuit has a variable amplification factor and a function of changing the amplification factor according to the output level of the pixel signal. The pixel signal amplified by the column amplifier circuit is input to the comparator of the corresponding column of the comparison circuit unit 40.

  In the solid-state imaging device according to the present embodiment, as shown in FIG. 31, the memory unit 50 has storage areas S1 to S12 for storing optical signals and storage areas N1 to N1 for storing noise signals as column memories for each column. In addition to N10, it further has a storage area J for storing determination signals. The storage area J stores information on whether or not the amplification factor of the column amplification circuit of the corresponding column has been changed when the pixel signal is processed by the amplification circuit unit 30. For example, “0” is stored when the amplification factor is not changed, and “1” is stored when the amplification factor is changed. In addition, the horizontal transfer circuit 70 responds to a control signal from the horizontal scanning circuit 60, information stored in the storage areas S1 to S12, information stored in the storage areas N1 to N10, and information stored in the storage area J. Is transferred to the output circuit 80. 32 is a configuration example in which the horizontal scanning circuit 60 is divided into a plurality of (N) blocks 60-1, 60-2,..., 60-N, as in the case of FIG. 20 described in the fifth embodiment. .

  FIG. 33 is a timing chart showing the operation of the solid-state imaging device according to the present embodiment. In FIG. 33, the control signals PSEL, PRES, and PTX supplied to the control line 14 of the row to be read from the vertical scanning circuit 20, the pixel signal amplified by the amplifier circuit unit 30 and input to the comparison circuit unit 40, and the comparison circuit The reference signal supplied from the reference signal generation part of the part 40 is shown.

  The operation from time t1 to time t7 is the same as that of the solid-state imaging device according to the sixth embodiment described with reference to FIG. By the operation up to time t7, the charge generated by the photoelectric conversion unit PD is transferred to the floating diffusion FD. The comparison circuit unit 40 receives a pixel signal obtained by amplifying a signal corresponding to the amount of charge transferred to the floating diffusion FD with a predetermined amplification factor in the column amplifier circuit.

  Next, in the period from time t8 to time t9, a reference signal for determining the output level of the pixel signal is supplied to the comparator of the comparison circuit unit 40 and compared with the pixel signal. The determination of the output level of the pixel signal is performed to determine whether it is necessary to shorten the AD conversion period of the S signal.

  In the period up to time t9 when the reference signal is reset, for example, when the level of the reference signal reaches the level of the pixel signal as shown by a solid line in FIG. 33, it is not necessary to shorten the AD conversion period of the S signal. Judge that it is. Then, the amplification factor of the amplifier circuit unit 30 does not change, and the AD conversion processing of the optical signal is started from time t10. When the magnitude relationship between the level of the S signal and the level of the reference signal changes at time t11, the memory unit 50 uses the count value corresponding to the time from time t10 to time t11 as the digital value of the S signal. Are stored in the storage areas S1 to S12. Further, since the amplification factor of the amplifier circuit unit 30 has not changed, the storage area J of the memory unit 50 stores information indicating that, for example, “0”.

  On the other hand, if the level of the reference signal does not reach the level of the pixel signal as indicated by a dotted line in FIG. 33, for example, until the time t9 when the reference signal is reset, it is estimated that AD conversion takes a long time. Therefore, it is determined that the AD conversion period of the S signal needs to be shortened. Then, the amplification factor of the amplifier circuit unit 30 is lowered, and the level of the pixel signal input to the comparator is lowered. Here, it is assumed that the amplification factor of the amplifier circuit unit 30 is reduced to ¼. Then, AD conversion processing of the optical signal is started from time t10 for the pixel signal whose signal level is lowered. When the magnitude relationship between the level of the S signal and the level of the reference signal changes at time t11 ′, the memory unit 50 stores the count value corresponding to the time from time t10 to time t11 ′ as a digital value of the S signal. The data is stored in the storage areas S1 to S12 of the unit 50. In addition, since the amplification factor of the amplifier circuit unit 30 is changed, information indicating that, for example, “1” is stored in the storage area J of the memory unit 50.

  The digital N signal and digital S signal held in the storage areas N1 to N10 and S1 to S12 of each column of the memory unit 50 are in the order of the digital N signal and the digital S signal for each column via the horizontal transfer circuit 70. It is transferred to the output circuit 80. The determination signal can be transferred to the output circuit 80 together with the digital N signal.

  The output circuit 80 performs a process of subtracting the digital value of the N signal from the digital value of the S signal, so-called digital CDS process. At this time, the information of the determination signal is confirmed, and when the amplification factor of the amplification circuit unit 30 with respect to the S signal is changed, the change factor of the amplification factor is considered. For example, when the amplification factor of the amplifier circuit 30 for the S signal is changed to ¼, the digital value of the N signal is subtracted from the value obtained by multiplying the digital value of the S signal by four. The presence or absence of a change in the amplification factor of the amplifier circuit unit 30 with respect to the S signal can be determined based on the determination information transferred to the output circuit 80 together with the digital N signal.

  In the solid-state imaging device according to the present embodiment, as column memory inspection data, 12-bit information corresponding to the storage areas S1 to S12, 10-bit information corresponding to the storage areas N1 to N10, and 1 corresponding to the storage area J A total of 23 bits of bit information are required. In order to output the column memory test data with the number of bits less than or equal to the number of output bits of the output circuit 80 (10 bits or less), the column memory test data is divided into three or more data as in the sixth embodiment. What is necessary is just to comprise so that it may output.

  The mode of dividing the column memory inspection data and the order of outputting the divided data from the solid-state imaging device are not particularly limited. For example, the column memory inspection data is output as inspection information for three rows of information on the upper 10 bits of the S memory, information on the lower 2 bits of the S memory and 1 bit of the determination signal, and information on the 10 bits of the N memory. be able to.

  As described above, according to the present embodiment, it is possible to execute a failure inspection of the reading unit such as the memory unit 50 and the horizontal scanning circuit 60 in real time without increasing the circuit scale of the output circuit 80.

[Eighth Embodiment]
A driving method of the solid-state imaging device according to the eighth embodiment of the present invention will be described with reference to FIG. The same components as those of the solid-state imaging device according to the fifth to seventh embodiments are denoted by the same reference numerals, and description thereof is omitted or simplified.

  In the present embodiment, another driving method of the solid-state imaging device according to the seventh embodiment will be described. The overall configuration of the solid-state imaging device according to the present embodiment is the same as that of the solid-state imaging device according to the seventh embodiment. In the present embodiment, the AD conversion period of the S signal is optimized by changing the AD conversion gain in the comparison circuit unit 40 instead of changing the amplification factor of the amplifier circuit unit 30. The AD conversion gain is variable depending on the slope of the reference signal supplied to the comparator.

  FIG. 34 is a timing chart showing a driving method of the solid-state imaging device according to the present embodiment. In FIG. 34, control signals PSEL, PRES, and PTX supplied from the vertical scanning circuit 20 to the control line 14 of the row to be read out, the pixel signal amplified by the amplifier circuit unit 30 and input to the comparison circuit unit 40, and the comparison circuit The reference signal supplied from the reference signal generation part of the part 40 is shown.

  The operation from time t1 to time t7 is the same as that of the solid-state imaging device according to the sixth embodiment described with reference to FIG. By the operation up to time t7, the charge generated by the photoelectric conversion unit PD is transferred to the floating diffusion FD. The comparison circuit unit 40 receives a pixel signal obtained by amplifying a signal corresponding to the amount of charge transferred to the floating diffusion FD with a predetermined amplification factor in the column amplifier circuit.

  Next, in the period from time t8 to time t9, a reference signal for determining the output level of the pixel signal is supplied to the comparator of the comparison circuit unit 40 and compared with the pixel signal. The determination of the output level of the pixel signal is performed to determine whether it is necessary to shorten the AD conversion period of the S signal.

  In the period up to time t9 when the reference signal is reset, for example, when the level of the reference signal reaches the level of the pixel signal as shown by a solid line in FIG. 34, it is not necessary to shorten the AD conversion period of the S signal. Judge that it is. Then, the slope of the reference signal used for AD conversion does not change, and the AD conversion processing of the optical signal is started from time t10. When the magnitude relationship between the level of the S signal and the level of the reference signal changes at time t11, the memory unit 50 uses the count value corresponding to the time from time t10 to time t11 as the digital value of the S signal. Are stored in the storage areas S1 to S12. Further, since the slope of the reference signal used for AD conversion has not changed, information indicating that, for example, “0” is stored in the storage area J of the memory unit 50.

  On the other hand, if the level of the reference signal does not reach the level of the pixel signal as indicated by a dotted line in FIG. 34, for example, until the time t9 when the reference signal is reset, it is estimated that AD conversion takes a long time. Therefore, the AD conversion gain is lowered by increasing the slope of the reference signal. Here, it is assumed that the slope of the reference signal is quadrupled to reduce the AD conversion gain to ¼. Then, AD conversion processing of the optical signal is started from time t10 using the reference signal having an increased inclination. When the magnitude relationship between the level of the S signal and the level of the reference signal changes at time t11 ′, the memory unit 50 stores the count value corresponding to the time from time t10 to time t11 ′ as a digital value of the S signal. The data is stored in the storage areas S1 to S12 of the unit 50. Further, since the AD conversion gain of the comparison circuit unit 40 is changed, information indicating that fact, for example, “1” is stored in the storage area J of the memory unit 50.

  The output circuit 80 performs a process of subtracting the digital value of the N signal from the digital value of the S signal, so-called digital CDS process. At this time, the information of the determination signal is confirmed, and when the AD conversion gain with respect to the S signal is changed, the change magnification of the AD conversion gain is taken into consideration. For example, when the AD conversion gain for the S signal is changed to ¼, the digital value of the N signal is subtracted from the value obtained by multiplying the digital value of the S signal by four. Whether the AD conversion gain has changed with respect to the S signal can be determined based on the determination information transferred to the output circuit 80 together with the digital N signal.

  The method for outputting the column memory inspection data from the solid-state imaging device to the external device is the same as in the case of the seventh embodiment.

  As described above, according to the present embodiment, it is possible to execute a failure inspection of the reading unit such as the memory unit 50 and the horizontal scanning circuit 60 in real time without increasing the circuit scale of the output circuit 80.

[Ninth Embodiment]
A moving body according to a ninth embodiment of the present invention will be described with reference to FIGS. The same components as those in the solid-state imaging device according to the first to eighth embodiments are denoted by the same reference numerals, and description thereof is omitted or simplified. FIG. 35 is a schematic diagram illustrating a configuration of a moving object according to the present embodiment. FIG. 36 is a block diagram of a moving body according to the present embodiment.

  FIG. 35A to FIG. 35C are schematic views showing the configuration of the moving body according to the present embodiment. FIG. 35A to FIG. 35C show a configuration of a vehicle 300 (automobile) as an example of a moving body in which the solid-state imaging device according to the first to eighth embodiments is incorporated. FIG. 35A is a schematic front view of the vehicle 300, FIG. 35B is a schematic plan view of the vehicle 300, and FIG. 35C is a schematic rear view of the vehicle 300. The vehicle 300 includes a pair of imaging devices 302 on the front. Here, the imaging device 302 is the solid-state imaging device 100 according to any one of the first to eighth embodiments. The vehicle 300 includes an integrated circuit 303, an alarm device 312 and a main control unit 313. The integrated circuit 303 is, for example, an application specific integrated circuit (ASIC).

  The alarm device 312 displays an alarm information on a display unit such as a car navigation system or a meter panel that sounds an alarm such as sound or vibration when a signal indicating abnormality is received from the imaging device 302, vehicle sensor, control unit, or the like. The user is warned by a method such as The main control unit 313 comprehensively controls the operations of the imaging device 302, the vehicle sensor, the control unit, and the like. The vehicle 300 may not include the main control unit 313. In this case, the imaging device 302, the vehicle sensor, and the control unit transmit and receive control signals via the communication network. For example, the CAN standard can be applied to the transmission / reception of the control signal.

  FIG. 36 is a block diagram showing a system configuration of vehicle 300. The imaging system 301 includes first and second imaging devices 302, an image preprocessing unit 315, an integrated circuit 303, and an optical system 314. A stereo camera is configured by providing a pair of the first imaging device 302 and the second imaging device 302. The optical system 314 forms an optical image of the subject on the imaging device 302. The imaging device 302 converts the optical image of the subject imaged by the optical system 314 into an electrical signal. The image preprocessing unit 315 performs predetermined signal processing on the signal output from the imaging device 302. The function of the image preprocessing unit 315 may be incorporated in the imaging device 302. The imaging system 301 includes at least two sets of the optical system 314, the imaging device 302, and the image preprocessing unit 315, and outputs from each set of the image preprocessing unit 315 are input to the integrated circuit 303. It is like that.

  The image preprocessing unit 315 performs processing such as calculating a difference between the optical signal VS and the noise signal VN, and adding a synchronization signal. When the vehicle 300 includes the imaging device 302 shown as the first embodiment or the third embodiment, the image preprocessing unit 315 has a function of performing processing such as matching determination shown in FIGS. 6 and 13. You may do it. Alternatively, when the vehicle 300 includes the imaging device 302 shown as the fifth to eighth embodiments, the image preprocessing unit 315 may have an inspection function of the memory unit 50.

  The integrated circuit 303 can include an image processing unit 304, an optical distance measuring unit 306, a parallax calculation unit 307, an object recognition unit 308, and an abnormality detection unit 309. The image processing unit 304 processes the image signal output from the image preprocessing unit 315. For example, the image processing unit 304 performs processing such as image signal correction and defect compensation. The image processing unit 304 includes a storage medium 305 that temporarily stores an image signal. The storage medium 305 may store the positions of known defective pixels in the imaging device 302. When the vehicle 300 includes the imaging device 302 shown as the first embodiment or the third embodiment, the image processing unit 304 has a function of performing processing such as matching determination shown in FIGS. 6 and 13. It may be. Alternatively, when the vehicle 300 includes the imaging device 302 shown as the fifth to eighth embodiments, the image processing unit 304 may have an inspection function of the memory unit 50.

  The optical distance measuring unit 306 performs focusing or distance measurement of the subject using the image signal. The parallax calculation unit 307 performs subject matching (stereo matching) of parallax images. The object recognition unit 308 analyzes the image signal and recognizes a subject such as a car, a person, a sign, or a road.

  The abnormality detection unit 309 detects an abnormality such as a failure or malfunction of the imaging device 302. When detecting an abnormality, the abnormality detection unit 309 transmits a signal indicating that an abnormality has been detected to the main control unit 313. The abnormality detection unit 309 may have a function of performing processing such as matching determination shown in FIGS. Alternatively, the abnormality detection unit 309 may have the inspection function of the memory unit 50 described in the fifth to eighth embodiments. The abnormality detection unit 309 is based on the result of the coincidence determination performed by the image processing device 302 or a signal processing unit (for example, the image preprocessing unit 315, the image processing unit 304, or the abnormality detection unit 309) in the imaging system. A signal indicating that an abnormality has been detected may be transmitted to 313. This coincidence determination is, for example, a process of comparing the first inspection signal stored in the column memory 106 described in the first to fourth embodiments with an expected value. Alternatively, this coincidence determination is, for example, a process of comparing column memory inspection data written in the memory unit 50 described in the fifth to eighth embodiments with an expected value. The abnormality detection unit 309 can detect that an abnormality has occurred in the memory unit 50 in the imaging device 302 based on the comparison result.

  The vehicle 300 includes a vehicle sensor 310 and a driving support control unit 311. The vehicle sensor 310 may include a speed / acceleration sensor, an angular velocity sensor, a rudder angle sensor, a ranging radar, a pressure sensor, and the like.

  The driving support control unit 311 includes a collision determination unit. The collision determination unit determines whether or not there is a possibility of collision with an object based on information from the optical distance measurement unit 306, the parallax calculation unit 307, and the object recognition unit 308. The optical distance measurement unit 306 and the parallax calculation unit 307 are examples of distance information acquisition means for acquiring distance information to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit may determine the possibility of collision using any of these distance information. The distance information acquisition unit may be realized by hardware designed exclusively, or may be realized by a software module.

  The example in which the driving support control unit 311 functions as a control unit that controls the vehicle 300 so as not to collide with other objects has been described. However, the driving support control unit 311 performs control for automatically driving following other vehicles, lanes You may control to drive automatically so that it may not protrude.

  The vehicle 300 further includes a drive unit used for traveling such as an airbag, an accelerator, a brake, a steering, and a transmission. Vehicle 300 includes those control units. The control unit controls the corresponding drive unit based on the control signal of the main control unit 313.

  As described above, according to the present embodiment, there is provided a mobile body that can perform driving support, automatic driving, and the like equipped with the solid-state imaging device or imaging system described in the first to eighth embodiments. Moreover, in order to constitute a stereo camera, a plurality of solid-state imaging devices or imaging systems can be used.

  The imaging system used in the present embodiment is not limited to a vehicle such as an automobile, and can be applied to a moving body (moving apparatus) such as a ship, an aircraft, or an industrial robot. In addition, the present invention can be applied not only to mobile objects but also to devices that widely use object recognition, such as intelligent road traffic systems (ITS).

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications can be made.

  For example, an example in which a part of the configuration of any of the embodiments is added to another embodiment, or an example in which a part of the configuration of another embodiment is replaced is also an embodiment of the present invention.

  In the first to eighth embodiments, when the number of bits of information stored in the column memory of each column of the memory unit 50 is larger than the number of bits of information that can be output by the output circuit 80, the memory unit 50. The information stored in the column memory of each column is divided and output in bit units. However, even when the number of bits of information stored in the column memory of each column of the memory unit 50 is smaller than the number of bits of information that can be output by the output circuit 80, the column memory of each column of the memory unit 50 stores the information. Information may be divided and output in units of bits.

  In the first to eighth embodiments, the number of information bits that can be output by the output circuit 80 is 10 bits. However, the number of information bits that can be output by the output circuit 80 is particularly limited. It is not something. Further, the number of bits of information that can be stored in the column memory of each column of the memory unit 50 is not limited to that described in the above embodiment. The number of times that the information held in each column memory is divided and output can be appropriately set according to the relationship between the number of bits of information that can be output by the output circuit 80 and the number of bits of information that can be stored in the column memory. .

  In the above embodiment, the column memory test data is output during a period between the period for acquiring an image of a certain frame and the period for outputting the image of the next frame. It is not necessarily between frames. For example, after outputting image data of one row in the middle of outputting an image of a certain frame, output column memory inspection data before outputting image data of another row to be read next. You may make it do.

  In addition, the circuit configurations of the pixel 12, the horizontal transfer circuit 70, and the like shown in the above embodiment are examples, and can be changed as appropriate.

  In addition, the imaging system and the moving body shown in the ninth embodiment exemplify the imaging system and the moving body to which the photodetection device of the present invention can be applied, and the imaging system to which the solid-state imaging device of the present invention can be applied. The moving body is not limited to the configuration shown in FIGS.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

  The present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in the computer of the system or apparatus read and execute the program This process can be realized. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

DESCRIPTION OF SYMBOLS 10,110 ... Pixel array part 12, 101 ... Pixel 14 ... Control line 16 ... Output line 20, 103 ... Vertical scanning circuit 30 ... Amplifier circuit part 40, 104 ... Comparison circuit part 50 ... Memory part 52, 105 ... Counter 54, 109: Voltage supply units 60, 107 ... Horizontal scanning circuit 70 ... Horizontal transfer circuit 80 ... Output circuits 90, 102 ... Timing generator 100 ... Solid-state imaging device 106 ... Column memory

Claims (34)

A pixel that outputs a pixel signal that is an analog signal;
A readout unit that converts the pixel signal into a digital signal to generate a digital pixel signal;
A storage unit for storing the digital pixel signal;
A first inspection signal output unit that outputs a first inspection signal to the storage unit and stores the first inspection signal in the storage unit;
The first inspection signal stored in the storage unit is stored in the storage unit during a period after the output of the digital pixel signal of a certain frame is finished and before the output of the digital pixel signal of the next frame is started. A solid-state imaging device, wherein The solid-state imaging device according to claim 1, wherein the first inspection signal output unit outputs the first inspection signal that is a digital signal to the storage unit without passing through the reading unit. The solid-state imaging device according to claim 1, wherein the first inspection signal includes a plurality of inspection patterns having different values. The solid-state imaging device according to claim 3, wherein the first inspection signal output unit sequentially outputs and stores the plurality of inspection patterns to the storage unit. The plurality of inspection patterns are output from the storage unit after the output of the digital pixel signal of a certain frame is finished and before the output of the digital pixel signal of the next frame is started. The solid-state imaging device according to claim 3 or 4. One inspection pattern of the plurality of inspection patterns is generated after the output of the digital pixel signal of the first frame is completed and the digital pixel signal of the second frame next to the first frame is output. It is output from the storage unit in a period before output starts,
Another inspection pattern of the plurality of inspection patterns is generated after the output of the digital pixel signal of the second frame and the digital of the third frame after the second frame. 5. The solid-state imaging device according to claim 3, wherein the storage unit outputs the pixel signal in a period before the output of the pixel signal starts. A first determination unit configured to determine abnormality of the storage unit by comparing the first inspection signal output from the first inspection signal output unit and the first inspection signal stored in the storage unit; The solid-state imaging device according to claim 1, further comprising: The first determination result in the first determination unit is that the first determination unit is in a period after the output of the digital pixel signal of a certain frame is finished and before the output of the digital pixel signal of the next frame is started. The solid-state imaging device according to claim 7, wherein A second inspection signal output unit that outputs a second inspection signal that is an analog signal;
An amplifier that selectively receives the second inspection signal or the pixel signal and amplifies the input signal as an analog signal;
The solid state according to any one of claims 1 to 8, wherein the second inspection signal output from the amplifying unit is converted into a digital signal by the reading unit and stored in the storage unit. Imaging device. The second inspection signal stored in the storage unit is stored in the storage unit during a period after the output of the digital pixel signal of a certain frame is finished and before the output of the digital pixel signal of the next frame is started. The solid-state imaging device according to claim 9, wherein A second determination unit that determines an abnormality of the amplification unit by comparing the second inspection signal output from the second inspection signal output unit with the second inspection signal stored in the storage unit; The solid-state imaging device according to claim 9, further comprising: The second determination result in the second determination unit is the second determination unit in a period after the output of the digital pixel signal of a certain frame is finished and before the output of the digital pixel signal of the next frame is started. The solid-state imaging device according to claim 11, wherein A solid-state imaging device according to any one of claims 1 to 12,
An image pickup system comprising: a signal processing unit that processes a signal output from the solid-state image pickup device. The imaging system according to claim 13, further comprising: an abnormality detection unit that detects an abnormality of the solid-state imaging device based on a comparison result between the first inspection signal stored in the storage unit and an expected value. . A moving object,
A solid-state imaging device according to any one of claims 1 to 12,
Distance information acquisition means for acquiring distance information to an object from a parallax image based on the pixel signal output from the pixel of the solid-state imaging device;
And a control means for controlling the mobile body based on the distance information. The mobile body according to claim 15, further comprising: an abnormality detection unit that detects an abnormality of the solid-state imaging device based on a comparison result between the first inspection signal stored in the storage unit and an expected value. . A plurality of pixels arranged to form a matrix including a plurality of columns and a plurality of rows;
A plurality of memories provided corresponding to the plurality of columns, each holding information based on signals output from the pixels arranged in the corresponding columns as digital values;
An inspection information supply unit for supplying inspection information for failure inspection to the plurality of memories;
An output circuit for outputting information held by the plurality of memories,
The output circuit outputs information based on signals output from the plurality of pixels in units of rows,
The output circuit outputs the inspection information held in a part of the plurality of memories in a first period corresponding to an output period for one row and holds it in another part of the plurality of memories. The inspection information is output in a second period that is separate from the first period and corresponds to an output period for one row,
Each of the first period and the second period is a period between an output operation of pixel information of one row by the output circuit and an output operation of pixel information of another row by the output circuit. A solid-state imaging device. The number of bits of information that can be stored in each of the plurality of memories is greater than the number of bits of information based on the signal output from the pixel,
The output circuit divides information stored in each of the plurality of memories in units of bits so that the number of bits of information output at one time is equal to or less than the number of bits of information based on a signal output from the pixel. The solid-state imaging device according to claim 17, wherein the solid-state imaging device outputs the solid-state imaging device. The output circuit supplies the inspection information between an output of first image data based on a signal output from the pixel and an output of second image data based on a signal output from the pixel. The solid-state imaging device according to claim 17 or 18, wherein information held in the plurality of memories is output from the memory. The solid-state imaging device according to claim 19, wherein the second image data is image data output next to the first image data. The first image data is image data of a first frame, and the second image data is image data of a second frame next to the first frame. 20. The solid-state imaging device according to 20. The solid-state imaging device according to claim 19 or 20, wherein the first image data and the second image data are data in different rows of one frame. The output circuit outputs all of the inspection information held by the plurality of memories between the output of the first image data and the output of the second image data. The solid-state imaging device according to any one of 19 to 22. The output circuit outputs a part of the inspection information held by the plurality of memories between the output of the first image data and the output of the second image data. The solid-state imaging device according to any one of claims 19 to 22. Each of the plurality of memories has a first memory that holds first information based on an optical signal output from the pixel, and a second memory that holds second information based on a noise signal output from the pixel. With a memory of
The output circuit outputs a third digital value obtained by subtracting a second digital value based on information held in the second memory from a first digital value based on information held in the first memory. The solid-state imaging device according to any one of claims 17 to 24, wherein: An AD conversion circuit unit that converts an analog signal output from the pixel into a digital signal with a variable AD conversion gain;
The first information is information obtained by converting the optical signal into a digital value with a first AD conversion gain,
The second information is information obtained by converting the noise signal into a digital value with a second AD conversion gain,
The solid-state imaging device according to claim 25, wherein the output circuit calculates the third digital value in consideration of the first AD conversion gain and the second AD conversion gain. 27. The solid memory according to claim 26, wherein each of the plurality of memories further includes a third memory that holds information indicating a relationship between the first AD conversion gain and the second AD conversion gain. Imaging device. An amplifier circuit unit for amplifying a signal output from the pixel at a variable amplification factor;
The first information is information obtained by converting a signal obtained by amplifying the optical signal with a first amplification factor into a digital value,
The second information is information obtained by converting a signal obtained by amplifying the noise signal with a second amplification factor into a digital value,
The solid-state imaging device according to claim 25, wherein the output circuit calculates the third digital value in consideration of the first amplification factor and the second amplification factor. The solid-state imaging device according to claim 28, wherein each of the plurality of memories further includes a third memory that holds information indicating a relationship between the first amplification factor and the second amplification factor. . 30. The inspection information supply unit supplies the different inspection information to at least two of the memories from which information is output from the output circuit at different timings. The solid-state imaging device described. A solid-state imaging device according to any one of claims 17 to 30,
An image pickup system comprising: a signal processing unit that processes a signal output from the solid-state image pickup device. 32. The apparatus according to claim 31, further comprising an abnormality detection unit that detects an abnormality of the solid-state imaging device based on a comparison result between inspection data output from the plurality of memories supplied with the inspection information and an expected value. Imaging system. A moving object,
A solid-state imaging device according to any one of claims 17 to 30,
Distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal output from the pixel of the solid-state imaging device;
And a control means for controlling the mobile body based on the distance information. 34. The apparatus according to claim 33, further comprising an abnormality detection unit that detects an abnormality of the solid-state imaging device based on a comparison result between inspection data output from the plurality of memories supplied with the inspection information and an expected value. Moving body.

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