JP2018120522A - Information processing system and control method of information processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing system which can be operated for a long time with a small capacity nonvolatile memory.SOLUTION: An information processing system comprises: a nonvolatile memory; memory control means for controlling allocation of blocks in a nonvolatile memory; a bad list; and a free list. The bad list is a list in which blocks consisting of consecutive pages including the bad page are collected, when a page including a memory cell whose error in the nonvolatile memory tends to increase is regarded as a bad page. The free list is a list in which blocks consisting of consecutive pages not including the above-mentioned bad page are collected. The memory control means previously attempts allocation processing of blocks of the free list, when performing block allocation control. Here, if it is impossible to allocate the free list blocks, allocation processing of blocks of the bad list is attempted.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an information processing system and a control method for the information processing system.

  In general, a hard disk, a flash memory, and the like have been used as a nonvolatile memory. In recent years, nonvolatile memories such as FeRAM, MRAM, PCRAM, ReRAM, and CBRAM that can be randomly accessed at high speed have been developed. The notation of these RAMs is an abbreviation for Random Access Memory. FeRAM is an abbreviation for Ferroelectric-RAM, MRAM is an abbreviation for Magnetoretic-RAM, and PCRAM is an abbreviation for Phase-Change-RAM. ReRAM is an abbreviation for Resistive-RAM, and CBRAM is an abbreviation for Conductive-Bridge-RAM. An information processing system using these emerging nonvolatile memories as a main memory in the same manner as a DRAM (Dynamic-RAM) has been proposed. For example, an information processing system that realizes a high-speed suspend / resume function by using a non-volatile memory has been proposed. However, emerging nonvolatile memories have problems such as wear due to writing. Therefore, a method for solving such a problem has been proposed.

  For example, Patent Document 1 discloses a memory system including a nonvolatile memory and a wear level management method thereof. The technique described in Patent Document 1 includes a page table including mapping information of a virtual address and a physical address of a nonvolatile memory, and the page table entry includes life information indicating the degree of wear of the page. Each time data is written to the page, the life information is updated, and control is performed so that memory allocation is not performed for the page that has reached the endurance limit. Further, when physically continuous pages need to be allocated, a buddy system that manages empty pages is used to control memory allocation for pages that have reached the endurance limit. With the above control, memory can be allocated to pages within the endurance limit.

  Patent Document 2 discloses a nonvolatile memory that stores memory remapping information. The technique described in Patent Document 2 selects a spare memory cell so as to stop using a memory cell whose number of errors exceeds a threshold and maintain the entire memory device capacity. By this control, it is possible to secure a capacity while selecting a memory cell whose error number is equal to or less than a threshold value.

JP 2010-186477 A JP 2011-040051 A

  In the technique described in Patent Document 1, as the operation period becomes longer, the number of pages that have reached the endurance limit increases, and memory fragmentation in units of pages proceeds. For this reason, when it is necessary to allocate physically continuous pages, there is a problem that memory cannot be allocated efficiently.

  The technique described in Patent Document 2 solves the problem of memory fragmentation by using a spare memory, but as the operation period becomes longer, the number of memory cells in which the number of errors exceeds the threshold increases. Therefore, in order to maintain the entire memory device capacity, there is a problem that many spare memory cells are required.

  The present invention has been made in view of the above problems, and an object thereof is to provide an information processing system that can be operated for a long time with a small-capacity nonvolatile memory.

  In order to solve the above-described problems, an information processing system according to the present invention includes a non-volatile memory, memory control means for performing block allocation control in the non-volatile memory, a bad list, a free list, Have The bad list is a list in which blocks including non-volatile memories including memory cells in which errors tend to increase are used as bad pages, and blocks including continuous pages including the bad pages are collected. The free list is a list in which blocks composed of continuous pages not including the bad page are collected. The memory control means first attempts free block allocation processing when performing block allocation control. If the free list block cannot be allocated, an attempt is made to allocate a bad list block.

  An effect of the present invention is to provide an information processing system that can be operated for a long time with a small-capacity nonvolatile memory.

It is a block diagram which shows the information processing system of 1st Embodiment. It is a block diagram which shows the whole structure of the information processing system of 2nd Embodiment. It is a block diagram which shows the main memory device of the information processing system of 2nd Embodiment. It is a block diagram which shows a part of main memory | storage device of the information processing system of 2nd Embodiment. It is a schematic diagram which shows the management method of the real page containing the bad page in the information processing system of 2nd Embodiment. It is another schematic diagram which shows the management method of the real page containing the bad page in the information processing system of 2nd Embodiment. It is a flowchart which shows the registration process of the bad page in the information processing system of 2nd Embodiment. It is a part of flowchart which shows the registration process of the bad page in the information processing system of 2nd Embodiment. It is a flowchart which shows the block allocation process in the information processing system of 2nd Embodiment. It is a flowchart which shows the allocation process of the block of the free list in the information processing system of 2nd Embodiment. It is a flowchart which shows the block allocation process of the bad list in the information processing system of 2nd Embodiment. 12 is a flowchart illustrating a part of a bad list block allocation process in the information processing system according to the second embodiment. It is a flowchart which shows the block release process in the information processing system of 2nd Embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the preferred embodiments described below are technically preferable for carrying out the present invention, but the scope of the invention is not limited to the following. In addition, the same number is attached | subjected to the same component of each drawing, and description may be abbreviate | omitted.

(First embodiment)
FIG. 1 is a block diagram showing the first embodiment. The information processing system includes a nonvolatile memory 1, a memory control unit 2 that controls allocation of blocks in the nonvolatile memory 1, a bad list 3, and a free list 4.

  The bad list 3 is a list in which the pages including the memory cells in which errors tend to increase in the non-volatile memory 1 are set as bad pages, and blocks including continuous pages including the bad pages are collected.

  The free list 4 is a list in which blocks including continuous pages not including the bad page are collected.

  The memory control means 2 first tries the block allocation process of the free list 4 when performing block allocation control. Here, when the block of the free list 4 cannot be allocated, the block allocation process of the bad list 3 is tried.

  With the above configuration, an information processing system that can be operated for a long time with a small-capacity nonvolatile memory can be provided.

(Second Embodiment)
FIG. 2 is a block diagram showing the overall configuration of the information processing system of the present invention. The information processing system 1000 includes a CPU (Central Processing Unit) 100, a main storage device 200, a secondary storage device 300, and an input / output device 400.

  The CPU 100 executes a program loaded from the secondary storage device 300 to the main storage device 200, and controls the main storage device 200, the secondary storage device 300, and the input / output device 400 via the bus 500. In addition, the CPU 100 executes a program in response to a control signal from each device.

  The secondary storage device 300 includes a hard disk, a flash memory, and the like as a nonvolatile memory. The input / output device 400 includes input means such as a keyboard and a mouse and output means such as a liquid crystal display.

  The main storage device 200 includes a nonvolatile memory 210 and a memory control device 220. Note that a volatile memory 230 may be included as the main storage device 200. The volatile memory 230 of the main storage device 200 includes DRAM and SRAM. The volatile memory 230 can hold data only while power is supplied. The non-volatile memory 210 includes a non-volatile memory that can be randomly accessed at high speed, such as FeRAM, MRAM, PCRAM, ReRAM, and CBRAM. The nonvolatile memory 210 can retain data even when power supply is interrupted. On the other hand, the volatile memory 230 stores programs and data processed by the CPU 100 during operation. The nonvolatile memory 210 stores programs and data processed by the CPU 100 during operation and suspend.

  The real memory provided by the main storage device 200 is divided into pages and managed. The virtual address space is also divided and managed in the same page unit. The CPU 100 provided with the virtual storage mechanism can operate the program in a unique virtual address space. The conversion from the virtual address to the real memory address (real address) is performed in units of pages based on the page table. The page table is a correspondence table between virtual pages and real pages.

  The real memory provided by the main storage device 200 in the information processing system 1000 of this embodiment can be managed by distinguishing between the volatile memory 230 and the nonvolatile memory 210. For example, Linux (registered trademark), which is one of the operating systems (OS), includes a mechanism for managing pages according to a combination of zones and nodes, but a similar mechanism may be applied. A zone is a unit that is managed by being divided according to the real address area. Pages are allocated for each zone. A node is a unit managed by dividing a memory in the system. Nodes are used, for example, to make a difference in how memory is allocated in a Non-Uniform Memory Access (NUMA) system.

  FIG. 3 is a block diagram showing the main storage device 200 of this embodiment. The main storage device 200 includes a nonvolatile memory 210, a nonvolatile spare memory 211, and a memory control device 220. The memory control device 220 transmits or receives signals including address signals, data signals, and control signals via the bus 500. The memory control device 220 is connected to the nonvolatile memory 210 and the nonvolatile spare memory 211 via the local bus 600 and transmits or receives signals including a local address signal, a local data signal, and a local control signal. The non-volatile spare memory 211 includes, for example, the same type of memory cells as the non-volatile memory.

  FIG. 4 is a schematic diagram showing a part of the memory control device. The memory control device 220 includes an address conversion unit 221, a switch unit 222, an error detection unit 223, and a bad page management unit 224.

  The address conversion unit 221 replaces the bad page in the nonvolatile memory 210 with a page in the nonvolatile spare memory 211 in units of pages. The bad page of the nonvolatile memory 210 is a page including memory cells in which errors tend to increase. The address conversion unit 221 includes a storage unit 221 a that stores correspondence information between the address of the replacement-source nonvolatile memory 210 and the replacement-destination nonvolatile spare memory 211. Then, the address signal on the bus 500 is converted into a local address signal on the local bus 600 with reference to the correspondence information in the storage unit 221a. The address conversion unit 221 may perform high-speed address conversion using a content addressable memory (CAM) or the like as the storage unit 221a that stores address correspondence information.

  The switch unit 222 selects a local data output signal that is read data of the memory cell specified by the local address signal, and supplies the local data output signal to the error detection unit 223. The switch unit 222 can use a signal switch such as a multiplexer.

  The error detection unit 223 detects a memory cell in which an error has occurred, and outputs error information to the bad page management unit 224. The memory control device 220 can use a technique such as Error Correction Code (ECC) as the error detection unit 223. The error detection unit 223 may correct the error using a technique such as ECC and output a data output signal.

  The bad page management unit 224 uses the error information supplied from the error detection unit 223 and the local address signal supplied from the address conversion unit 221 to determine whether the memory cell specified by the local address has a tendency to increase errors. Judge whether or not. When it is determined that the error tends to increase, the page including the memory cell is registered as a bad page. For example, the bad page management unit 224 records the address of the memory cell in which an error has occurred and the number of times of the error. Alternatively, if the number of errors in the code word is greater than a certain threshold value for a plurality of memory cells forming an ECC code word, the bad page management unit 224 determines that the memory cells tend to increase in error. . The bad page management unit 224 includes a storage unit 224a for registering a bad page, and stores an identifier such as a page frame number of the bad page. The page frame number is composed of some bits of the address used by the CPU 100. Furthermore, the bad page management unit 224 includes a notification unit 224b that notifies the CPU 100 of registration of a bad page. For example, the notification unit 224b uses notification means such as an interrupt request. Upon receiving the notification from the memory control device 220, the CPU 100 reads the registered bad page identifier from the storage unit 224a of the bad page management unit 224 in the interrupt process. The CPU 100 manages bad pages using software such as an OS described later.

  FIG. 5 is a schematic diagram showing a management method for real pages including bad pages in the information processing system of this embodiment. The information processing system according to the present embodiment manages real pages by a buddy system including a free area and a bad area. The buddy system manages pages in units of powers of 2. In the free area, continuous pages in units of powers of 2 composed of empty pages are collected, and in the bad area, continuous pages in units of powers of 2 including bad pages are collected. The buddy system manages continuous pages as blocks.

  FIG. 5 illustrates eight pages and respective buddy system blocks. The buddy system manages unused pages, used pages, and bad pages. The order represents a power index. The block of order N has a page size of 2 N and the page frame number of the first page of the block of order N is an integer multiple of 2 N. Here, a buddy block is defined as an adjacent block of the same order N and, when integrated, a block of order (N + 1) can be formed.

  As shown in FIG. 5, a block is configured as large as possible using unused pages and bad pages. This is done by investigating whether the buddy block exists in the bad area or the free area, and if there is a buddy block, these blocks are integrated to form a large block. Further, when a bad page is included in the block, the block is made to belong to the bad area. If a bad page is not included, the block is assigned to a free area. In FIG. 5, there is one block for order 0, one block for order 1, and one block for order 2. Among them, the block of order 2 includes a bad page. For this reason, the block of order 2 belongs to the bad area. Since the blocks of order 0 and order 1 do not include bad pages, they belong to the free area.

FIG. 6 is a schematic diagram showing a management method for real pages including bad pages in the information processing system of this embodiment. The information processing system according to the present embodiment manages real pages using a free list and a bad list that are composed of zone descriptors and page descriptors. The zone descriptor is a descriptor for managing a zone to which a real page of the nonvolatile memory belongs. The page descriptor is a descriptor that manages an actual page of the nonvolatile memory.
The zone descriptor includes a free_area member and a bad_area member. The free_area member has a free_list array. The bad_area member has a bad_list array. The indices of these arrays are orders.

  The free_list [N] member points to the first page descriptor of the free list whose order is N. The free list with the order N is composed of the page descriptor of the first page among the blocks belonging to the free area with the order N.

  The bad_area [N] member points to the first page descriptor of the bad list whose order is N. The bad list with the order N is composed of the page descriptor of the first page among the blocks belonging to the bad area with the order N.

  The page descriptor includes a PG_bad flag and a next member. The PG_bad flag is set to 1 when the page is a bad page. Set to 0 if the page is not a bad page. The next member points to the subsequent page descriptor of each list.

  FIG. 7 is a flowchart of bad page registration processing in the information processing system of this embodiment. When a notification of bad page registration is received from the memory control device, a soft wafer such as an OS acquires the page frame number of the page P1 registered as a bad page from the memory control device (S1). Then, a PG_bad flag is set in the page descriptor of page P1 (S2).

  If the page P1 is not in use (S3_No), control is performed so that the block including the page P1 is connected to the bad list, and the block is updated (S4).

  On the other hand, when the page P1 is in use (S3_Yes), the process proceeds to the process A. FIG. 8 is a flowchart showing the process A. In the process A, first, it is checked whether or not the page P1 is a continuous page (S5).

  If the page P1 is not a continuous page (S5_No), an attempt is made to allocate a new page P2 (S6). When the allocation is successful (S7_Yes), the contents of the page P1 are moved to the new page P2. Then, the page table entry is updated so as to point to the new page P2 from the page P1 (S8). If the allocation has failed (S7_No), a new page allocation error is returned (S9). Then, the process returns to B in the flowchart of FIG.

  On the other hand, when the page P1 is a continuous page (S5_Yes), replacement of the page P1 with the spare page P3 is attempted (S10). If there is an unused spare page that can be replaced (S11_Yes), the contents of page P1 are moved to spare page P3. Then, the address conversion unit of the memory control device is updated so as to convert the address of page P1 into the address of spare page P3 (S12). If the replacement is not possible (S11_No), a spare page replacement error is returned (S13). Then, the process returns to B in the flowchart of FIG.

  FIG. 9 is a flowchart of block allocation processing in the information processing system of this embodiment. When a block allocation request is received (S101), software such as an OS tries to allocate a free list block (S102).

  When the free list block is acquired (S103_Yes), the acquired block is returned (S107). On the other hand, if a free list block could not be acquired (S103_No), an attempt is made to allocate a bad list block (S104).

  When the bad list block is acquired (S105_Yes), the acquired block is returned (S107). On the other hand, if a bad list block could not be acquired (105_No), NULL is returned as an allocation failure (S106).

  FIG. 10 is a flowchart of free list block allocation processing in the information processing system of this embodiment. First, upon receiving a request to allocate a block having a page size of 2 to the power of M (S201), software such as the OS tries to acquire a block having a page size of the power of 2N under the condition of N ≧ M ( S202). At this time, in order to obtain as small a block as possible, the block is examined from a small order free list.

  If a 2 N block cannot be obtained (S203_No), NULL is returned as an allocation failure (S204).

  On the other hand, when a 2 N block can be acquired (S203_Yes), the block size is checked. When the block size is equal to the requested size, that is, when N = M (S205_Yes), an acquisition block is returned (S207). On the other hand, when the block size is larger than the requested size, that is, when N> M (S205_No), an unnecessary block is released (S206), and an acquired block is returned (S207).

  FIG. 11 is a flowchart of block list allocation processing in the information processing system of this embodiment. First, upon receiving an allocation request for a block having a page size of M to the power of 2 (S301), software such as the OS tries to acquire a block having a page size of the power of 2N under the condition of N ≧ M ( S302). At this time, in order to obtain as small a block as possible, the block is examined from a bad order bad list.

  If a 2 N block cannot be acquired (S303_No), NULL is returned as an allocation failure (S304).

  On the other hand, if a 2 N block can be acquired (S303_Yes), the process proceeds to process C. FIG. 12 is a flowchart showing the process C. In process C, the block size is first examined. If the block size is equal to the requested size (if N = M, S305_Yes), it is checked whether there is a bad page in the acquired block (S307). On the other hand, if the block size is larger than the requested size (if N> M, S305_No), an unnecessary block is released (S306), and it is checked whether there is a bad page in the acquired block (S307). In the process of releasing an unnecessary block, control may be performed so that a bad page is not included in the acquired block as much as possible to suppress the use of a spare page.

  In S307, it is checked whether there is a bad page in the acquired block. If the bad page is not included (S307_No), the acquisition block is returned (S311), and the process returns to D in the flowchart of FIG.

  On the other hand, if a bad page is included (S307_Yes), an attempt is made to replace the bad page with a spare page (S308). If there is an unused spare page and it can be replaced (S309_Yes), the address conversion unit of the memory control device is updated so as to convert the bad page address into the spare page address (S310). And an acquisition block is returned (S311) and it returns to D of the flowchart of FIG. On the other hand, if the replacement is not possible (S309_No), the acquired block is released (S312), the process returns to E in the flowchart of FIG. 11, returns NULL as an allocation failure (S304), and ends.

FIG. 13 is a flowchart of block release processing in the information processing system of this embodiment. First, upon receiving a request to release a block having a page size of M to the power of 2 (S401), software such as the OS integrates the block with a page size of N to the power of 2 under the condition of N ≧ M (S402). ). Here, the buddy blocks in the small order free list or the bad list are sequentially checked and integrated into as large a block as possible.
When a bad page is not included in the integrated block (S403_No), the block is connected to the free list (S404).

  On the other hand, if a bad page is included in the integrated block (S403_Yes), it is checked whether the bad page is replaced with a spare page (S405). As a method for checking whether or not a spare page has been replaced, for example, a PG_spare flag may be provided in the page descriptor, and the PG_spare flag may be set to 1 when the spare page is replaced.

  If it has not been replaced with a spare page (S405_No), the block is connected to the bad list (S407).

  On the other hand, if the spare page has been replaced (S405_Yes), the spare page is released (S406). Spare page release processing includes processing for deleting the correspondence between bad pages and spare pages from the address translation unit. Then, the block is connected to the bad list (S407).

  Spare page management may be performed using hardware such as a memory control device or software such as an OS.

(effect)
When it is necessary to allocate physically continuous pages, the information processing system of this embodiment replaces bad pages with spare pages on demand. Thereby, a plurality of bad pages can share a spare page in a time-sharing manner. Furthermore, the use of spare pages is suppressed by trying to allocate pages in the order of free list and bad list. As a result, it is expected that the required spare memory capacity can be reduced even during long-term operation.

  Therefore, the information processing system of this embodiment can provide an information processing system including a nonvolatile memory that can be operated for a long time with a small-capacity spare memory.

  A program for causing a computer to execute the processes of the first and second embodiments described above and a recording medium storing the program are also included in the scope of the present invention. As the recording medium, for example, a magnetic disk, a magnetic tape, an optical disk, a magneto-optical disk, a semiconductor memory, or the like can be used.

  A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.

(Appendix 1)
Non-volatile memory;
Memory control means for controlling the nonvolatile memory;
A page including non-volatile memory cells in which errors in the non-volatile memory tend to increase is defined as a bad page, and a bad list in which blocks including continuous pages including the bad page are collected;
A free list in which blocks consisting of continuous pages not including the bad page are collected;
Have
The memory control means includes
In the block allocation process, the free list block allocation process is tried first, and when the free list block allocation is impossible, the bad list block allocation process is attempted. Processing system.

(Appendix 2)
A nonvolatile spare memory constituting a spare page; and
An address conversion unit that converts the address of the page in page units,
The address conversion unit
The information processing system according to appendix 1, wherein the bad page address is converted into the spare page address during block assignment processing of the bad list.

(Appendix 3)
The memory control means;
In the block release processing, if the block has the bad page replaced with the spare page, the correspondence between the bad page and the spare page is deleted from the address conversion unit. The information processing system described.

(Appendix 4)
The memory control means is
During the bad page registration process, if the bad page is in use and is a continuous page, an attempt is made to replace the bad page with the spare page,
If the replacement to the spare page is possible, the content of the bad page is moved to the spare page,
The information processing system according to appendix 3, wherein the address conversion unit is updated so as to convert the address of the bad page into the address of the spare page.

(Appendix 5)
The memory control means is
During the bad page registration process, if the bad page is in use and is a non-continuous page, an attempt is made to allocate a new page,
If assignment of the new page is possible, move the contents of the bad page to the new page,
The information processing system according to appendix 4, wherein a page table entry is updated so as to convert the address of the bad page into the address of the new page.

(Appendix 6)
The memory control means is
6. The information processing system according to appendix 5, wherein, when the bad page is not used during the bad page registration process, a block including the bad page is connected to the bad list.

(Appendix 7)
The memory control means is
When the block size acquired from the bad list is larger than the requested block size during the block allocation process of the bad list, an unnecessary block is released,
7. The information processing system according to appendix 6, wherein when the unnecessary block is released, control is performed so that the acquired block does not include the bad page as much as possible.

(Appendix 8)
The memory control means is
A switch unit, an error detection unit, and a bad page management unit;
The switch unit selects read data of the memory cell specified by the address signal converted by the address conversion unit, and supplies the read data to the error detection unit,
The error detection unit detects a memory cell in which an error has occurred, and supplies error information to the bad page management unit.
The information processing system according to appendix 7, wherein the bad page management unit registers, as the bad page, a page including the nonvolatile memory cells in which errors tend to increase.

(Appendix 9)
A CPU that executes information processing;
The bad page management unit
The information processing system according to appendix 7 or appendix 8, further comprising a notification unit that notifies the CPU of registration of the bad page.

(Appendix 10)
A bus connecting the CPU and the memory control means;
The information processing system according to claim 9, further comprising: a local bus that connects the memory control unit and the nonvolatile memory and the nonvolatile spare memory.

(Appendix 11)
Control non-volatile memory,
A page including a nonvolatile memory cell in which errors in the nonvolatile memory tend to increase is defined as a bad page, and a bad list is created by collecting blocks including continuous pages including the bad page,
Create a free list that collects blocks of consecutive pages that do not include the bad page,
At the time of block allocation processing, first try block allocation processing of the free list,
A control method for an information processing system, characterized in that, when the free list block cannot be allocated, an attempt is made to allocate the bad list block.

(Appendix 12)
Configure spare pages using non-volatile spare memory,
Convert the address of the page in page units,
In the conversion of the address,
12. The information processing system control method according to appendix 11, wherein an address of the bad page is converted into an address of the spare page during block assignment processing of the bad list.

(Appendix 13)
The appendix 12 is characterized in that, when the block has the bad page replaced with the spare page during the block release processing, the correspondence relationship between the bad page and the spare page is deleted from the address conversion unit. A control method of the information processing system described.

(Appendix 14)
During the bad page registration process, if the bad page is in use and is a continuous page, an attempt is made to replace the bad page with the spare page,
If the replacement to the spare page is possible, the content of the bad page is moved to the spare page,
14. The information processing system control method according to appendix 13, wherein the address conversion unit is updated so as to convert the address of the bad page into the address of the spare page.

(Appendix 15)
During the bad page registration process, if the bad page is in use and is a non-continuous page, an attempt is made to allocate a new page,
If assignment of the new page is possible, move the contents of the bad page to the new page,
15. The information processing system control method according to appendix 14, wherein a page table entry is updated so as to convert an address of the bad page into an address of the new page.

(Appendix 16)
16. The information processing system control method according to appendix 15, wherein, when the bad page is not used during the bad page registration process, a block including the bad page is connected to the bad list.

(Appendix 17)
When the block size acquired from the bad list is larger than the requested block size during the block allocation process of the bad list, an unnecessary block is released,
17. The information processing system control method according to appendix 16, wherein when an unnecessary block is released, control is performed so that the acquired block does not include the bad page as much as possible.

(Appendix 18)
The switch unit selects the read data of the memory cell specified by the address signal converted by the address conversion unit, and supplies it to the error detection unit,
The error detection unit detects a memory cell in which an error has occurred, and supplies error information to a bad page management unit.
18. The information processing system control method according to appendix 17, wherein the bad page management unit registers a page including the nonvolatile memory cell in which errors tend to increase as the bad page.

(Appendix 19)
The bad page management unit
19. The information processing system control method according to appendix 18, wherein registration of the bad page is notified to the CPU.

(Appendix 20)
Controlling the non-volatile memory;
Creating a bad list in which blocks including non-volatile memory cells in the non-volatile memory that have a tendency to increase are set as bad pages, and a block including continuous pages including the bad pages is collected;
Creating a free list of blocks composed of continuous pages that do not include the bad page;
At the time of block allocation processing, the step of first trying block allocation processing of the free list;
A control program for an information processing system, comprising: trying to assign a block of the bad list when the free list block cannot be assigned.

  As mentioned above, although preferable embodiment of this invention was described, this invention is not limited to this. It goes without saying that various modifications are possible within the scope of the invention described in the claims, and these are also included in the scope of the present invention.

1,210 Non-volatile memory 2 Memory control means 3 Bad list 4 Free list 100 CPU
200 Main Storage Device 220 Memory Control Device 230 Volatile Memory 300 Secondary Storage Device 400 Input / Output Device 500 Bus 600 Local Bus 1000 Information Processing System

Claims (10)

Non-volatile memory;
Memory control means for controlling the nonvolatile memory;
A page including non-volatile memory cells in which errors in the non-volatile memory tend to increase is defined as a bad page, and a bad list in which blocks including continuous pages including the bad page are collected;
A free list in which blocks consisting of continuous pages not including the bad page are collected;
Have
The memory control means includes
In the block allocation process, the free list block allocation process is tried first, and when the free list block allocation is impossible, the bad list block allocation process is attempted. Processing system. A nonvolatile spare memory constituting a spare page; and
An address conversion unit that converts the address of the page in page units,
The address conversion unit
The information processing system according to claim 1, wherein the bad page address is converted into the spare page address when the bad list block is allocated. The memory control means;
3. The correspondence relationship between the bad page and the spare page is deleted from the address conversion unit when the block has the bad page replaced with the spare page during the block release process. Information processing system described in 1. The memory control means is
During the bad page registration process, if the bad page is in use and is a continuous page, an attempt is made to replace the bad page with the spare page,
If the replacement to the spare page is possible, the content of the bad page is moved to the spare page,
The information processing system according to claim 3, wherein the address conversion unit is updated so as to convert the address of the bad page into the address of the spare page. The memory control means;
During the bad page registration process, if the bad page is in use and is a non-continuous page, an attempt is made to allocate a new page,
If assignment of the new page is possible, move the contents of the bad page to the new page,
5. The information processing system according to claim 4, wherein a page table entry is updated so as to convert the address of the bad page into the address of the new page. The memory control means is
6. The information processing system according to claim 5, wherein, when the bad page is not used during the bad page registration process, a block including the bad page is connected to the bad list. The memory control means is
When the block size acquired from the bad list is larger than the requested block size during the block allocation process of the bad list, an unnecessary block is released,
The information processing system according to claim 6, wherein when the unnecessary block is released, the acquired block is controlled so as not to include the bad page as much as possible. The memory control means is
A switch unit, an error detection unit, and a bad page management unit;
The switch unit selects read data of the memory cell specified by the address signal converted by the address conversion unit, and supplies the read data to the error detection unit,
The error detection unit detects a memory cell in which an error has occurred, and supplies error information to the bad page management unit.
The information processing system according to claim 7, wherein the bad page management unit registers, as the bad page, a page including the nonvolatile memory cells in which errors tend to increase. Control non-volatile memory,
A page including a nonvolatile memory cell in which errors in the nonvolatile memory tend to increase is defined as a bad page, and a bad list is created by collecting blocks including continuous pages including the bad page,
Create a free list that collects blocks of consecutive pages that do not include the bad page,
At the time of block allocation processing, first try block allocation processing of the free list,
A control method for an information processing system, characterized in that, when the free list block cannot be allocated, an attempt is made to allocate the bad list block. Controlling the non-volatile memory;
Creating a bad list in which blocks including non-volatile memory cells in the non-volatile memory that have a tendency to increase are set as bad pages, and a block including continuous pages including the bad pages is collected;
Creating a free list of blocks composed of continuous pages that do not include the bad page;
At the time of block allocation processing, the step of first trying block allocation processing of the free list;
A control program for an information processing system, comprising: trying to assign a block of the bad list when the free list block cannot be assigned.

Images