JP2018117147A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of stabilizing electrical characteristics while showing the original performance of the semiconductor device, by removing metal impurities of the substrate with a simple method.SOLUTION: A semiconductor device includes a drift layer formed in the active region of a substrate, a MOS structure formed on the upper surface side of the drift layer and having a trench gate, a buffer layer in contact with the lower surface of the drift layer, and a collector layer in contact with the lower surface of the buffer layer. Lifetime of carriers in the drift layer satisfies following mathematical formula 1, where τ (sec) is the lifetime of carriers in the drift layer, and t(m) is the thickness of the drift layer.SELECTED DRAWING: Figure 16

Description

  The present invention relates to a semiconductor device (for example, IGBT or diode) used for high voltage, large current switching or the like.

  Patent Document 1 discloses a method for manufacturing a semiconductor device that employs gettering technology. According to this gettering technique, first, gettering sites are formed on the lower surface of a semiconductor wafer (substrate). Thereafter, heat treatment is performed on the substrate to capture metal impurities in the substrate at the gettering site. Thereafter, the contaminated layer, which is a gettering site capturing the metal impurities, is removed. In the method of manufacturing a semiconductor device disclosed in Patent Document 1, these processes are performed a plurality of times.

Japanese Patent Laid-Open No. 4-218921 Japanese Patent Laid-Open No. 7-263692 International Publication No. 2009-122486 International Publication No. 2002-058160 International Publication No. 2002-061845 Japanese Unexamined Patent Publication No. 2001-085686 Japanese Unexamined Patent Publication No. 2010-283131 Japanese Unexamined Patent Publication No. 2012-9811

  In the method of manufacturing a semiconductor device disclosed in Patent Document 1, gettering sites are formed, the substrate is heated, and the contaminated layer is removed a plurality of times. Therefore, there is a problem that the manufacturing process of the semiconductor device is complicated.

  Further, in the method for manufacturing a semiconductor device disclosed in Patent Document 1, it has not been sufficiently examined how the use of the gettering technology affects the electrical characteristics of the semiconductor device. There was a problem that it was not clear if it should be used.

  The present invention has been made in order to solve the above-described problems, and a semiconductor capable of stabilizing the electrical characteristics while removing the metal impurities and the like of the substrate by an easy method and showing the original performance of the semiconductor device. An object is to provide an apparatus.

A semiconductor device according to the present invention includes a drift layer formed in an active region of a substrate, a MOS structure formed on an upper surface side of the drift layer and having a trench gate, and a buffer layer in contact with the lower surface of the drift layer, A lifetime of carriers in the drift layer is τ [sec], and the thickness of the drift layer is t _{When N−} [m], the following formula 1 is satisfied.

  Other features of the present invention will become apparent below.

  According to the present invention, it is possible to remove the metal impurities and the like of the substrate by an easy method and to stabilize the electrical characteristics while showing the original performance of the semiconductor device.

1 is a plan view of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing in the II-II line of FIG. It is sectional drawing which shows having formed the N layer and the base layer in the board | substrate with which the N < ^- > drift layer of IGBT was formed. It is sectional drawing which shows having formed the emitter in IGBT. It is sectional drawing which shows having formed the trench in IGBT. It is sectional drawing which shows having filled the trench in IGBT with the polysilicon. It is sectional drawing which shows having formed the interlayer film which consists of a silicate glass or a TEOS film. It is sectional drawing which shows having exposed the N < ^- > drift layer of the board | substrate lower surface. It is sectional drawing which shows having formed the polysilicon which doped phosphorus. It is sectional drawing which shows having formed the gettering layer in IGBT. It is a graph which shows the impurity density of the board | substrate after the pre-processing annealing process in IGBT. It is sectional drawing which shows having removed the doped polysilicon of the board | substrate upper surface in IGBT. It is sectional drawing which shows having formed the contact hole in IGBT. It is sectional drawing which shows having formed the silicide film | membrane etc. in IGBT. It is sectional drawing which shows having removed the gettering layer and doped polysilicon in IGBT. It is sectional drawing which shows having formed the buffer layer, collector layer, and electrode in IGBT. It is a graph which shows the relationship of ON voltage ( _VCE (sat)) and withstand pressure | voltage ( _BVCES ), and the carrier lifetime of a N _< ^- > drift layer. It is a graph which shows the relationship between the main junction leakage current (J _CES ) and the carrier lifetime of the N ⁻ drift layer. N ^- is a graph showing the carrier lifetime region where the carrier lifetime dependence is eliminated in V _{CE (sat)} to the thickness of the drift layer. It is a table | surface which shows the difference in the carrier lifetime by the presence or absence of a gettering layer formation process. ON voltage _(V CE _(sat)), the main junction leakage current _{(J CES),} and is a graph showing the doped polysilicon layer thickness dependence phosphorus loss at the turn-off time _{(E OFF).} Polysilicon doped with phosphorus having a value obtained by subtracting a threshold voltage (Vth) from a maximum gate voltage necessary for blocking in the short-circuit state of the IGBT (ΔVg (break)) and a maximum blocking energy (Esc) at the time of short-circuiting It is a graph which shows layer thickness dependence. It is a graph which shows the impurity density dependence of the polysilicon which doped the phosphorus to ON voltage ( _VCE (sat)) and the main junction leakage current ( _JCES ). 4 is a graph comparing output characteristics of a semiconductor device manufactured by the method of manufacturing a semiconductor device according to the first embodiment of the present invention and a semiconductor device of a comparative example. Is a graph showing the trade-off characteristic between the ON-state voltage _(V CE _(sat)) and turn-off loss _{(E OFF).} It is a J _C -V _CE characteristic of a plurality of semiconductor devices manufactured by a manufacturing method of a semiconductor device concerning Embodiment 1 of the present invention. It is a J _C -V _CE characteristic of a plurality of semiconductor devices manufactured with a manufacturing method of a semiconductor device of a comparative example. It is a J _CES- V _CES characteristic graph of a plurality of semiconductor devices manufactured by a manufacturing method of a semiconductor device concerning Embodiment 1 of the present invention. It is a J _CES -V _CES characteristic of a plurality of semiconductor devices manufactured with a manufacturing method of a semiconductor device of a comparative example. It is a table | surface which shows a response | compatibility with the electrical property in 6500V class IGBT, and a manufacturing method. It is a graph which shows the annealing time dependence in the annealing process after the polysilicon doped with phosphorus of V _CE (sat) and J _CES . It is sectional drawing which shows having formed the diffused layer in the board | substrate in a diode. It is sectional drawing which shows having formed the P anode layer in the active region in a diode. It is sectional drawing which shows having formed the N ^<+> layer, TEOS film | membrane, and doped polysilicon in the diode. It is sectional drawing which shows having formed the gettering layer in a diode. It is sectional drawing which shows having formed the metal wiring in a diode. It is sectional drawing which shows that the passivation film in the diode was formed and the gettering layer and the doped polysilicon were removed. It is sectional drawing which shows having formed the diffused layer and the electrode in the lower surface of the N < ^- > drift layer in a diode. It is a graph which compares the output characteristic of the diode manufactured with the manufacturing method of the semiconductor device concerning Embodiment 2 of the present invention, and the diode of a comparative example. Is a graph comparing the trade-off characteristics of the loss at the turn-off and turn-on voltage of the diode in the comparative example a diode and manufactured by the method according to the second embodiment _(VF) (E _REC). It is sectional drawing which shows the gettering layer formation process in the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention using IGBT as an example. 42 is a table showing a difference in carrier lifetime depending on the presence or absence of a gettering layer forming step shown in FIG. 4 is a graph showing the relationship between the power density of laser light when forming a gettering layer and the carrier lifetime (τ) of an N ⁻ drift layer 20.

  A semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

Embodiment 1 FIG.
FIG. 1 is a plan view of a semiconductor device according to Embodiment 1 of the present invention. The semiconductor device 10 has an active region 12 and an edge termination region 14 formed so as to surround the active region 12. 2 is a cross-sectional view taken along line II-II in FIG. An IGBT having a trench structure is formed as a semiconductor device. The semiconductor device has an N ⁻ drift layer 20. The impurity density of the N ⁻ drift layer 20 is, for example, one of 1.0 × 10 ^{12 to} 1.0 × 10 ¹⁵ [cm ⁻³ ].

An N-type buffer layer 22 is formed on the lower surface of the N ⁻ drift layer 20. A P-type collector layer 24 is formed on the lower surface of the buffer layer 22. An electrode 26 is formed on the lower surface of the collector layer 24.

An N layer 28 is formed on the upper surface of the N ⁻ drift layer 20. For example, the N layer 28 has a peak impurity density of 1.0 × 10 ^{15 to} 1.0 × 10 ¹⁷ [cm ⁻³ ] and a depth of 0.5 to 5.0 [μm]. is there. A P-type base layer 30 is formed on the upper surface of the N layer 28. For example, the P base layer 30 has a peak impurity density of 1.0 × 10 ^{16 to} 1.0 × 10 ¹⁸ [cm ⁻³ ], and the depth is deeper than the N ⁺ emitter layer 36 and shallower than the N layer 28. To form. A trench 37 in which polysilicon 32 is buried so as to penetrate the base layer 30 and the N layer 28 in the vertical direction is formed. Polysilicon 32 is in contact with N ⁻ drift layer 20, N layer 28, base layer 30, and N ⁺ emitter layer 36 through gate oxide film 34.

An N-type N ⁺ emitter layer is formed on the surface side of the base layer 30 so as to be in contact with the gate oxide film 34. The peak impurity density of the N ⁺ emitter layer 36 is, for example, one of 1.0 × 10 ^{18 to} 1.0 × 10 ²¹ [cm ⁻³ ], and the depth is approximately 0.2 to 1.0 [μm]. Either. A P ⁺ layer 38 is formed on the upper surface side of the P base layer 30. The impurity density on the surface of the P ⁺ layer 38 is, for example, one of 1.0 × 10 ^{18 to} 1.0 × 10 ²¹ [cm ⁻³ ]. A silicide film 39 is formed on the upper surfaces of the N ⁺ emitter layer 36 and the P ⁺ layer 38 (hereinafter, the N ⁺ emitter layer 36 and P ⁺ 38 may be referred to as a first diffusion layer). Further, a barrier metal 42 is formed on the polysilicon 32 through an oxide film 32 a and an oxide film 40. A metal wiring 44 is formed so as to be in contact with the silicide film 39.

Next, a method for manufacturing the semiconductor device according to the first embodiment of the present invention will be described. First, a silicon wafer formed by the FZ method (hereinafter, this silicon wafer or a silicon wafer subjected to processing is referred to as a substrate) is prepared. FIG. 3 is a cross-sectional view showing that the N layer 28 and the P base layer 30 are formed on the substrate on which the N ⁻ drift layer 20 is formed. The N ^- drift layer 20 is subjected to ion implantation and annealing to form an N layer 28 and a P base layer 30. Proceed to the next process. FIG. 4 is a cross-sectional view showing that an N ⁺ emitter is formed. The substrate is subjected to ion implantation and annealing to form a plurality of N ⁺ emitter layers 36 on the surface side of the P base layer 30.

  Proceed to the next process. FIG. 5 is a cross-sectional view showing that a trench is formed. An oxide film 31 is formed on the upper surface of the substrate and patterned using a photoengraving technique. Then, reactive ion etching using plasma is performed on the exposed portion of the oxide film 31 to form a trench 37. Thereafter, chemical dry etching and sacrificial oxidation are performed for the purpose of removing crystal defects and plasma damage layers around the trench 37, rounding the bottom of the trench 37, and flattening the inner wall of the trench 37. Chemical dry etching and sacrificial oxidation treatment are disclosed in, for example, Japanese Patent Application Laid-Open No. 7-263692. A suitable depth of the trench 37 is disclosed in, for example, International Publication No. 2009-122486.

  Proceed to the next process. FIG. 6 is a cross-sectional view showing that the trench 37 is filled with polysilicon 32 doped with phosphorus. A gate oxide film 34 is formed on the inner wall of the trench by a thermal oxidation method or a CVD method (see, for example, JP-A-2001-085686). Then, polysilicon 32 doped with phosphorus is formed so as to be in contact with the gate oxide film 34 to fill the trench. Note that an oxide film 50 is formed simultaneously with the formation of the gate oxide film 34 and a polysilicon 52 is formed simultaneously with the formation of the polysilicon 32 on the lower surface of the substrate.

Proceed to the next process. FIG. 7 is a cross-sectional view showing that the oxide film 40 and the TEOS film 41 are formed. First, the portion of the polysilicon 32 that has gone out of the trench 37 is etched. After the etching, the polysilicon 32 exposed on the upper surface of the substrate and the buried surface of the trench 37 is oxidized or deposited by a thermal oxidation method or a CVD method to form an oxide film 32a. Thereafter, a P ⁺ layer 38 is formed on the upper surface of the substrate. Thereafter, an oxide film 40 doped with boron or phosphorus and a TEOS film 41 are formed by a CVD method. A TEOS film or a silicate glass may be formed as the oxide film 40. A TEOS film 54 is formed on the lower surface of the substrate simultaneously with the formation of the oxide film 40 and the TEOS film 41.

Proceed to the next process. FIG. 8 is a cross-sectional view showing that the N ⁻ drift layer 20 on the lower surface of the substrate is exposed. The N ^- drift layer 20 is etched by etching the TEOS film 54, the polysilicon 52, and the oxide film 50 on the lower surface of the substrate using a liquid containing hydrofluoric acid or a mixed acid (for example, a mixed liquid of hydrofluoric acid, nitric acid, and acetic acid). To expose. In addition, each process so far is collectively called a manufacturing process.

Proceed to the next process. FIG. 9 is a cross-sectional view showing that polysilicon 60 and 62 doped with impurities are formed. A polysilicon 60 doped with impurities (hereinafter, the polysilicon doped with impurities is referred to as doped polysilicon) is formed so as to be in contact with the N ⁻ drift layer 20 exposed on the lower surface of the substrate. At this time, undesired doped polysilicon 62 is also formed on the upper surface of the substrate. The doped polysilicons 60 and 62 are formed by LPCVD. As an impurity doped into the doped polysilicon 60, 62, phosphorus, arsenic, antimony, or the like is used so that the doped polysilicon 60, 62 becomes an N ⁺ layer. The impurity density of doped polysilicon 60 and 62 is 1 × 10 ¹⁹ [cm ⁻³ ] or more. The layer thickness of doped polysilicon 60 and 62 is 500 [nm] or more.

Proceed to the next process. FIG. 10 is a cross-sectional view showing that the gettering layer 64 is formed. In a nitrogen atmosphere, the temperature of the substrate is heated to any one of 900 to 1000 [° C.] to diffuse impurities of doped polysilicon 60 to the lower surface side of N ⁻ drift layer 20. By this diffusion, a gettering layer 64 having crystal defects and high-concentration impurities is formed on the lower surface side of the N ⁻ drift layer 20. This process is referred to as a pretreatment annealing process. The process of forming doped polysilicon 60 and the pretreatment annealing process are collectively referred to as a gettering layer forming process. That is, the gettering layer forming step is a step of forming the gettering layer 64 on the lower surface side of the N ⁻ drift layer 20 exposed on the lower surface of the substrate. The surface impurity density of the gettering layer 64 is, for example, one of 1.0 × 10 ^{19 to} 1.0 × 10 ²² [cm ⁻³ ].

After the gettering layer forming step, the temperature of the substrate is lowered to any of 600 to 700 [° C.] at an arbitrary temperature lowering speed, and the temperature is maintained for 4 hours or more. This process is called an annealing process. In the annealing process, the substrate is heated, and metal impurities, contaminating atoms, and damage introduced into the N ⁻ drift layer 20 in the manufacturing process are diffused and captured by the gettering layer 64.

FIG. 11 is a graph showing the impurity density of the substrate after the pretreatment annealing step and the annealing step. Impurities are diffused from doped polysilicon 60 to N ⁻ drift layer 20 to form gettering layer 64 having an impurity density higher than that of N ⁻ drift layer 20. The maximum impurity density of the gettering layer 64 is about 1 × 10 ²⁰ [cm ⁻³ ].

  Proceed to the next process. FIG. 12 is a cross-sectional view showing that doped polysilicon 62 on the upper surface of the substrate has been removed. The doped polysilicon (doped polysilicon 62 in FIG. 10) on the upper surface of the substrate is selectively removed using a solution of hydrofluoric acid or mixed acid (for example, a mixed solution of hydrofluoric acid / nitric acid / acetic acid). Proceed to the next process. FIG. 13 is a cross-sectional view showing that a contact hole has been formed. On the upper surface side of the substrate, the oxide film 40 and the TEOS film 41 are partially etched to expose a part of the first diffusion layer to the outside to form a trench exposed portion 70 having a contact hole. A portion other than the trench exposed portion 70 is a MOSTr portion 72.

  As shown in FIG. 13, the purpose of partially forming a contact hole in the region where the trench 37 filled with the polysilicon 32 is formed is effective by setting a part of the polysilicon 32 as an emitter potential. And reducing the gate width and adjusting the capacitance. As a result, saturation current density suppression, oscillation suppression at the time of short-circuit by capacity control, short-circuit withstand capability improvement (for details, see International Publication Nos. 2002-058160 and 2002-061845), and low emitter-side carrier density improvement in on-state An on-voltage can be achieved.

  Proceed to the next process. FIG. 14 is a cross-sectional view showing that a silicide film or the like is formed. A silicide film 39 and a barrier metal 42 are formed on the upper surface of the substrate by sputtering and annealing. A refractory metal material such as Ti, Pt, Co or W is used as the metal during sputtering. Next, a metal wiring 44 doped with about 1 to 3% of Si is formed on the upper surface of the substrate by sputtering. The material of the metal wiring 44 is, for example, AlSi, AlSiCu, or AlCu. The metal wiring 44 is electrically connected to the first diffusion layer through a contact hole. Next, a passivation film is formed in the edge termination region.

Proceed to the next process. FIG. 15 is a cross-sectional view showing that the gettering layer and doped polysilicon are removed. The gettering layer 64 and the doped polysilicon 60 formed on the lower surface side of the substrate are removed by polishing or etching. The process of removing the gettering layer and the like in this way is referred to as a removal process. In the removing step, a portion of the N ⁻ drift layer 20 that contacts the gettering layer may be removed by a desired thickness. Thereby, the thickness of the substrate (N ⁻ drift layer 20) can be made to correspond to the breakdown voltage class of the semiconductor device.

Proceed to the next process. FIG. 16 is a cross-sectional view showing that the buffer layer 22, the collector layer 24, and the electrode 26 of the IGBT are formed. A buffer layer 22 is formed on the lower surface of the substrate. A P-type collector layer 24 is formed on the lower surface of the buffer layer 22. An electrode 26 is formed on the lower surface of the collector layer 24. The buffer layer 22 and the collector layer 24 that are diffusion layers formed on the lower surface side of the N ⁻ drift layer 20 are referred to as second diffusion layers. Finally, the electrode 26 is formed so as to be in contact with the collector layer 24 that is a part of the second diffusion layer. The electrode 26 is a portion that is soldered to a substrate or the like in the module when the semiconductor device is mounted on the module. Therefore, it is preferable that the electrode 26 is formed by stacking a plurality of metals to have a low contact resistance.

According to the method of manufacturing a semiconductor device according to the first embodiment of the present invention, the annealing step is performed after the gettering layer 64 is formed. Metal impurities, contaminating atoms, and damage introduced into the N ⁻ drift layer 20 in the manufacturing process in which the first diffusion layer is formed on the upper surface side of the substrate, formed, and subjected to the etching process are obtained in the annealing process. Captured by 64. The term “damage” as used herein refers to damage to the Si crystal due to thermal stress during thermal annealing, and damage to the Si crystal due to plasma in the plasma etching process. Thus, impurities and crystal defects in the gettering layer 64 become getter sites.

The crystal defects of the gettering layer 64 include high-density dislocations and lattice defects, which capture metal impurities such as heavy metals and contaminating atoms. Further, doped polysilicon 60 and N were used to form the gettering layer 64 ^- the difference in thermal expansion coefficients of the drift layer 20, the doped polysilicon 60 and the N ^- distortion on the surface and the drift layer 20 is in contact Arise. This distortion also functions as a getter site. With these effects, it is possible to recover the carrier lifetime of the N ⁻ drift layer 20 that has decreased due to external factors in the manufacturing process, the annealing process, and the plasma etching process.

Next, to what extent it is preferable to increase the carrier lifetime in order to stabilize the electrical characteristics of the semiconductor device (hereinafter simply referred to as characteristics) will be discussed. FIG. 17 is a graph showing the relationship between the on-voltage (V _CE (sat)) and breakdown voltage (BV _CES ) of the IGBT and the carrier lifetime of the N ⁻ drift layer 20. FIG. 18 is a graph showing the relationship between the main junction leakage current (J _CES ) and the carrier lifetime of the N ⁻ drift layer. FIGS. 17 and 18 show simulation results for a breakdown voltage class 6500 V class IGBT in which the layer thickness of the N ⁻ drift layer 20 is 650 [μm].

As can be seen from FIG. 17, if there is a carrier lifetime of 5.0E-04 [s] or more, V _CE (sat) can be stabilized against a slight variation in the carrier lifetime. Further, the value of BV _CES hardly depends on the carrier lifetime. As can be seen from FIG. 18, J _CES can be reduced as the carrier lifetime increases. The reduction of J _CES is effective for suppressing thermal runaway at a high temperature of, for example, 398K or higher. From the above, when the carrier lifetime of the N ⁻ drift layer 20 is approximately 5.0E-04 [s] or more, it is possible to suppress the carrier lifetime dependency of V _CE (sat) and to suppress J _CES .

The above-described simulation was performed on a plurality of IGBTs having various withstand voltage classes within the range of the withstand voltage class 600 to 6500 V class. That is, for example, in the case of the withstand voltage class 600 [V], the layer thickness of the N ⁻ drift layer is 60 [μm], and in the case of the withstand voltage class 6500 [V], the layer thickness of the N ⁻ drift layer is 6500 [μm]. The simulation was performed while changing the thickness of the N ⁻ drift layer within a range of 60 to 6500 [μm]. Then, N ^- layer by layer thickness of the drift layer, was calculated carrier lifetime can be suppressed carrier lifetime dependence of V _{CE (sat).} FIG. 19 is a graph plotting the carrier lifetime that can suppress the carrier lifetime dependency of V _CE (sat). For example, when the thickness of the N ⁻ drift layer is 400 [μm], V _CE (sat) can be stabilized by setting the carrier lifetime to 1.1 × 10 ⁻⁴ [sec] or more. The carrier lifetime in the “device characteristic stabilization region” in FIG.

In FIG. 19, Formula 2 is represented by a straight line. By ensuring a carrier lifetime higher than the carrier lifetime defined by this straight line, the carrier lifetime dependency of V _CE (sat) can be suppressed and the device characteristics can be stabilized. On the other hand, the carrier lifetime dependency of V _CE (sat) cannot be suppressed at a carrier lifetime lower than the carrier lifetime defined by this straight line. This region is called a device characteristic instability region. The carrier lifetime in the N ⁻ drift layer 20 according to the first embodiment of the present invention satisfies Equation 2 and belongs to the device characteristic stabilization region. Therefore, according to the method for manufacturing a semiconductor device according to the first embodiment of the present invention, variations due to carrier lifetime due to carrier lifetime characteristics can be suppressed.

  FIG. 20 is a table showing the difference in carrier lifetime depending on the presence or absence of the gettering layer forming step. The comparative example of FIG. 20 is different from the semiconductor device according to the first embodiment of the present invention only in that the formation of doped polysilicon 60 and 62 in the process of FIGS. Different (same below). In the comparative example and the first embodiment of the present invention, there is no difference in processing content until “etching of the lower surface of the wafer” corresponding to the step shown in FIG. 8, so the carrier lifetime in “after etching of the lower surface of the wafer” is the same. Yes. However, the carrier lifetime after the annealing process is greatly improved in the first embodiment of the present invention, whereas the improvement effect is not seen in the comparative example. Therefore, it can be understood that the carrier lifetime can be improved by the gettering of the gettering layer.

FIG. 21 is a graph showing the dependence of V _CE (sat), J _CES , and loss at turn-off (E _OFF (sat)) on the doped polysilicon layer thickness. FIG. 22 shows the dependence of the maximum gate voltage necessary for breaking the short circuit state of the IGBT on the doped polysilicon layer thickness of the value ΔVg (break) obtained by subtracting the threshold voltage and the maximum cutoff energy Esc at the time of the short circuit. It is a graph to show. ΔVg (break) is calculated by “Vg (break) −V _GE (th)”. Here, Vg (break) is the maximum gate voltage (Vg) value necessary for interrupting the short-circuit state, and V _GE (th) is a gate voltage necessary for forming a channel in the MOS channel portion of the IGBT. (Threshold voltage). The data in the graphs shown in FIGS. 21 and 21 are obtained for an IGBT having an impurity density of doped polysilicon of 1 × 10 ¹⁹ [cm ⁻³ ] or more and a withstand voltage class of 4500V.

21 and 22, it can be seen that the thicker the doped polysilicon, the better the characteristics. FIG. 21 shows that V _CE (sat), J _CES , and E _OFF can be lowered as the doped polysilicon is thicker. Further, FIG. 22 shows that the thicker the doped polysilicon, the better the characteristics when the IGBT is short-circuited. This result means that the thicker the doped polysilicon, the higher the gettering effect and the longer the carrier lifetime. If the layer thickness of the doped polysilicon is 500 [nm] or more, good characteristics can be obtained, and the stability in film thickness control is high.

FIG. 23 is a graph showing the dependency of V _CE (sat) and J _CES on the impurity density of doped polysilicon. This graph relates to a semiconductor device having a breakdown voltage class of 4500 V, which is formed by forming 500 [nm] doped polysilicon. From FIG. 23, when the impurity density of doped polysilicon is 1 × 10 ¹⁹ [cm ⁻³ ] or more, V _CE (sat) and J _CES can be lowered.

FIG. 24 is a graph comparing the output characteristics of the IGBT manufactured by the semiconductor device manufacturing method according to the first embodiment of the present invention and the IGBT of the comparative example. Here, a semiconductor device having a withstand voltage class of 4500 V was evaluated. N of Comparative Example ^- carrier lifetime in the drift layer N of the present invention ^- is shorter than the carrier lifetime in the drift layer, the output characteristic of the comparative example is sleep waveform, and the values which the current density (Jc) is saturated Low. That is, the IGBT MOS transistor characteristics are degraded. From FIG. 24, it can be seen that the carrier lifetime of the N ⁻ drift layer has a great influence on the output characteristics, and that the output characteristics can be improved by the method of manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 25 is a graph showing a trade-off characteristic between V _CE (sat) and E _OFF (sat), which is an index of the basic performance of the IGBT. V _CE (sat) is the V _CE value at the rated current density in FIG. 24 (“ratedJc” in the figure). The withstand voltage class of the evaluated IGBT is 4500V. From FIG. 25, it can be seen that the trade-off characteristics can be significantly improved in the IGBT of the present invention having a long carrier lifetime as compared with the IGBT of the comparative example having a short carrier lifetime.

26 is a graph of output characteristics (J _C vs. V _CE characteristics) of a plurality of IGBTs manufactured by the method for manufacturing a semiconductor device according to the first embodiment of the present invention. A plurality of IGBTs were formed in one wafer surface. FIG. 27 is a graph of output characteristics of a plurality of IGBTs manufactured by the IGBT manufacturing method of the comparative example. Obviously, the IGBT manufactured by the method of manufacturing a semiconductor device according to the first embodiment of the present invention can improve the variation in output characteristics, and the characteristics are stable.

FIG. 28 is a graph of J _CES- V _CES characteristics of a plurality of IGBTs manufactured by the method for manufacturing a semiconductor device according to the first embodiment of the present invention. A plurality of IGBTs were formed in one wafer surface. FIG. 29 is a graph of J _CES- V _CES characteristics of a plurality of IGBTs manufactured by a method for manufacturing a semiconductor device of a comparative example. Comparing FIG. 28 and FIG. 29, it can be seen that by using the semiconductor device manufacturing method according to the first embodiment of the present invention, J _CES can be reduced by an order of magnitude and in-plane variation can be reduced as compared with the comparative example. . That is, the characteristics of the IGBT are stabilized by the effect of the present invention.

  FIG. 30 is a table showing the correspondence between the electrical characteristics and the manufacturing method in the IGBT whose breakdown voltage class is 6500V. The additional comparative example in FIG. 30 indicates a structure in which doped polysilicon is formed on the lower surface of the substrate and the annealing process is performed after the structure of FIG. 3 is formed. That is, the additional comparative example indicates a semiconductor device manufactured by performing a gettering layer forming step and an annealing step before completing the “manufacturing step”. 30 that the effect of improving the characteristics is high when the gettering layer forming step and the annealing step are performed after the manufacturing process is performed as in the semiconductor manufacturing apparatus according to the first embodiment of the present invention. In other words, it is preferable to perform a gettering layer forming step and an annealing step before forming the contact hole.

FIG. 31 is a graph showing the dependency of V _CE (sat) and J _{CES on} the annealing time in the annealing process. The annealing process was performed in a nitrogen atmosphere while maintaining the substrate temperature at any of 600 to 700 [° C.]. From FIG. 31, V _CE (sat) and J _CES are sufficiently lowered and stabilized in an annealing time of 4 hours or more. That is, in the annealing step, it is preferable to keep any substrate temperature of 600 to 700 [° C.] for 4 hours or more in a nitrogen atmosphere.

By the way, when a wafer formed by the CZ method is used, there is a problem that the cost is high because the N ⁻ drift layer is generally formed by an epitaxial growth method. For example, N of if 600V class 50-60 [nm] ^- forming a drift layer, if 6500V class of about 500~600 [nm] N ^- because it forms a drift layer, N ^- the need to form a thick drift layer The cost of a certain high voltage semiconductor device increases.

Therefore, it is preferable to use a substrate formed by the FZ method. Since the substrate formed by the FZ method has a desired thickness by thinning the N ⁻ drift layer, the cost of the substrate does not vary depending on the breakdown voltage class. However, a substrate formed by the FZ method has a low self-gettering ability (IG), and the effect of well-known EG (Extrinsic Gettering) is also low. Therefore, when a substrate formed by the FZ method is used for a bipolar semiconductor device such as an IGBT or a diode, the carrier lifetime of the N ⁻ drift layer is lowered. In order to avoid this, as shown in the method for manufacturing a semiconductor device according to the first embodiment of the present invention, metal impurities and the like in the N ⁻ drift layer are captured by the gettering layer. Then, a semiconductor device can be manufactured on a substrate formed by the FZ method at low cost, and the carrier lifetime of the N ⁻ drift layer can be controlled to be long, so that the on-state loss can be reduced. Such an effect can be obtained not only when the substrate is formed by the FZ method but also when an epi-wafer is used, for example.

The semiconductor device manufacturing method according to the first embodiment of the present invention includes a gettering layer forming step after a manufacturing step for forming an emitter, a base, and a trench constituting the surface structure of the IGBT and before a contact hole is formed. By performing the annealing process, the carrier lifetime of the N ⁻ drift layer 20 is lengthened. Various modifications are possible without departing from this characteristic. For example, a removal step of removing the doped polysilicon 60 and the gettering layer 64 may be performed immediately after performing the gettering layer forming step and the annealing step.

  Although the substrate according to Embodiment 1 of the present invention is formed of silicon, it may be formed of a wide band gap semiconductor having a larger band gap than silicon. Examples of the wide band gap semiconductor include silicon carbide, a gallium nitride-based material, and diamond. Further, the conductivity type of each part of the semiconductor element may be appropriately reversed.

Embodiment 2. FIG.
The semiconductor device manufacturing method according to the second embodiment of the present invention is obtained by applying the semiconductor device manufacturing method according to the first embodiment to a diode. Hereinafter, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described. FIG. 32 is a cross-sectional view showing that a diffusion layer is formed on the substrate. FIG. 32 shows an active region Ra and an edge termination region Re formed so as to surround the active region Ra. First, a substrate on which only the N ⁻ drift layer 100 is formed is prepared. The impurity density of the substrate is set according to the breakdown voltage class. For example, if the breakdown voltage class is any one of 600 to 6500 [V], the impurity density of the substrate is any one of 1.0 × 10 ^{12 to} 1.0 × 10 ¹⁵ [cm ⁻³ ].

A plurality of P layers 102 are formed in the edge termination region Re. The P layer 102 is formed by ion implantation using the previously formed insulating films 104 and 106 as a mask, and then annealing the substrate. The surface concentration of the P layer 102 is, for example, one of 1.0 × 10 ^{16 to} 1.0 × 10 ¹⁸ [cm ⁻³ ]. An undesired oxide film 108 is also formed on the lower surface of the substrate.

Proceed to the next process. FIG. 33 is a cross-sectional view showing that the P anode layer 110 is formed in the active region. The active region Ra is subjected to ion implantation and annealing to form the P anode layer 110. The surface concentration of the P anode layer 110 is, for example, one of 1.0 × 10 ^{16 to} 1.0 × 10 ¹⁸ [cm ⁻³ ]. In the second embodiment of the present invention, the “first diffusion layer” formed on the upper surface side of the substrate is the P layer 102 and the P anode layer 110.

Proceed to the next process. FIG. 34 is a cross-sectional view showing that an N ⁺ layer, a TEOS film, and doped polysilicon are formed. An N ⁺ layer 120 is formed at the end of the edge termination region Re on the upper surface side of the substrate. The surface concentration of the N ⁺ layer 120 is, for example, one of 1.0 × 10 ^{18 to} 1.0 × 10 ²¹ [cm ⁻³ ]. The depth is, for example, any one of 0.2 to 10.0 [μm]. Next, a TEOS film 122 is formed on the upper surface of the substrate. The TEOS film 122 may be configured like the oxide film 40 and the TEOS film 41 in FIG. Thereafter, the oxide film 108 on the lower surface of the substrate is removed. Then, doped polysilicon 130 doped with impurities is formed in contact with the N ⁻ drift layer 100 exposed on the lower surface of the substrate. At this time, doped polysilicon 132 is also formed on the upper surface of the substrate.

Proceed to the next process. FIG. 35 is a cross-sectional view showing that a gettering layer is formed. Impurities doped polysilicon 130 by heating the substrate N ^- diffuse to the lower side of the drift layer 100, N ^- forming a gettering layer 150 having a crystal defect and impurity on the lower surface side of the drift layer 100. This step is the same as the pretreatment annealing step of the first embodiment. Thereafter, an annealing process is performed to capture metal impurities, contaminating atoms, and damage in the N ⁻ drift layer 100 by the gettering layer 150.

  Proceed to the next process. FIG. 36 is a cross-sectional view showing that a metal wiring is formed. First, contact holes for exposing the P layer 102 and the P anode layer 110 are formed on the upper surface of the substrate. That is, the TEOS film 122 is processed as shown in FIG. Thereafter, an aluminum wiring 152 to which Si is added by about 1 to 3% is formed by a sputtering method.

Proceed to the next process. FIG. 37 is a cross-sectional view showing that a passivation film is formed and the gettering layer and doped polysilicon are removed. A passivation film 154 is formed on the upper surface of the substrate. Thereafter, the gettering layer 150 and the doped polysilicon 130 formed on the lower surface side of the substrate are removed by polishing or etching. The processing content of this step is the same as the removal step of the first embodiment. By the removing step, the thickness of the substrate (N ⁻ drift layer) is made to correspond to the breakdown voltage class of the semiconductor device.

Proceed to the next process. FIG. 38 is a cross-sectional view showing that a diffusion layer and an electrode are formed on the lower surface of the N ⁻ drift layer. N layer 160 is formed on the lower surface side of N ⁻ drift layer 100. The surface concentration of the N layer 160 (concentration of the lower surface portion of the N layer 160) is, for example, one of 1.0 × 10 ^{15 to} 1.0 × 10 ¹⁸ [cm ⁻³ ]. A P layer 162 is formed on the lower surface of the N layer 160. The surface concentration of the P layer 162 (the concentration of the lower surface portion of the P layer 162) is, for example, one of 1.0 × 10 ^{16 to} 1.0 × 10 ²⁰ [cm ⁻³ ].

An N ⁺ layer 164 is formed on part of the P layer 162. The surface concentration of the N ⁺ layer 164 is, for example, one of 1.0 × 10 ^{19 to} 1.0 × 10 ²¹ [cm ⁻³ ]. The N layer 160, the P layer 162, and the N ⁺ layer 164 are diffusion layers formed by ion implantation and annealing. Finally, an electrode 166 is formed on the lower surface of the substrate. In the second embodiment of the present invention, the “second diffusion layer” formed on the lower surface side of the substrate is the N layer 160, the P layer 162, and the N ⁺ layer 164. The significance of forming these layers is disclosed in JP 2010-283131 A and JP 2012-9811 A.

According to the method for manufacturing a semiconductor device according to the second embodiment of the present invention, the carrier lifetime of the N ⁻ drift layer can be increased, and therefore the characteristics of the diode can be improved. FIG. 39 is a graph comparing the output characteristics of the diode manufactured by the semiconductor device manufacturing method according to the second embodiment of the present invention and the diode of the comparative example. The withstand voltage class of the evaluated diode is 3300V. In both the measurement at 298 [K] and the measurement at 398 [K], the diode using the semiconductor device manufacturing method of the second embodiment of the present invention shows better results.

FIG. 40 compares the trade-off characteristics of the on-voltage (V _F ) and the loss at turn-off (E _REC ) of the diode manufactured by the semiconductor device manufacturing method according to the second embodiment of the present invention and the diode of the comparative example. It is a graph. ON voltage _{(V F)} is that of the _{V AK when J A} is RatedJ _A in FIG. 39. N ^- carrier lifetime longer low _{V F} and high _{E REC} next to the drift layer, N ^- the carrier lifetime of the drift layer is short and high _{V F} and low _{E REC.} As it can be seen from FIG. 40, a low V _F and higher E _REC than Comparative Example According to the diode according to a second embodiment of the present invention. Therefore, the diode according to the second embodiment of the present invention can increase the carrier lifetime of the N ⁻ drift layer and improve the characteristics of the diode as compared to the diode of the comparative example.

Incidentally, as in the first embodiment, the gettering layer forming step and the annealing step in the method for manufacturing a semiconductor device according to a second embodiment of the present invention is carried out after the production process, N ^- drift layer metal impurities, contamination atom It is preferable to capture the damage by a gettering layer. The manufacturing process in the case of manufacturing a diode is a process of forming the P anode layer 110 and the insulating films 104 and 106 constituting the surface structure of the diode. The semiconductor device and the manufacturing method thereof according to the second embodiment of the present invention can be modified at least as much as the first embodiment.

Embodiment 3 FIG.
The semiconductor device manufacturing method according to the third embodiment of the present invention is obtained by changing the processing content of the gettering layer forming step in the semiconductor device manufacturing method according to the first embodiment. FIG. 41 is a cross-sectional view showing a gettering layer forming step in the method for manufacturing a semiconductor device according to the third embodiment of the present invention. In this gettering layer forming step, the N ⁻ drift layer 20 exposed on the lower surface of the substrate is heated to form a gettering layer 200 having crystal defects on the lower surface side of the N ⁻ drift layer 20. For heating the N ⁻ drift layer 20, it is preferable to use a laser annealing technique using laser light emitted from the laser light source 202. The power of the laser beam is preferably 4.0 [J / cm ² ] or more. The wavelength of the laser light is, for example, any of 500 to 1000 [nm].

According to the method of manufacturing a semiconductor device according to the third embodiment of the present invention, the gettering layer 200 can be easily formed simply by heating the lower surface of the N ⁻ drift layer 20. FIG. 42 is a table showing the difference in carrier lifetime depending on the presence or absence of the gettering layer forming step. In the third embodiment and the comparative example, the carrier lifetime is almost the same immediately after “etching of the lower surface of the wafer”. However, after the annealing process, the carrier lifetime is longer in the third embodiment than in the comparative example. The reason why the carrier lifetime can be increased is that the gettering layer 200 functions as a getter site.

FIG. 43 is a graph showing the relationship between the laser beam power density and the carrier lifetime (τ) of the N ⁻ drift layer 20 when the gettering layer is formed. Δτ in the figure indicates the amount of change in τ before and after the laser annealing process and the annealing process. From FIG. 43, it is understood that the effect of improving the carrier lifetime by laser annealing can be stably obtained by setting the power density of laser annealing to 4 [J / cm ² ] or more.

  The semiconductor device and the manufacturing method thereof according to the third embodiment of the present invention can be modified at least as much as the first embodiment. Further, the features of the semiconductor device according to each embodiment may be combined as appropriate.

10 semiconductor device, 12 active region, 14 edge termination region, 20 N ^- drift layer, 22 buffer layer, 24 collector layer, 26 electrode, 28 N layer, 30 base layer, 31 oxide film, 32 polysilicon, 32a oxide film, 34 gate oxide film, 36 N ⁺ emitter layer, 37 trench, 38 P ⁺ layer, 39 silicide film, 40 oxide film, 41 TEOS film, 42 barrier metal, 44 metal wiring, 60, 62 doped polysilicon, 64 gettering Layer, 100 N ^- drift layer, 102 P layer, 104, 106, 108 oxide film, 110 anode layer, 120 N ⁺ layer, 122 TEOS film, 130, 132 doped polysilicon, 150 gettering layer, 152 aluminum wiring, 154 Passivation film, 166 electrode, 2 00 Gettering layer, 202 Laser light source

Claims (4)

A drift layer formed in the active region of the substrate;
A MOS structure formed on the upper surface side of the drift layer and having a trench gate;
A buffer layer in contact with the lower surface of the drift layer;
A collector layer in contact with the lower surface of the buffer layer,
The carrier lifetime in the drift layer satisfies the following Equation 1 when the carrier lifetime in the drift layer is τ [sec] and the thickness of the drift layer is t _N− [m]. A semiconductor device.

  The semiconductor device according to claim 1, wherein the MOS structure includes an emitter, a base, and a gate trench that form a surface structure of the IGBT. An active region formed in the substrate;
An edge termination region provided in contact with the active region on the substrate;
A drift layer provided in the active region and the edge termination region;
An anode layer formed on the upper surface side of the drift layer in the active region;
An n-type N layer in contact with the lower surface of the drift layer of the active region and the edge termination region;
An N ⁺ layer in contact with the lower surface of the N layer in the active region and having a higher n-type impurity concentration than the N layer;
A p layer in contact with the lower surface of the N layer in the active region, adjacent to the N ⁺ layer, and in contact with the lower surface of the N layer in the edge termination region;
The carrier lifetime in the drift layer satisfies the following Equation 2 when the carrier lifetime in the drift layer is τ [sec] and the thickness of the drift layer is t _N− [m]. A semiconductor device.

An electrode in contact with the lower surface of the N ⁺ layer and the p layer;
The semiconductor device according to claim 3, wherein the semiconductor device is a diode.

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