JP2018116972A - Electronic circuit device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress deterioration of a frequency characteristic of a signal transfer .SOLUTION: An electronic circuit device 1 comprises: a first semiconductor chip 11; a second semiconductor chip 21 adjacent to the first semiconductor chip; and a first substrate 31 which is arranged on a part opposite to a surface in which a circuit of the first semiconductor chip 11 is formed and a part opposite to the surface in which the circuit of the second semiconductor chip 21 is formed. The part opposite to the second semiconductor chip 21 of an outer periphery of the first semiconductor chip 11 is thinner than the thickness of a central part of the first semiconductor chip 11. A first penetration electrode 14 reaching a circuit 13 of the first semiconductor chip from the surface opposite to the surface of the first semiconductor chip 11 is formed in the thin part of the first semiconductor chip. A substrate 31 overlaps with the thin part of the first semiconductor chip 11. One end of a wiring 32 provided in the substrate 31 is connected to the first penetration electrode 14. The other end of the wiring is connected to a second penetration electrode 24 reaching circuit 23 of the second semiconductor 21 from the surface opposite to the second semiconductor chip 21.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an electronic circuit device and a method for manufacturing the electronic circuit device.

As a method of connecting a plurality of large scale integration (LSI) chips, a plurality of L
A method is known in which SI chips are stacked in a three-dimensional direction and the LSI chips are connected by through electrodes or the like. When stacking LSI chips with large power consumption, there is a problem that it is difficult to ensure heat dissipation characteristics and power supply quality. When a plurality of LSI chips are mounted side by side on a printed circuit board such as an organic substrate, wiring formed on the printed circuit board is used for signal connection between the LSI chips.

However, since the miniaturization of wiring that can be formed on the printed circuit board is limited, a sufficient number of wirings may not be formed on the printed circuit board. Therefore, a method is known in which a silicon substrate (silicon interposer) is sandwiched between an LSI chip and a printed board, and signal connection between LSI chips is performed by fine wiring formed on the silicon substrate. A through-electrode such as Through Silicon Via (TSV) formed on a silicon substrate is used for conduction between the LSI chip and the lower printed circuit board for grounding, power supply, and signal lines. Therefore, when mounting a plurality of LSI chips on a silicon substrate, it is used for the TSV area that is necessary as a secondary, and between LSI chips, in addition to the part necessary for high-density wiring connection between adjacent LSI chips. The part which is not present also exists in the silicon substrate. For this reason, an expensive silicon substrate on which TSVs or fine wirings are formed has a lot of useless area. When a large LSI chip is mounted or a large number of LSI chips are connected, the silicon substrate is also enlarged and wasted. The area becomes prominent.

JP 2004-228142 A Special table 2011-527113 gazette Japanese Unexamined Patent Publication No. 2016-21565

  In order to facilitate the handling of the LSI chip, it is preferable that the thickness of the LSI chip is several hundred μm. However, as the thickness of the LSI chip increases, the through electrode that penetrates the LSI chip also increases. For connection between two LSI chips, a through electrode is passed through each LSI chip once. By forming a thin insulating film such as an oxide film between the through electrode and the silicon substrate, the through electrode and the non-insulating silicon substrate are insulated, so that the through electrode has a parasitic capacitance component. When the through electrode is long, the parasitic capacitance load of the through electrode is increased, which causes a problem that the frequency characteristic of signal transmission is deteriorated and the power consumption is increased. Further, Patent Document 1 describes a method in which the front and back sides of adjacent LSI chips are reversed and connected to each other. In this case, the surface on which the circuit of one connected LSI chip is formed faces upward. The connection between the circuit of the LSI chip and the printed board cannot be provided at the shortest distance, the signal transmission characteristics of the connection with the printed board are deteriorated, and it is difficult to form the connection at a high density.

  An object of this application is to provide the technique which suppresses the deterioration of the frequency characteristic of signal transmission.

  In one aspect, an electronic circuit device includes a first semiconductor chip, a second semiconductor chip disposed adjacent to the first semiconductor chip, and a surface opposite to a surface on which a circuit of the first semiconductor chip is formed. And a first substrate disposed on a part of the surface opposite to the surface on which the circuit of the second semiconductor chip is formed, and the second of the outer peripheral portions of the first semiconductor chip. The portion facing the semiconductor chip has a portion thinner than the thickness of the central portion of the first semiconductor chip, and the first through electrode reaches the circuit of the first semiconductor chip from the opposite surface of the first semiconductor chip. Is formed in the thin portion of the first semiconductor chip, the first substrate overlaps the thin portion of the first semiconductor chip, and one end of the wiring provided on the first substrate is the Connected to first through electrode And, the other end of the wiring is connected to the second through electrode extending from the opposite surface of the second semiconductor chip to the circuit of the second semiconductor chip.

  In one aspect, the method of manufacturing an electronic circuit device includes a first semiconductor chip having a portion thinner than a thickness of a central portion of the first semiconductor chip in an outer peripheral portion of the first semiconductor chip opposed to the second semiconductor chip. Disposing a chip and the second semiconductor chip; and on the thin portion of the first semiconductor chip, on a surface opposite to a surface on which the circuit of the first semiconductor chip is formed, and on the second semiconductor chip. A step of disposing a substrate on a surface opposite to the surface on which the circuit is formed, a first through electrode extending from the opposite surface of the first semiconductor chip to the circuit of the first semiconductor chip, and the substrate. Bonding one end of the interconnect and connecting the second through electrode reaching the circuit of the second semiconductor chip from the opposite surface of the second semiconductor chip and the other end of the interconnect. Preparation That.

  ADVANTAGE OF THE INVENTION According to this invention, the technique which suppresses deterioration of the frequency characteristic of signal transmission can be provided.

FIG. 1 is a cross-sectional view of the electronic circuit device according to the first embodiment. FIG. 2 is a cross-sectional view of the electronic circuit device according to the first embodiment. FIG. 3 is a cross-sectional view of the electronic circuit device according to the first embodiment. FIG. 4A is a cross-sectional view of the electronic circuit device according to the first embodiment. FIG. 4B is a cross-sectional view of the electronic circuit device according to the first embodiment. FIG. 5A is a cross-sectional view of the electronic circuit device according to the second embodiment. FIG. 5B is a cross-sectional view of the electronic circuit device according to the second embodiment. FIG. 6 is a cross-sectional view of the electronic circuit device according to the third embodiment. FIG. 7 is a plan view showing an example of the electronic circuit device according to the first to third embodiments. FIG. 8 is a plan view illustrating an example of the electronic circuit device according to the first to third embodiments. FIG. 9 is a plan view illustrating an example of the electronic circuit device according to the first to third embodiments. FIG. 10A is a plan view illustrating an example of an electronic circuit device according to the first to third embodiments. FIG. 10B is a plan view illustrating an example of the electronic circuit device according to the first to third embodiments. FIG. 11 is a process diagram of a method for manufacturing an electronic circuit device. FIG. 12 is a process diagram of a method for manufacturing an electronic circuit device. FIG. 13 is a process diagram of a method for manufacturing an electronic circuit device. FIG. 14 is a process diagram of a method for manufacturing an electronic circuit device. FIG. 15 is a process diagram of a method for manufacturing an electronic circuit device. FIG. 16 is a process diagram of a method for manufacturing an electronic circuit device. FIG. 17 is a process diagram of a method for manufacturing an electronic circuit device. FIG. 18 is a process diagram of a method for manufacturing an electronic circuit device.

  Hereinafter, embodiments will be described in detail with reference to the drawings. The configurations of the following embodiments are examples, and the present invention is not limited to the configurations of the embodiments. Moreover, you may combine each embodiment suitably.

<First Embodiment>
A first embodiment will be described. FIG. 1 is a cross-sectional view of an electronic circuit device 1 according to the first embodiment. The electronic circuit device 1 is mounted on a printed circuit board (wiring board) 3 via a plurality of connection electrodes 2A and 2B. The electronic circuit device 1 includes semiconductor chips 11 and 21 and a bridge substrate 31. The semiconductor chip 11 and the semiconductor chip 21 are disposed adjacent to each other. The bridge substrate 31 is disposed on a part of the semiconductor chip 11 and on a part of the semiconductor chip 21. The semiconductor chips 11 and 21 are, for example, LSI chips. The LSI chip may be, for example, a logic chip or a memory chip, or may be a system LSI chip in which a logic chip and a memory chip are mixedly mounted. The semiconductor chip 11 includes a semiconductor substrate 12 and a circuit 13 formed on the semiconductor substrate 12. The semiconductor chip 21 includes a semiconductor substrate 22 and a circuit 23 formed on the semiconductor substrate 22. The semiconductor substrates 12 and 22 are, for example, silicon (Si) substrates. The semiconductor chip 11 is an example of a first semiconductor chip. The semiconductor chip 21 is an example of a second semiconductor chip. The bridge substrate 31 is an example of a first substrate.

  The semiconductor chips 11 and 21 are flip-chip bonded to the printed circuit board 3. The electrodes formed on the circuit 13 of the semiconductor chip 11 and the printed circuit board with the surface of the semiconductor chip 11 on which the circuit 13 is formed (hereinafter referred to as the circuit surface of the semiconductor chip 11) facing the printed circuit board 3 (face down). 3 is joined to the connection electrode 2 </ b> A formed in 3. The connection electrode 2 </ b> A is provided between the semiconductor chip 11 and the printed board 3 and is used for connecting the semiconductor chip 11 and the printed board 3. With the surface of the semiconductor chip 21 on which the circuit 23 is formed (hereinafter referred to as the circuit surface of the semiconductor chip 21) facing the printed circuit board 3, the electrode formed on the circuit 23 of the semiconductor chip 21 and the printed circuit board 3 are formed. The connection electrode 2B is joined. The connection electrode 2 </ b> B is provided between the semiconductor chip 21 and the printed board 3 and is used for connecting the semiconductor chip 21 and the printed board 3. An underfill 4 may be formed between the semiconductor chips 11 and 21 and the printed circuit board 3.

  The semiconductor chip 11 has a thick part and a thin part. The entire thickness of the outer peripheral portion of the semiconductor chip 11 may be thinner than the thickness of the central portion of the semiconductor chip 11. The thickness of a part of the outer peripheral portion of the semiconductor chip 11 may be thinner than the thickness of the central portion of the semiconductor chip 11. The thickness of the outer peripheral portion of the semiconductor chip 11 facing the semiconductor chip 21 may be thinner than the thickness of the central portion of the semiconductor chip 11. Therefore, at least a part of the outer peripheral portion of the semiconductor chip 11 has a protruding portion (thin portion) protruding from the main body (thick portion) of the semiconductor chip 11. The thickness of the thick portion of the semiconductor chip 11 is several hundred microns, for example, and the thickness of the thin portion of the semiconductor chip 11 is several tens of microns, for example. The length of the thin portion of the semiconductor chip 11 in the planar direction is, for example, several hundred μm to several mm. By ensuring the thickness of the thick part of the semiconductor chip 11 and by setting the length of the thin part of the semiconductor chip 11 in the planar direction to a predetermined length, the strength of the semiconductor chip 11 can be ensured. Warping is suppressed.

  The semiconductor chip 11 has a plurality of through electrodes (vias) 14. The through electrode 14 is formed in a thin portion of the semiconductor chip 11 and reaches the circuit 13 of the semiconductor chip 11 from the opposite surface (non-circuit surface) of the circuit surface of the semiconductor chip 11. The through electrode 14 is connected to a wiring included in the circuit 13. Accordingly, the through electrode 14 is connected to the wiring of the circuit 13 through the inside of the semiconductor chip 11 (semiconductor substrate 12). A plurality of coupling electrodes 15 are formed on the surface opposite to the circuit surface of the semiconductor chip 11. The through electrode 14 is exposed from the surface opposite to the circuit surface of the semiconductor chip 11 in the thin portion of the semiconductor chip 11. The coupling electrode 15 is connected to the through electrode 14. The length of the through electrode 14 is approximately the same as the thickness of the semiconductor chip 11 and is, for example, several tens of microns. Compared with the case where the through electrode 14 is formed in the thick part of the semiconductor chip 11, the length of the through electrode 14 formed in the thin part of the semiconductor chip 11 is short, so that the capacity of the through electrode 14 can be reduced. Therefore, a decrease in frequency characteristics of signal transmission using the through electrode 14 is suppressed, and the power consumption of the semiconductor chip 11 can be reduced.

  The semiconductor chip 21 has a thick part and a thin part. The total thickness of the outer peripheral portion of the semiconductor chip 21 may be thinner than the thickness of the central portion of the semiconductor chip 21. The thickness of a part of the outer peripheral portion of the semiconductor chip 21 may be thinner than the thickness of the central portion of the semiconductor chip 21. The thickness of the outer peripheral portion of the semiconductor chip 21 facing the semiconductor chip 11 may be thinner than the thickness of the central portion of the semiconductor chip 21. Therefore, at least a part of the outer peripheral portion of the semiconductor chip 21 has a protruding portion (thin portion) protruding from the main body (thick portion) of the semiconductor chip 21. The thickness of the thick portion of the semiconductor chip 21 is several hundred microns, for example, and the thickness of the thin portion of the semiconductor chip 21 is several tens of microns, for example. The length of the thin portion of the semiconductor chip 21 in the planar direction is, for example, several hundred μm to several mm. By ensuring the thickness of the thick part of the semiconductor chip 21 and by setting the length of the thin part of the semiconductor chip 21 in the planar direction to a predetermined length, the strength of the semiconductor chip 21 can be ensured. Warping is suppressed.

  The semiconductor chip 21 has a plurality of through electrodes (vias) 24. The through electrode 24 is formed in a thin portion of the semiconductor chip 21 and reaches the circuit 23 of the semiconductor chip 21 from the opposite surface (non-circuit surface) of the circuit surface of the semiconductor chip 21. The through electrode 24 is connected to a wiring included in the circuit 23. Accordingly, the through electrode 24 is connected to the wiring of the circuit 23 through the inside of the semiconductor chip 21 (semiconductor substrate 22). A plurality of coupling electrodes 25 are formed on the surface opposite to the circuit surface of the semiconductor chip 21. The through electrode 24 is exposed from the surface opposite to the circuit surface of the semiconductor chip 21 in the thin portion of the semiconductor chip 21. The coupling electrode 25 is connected to the through electrode 24. The length of the through electrode 24 is approximately the same as the thickness of the semiconductor chip 21 and is, for example, several tens of microns. Compared with the case where the through electrode 24 is formed in the thick part of the semiconductor chip 21, the length of the through electrode 24 formed in the thin part of the semiconductor chip 21 is short, so that the capacity of the through electrode 24 can be reduced. Therefore, a decrease in frequency characteristics of signal transmission using the through electrode 24 is suppressed, and the power consumption of the semiconductor chip 21 can be reduced.

The bridge substrate 31 is disposed so as to overlap a part of the semiconductor chip 11 and a part of the semiconductor chip 21 in plan view. In the example shown in FIG. 1, the bridge substrate 31 is fitted in a groove shape (concave portion) formed by the thin portion of the semiconductor chip 11 and the thin portion of the semiconductor chip 21. Therefore, the bridge substrate 31 overlaps the thin part of the semiconductor chip 11 and the thin part of the semiconductor chip 21. The bridge substrate 31 is, for example, a silicon substrate or a glass substrate. Since silicon substrates and glass substrates are excellent in surface smoothness and thermal stability, fine wiring with a width of several microns or less can be formed in multiple layers. A low dielectric material or a resin such as polyimide may be used as an insulating layer between the multilayer wirings. The bridge substrate 31 has a plurality of wirings 32 and an insulating layer 33. By filling the resin 5 in the gap between the semiconductor chips 11 and 21 and the bridge substrate 31 and curing, the semiconductor chips 11 and 21 and the bridge substrate 31 are integrally fixed. As a result, it is possible to suppress the stress caused by the temperature change due to the difference between the thermal expansion coefficient of the printed circuit board 3 and the thermal expansion coefficient of the semiconductor chips 11 and 21 from being concentrated on the coupling electrode 15. Furthermore, the difference between the thermal expansion coefficient of the semiconductor chips 11 and 21 and the thermal expansion coefficient of the bridge substrate 31 can be reduced by using a silicon substrate or a glass substrate having a thermal expansion coefficient close to that of the silicon substrate as the bridge substrate 31. . As a result, application of stress to the coupling electrodes 15 and 25 due to temperature change is suppressed.

  In the example shown in FIG. 1, the wiring 32 is provided in the insulating layer 33, but the wiring 32 may be provided on the surface of the insulating layer 33. That is, the wiring 32 may be provided in the bridge substrate 31, or the wiring 32 may be provided on the surface of the bridge substrate 31. One end of the wiring 32 is connected to the coupling electrode 15. Specifically, an electrode is provided at one end of the wiring 32, and the electrode at one end of the wiring 32 and the coupling electrode 15 are connected. Therefore, one end of the wiring 32 is connected to the through electrode 14 via the coupling electrode 15. The other end of the wiring 32 is connected to the coupling electrode 25. Specifically, an electrode is provided at the other end of the wiring 32, and the electrode at the other end of the wiring 32 and the coupling electrode 25 are connected. Therefore, the other end of the wiring 32 is connected to the through electrode 24 through the coupling electrode 25. The semiconductor chip 11 and the semiconductor chip 21 are electrically connected via the wiring 32, and signals (data) are transmitted and received between the semiconductor chip 11 and the semiconductor chip 21.

  The connection electrode 2 </ b> A is not provided on the circuit surface of the semiconductor chip 11 in the thin portion of the semiconductor chip 11. That is, the connection electrode 2 </ b> A is not provided between the thin portion of the semiconductor chip 11 and the printed board 3. The connection electrode 2 </ b> B is not provided on the circuit surface of the semiconductor chip 21 in the thin portion of the semiconductor chip 21. That is, the connection electrode 2 </ b> B is not provided between the thin portion of the semiconductor chip 21 and the printed board 3. Therefore, the connection electrode 2A and the coupling electrode 15 do not overlap in plan view, and the connection electrode 2B and the coupling electrode 25 do not overlap in plan view. Therefore, the stress applied from the printed board 3 to the coupling electrode 15 is reduced, and the stress applied from the printed board 3 to the coupling electrode 25 is reduced. Further, the connection electrode 2A and the through electrode 14 connected to the coupling electrode 15 do not overlap in plan view, and the connection electrode 2B and the through electrode 24 connected to the coupling electrode 25 do not overlap in plan view. Therefore, the stress applied to the through electrode 14 connected to the coupling electrode 15 from the printed board 3 is reduced, and the stress applied to the through electrode 24 connected to the coupling electrode 25 from the printed board 3. Is reduced.

  As shown in FIG. 2, the electronic circuit device 1 may include a fixed substrate 41. FIG. 2 is a cross-sectional view of the electronic circuit device 1 according to the first embodiment. The fixed substrate 41 is disposed on the opposite surface of the circuit surface of the semiconductor chip 11 in a portion other than the thin portion of the semiconductor chip 11 and on the opposite surface of the circuit surface of the semiconductor chip 21 in a portion other than the thin portion of the semiconductor chip 21. Yes. The semiconductor chips 11 and 21 are bonded and fixed to a fixed substrate 41. Accordingly, the fixed substrate 41 is fixed to the opposite surface of the circuit surface of the semiconductor chip 11 in the portion other than the thin portion of the semiconductor chip 11 and the opposite surface of the circuit surface of the semiconductor chip 21 in the portion other than the thin portion of the semiconductor chip 21. Yes. Further, the fixed substrate 41 may be fixed to a surface opposite to the circuit surface of the semiconductor chip 11 in the central portion of the semiconductor chip 11 and a surface opposite to the circuit surface of the semiconductor chip 21 in the central portion of the semiconductor chip 21. The fixed substrate 41 is an example of a second substrate.

The fixed substrate 41 is, for example, a silicon substrate, a glass substrate, a metal plate, an alloy plate, or a composite material plate. By fixing the semiconductor chips 11 and 21 to the fixed substrate 41, stress is applied to the coupling electrodes 15 and 25 due to the difference between the thermal expansion coefficient of the printed circuit board 3 and the thermal expansion coefficient of the semiconductor chips 11 and 21. Is suppressed. At the same time, the application of stress to the bridge substrate 31 is suppressed. The bridge substrate 31 may be fixed to the fixed substrate 41. The bridge substrate 31 may be in contact with the fixed substrate 41. A gap may be provided between the bridge substrate 31 and the fixed substrate 41.

  By using a silicon substrate or a glass substrate having a thermal expansion coefficient close to that of the silicon substrate as the fixed substrate 41, the difference between the thermal expansion coefficients of the semiconductor chips 11 and 21 and the thermal expansion coefficient of the fixed substrate 41 can be reduced. As a result, application of stress to the coupling electrodes 15 and 25 due to temperature change is suppressed. Moreover, the heat dissipation efficiency of the semiconductor chips 11 and 21 can be improved by using the metal plate or the alloy plate having high thermal conductivity as the fixed substrate 41 and transferring the heat of the semiconductor chips 11 and 21 to the fixed substrate 41. . By using a substrate having a small thermal expansion coefficient or a metal plate, an alloy plate, or a metal composite material plate having a thermal expansion coefficient close to that of a silicon substrate as the fixed substrate 41, the thermal expansion coefficient of the semiconductor chips 11 and 21 and the heat of the fixed substrate 41 can be obtained. The difference from the expansion coefficient can be reduced, and the heat dissipation efficiency of the semiconductor chips 11 and 21 can be improved. The metal substrate having a thermal expansion coefficient close to that of a silicon substrate is, for example, a tantalum substrate. An alloy plate having a thermal expansion coefficient close to that of a silicon substrate is, for example, a Kovar substrate. The metal composite material plate having a thermal expansion coefficient close to that of the silicon substrate is, for example, a composite material plate containing invar and copper. Further, an air cooling fin structure and air cooling and liquid cooling channels may be formed on the fixed substrate 41.

  As shown in FIG. 3, the electronic circuit device 1 may include fixed substrates 42 and 43. FIG. 3 is a cross-sectional view of the electronic circuit device 1 according to the first embodiment. The fixed substrate 42 is disposed on the surface opposite to the circuit surface of the semiconductor chip 11 in a portion other than the thin portion of the semiconductor chip 11. The semiconductor chip 11 is bonded and fixed to the fixed substrate 42. Therefore, the fixed substrate 42 is fixed to the surface opposite to the circuit surface of the semiconductor chip 11 in a portion other than the thin portion of the semiconductor chip 11. Further, the fixed substrate 42 may be fixed to the surface opposite to the circuit surface of the semiconductor chip 11 in the central portion of the semiconductor chip 11. Further, the fixed substrate 42 is bonded and fixed to the left side of the bridge substrate 31, and thus the space between the semiconductor chip 11 and the left side of the bridge substrate 31 is fixed. The fixed substrate 43 is disposed on the surface opposite to the circuit surface of the semiconductor chip 21 in a portion other than the thin portion of the semiconductor chip 21. The semiconductor chip 21 is bonded and fixed to the fixed substrate 43. Therefore, the fixed substrate 43 is fixed to the surface opposite to the circuit surface of the semiconductor chip 21 in a portion other than the thin portion of the semiconductor chip 21. Further, the fixed substrate 43 may be fixed to the surface opposite to the circuit surface of the semiconductor chip 21 in the central portion of the semiconductor chip 21. Further, the fixed substrate 43 is bonded and fixed to the right side of the bridge substrate 31, and thus the space between the semiconductor chip 21 and the right side of the bridge substrate 31 is fixed. The fixed substrate 42 is an example of a second substrate. The fixed substrate 43 is an example of a third substrate.

  The fixed substrates 42 and 43 are, for example, a silicon substrate, a glass substrate, a metal plate, an alloy plate, or a composite material plate. By fixing the left side of the bridge substrate 31 and the semiconductor chip 11 to the fixed substrate 42, application of stress due to a temperature change to the coupling electrode 15 due to the difference between the thermal expansion coefficient of the printed circuit board 3 and the thermal expansion coefficient of the semiconductor chip 11 Is suppressed. By fixing the right side of the bridge substrate 31 and the semiconductor chip 21 to the fixed substrate 43, application of stress due to the temperature change to the coupling electrode 25 due to the difference between the thermal expansion coefficient of the printed circuit board 3 and the thermal expansion coefficient of the semiconductor chip 21. Is suppressed.

As shown in FIG. 4A, the thickness of the semiconductor chip 21 may be constant. That is, the thickness of the outer peripheral portion of the semiconductor chip 21 and the thickness of the central portion of the semiconductor chip 21 may be the same. FIG. 4A is a cross-sectional view of the electronic circuit device 1 according to the first embodiment. The bridge substrate 31 is disposed on a part of the semiconductor chip 11 and on a part of the semiconductor chip 21. The bridge substrate 31 overlaps the thin portion of the semiconductor chip 11. For example, the semiconductor chip 11 may be a logic chip and the semiconductor chip 21 may be a memory chip. It is preferable that the gap between the semiconductor chip 11 or the semiconductor chip 21 and the bridge substrate 31 is filled with the resin 5 and cured. Similarly to the electronic circuit device 1 shown in FIG. 3, the fixed substrate 42 may be fixed to the surface opposite to the circuit surface of the semiconductor chip 11 in a portion other than the thin portion of the semiconductor chip 11. Further, the fixed substrate 42 may be fixed to the surface opposite to the circuit surface of the semiconductor chip 11 in the central portion of the semiconductor chip 11. The thickness of the semiconductor chip 11 may be constant, and the semiconductor chip 21 may have a thick part and a thin part. In this case, similarly to the electronic circuit device 1 shown in FIG. 3, the fixed substrate 43 may be fixed to a surface opposite to the circuit surface of the semiconductor chip 21 in a portion other than the thin portion of the semiconductor chip 21. Further, the fixed substrate 43 may be fixed to the surface opposite to the circuit surface of the semiconductor chip 21 in the central portion of the semiconductor chip 21.

  As shown in FIG. 4B, a laminated semiconductor chip 61 may be further disposed on the region of the semiconductor chip 21 where the through electrode 24 and the coupling electrode 25 are not formed. FIG. 4B is a cross-sectional view of the electronic circuit device 1 according to the first embodiment. The laminated semiconductor chip 61 includes a plurality of semiconductor chips 62. The plurality of semiconductor chips 62 are stacked and connected via bumps, TSVs, and the like. The semiconductor chip 21 and the plurality of semiconductor chips 62 are connected via bumps, TSVs, and the like. About another structure, it is the same as that of the electronic circuit apparatus 1 shown to FIG. 4A. In the configuration example of the electronic circuit device 1 shown in FIG. 4B, the three semiconductor chips 62 are arranged on the semiconductor chip 21, but the configuration is not limited to this configuration example. One semiconductor chip 62 may be disposed on the semiconductor chip 21. Two semiconductor chips 62 may be stacked on the semiconductor chip 21, or four or more semiconductor chips 62 may be stacked on the semiconductor chip 21. For example, a plurality of semiconductor chips 62 may be arranged side by side on the semiconductor chip 21. The semiconductor chip 62 is an example of a third semiconductor chip.

Second Embodiment
A second embodiment will be described. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and description thereof is omitted. FIG. 5A is a cross-sectional view of the electronic circuit device 1 according to the second embodiment. The electronic circuit device 1 includes semiconductor chips 11 and 21, bridge substrates 31 </ b> A and 31 </ b> B, and a fixed substrate 41. As shown in FIG. 5A, a step having a plurality of step surfaces is formed on a thin portion of the semiconductor chip 11 on the surface opposite to the circuit surface of the semiconductor chip 11. Thus, a high numerical aperture (NA) lens can be used in photolithography when forming an electrode pattern such as the coupling electrode 15 on a thin portion of the semiconductor chip 11. Therefore, the coupling electrode 15 having a fine pattern can be formed on the thin portion of the semiconductor chip 11. The through electrode 14 may be exposed from each of the plurality of step surfaces of the thin portion of the semiconductor chip 11. The coupling electrode 15 may be formed on each step surface of the thin portion of the semiconductor chip 11, and the coupling electrode 15 may be connected to the through electrode 14 exposed from each step surface. The bridge substrates 31A and 31B are examples of the first substrate. The plurality of step surfaces of the thin portion of the semiconductor chip 11 is an example of a plurality of first step surfaces.

  As shown in FIG. 5A, a step is provided in the thin portion of the semiconductor chip 21. Therefore, the thin part of the semiconductor chip 21 has a plurality of step surfaces. Thereby, a lens with a high NA can be used in photolithography when forming an electrode pattern such as the coupling electrode 25 on a thin portion of the semiconductor chip 21. Therefore, the coupling electrode 25 having a fine pattern can be formed on the thin portion of the semiconductor chip 21. The through electrode 24 may be exposed from each of the plurality of step surfaces of the thin portion of the semiconductor chip 21. The coupling electrode 25 may be formed on each step surface of the thin portion of the semiconductor chip 21, and the coupling electrode 25 may be connected to the through electrode 24 exposed from each step surface. The plurality of step surfaces of the thin portion of the semiconductor chip 21 is an example of a plurality of second step surfaces.

The bridge substrate 31 </ b> A overlaps the lower step surface of the thin portion of the semiconductor chip 11 and the lower step surface of the thin portion of the semiconductor chip 21. The bridge substrate 31 </ b> B overlaps the upper step surface of the thin portion of the semiconductor chip 11 and the upper step surface of the thin portion of the semiconductor chip 21. As shown in FIG. 5A, bridge substrates 31A and 31B are stacked. The bridge substrates 31A and 31B are, for example, silicon substrates or glass substrates. The bridge substrate 31A includes a wiring 32A and an insulating layer 33A. The bridge substrate 31A may have a plurality of wirings 32A. The bridge substrate 31B includes a wiring 32B and an insulating layer 33B. The bridge substrate 31B may have a plurality of wirings 32B. A low elastic modulus polyimide or the like may be used as the material of the insulating layers 33A and 33B. The coupling electrode 15A provided on the lower step surface of the thin portion of the semiconductor chip 11 and the coupling electrode 25A provided on the lower step surface of the thin portion of the semiconductor chip 21 are connected via the wiring 32A of the bridge substrate 31A. Has been. The coupling electrode 15B provided on the upper step surface of the thin portion of the semiconductor chip 11 and the coupling electrode 25B provided on the upper step surface of the thin portion of the semiconductor chip 21 are connected via the wiring 32B of the bridge substrate 31B. Has been.

  In the configuration example of the electronic circuit device 1 illustrated in FIG. 5A, the wiring 32A is provided in the insulating layer 33A. However, the wiring 32A may be provided on the surface of the insulating layer 33A. That is, the wiring 32A may be provided in the bridge substrate 31A, or the wiring 32A may be provided on the surface of the bridge substrate 31A. One end of the wiring 32A is connected to the coupling electrode 15A. Specifically, an electrode is provided at one end of the wiring 32A, and the electrode at one end of the wiring 32A and the coupling electrode 15A are connected. Therefore, one end of the wiring 32A is connected to the through electrode 14 via the coupling electrode 15A. The other end of the wiring 32A is connected to the coupling electrode 25A. Specifically, an electrode is provided at the other end of the wiring 32A, and the electrode at the other end of the wiring 32A is connected to the coupling electrode 25A. Therefore, the other end of the wiring 32A is connected to the through electrode 24 through the coupling electrode 25A.

  In the configuration example of the electronic circuit device 1 shown in FIG. 5A, the wiring 32B is provided in the insulating layer 33B, but the wiring 32B may be provided on the surface of the insulating layer 33B. That is, the wiring 32B may be provided in the bridge substrate 31B, or the wiring 32B may be provided on the surface of the bridge substrate 31B. One end of the wiring 32B is connected to the coupling electrode 15B. Specifically, an electrode is provided at one end of the wiring 32B, and the electrode at one end of the wiring 32B is connected to the coupling electrode 15B. Therefore, one end of the wiring 32B is connected to the through electrode 14 through the coupling electrode 15B. The other end of the wiring 32B is connected to the coupling electrode 25B. Specifically, an electrode is provided at the other end of the wiring 32B, and the electrode at the other end of the wiring 32B is connected to the coupling electrode 25B. Therefore, the other end of the wiring 32B is connected to the through electrode 24 through the coupling electrode 25B.

  The semiconductor chip 11 and the semiconductor chip 21 are electrically connected via the wirings 32 </ b> A and 32 </ b> B, and signals (data) are transmitted and received between the semiconductor chip 11 and the semiconductor chip 21. In the configuration example of the electronic circuit device 1 shown in FIG. 5A, bridge substrates 31A and 31B are stacked. Therefore, a step surface is formed by the bridge substrates 31A and 31B. The bridge substrates 31A and 31B are arranged so that the step surfaces of the bridge substrates 31A and 31B correspond to the step surface of the semiconductor chip 11 and the step surface of the semiconductor chip 21, respectively. Alternatively, a bridge substrate 31 in which the bridge substrates 31A and 31B are integrated may be used. That is, a step having a plurality of step surfaces may be formed on one bridge substrate 31, and the wiring 32 and the insulating layer 33 may be provided on each step surface. In the configuration example of the electronic circuit device 1 shown in FIG. 5A, the fixed substrate 41 is disposed on the semiconductor chips 11 and 21, but the arrangement of the fixed substrate 41 may be omitted. Instead of the fixed substrate 41, fixed substrates 42 and 43 may be used.

Not only the configuration example of the electronic circuit device 1 shown in FIG. 5A but also the bridge substrate 31 on the lower step surface of the thin portion of the semiconductor chip 11 and the lower step surface of the thin portion of the semiconductor chip 21 as shown in FIG. 5B. You may overlap. FIG. 5B is a cross-sectional view of the electronic circuit device 1 according to the second embodiment. A coupling electrode 15 is provided below the thin portion of the semiconductor chip 11, and the through electrode 14 is connected to the coupling electrode 15. The coupling electrode 15 is not provided on the upper part of the thin portion of the semiconductor chip 11. A coupling electrode 25 is formed below the thin portion of the semiconductor chip 21, and the through electrode 24 is connected to the coupling electrode 25. The coupling electrode 25 is not provided on the upper part of the thin portion of the semiconductor chip 21. In the configuration example of the electronic circuit device 1 illustrated in FIG. 5B, the fixed substrate 41 is disposed on the semiconductor chips 11 and 21, but the arrangement of the fixed substrate 41 may be omitted. Instead of the fixed substrate 41, fixed substrates 42 and 43 may be used.

<Third Embodiment>
A third embodiment will be described. In the third embodiment, the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and description thereof is omitted. FIG. 6 is a cross-sectional view of the electronic circuit device 1 according to the third embodiment. The electronic circuit device 1 includes semiconductor chips 11 and 21 and a bridge substrate 51. The bridge substrate 51 is disposed so as to overlap a part of the semiconductor chip 11 and a part of the semiconductor chip 21 in plan view. As shown in FIG. 6, the semiconductor chip 11 and the semiconductor chip 21 may be arranged apart from each other. A part (first end) of the bridge substrate 51 is disposed on the thin portion of the semiconductor chip 11, and another part (second end) of the bridge substrate 51 is disposed on the thin portion of the semiconductor chip 21. Has been. The bridge substrate 51 is an example of a first substrate.

  The bridge substrate 51 is a flexible substrate. When the thermal expansion coefficients of the semiconductor chips 11 and 21 and the thermal expansion coefficient of the printed circuit board 3 are different, stress may be applied to the semiconductor chips 11 and 21 and the positions of the semiconductor chips 11 and 21 may be shifted. Since the flexibility of the flexible substrate absorbs the misalignment of the semiconductor chips 11 and 21, occurrence of poor connection between the semiconductor chip 11 and the bridge substrate 51 and poor connection between the semiconductor chip 21 and the bridge substrate 51 are suppressed.

  The bridge substrate 51 has wiring 52. The wiring 52 may be provided in the bridge substrate 51, or the wiring 52 may be provided on the surface of the bridge substrate 51. One end of the wiring 52 is connected to the coupling electrode 15. Specifically, an electrode is provided at one end of the wiring 52, and the electrode at one end of the wiring 52 and the coupling electrode 15 are connected. Therefore, one end of the wiring 52 is connected to the through electrode 14 via the coupling electrode 15. The other end of the wiring 52 is connected to the coupling electrode 25. Specifically, an electrode is provided at the other end of the wiring 52, and the electrode at the other end of the wiring 52 and the coupling electrode 25 are connected. Therefore, the other end of the wiring 52 is connected to the through electrode 14 via the coupling electrode 25. The semiconductor chip 11 and the semiconductor chip 21 are electrically connected via the wiring 52, and signals (data) are transmitted and received between the semiconductor chip 11 and the semiconductor chip 21.

The electronic circuit device 1 may include fixed substrates 53 and 54. As illustrated in FIG. 6, the fixed substrate 53 and the fixed substrate 54 may be separated so that the fixed substrate 53 reinforces the semiconductor chip 11 and the fixed substrate 54 reinforces. The fixed substrate 53 is disposed on the surface opposite to the circuit surface of the semiconductor chip 11 in a portion other than the thin portion of the semiconductor chip 11. The semiconductor chip 11 is bonded and fixed to the fixed substrate 53. Therefore, the fixed substrate 53 is fixed to the surface opposite to the circuit surface of the semiconductor chip 11 in a portion other than the thin portion of the semiconductor chip 11. Further, the fixed substrate 53 may be fixed to the surface opposite to the circuit surface of the semiconductor chip 11 in the central portion of the semiconductor chip 11. Further, the fixed substrate 53 is bonded and fixed to the left end of the bridge substrate 51, and thus the space between the semiconductor chip 11 and the left end of the bridge substrate 51 is fixed. The fixed substrate 54 is disposed on the surface opposite to the circuit surface of the semiconductor chip 21 in a portion other than the thin portion of the semiconductor chip 21. The semiconductor chip 21 is bonded and fixed to the fixed substrate 54. Therefore, the fixed substrate 54 is fixed to the surface opposite to the circuit surface of the semiconductor chip 21 in a portion other than the thin portion of the semiconductor chip 21. Further, the fixed substrate 54 may be fixed to the surface opposite to the circuit surface of the semiconductor chip 21 in the central portion of the semiconductor chip 21. Further, the fixed substrate 54 is bonded and fixed to the right end of the bridge substrate 51, and thus the space between the semiconductor chip 21 and the right end of the bridge substrate 51 is fixed. The fixed substrate 53 is an example of a second substrate. The fixed substrate 54 is an example of a third substrate.

  The fixed substrates 53 and 54 are, for example, a silicon substrate, a glass substrate, a metal plate, an alloy plate, or a composite material plate. By fixing the left end of the bridge substrate 51 and the semiconductor chip 11 to the fixed substrate 53 and fixing the right end of the bridge substrate 51 and the semiconductor chip 21 to the fixed substrate 54, the thermal expansion coefficient of the printed circuit board 3 and the semiconductor chips 11, 21 are fixed. Stress application due to temperature changes to the coupling electrodes 15 and 25 due to the difference from the thermal expansion coefficient is suppressed. The left end of the bridge substrate 51 and the semiconductor chip 11 and the right end of the bridge substrate 51 and the semiconductor chip 21 may be bonded by underfill or the like. At this time, installation of the fixed substrates 53 and 54 is omitted. Also good.

  The bridge substrate 51 may be fixed to the fixed substrate 53 via the support substrate 55. For example, the support substrate 55 may be bonded and fixed to the bridge substrate 51 and the fixed substrate 53. The bridge substrate 51 and the support substrate 55 may be integrated, or the fixed substrate 53 and the support substrate 55 may be integrated. The bridge substrate 51 may be fixed to the fixed substrate 54 via the support substrate 56. For example, the support substrate 56 may be bonded and fixed to the bridge substrate 51 and the fixed substrate 54. The bridge substrate 51 and the support substrate 56 may be integrated, or the fixed substrate 54 and the support substrate 56 may be integrated. Installation of the support substrates 55 and 56 may be omitted.

  7 and 8 are plan views illustrating an example of the electronic circuit device 1 according to the first to third embodiments. As shown in FIGS. 7 and 8, a plurality of semiconductor chips 71 are arranged, and adjacent semiconductor chips 71 are connected by a bridge substrate 72. The configuration of the semiconductor chip 71 is the same as that of the semiconductor chips 11 and 21. The configuration of the bridge substrate 72 may be the same as the configuration of the bridge substrate 31 or the configuration of the bridge substrate 31B. The configuration of the bridge substrate 71 may be the same as the configuration of the bridge substrate 31 in which the bridge substrate 31A and the bridge substrate 31B are integrated. The configuration of the bridge substrate 72 may be the same as the configuration of the bridge substrate 51. Semiconductor chips 71 having the same size may be arranged, or semiconductor chips 71 having different sizes may be arranged. The bridge substrates 72 having the same size may be disposed, or the bridge substrates 72 having different sizes may be disposed. Further, as shown in FIG. 8, three or more semiconductor chips 71 may be connected by one bridge substrate 72.

  FIG. 9 is a plan view showing an example of the electronic circuit device 1 according to the first to third embodiments. As shown in FIG. 9, semiconductor chips 71 </ b> A to 71 </ b> D are arranged, and adjacent semiconductor chips 71 </ b> A to 71 </ b> D are connected by a bridge substrate 72. The configuration of the semiconductor chips 71A to 71D is the same as that of the semiconductor chips 11 and 21. In FIG. 9, the communication direction between the semiconductor chips 71A to 71D is indicated by arrows. For example, communication is performed between the adjacent semiconductor chip 71A and the semiconductor chip 71B via the wiring 73 of the bridge substrate 72. Further, the semiconductor chip 71A is connected not only to the adjacent semiconductor chips 71B and 71C but also to the semiconductor chip 71D located in the diagonal direction of the electronic circuit device 1 via the wiring 73 of the bridge substrate 72. The thickness of the outer peripheral portion connected to the adjacent semiconductor chip of the semiconductor chip 71A is thinner than the thickness of the central portion of the semiconductor chip 71A. The outer peripheral portions of the semiconductor chips 71B to 71D are the same as the outer peripheral portion of the semiconductor chip 71A.

10A and 10B are plan views illustrating an example of the electronic circuit device 1 according to the first to third embodiments. In FIG. 10A, the communication direction between adjacent semiconductor chips 71 is indicated by arrows, and the bridge substrate 72 is not shown. As shown in FIG. 10A, the semiconductor chip 71
The external shape is square in plan view, and a total of 16 semiconductor chips 71 are connected by a bridge substrate 72 in an array of 4 vertical × 4 horizontal. The outer shape of the semiconductor chip 71 may be a rectangle or a parallelogram, and the number of arrangements in the vertical and horizontal directions is arbitrary. Further, the semiconductor chip 71 itself shown in FIG. 10A may be one in which a plurality of semiconductor chips are connected by a bridge substrate 72. For example, as shown in FIG. 10B, the outer peripheral portion of the electronic device 1 in FIG. It may be one that can be connected by the substrate 72.

(Method for manufacturing electronic circuit device 1)
A method for manufacturing the electronic circuit device 1 will be described with reference to FIGS. 11 to 18 are process diagrams of the method for manufacturing the electronic circuit device 1. Here, although the manufacturing method of the electronic circuit device 1 which concerns on 1st Embodiment is demonstrated, the manufacturing method of the electronic circuit device 1 demonstrated with reference to FIGS. 11-18 is based on 2nd, 3rd embodiment. You may apply to the manufacturing method of the electronic circuit device 1. FIG. As shown in FIG. 11A, the semiconductor chip 11 is prepared, and a support plate 82 is bonded to the circuit surface of the semiconductor chip 11 via an adhesive layer 81. Next, as shown in FIG. 11B, grooves 16 are formed in the semiconductor chip 11 by dicing using a dicing blade, plasma etching, or the like, so that the semiconductor chip 11 is partially thinned. The width (W1) of the groove 16 is, for example, about 1 mm. The thickness of the thin portion of the semiconductor chip 11 is, for example, not less than 10 μm and not more than 50 μm. Note that patterning of a resist may be used as a mask for etching, or a metal mask may be used.

Next, as shown in FIG. 11C, a via-forming hole 17 reaching the circuit 13 of the semiconductor chip 11 is formed by a laser, reactive ion etching (RIE), or the like. For example, the diameter of the holes 17 is about 10 μm, and the pitch of the holes 17 is about 40 μm. After an insulating film such as SiO ₂ or resist is formed on the surface of the groove 16 and the inner wall and bottom of the hole 17, the insulating film at the bottom of the hole 17 is removed by bottom etching. For applying the resist, a spraying method using nano spray may be used.

  Next, as shown in FIG. 12A, after a barrier layer such as Ti and a seed layer for electrolytic plating are formed in the hole 17 by sputtering or the like, Cu is embedded in the hole 17 by electrolytic plating. Thus, the through electrode 14 is formed in the thin portion of the semiconductor chip 11. If the through electrode 14 has already been formed in the semiconductor chip 11 by the wafer process, the step shown in FIG. 11C and the step shown in FIG. 12A can be omitted. Next, as illustrated in FIG. 12B, the coupling electrode 15 is formed on the through electrode 14.

  Next, as shown in FIG. 13A, the semiconductor chip 11 is diced. Next, as shown in FIG. 13B, the adhesive layer 81 and the support plate 82 are removed, and the semiconductor chip 11 is separated into individual pieces, whereby the semiconductor chip 11 is manufactured. The width (W2) of the semiconductor chip 11 is 20 mm, for example. The thickness (T1) of the main body of the semiconductor chip 11 is, for example, 400 μm. The thickness (T2) of the thin portion of the semiconductor chip 11 is, for example, 10 μm or more and 50 μm or less. The length (L1) in the planar direction of the thin portion of the semiconductor chip 11 is, for example, 0.9 mm. The semiconductor chip 21 is manufactured by performing the same process as the process shown in FIGS.

Next, as shown in FIG. 14A, the semiconductor chips 11 and 21 are aligned, and the semiconductor chips 11 and 21 are mounted on the printed circuit board 3. In this case, the thin portion of the semiconductor chip 11 and the thin portion of the semiconductor chip 21 are opposed to each other, and the semiconductor chip 11 and the semiconductor chip 21 are disposed adjacent to each other. When the thickness of the semiconductor chip 21 is constant, the thin portion of the semiconductor chip 11 is opposed to the semiconductor chip 21 and the semiconductor chip 11 and the semiconductor chip 21 are disposed adjacent to each other. When the thickness of the semiconductor chip 11 is constant, the thin portion of the semiconductor chip 21 is opposed to the semiconductor chip 11 and the semiconductor chip 11 and the semiconductor chip 21 are disposed adjacent to each other.

  Next, the electrodes formed on the circuit 13 of the semiconductor chip 11 and the connection electrodes 2A formed on the printed circuit board 3 are soldered together, and the electrodes formed on the circuit 23 of the semiconductor chip 21 and the printed circuit board 3 are formed. The connection electrode 2B is soldered. For example, solder bonding is performed by performing heat treatment using solder paste or solder balls. After filling the underfill 4 between the semiconductor chips 11, 21 and the printed circuit board 3, the underfill 4 is cured by heat treatment.

  Next, as shown in FIG. 14B, the semiconductor chip 21 is on the thin portion of the semiconductor chip 11, on the surface opposite to the circuit surface of the semiconductor chip 11 and on the thin portion of the semiconductor chip 21. The bridge substrate 31 is disposed on the opposite surface of the circuit surface. The bridge substrate 31 overlaps the thin part of the semiconductor chip 11 and the thin part of the semiconductor chip 21. When the thickness of the semiconductor chip 21 is constant, the bridge substrate 31 overlaps the thin part of the semiconductor chip 11 and a part of the semiconductor chip 21. When the thickness of the semiconductor chip 11 is constant, the bridge substrate 31 overlaps a part of the semiconductor chip 11 and a thin part of the semiconductor chip 21. The thickness of the bridge substrate 31 is, for example, 300 μm. The electrode provided at one end of the wiring 32 of the bridge substrate 31 and the coupling electrode 15 of the semiconductor chip 11 are solder-bonded, and the electrode provided at the other end of the wiring 32 of the bridge substrate 31 and the coupling electrode 25 of the semiconductor chip 21. And soldered together. For example, solder bonding is performed by performing heat treatment using solder paste or solder balls. After filling the resin between the semiconductor chips 11 and 21 and the bridge substrate 31, the resin is cured by performing a heat treatment.

  Next, as shown in FIG. 15, the fixed substrate is placed on the opposite surface of the semiconductor chip 11 in a portion other than the thin portion of the semiconductor chip 11 and on the opposite surface of the semiconductor chip 21 in a portion other than the thin portion of the semiconductor chip 21. 41 is arranged. For example, the fixed substrate 41 is disposed on the opposite surface of the semiconductor chip 11 in the central portion of the semiconductor chip 11 and on the opposite surface of the semiconductor chip 21 in the central portion of the semiconductor chip 21. An adhesive is formed between the fixed substrate 41 and the semiconductor chips 11 and 21. Accordingly, the fixed substrate 41 is fixed on the opposite surface of the semiconductor chip 11 in a portion other than the thin portion of the semiconductor chip 11 and is fixed on the opposite surface of the semiconductor chip 21 in a portion other than the thin portion of the semiconductor chip 21. The Instead of the fixed substrate 41, fixed substrates 42 and 43 may be used. The process shown in FIG. 15 may be omitted.

  Instead of the steps shown in FIGS. 14 and 15, the steps shown in FIGS. 16 to 18 may be performed. As shown in FIG. 16A, the semiconductor chips 11 and 21 are aligned, and the semiconductor chips 11 and 21 are placed on the support glass 91. In this case, the thin portion of the semiconductor chip 11 and the thin portion of the semiconductor chip 21 are opposed to each other, and the semiconductor chip 11 and the semiconductor chip 21 are disposed adjacent to each other. When the thickness of the semiconductor chip 21 is constant, the thin portion of the semiconductor chip 11 is opposed to the semiconductor chip 21 and the semiconductor chip 11 and the semiconductor chip 21 are disposed adjacent to each other. When the thickness of the semiconductor chip 11 is constant, the thin portion of the semiconductor chip 21 is opposed to the semiconductor chip 11 and the semiconductor chip 11 and the semiconductor chip 21 are disposed adjacent to each other. The semiconductor chips 11 and 21 may be temporarily fixed to the support glass 91 with an adhesive.

Next, as shown in FIG. 16B, the semiconductor chip 21 is on the thin portion of the semiconductor chip 11, on the surface opposite to the circuit surface of the semiconductor chip 11 and on the thin portion of the semiconductor chip 21. The bridge substrate 31 is disposed on the opposite surface of the circuit surface. The bridge substrate 31 overlaps the thin part of the semiconductor chip 11 and the thin part of the semiconductor chip 21. When the thickness of the semiconductor chip 21 is constant, the bridge substrate 31 overlaps the thin part of the semiconductor chip 11 and a part of the semiconductor chip 21. When the thickness of the semiconductor chip 11 is constant, the bridge substrate 31 overlaps a part of the semiconductor chip 11 and a thin part of the semiconductor chip 21. Next, the electrode provided at one end of the wiring 32 of the bridge substrate 31 and the coupling electrode 15 of the semiconductor chip 11 are solder-bonded, and the electrode provided at the other end of the wiring 32 of the bridge substrate 31 and the coupling of the semiconductor chip 21. The electrode 25 is soldered. After filling the resin between the semiconductor chips 11 and 21 and the bridge substrate 31, the resin is cured by performing a heat treatment.

  Next, as shown in FIG. 17A, on the opposite surface of the semiconductor chip 11 in a portion other than the thin portion of the semiconductor chip 11 and on the opposite surface of the semiconductor chip 21 in a portion other than the thin portion of the semiconductor chip 21. The fixed substrate 41 is arranged in the above. For example, the fixed substrate 41 is disposed on the opposite surface of the semiconductor chip 11 in the central portion of the semiconductor chip 11 and on the opposite surface of the semiconductor chip 21 in the central portion of the semiconductor chip 21. An adhesive is formed between the fixed substrate 41 and the semiconductor chips 11 and 21. Accordingly, the fixed substrate 41 is fixed on the opposite surface of the semiconductor chip 11 in a portion other than the thin portion of the semiconductor chip 11 and is fixed on the opposite surface of the semiconductor chip 21 in a portion other than the thin portion of the semiconductor chip 21. The Instead of the fixed substrate 41, fixed substrates 42 and 43 may be used. You may abbreviate | omit the process shown to (A) of FIG. Next, as shown in FIG. 17B, the semiconductor chips 11 and 21 are removed from the support glass 91.

  Next, as shown in FIG. 18, the semiconductor chips 11 and 21 are mounted on the printed circuit board 3. Next, the electrodes formed on the circuit 13 of the semiconductor chip 11 and the connection electrodes 2A formed on the printed circuit board 3 are soldered together, and the electrodes formed on the circuit 23 of the semiconductor chip 21 and the printed circuit board 3 are formed. The connecting electrode 2B is soldered. For example, solder bonding is performed by performing heat treatment using solder paste or solder balls. After filling the underfill 4 between the semiconductor chips 11, 21 and the printed circuit board 3, the underfill 4 is cured by heat treatment.

DESCRIPTION OF SYMBOLS 1 Electronic circuit apparatus 2A, 2B Connection electrode 3 Printed circuit board 4 Underfill 11, 21, 62, 71, 71A-71E Semiconductor chip 12, 22 Semiconductor substrate 13, 23 Circuit 14, 24 Through-electrode 15, 15A, 25, 25A Connection Electrodes 31, 31A, 31B, 51, 72 Bridge substrates 32, 32A, 32B, 52, 73 Wiring 33, 33A, 33B Insulating layers 41, 42, 43, 53, 54 Fixed substrate 61, laminated semiconductor chip

Claims (14)

A first semiconductor chip;
A second semiconductor chip disposed adjacent to the first semiconductor chip;
A first substrate disposed on a portion of the surface opposite to the surface on which the circuit of the first semiconductor chip is formed and on a portion of the surface opposite to the surface on which the circuit of the second semiconductor chip is formed;
With
Of the outer peripheral portion of the first semiconductor chip, the portion facing the second semiconductor chip has a portion thinner than the thickness of the central portion of the first semiconductor chip,
A first through electrode extending from the opposite surface of the first semiconductor chip to the circuit of the first semiconductor chip is formed in the thin portion of the first semiconductor chip;
The first substrate overlaps the thin portion of the first semiconductor chip;
One end of the wiring provided on the first substrate is connected to the first through electrode,
The other end of the wiring is connected to a second through electrode extending from the opposite surface of the second semiconductor chip to the circuit of the second semiconductor chip;
An electronic circuit device. Of the outer peripheral portion of the second semiconductor chip, the portion facing the first semiconductor chip has a portion thinner than the thickness of the central portion of the second semiconductor chip,
The second through electrode is formed in the thin portion of the second semiconductor chip;
The first substrate overlaps the thin portion of the second semiconductor chip;
The electronic circuit device according to claim 1. A step is formed on the opposite surface of the first semiconductor chip in the thin portion of the first semiconductor chip;
The electronic circuit device according to claim 1, wherein: A step is formed on the opposite surface of the first semiconductor chip in the thin portion of the first semiconductor chip;
A step is formed on the opposite surface of the second semiconductor chip in the thin portion of the second semiconductor chip;
The electronic circuit device according to claim 2. A plurality of the first through electrodes are formed in the thin portion of the first semiconductor chip;
A plurality of second through electrodes are formed in the thin portion of the second semiconductor chip;
A plurality of the wirings are provided on the first substrate;
The step formed on the opposite surface of the first semiconductor chip has a plurality of first step surfaces,
The step formed on the opposite surface of the second semiconductor chip has a plurality of second step surfaces,
The first through electrode is exposed from each of the plurality of first step surfaces,
The second through electrode is exposed from each of the plurality of second step surfaces;
The electronic circuit device according to claim 4. A second substrate fixed to the opposite surface of the first semiconductor chip in a portion other than the thin portion of the first semiconductor chip;
The electronic circuit device according to claim 1, wherein the electronic circuit device is an electronic circuit device. A second substrate fixed to the opposite surface of the first semiconductor chip in a portion other than the thin portion of the first semiconductor chip;
A third substrate fixed to the opposite surface of the first semiconductor chip in a portion other than the thin portion of the second semiconductor chip;
The electronic circuit device according to claim 2, 4, or 5. The opposite surface of the second semiconductor chip is fixed to the opposite surface of the first semiconductor chip in a portion other than the thin portion of the first semiconductor chip, and the portion of the second semiconductor chip other than the thin portion. A second substrate fixed to
The electronic circuit device according to claim 2, 4, or 5. A connection electrode used for connection between the first semiconductor chip and a wiring board is not provided on a surface of the thin portion of the first semiconductor chip where the circuit of the first semiconductor chip is formed.
The electronic circuit device according to claim 1, wherein the electronic circuit device is an electronic circuit device. The surface on which the circuit of the first semiconductor chip is formed in the thin portion of the first semiconductor chip is not provided with a connection electrode used for connection between the first semiconductor chip and a wiring board,
A connection electrode used for connecting the second semiconductor chip and the wiring board is not provided on the surface of the thin portion of the second semiconductor chip where the circuit of the second semiconductor chip is formed.
9. The electronic circuit device according to claim 2, 4, 5, 7, or 8.   The electronic circuit device according to claim 1, wherein the first substrate is a silicon substrate, a glass substrate, or a flexible substrate.   The electronic circuit device according to claim 1, wherein at least one third semiconductor chip is disposed on the second semiconductor chip. A step of disposing the first semiconductor chip and the second semiconductor chip by causing a portion thinner than the thickness of the central portion of the first semiconductor chip to face the second semiconductor chip among the outer peripheral portions of the first semiconductor chip;
On the thin portion of the first semiconductor chip, on the surface opposite to the surface on which the circuit of the first semiconductor chip is formed and on the surface opposite to the surface on which the circuit of the second semiconductor chip is formed. Arranging the substrate; and
The first through electrode reaching from the opposite surface of the first semiconductor chip to the circuit of the first semiconductor chip is joined to one end of a wiring provided on the substrate, and the opposite surface of the second semiconductor chip Bonding the second through electrode reaching the circuit of the second semiconductor chip and the other end of the wiring;
A method of manufacturing an electronic circuit device, comprising: Of the outer peripheral portion of the second semiconductor chip, the portion facing the first semiconductor chip has a portion thinner than the thickness of the central portion of the second semiconductor chip,
The second through electrode is formed in the thin portion of the second semiconductor chip;
The method of manufacturing an electronic circuit device according to claim 13, wherein the substrate overlaps the thin portion of the second semiconductor chip.

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