JP2018112922A - Electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic device capable of preventing shortening of life due to rewriting of memory information.SOLUTION: An electronic device includes first and second memory areas, a first communication unit, and a first processing unit. The first communication unit receives a command. The first processing unit writes information into one of the first and second memory areas selected as a writing destination of the information according to the processing of the command and, in response to completion of a series of writing, updates information in the non-selected memory area on the basis of the information written in the selected memory area.SELECTED DRAWING: Figure 2

Description

  Embodiments described herein relate generally to an electronic device.

  An electronic device such as an IC card having an IC (integrated circuit) chip is widely used. The IC card receives a command from the reader / writer and executes a process according to the received command. For example, the IC card writes information in a nonvolatile memory (hereinafter referred to as memory) in response to execution of command processing.

  In the case of an application that requires authentication and verification, the IC card rewrites memory information each time authentication and verification are performed.

JP 2011-70321 A

  When the number of times of authentication and verification is large, the frequency of rewriting information in the memory increases. Such frequent rewriting may shorten the life of the IC card.

  An object of the present invention is to provide an electronic device that prevents a shortening of life due to rewriting of information in a memory.

  The electronic device according to the embodiment includes first and second memory areas, a first communication unit, and a first processing unit. The first communication unit receives a command. The first processing unit writes information into one of the memory areas selected from the first and second memory areas as a writing destination of information according to the processing of the command, and upon completion of a series of writing The information in the non-selected memory area is updated based on the information written in the selected memory area.

It is a block diagram which shows an example of an IC card system common to each embodiment. It is a block diagram which shows an example of the IC card which concerns on 1st and 2nd embodiment. It is a sequence diagram which shows an example of the writing process by the IC card which concerns on 1st Embodiment. It is a flowchart which shows an example of the write-in process by the IC card which concerns on 2nd Embodiment. It is a flowchart which shows an example of the matching process by the IC card which concerns on 2nd Embodiment. It is a block diagram which shows an example of the IC card which concerns on 3rd Embodiment. It is a block diagram which shows an example of the IC card which concerns on 4th Embodiment. It is a flowchart which shows an example of the write-in process by the IC card which concerns on 4th Embodiment. It is a block diagram which shows an example of the IC card which concerns on 5th Embodiment.

  Hereinafter, IC card systems according to some embodiments will be described with reference to the drawings.

  FIG. 1 is a block diagram illustrating an example of an IC card system common to the embodiments. The IC card system 1 includes a communication device 10 and an IC card 20.

  The communication device 10 transmits a command to the IC card 20 and receives a response transmitted from the IC card 20. The communication device 10 includes a central processing unit (CPU) 11, a read-only memory (ROM) 12, a random-access memory (RAM) 13, a nonvolatile memory 14, a reader / writer 15, a display 16, an operation unit 17, and a communication interface 18. including.

  The CPU 11 corresponds to a central part of a computer that performs processing and control necessary for the operation of the communication device 10. The CPU 11 controls each unit to realize various functions of the communication device 10 based on a program such as an operating system and application software stored in the ROM 12 or the nonvolatile memory 14.

  The ROM 12 is a read-only nonvolatile memory corresponding to the main storage portion of the computer. The ROM 12 stores a program such as an operating system or application software. The ROM 12 stores data used when the CPU 11 performs various processes.

  The RAM 13 is a volatile memory corresponding to the main storage portion of the computer. The RAM 13 is used as a so-called work area that stores data temporarily used when the CPU 11 performs various processes.

  The nonvolatile memory 14 is a readable / writable storage medium corresponding to the auxiliary storage portion of the computer. The RAM 13 is, for example, an EEPROM (electrically erasable programmable read-only memory) (registered trademark), an HDD (hard disk drive), or an SSD (solid state drive). The non-volatile memory 14 may store a program such as an operating system or application software. Further, the nonvolatile memory 14 stores data used when the CPU 11 performs various processes, data generated by the processes in the CPU 11, and the like. Note that the communication device 10 may include an interface such as a card slot into which a storage medium such as a memory card can be inserted instead of or in addition to the nonvolatile memory 14. The memory card corresponds to an auxiliary storage part of the computer.

  The program stored in the ROM 12 or the nonvolatile memory 14 includes a control program. As an example, the communication device 10 is transferred to a user or the like with the control program stored in the ROM 12 or the nonvolatile memory 14. However, the communication device 10 may be transferred to a user or the like in a state where a control program described regarding control processing described later is not stored in the ROM 12 or the nonvolatile memory 14. The communication device 10 may be transferred to a user or the like in a state where another control program is stored in the ROM 12 or the nonvolatile memory 14. Then, the control program may be separately transferred to a user or the like and written to the nonvolatile memory 14 under the operation of the user or a service person. The transfer of the control program at this time can be realized, for example, by recording on a removable recording medium such as a magnetic disk, a magneto-optical disk, an optical disk, a semiconductor memory, or by downloading via a network.

  The reader / writer 15 communicates with a contact-type IC card or a non-contact-type IC card (hereinafter, IC card 20). The reader / writer 15 communicates with a non-contact type IC chip mounted on an electronic device (for example, a mobile phone, a smartphone, a tablet PC (personal computer), etc.). The reader / writer 15 transmits a command to the IC card 20 using the communication. Further, the reader / writer 15 receives a response transmitted from the IC card 20 using the communication. Hereinafter, in each embodiment, a case where the reader / writer 15 and the IC card 20 communicate with each other will be described. However, the IC card 20 may be read as the above-described non-contact type IC chip.

  The display 16 displays a screen for notifying the operator of the communication device 10 of various information. The display 16 is, for example, a liquid crystal display or an organic EL (electro-luminescence) display.

  The operation unit 17 receives an operation by an operator of the communication device 10. The operation unit 17 is, for example, a keyboard, a keypad, a touch pad, or a mouse. In addition, as the operation unit 17, a touch pad arranged on the display panel of the display 16 can be used. That is, the display panel included in the touch panel can be used as the display 16, and the touch pad included in the touch panel can be used as the operation unit 17.

  The communication interface 18 is an interface for communicating with other devices. The communication interface 18 is configured to be connectable to a network (not shown), for example. The communication interface 18 communicates with other devices (not shown) via a network.

[First Embodiment / Selection of Module by Communication Device]
FIG. 2 is a block diagram illustrating an example of an IC card according to the first embodiment. The IC card 20 is a contact IC card or a non-contact IC card. The IC card 20 includes, for example, a card-like main body 21, an IC module 22A built in the main body 21, and an IC module 22B. In this embodiment, the case where the IC card 20 includes two IC modules 22A and 22B will be described. However, the IC card 20 may include three or more IC modules.

  The IC module 22A includes an IC chip 23A and a communication circuit connected to the IC chip 23A. The communication circuit is configured as an antenna or a contact terminal (contact pattern), for example. The communication circuit is electrically connected to the reader / writer 15 of the communication device 10. The IC card 20 is an example of an electronic device.

  The IC chip 23A includes a central processing unit (CPU) 231A, a read-only memory (ROM) 232A, a random-access memory (RAM) 233A, a nonvolatile memory 234A, a communication unit 235A, and a power supply unit 236A.

  The CPU 231 </ b> A corresponds to a central part of a computer that performs processing and control necessary for the operation of the IC card 20. The CPU 231A controls each unit to realize various functions of the IC card 20 based on a program such as an operating system or application software stored in the ROM 232A or the nonvolatile memory 234A.

  The ROM 232A is a read-only nonvolatile memory corresponding to the main storage portion of the computer. The ROM 232A stores a program such as an operating system or application software. The ROM 232A stores data used when the CPU 231A performs various processes.

  The RAM 233A is a volatile memory corresponding to the main storage portion of the computer. The RAM 233A is used as a so-called work area that stores data temporarily used when the CPU 231A performs various processes.

  The non-volatile memory 234A corresponds to the auxiliary storage portion of the computer. The nonvolatile memory 234A is configured by, for example, a semiconductor memory. The nonvolatile memory 234A may store a program such as an operating system or application software. The non-volatile memory 234A stores data used when the CPU 231A performs various processes according to commands or the like, or data generated by the processes in the CPU 231A.

  The program stored in the ROM 232A or the non-volatile memory 234A includes a control program described regarding control processing described later. As an example, the IC card 20 is transferred to a user or the like in a state where the control program is stored in the ROM 232A or the nonvolatile memory 234A. However, the IC card 20 may be transferred to a card manager (issuer) or the like in a state in which a control program described regarding control processing described later is not stored in the ROM 232A or the nonvolatile memory 234A. Further, the IC card 20 may be transferred to a card manager or the like in a state where another control program is stored in the ROM 232A or the nonvolatile memory 234A. Then, a control program described regarding a control process to be described later may be separately transferred to a card manager or the like and written into the nonvolatile memory 234A under the operation of the card manager or the like. The transfer of the control program at this time can be realized, for example, by recording on a removable recording medium such as a magnetic disk, a magneto-optical disk, an optical disk, a semiconductor memory, or by downloading via a network.

  The communication unit 235A is a circuit for communicating with the communication device 10, and is also a circuit for communicating with the communication unit 235B. The communication unit 235A transmits and receives data to and from the communication device 10 by contact communication or non-contact communication via the communication circuit. For example, the communication unit 235A obtains data such as a command transmitted by the communication device 10 by performing signal processing on a signal transmitted from the communication device 10. The communication unit 235A passes the acquired data to the CPU 231A. The communication unit 235 </ b> A generates a signal based on data such as a response passed from the CPU 231 </ b> A, and transmits the generated signal to the communication device 10.

  The power supply unit 236 </ b> A supplies power to each unit of the IC card 20. The power supply unit 236A converts the power supplied from the communication device 10 through the communication circuit described above into the rated voltage of each unit and supplies it to each unit. The power supply unit 236A may include a battery and supply the power of the battery to each unit.

  The IC module 22B includes an IC chip 23B and a communication circuit connected to the IC chip 23B. The communication circuit is as described above.

  The IC chip 23B includes a CPU 231B, a ROM 232B, a RAM 233B, a nonvolatile memory 234B, a communication unit 235B, and a power supply unit 236B.

  The IC module 22A corresponds to the IC module 22B. That is, the IC chip 23A corresponds to the IC chip 23B. That is, the CPU 231A, ROM 232A, RAM 233A, nonvolatile memory 234A, communication unit 235A, and power supply unit 236A correspond to the CPU 231B, ROM 232B, RAM 233B, nonvolatile memory 234B, communication unit 235B, and power supply unit 236B, respectively. Therefore, descriptions of the CPU 231B, the ROM 232B, the RAM 233B, the nonvolatile memory 234B, the communication unit 235B, and the power supply unit 236B are omitted.

  For example, the ROM 232A of the IC module 22A stores IDA as the identification ID, and the ROM 232B of the IC module 22B stores IDB as the identification ID. As a result, the IC module 22A and the IC module 22B can be identified.

  The IC module 22A and the IC module 22B (IC chip 23A and IC chip 23B) are examples of electronic devices.

  Next, the writing process according to the first embodiment will be described. The CPU 231A and the CPU 231B execute a write process according to a process such as a command from the communication device, and the write destination of information is set to the nonvolatile memory 234A (the first memory area MA of the nonvolatile memory 234A) and the main write process. The data is distributed to the nonvolatile memory 234B (second memory area MB of the nonvolatile memory 234B). Thus, the load caused by rewriting in the nonvolatile memory 234A and the nonvolatile memory 234B, which are information write destinations, can be reduced, and the lifetime of the nonvolatile memory 234A and the nonvolatile memory 234B can be extended. As a result, the life of the IC card 20 can be extended.

  FIG. 3 is a sequence diagram illustrating an example of a writing process by the IC card according to the first embodiment.

  For example, the CPU 11 of the communication device 10 includes a random number generation unit, and generates a random number periodically or at the timing of the writing process. The CPU 11 selects one of the IC module 22A and the IC module 22B based on the random number, and communicates with the selected module. Further, it is assumed that the IC module 22A of the IC card 20 uses the logical channel Ch0 and the IC module 22B uses the logical channel Ch1. For example, the ROM 232A or the non-volatile memory 234A of the IC module 22A stores a program corresponding to the logical channel Ch0. Further, the ROM 232B or the nonvolatile memory 234B of the IC module 22B stores a program corresponding to the logical channel Ch1.

  When the IC card 20 is reset, the IC module 22A (communication unit 235A) of the IC card 20 transmits an ATR (answer to reset) to the communication device 10 using the logical channel Ch0 (ST101). IC module 22B (communication unit 235B) transmits ATR to communication device 10 using logical channel Ch1 (ST102).

  The communication device 10 receives the ATR from the IC module 22A using the logical channel Ch0 and the ATR from the IC module 22B using the logical channel Ch1 via the reader / writer 15, and receives the IC module 22A of the IC card 20 and the ATR. Two IC modules 22B are recognized.

For example, the communication device 10 selects one of the IC module 22A and the IC module 22B by a calculation method using random numbers, and communicates with the selected module. For example, when the IC module 22A is selected, the communication device 10 communicates with the IC module 22A using the logical channel Ch0, and when the IC module 22B is selected, the communication device 10 communicates with the IC module 22A using the logical channel Ch1. ,
For example, the communication device 10 selects the IC module 22A by a calculation method using random numbers, communicates with the IC module 22A using the logical channel Ch0, and transmits an authentication command (key A) (ST103). The IC module 22A responds to communication on the logical channel Ch0 and does not respond to communication on other logical channels. The IC module 22A (CPU 231A) receives the authentication command (key A) transmitted using the logical channel Ch0, and collates the key A stored in the ROM 232A or the nonvolatile memory 234A with the key A of the authentication command. Then, the verification success is transmitted (ST104). For example, in one authentication and successful verification, the IC module 22A (CPU 231A) rewrites the PTC (Pin Try Counter) of the nonvolatile memory 234A (first memory area MA) twice.

  Communication apparatus 10 transmits a READ command (Data A) using logical channel Ch0 (ST105). The IC module 22A (CPU 231A) receives the READ command (Data A) transmitted using the logical channel Ch0, and transmits a response including Data A stored in the ROM 232A or the nonvolatile memory 234A (ST106). When the communication device 10 uses the logical channel Ch0 and transmits the WRITE command (Data A) instead of the READ command, the IC module 22A (CPU 231A) transmits the WRITE command transmitted using the logical channel Ch0. (Data A) is received, Data A is written to the nonvolatile memory 234A (first memory area MA), and a response is transmitted.

  A series of processes (one transaction) by the authentication command (key A) and the READ command (Data A) or the WRITE command (Data A) is defined as one transaction process.

  Communication device 10 selects IC module 22B by a calculation method using random numbers, communicates with IC module 22B using logical channel Ch1, and transmits an authentication command (key A) (ST107). The IC module 22B responds to communication on the logical channel Ch1, and does not respond to communication on other logical channels. The IC module 22B (CPU 231B) receives the authentication command (key A) transmitted using the logical channel Ch1, and collates the key A stored in the ROM 232B or the nonvolatile memory 234B with the key A of the authentication command. Then, the verification success is transmitted (ST108). For example, in one authentication and successful verification, the PTC (Pin Try Counter) of the nonvolatile memory 234B is rewritten twice.

  Communication apparatus 10 transmits a READ command (Data B) using logical channel Ch1 (ST109). The IC module 22B (CPU 231B) receives the READ command (DataB) transmitted using the logical channel Ch1, and transmits a response including DataB stored in the ROM 232B or the nonvolatile memory 234B (ST110). When the communication device 10 uses the logical channel Ch1 and transmits a WRITE command (Data B) instead of the READ command, the IC module 22B (CPU 231B) transmits the WRITE command transmitted using the logical channel Ch1. (DataB) is received, DataB is written in the nonvolatile memory 234B (second memory area MB), and a response is transmitted.

  A series of processes based on the authentication command (key B) and the READ command (Data B) or the WRITE command (Data B) is defined as one transaction process.

  According to the above writing process, writing can be distributed by the nonvolatile memory 234A and the nonvolatile memory 234B. As a result, the life of the IC card 20 can be extended.

  Further, when a data change occurs in the nonvolatile memory 234A, for example, in response to the end of a series of writing to the nonvolatile memory 234A (corresponding to the end of one transaction process), the CPU 231A and the CPU 231B communicate, The CPU 231B updates the data in the nonvolatile memory 234B based on the data in the nonvolatile memory 234A (copies the data in the nonvolatile memory 234A to the nonvolatile memory 234B), and stores the data in the nonvolatile memory 234A and the nonvolatile memory 234B. Maintain consistency. Similarly, when data change occurs in the nonvolatile memory 234B, for example, the CPU 231B and the CPU 231A communicate with each other in response to the end of a series of writes to the nonvolatile memory 234B (corresponding to the end of one transaction process). The CPU 231A updates the data in the nonvolatile memory 234A based on the data in the nonvolatile memory 234B (copies the data in the nonvolatile memory 234B to the nonvolatile memory 234A), and the data in the nonvolatile memory 234A and the nonvolatile memory 234B Maintain the integrity of

  As described above, the PTC of the non-volatile memory 234A or the non-volatile memory 234B is rewritten a plurality of times in the series of processes, but the PCT of the non-volatile memory 234B or the non-volatile memory 234A can be rewritten once in the update process.

  When the IC module 22A is abnormal (an abnormality occurs in the IC module 22A) and the IC module 22B is normal, the IC module 22A does not transmit the ATR, and the IC module 22B transmits the ATR. The communication device 10 communicates with the IC module 22B based on the ATR from the IC module 22B (not communicates with the IC module 22A). The same applies when the IC module 22B is abnormal (the IC module 22B has an abnormality) and the IC module 22A is normal.

  According to the present embodiment, for example, it is effective in the case of an application that requires the same key to be authenticated and verified many times in one reading process, reducing the load on the memory and extending the life of the card. Can be achieved.

[Second Embodiment / Selection of Module Using IC Card]
In the first embodiment, the module selection by the communication device has been described. In the second embodiment, the module selection by the IC card 20 will be described. Description of parts common to the first embodiment will be omitted as appropriate.

  FIG. 2 is also a block diagram illustrating an example of an IC card according to the second embodiment. Furthermore, a second embodiment will be described with reference to FIGS. 4 and 5.

  FIG. 4 is a flowchart illustrating an example of a writing process by the IC card according to the second embodiment.

  The CPU 11 of the communication device 10 communicates with the IC card 20 without selecting the IC module 22A or the IC module 22B. Further, it is assumed that the IC module 22A of the IC card 20 uses a predetermined logical channel, and the IC module 22B also uses a predetermined logical channel. For example, the ROM 232A or the non-volatile memory 234A of the IC module 22A stores a program corresponding to a predetermined logical channel. Further, the ROM 232B or the non-volatile memory 234B of the IC module 22B stores a program corresponding to a predetermined logical channel.

  The communication device 10 transmits a command or the like to the IC card 20 using a predetermined logical channel via the reader / writer 15. The IC module 22A (CPU 231A) and IC module 22B (CPU 231B) of the IC card 20 receive commands and the like (ST201).

  For example, the CPU 231A includes a distribution counter CA, and the CPU 231B includes a distribution counter CB. The distribution counter CA and the distribution counter CB are synchronized and output the same count value. For example, the distribution counter CA and the distribution counter CB change the count value corresponding to the end of one transaction process. For example, the count value is changed by counting up the current count value (+1 addition). As a result, the count value alternately indicates even and odd numbers.

  When the count value is an even number (ST202, YES), the IC module 22A (CPU 231A) selects the IC module 22A as an operation target, continues the operation of the IC module 22A (ST203), and the IC module 22B (CPU 231B). If the count value is an even number (ST202, YES), the operation of the IC module 22B is suspended (ST203). Further, when the count value is an odd number (ST202, NO), the IC module 22A stops the operation of the IC module 22A (ST204), and the IC module 22B determines that the count value is an odd number (ST202, NO). ), The IC module 22B is selected as an operation target, and the operation of the IC module 22B is continued (ST204).

  That is, when the count value of ST202 is an even number, the IC module 22A executes transaction processing and writes information to the nonvolatile memory 234A (first memory area MA) according to a received command or the like. Or rewrite the written information (ST205). When the count value of ST202 is an odd number, the IC module 22B executes transaction processing and writes information to the non-volatile memory 234B (second memory area MB) according to a received command or the like. The written information is rewritten (ST205).

  Further, in response to the end of one transaction process, the CPU 231A and the CPU 231B perform a matching process between the nonvolatile memory 234A (first memory area MA) and the nonvolatile memory 234B (second memory area MB) (ST206). The information in the nonvolatile memory 234A (first memory area MA) and the information in the nonvolatile memory 234B (second memory area MB) are synchronized.

  In response to the end of the matching process, a response corresponding to the received command is transmitted to communication device 10 (ST207). That is, when the count value of ST202 is an even number, the CPU 231A transmits a response corresponding to the received command to the communication apparatus 10 (ST207). When the count value of ST202 is an odd number, the CPU 231B sets the received command as a response. A corresponding response is transmitted to the communication device 10 (ST207).

  FIG. 5 is a flowchart showing an example of matching processing by the IC card according to the second embodiment.

  For example, the IC module 22A (CPU 231A) writes the second data (new data) to the write destination (the write destination where the first data is written) of the nonvolatile memory 234A (first memory area MA). The case of (overwriting) will be described. Note that the IC module 22B (CPU 231B) does not write data.

  The first data of the write destination of the non-volatile memory 234A is the old data, the first CRC (cyclic redundancy check) corresponding to the first data (old data) is the old CRC, and the non-volatile memory 234A is the old CRC Hold.

  The CPU 231A (that is, the written CPU) encrypts and transmits the write destination address, the old CRC, and the new data in the nonvolatile memory 234A (the first memory area MA) to the CPU 231B (that is, the unwritten CPU) ( ST301). When the CPU 231B acquires the old CRC corresponding to the old data written in the nonvolatile memory 234B based on the write destination address, and confirms that the old CRC transmitted from the CPU 231A matches the acquired old CRC, Data is overwritten with new data, and a response including a new CRC corresponding to the new data is transmitted (ST302).

  CPU 231A receives the response including the new CRC, and checks whether the new CRC corresponding to the new data written in nonvolatile memory 234A matches the new CRC included in the received response (ST303). If the match is confirmed, the CPU 231A updates (adds +1) the count value of the distribution counter CA, transmits the count value of the distribution counter CA to the CPU 231B, and the CPU 231B receives the count value of the distribution counter CA. The count value of the distribution counter CB is updated based on the received count value (ST304).

  If the new CRC corresponding to the new data written in the non-volatile memory 234A and the new CRC included in the received response are not confirmed, the CPU 231A renews the new memory to the non-volatile memory 234B in ST301 and ST302. Data is written and the count values of the first and distribution counters CB are updated.

  As described above, the same effects as those of the first embodiment can be obtained. In addition, since the IC card 20 selects a module, a mechanism for module selection by the communication device (higher application) becomes unnecessary.

[Third Embodiment / Selection of Module by Main Module of IC Card]
In the second embodiment, the module selection by the IC card 20 has been described, but in the third embodiment, the module selection by the main module of the IC card 20 will be described. Description of parts common to the first and second embodiments will be omitted as appropriate.

  FIG. 6 is a block diagram illustrating an example of an IC card according to the third embodiment. As shown in FIG. 6, the IC module 22A is a main module, and the IC module 22B is a submodule. The communication unit 235A of the IC module 22A is a circuit for communicating with the communication device 10, and is also a circuit for communicating with the communication unit 235B. The communication unit 235B of one IC module 22B is also a circuit for communicating with the communication unit 235A.

  Further, the IC module 22A includes a distribution counter CA. The IC module 22A (CPU 231A) selects one of the IC module 22A and the IC module 22B based on the count value of the distribution counter CA. For example, the IC module 22A (CPU 231A) selects the IC module 22A when the count value is an even number, and selects the IC module 22B when the count value is an odd number.

  That is, when the count value is an even number, the CPU 231A executes a transaction process, and writes or writes information in the nonvolatile memory 234A (first memory area MA) according to a received command or the like. Rewrite information. When the count value is an odd number, the CPU 231B that has received the selection notification from the CPU 231A executes transaction processing, and sends information to the nonvolatile memory 234B (second memory area MB) according to the received command or the like. Write or rewrite written information.

  Furthermore, in response to the end of one transaction process, the CPU 231A and the CPU 231B perform a matching process between the nonvolatile memory 234A (first memory area MA) and the nonvolatile memory 234B (second memory area MB), and the nonvolatile memory The information in the memory 234A (first memory area MA) and the information in the nonvolatile memory 234B (second memory area MB) are synchronized.

  In response to the end of the matching process, a response corresponding to the received command is transmitted. That is, when the count value is an even number, the CPU 231A transmits a response corresponding to the received command to the communication device 10, and when the count value is an odd number, the CPU 231A transmits a response corresponding to the received command from the CPU 231B. Transmit to the communication device 10.

  As described above, the same effects as those of the first and second embodiments can be obtained. In addition, by managing the count value on the main module side, a mechanism for synchronizing the count value becomes unnecessary.

[Fourth Embodiment / Memory Selection by IC Card]
In the second and third embodiments, the module selection by the IC card 20 has been described. In the fourth embodiment, the memory selection by the IC card 20 will be described. A description of portions common to the first to third embodiments will be omitted as appropriate.

  FIG. 7 is a block diagram illustrating an example of an IC card according to the fourth embodiment. As shown in FIG. 7, the IC card 20 includes, for example, a card-like main body 21 and an IC module 22 </ b> A built in the main body 21. The basic configuration of the IC module 22A is as shown in FIG. 2, but the IC module 22A includes a distribution counter CA, and includes a first nonvolatile memory 234A1 (first memory area MA) and a second nonvolatile memory. A memory 234A2 (second memory area MB) is provided.

  FIG. 8 is a flowchart illustrating an example of a writing process by the IC card according to the fourth embodiment.

  The communication device 10 transmits a command or the like to the IC card 20 using a predetermined logical channel via the reader / writer 15. The IC module 22A (CPU 231A) of the IC card 20 receives a command or the like (ST401), and counts up (+1 addition) the distribution counter CA (ST402).

  The IC module 22A (CPU 231A) selects one of the first nonvolatile memory 234A1 and the second nonvolatile memory 234A2 based on the count value of the distribution counter CA. For example, when the count value is an even number (ST403, YES), the IC module 22A (CPU 231A) selects the first nonvolatile memory 234A1, and when the count value is an odd number (ST403, NO) The second non-volatile memory 234A2 is selected.

  That is, when the count value is an even number, the CPU 231A executes transaction processing using the first nonvolatile memory 234A1, and sends information to the first nonvolatile memory 234A1 according to the received command or the like. Is written or the written information is rewritten (ST404). When the count value is an odd number, the CPU 231A executes a transaction process by using the second nonvolatile memory 234A2, and sends information to the second nonvolatile memory 234A2 according to a received command or the like. Write or rewrite the written information (ST405).

  Further, in response to the end of one transaction process, the CPU 231A executes the matching process of the first nonvolatile memory 234A1 and the second nonvolatile memory 234A2, and the information of the first nonvolatile memory 234A1 and the second nonvolatile memory 234A1. Synchronize the information in the volatile memory 234A2.

  In response to the end of the matching process, a response corresponding to the received command is transmitted. That is, regardless of whether the count value is even or odd, the CPU 231A transmits a response corresponding to the received command to the communication device 10.

  As described above, the same operational effects as those of the first to third embodiments can be obtained. In addition, an IC card can be configured with one module. That is, it is possible to extend the life without increasing the cost.

[Fifth Embodiment / Selection of Memory Area by IC Card]
In the fourth embodiment, the selection of the memory by the IC card 20 has been described. In the fifth embodiment, the selection of the memory area by the IC card 20 will be described. Description of parts common to the first to fourth embodiments will be omitted as appropriate.

  FIG. 9 is a block diagram illustrating an example of an IC card according to the fifth embodiment. As shown in FIG. 9, the IC card 20 includes, for example, a card-like main body 21 and an IC module 22 </ b> A built in the main body 21. The basic configuration of the IC module 22A is as shown in FIG. 2, but the IC module 22A includes a distribution counter CA, a non-volatile memory 234A, and the non-volatile memory 234A includes the first memory area MA and the second memory area MA. Memory area MB.

  The IC module 22A (CPU 231A) selects one of the first memory area MA and the second memory area MB based on the count value of the distribution counter CA. For example, the IC module 22A (CPU 231A) selects the first memory area MA when the count value is an even number, and selects the second memory area MB when the count value is an odd number.

  That is, when the count value is an even number, the CPU 231A executes a transaction process, and writes information in the first memory area MA or rewrites the written information in accordance with a received command or the like. When the count value is an odd number, the CPU 231A executes a transaction process and writes information to the second memory area MB or rewrites the written information in accordance with a received command or the like.

  Further, in response to the end of one transaction process, the CPU 231A executes the matching process between the first memory area MA and the second memory area MB, and the information of the first memory area MA and the second memory area MB Synchronize with information.

  In response to the end of the matching process, a response corresponding to the received command is transmitted. That is, regardless of whether the count value is even or odd, the CPU 231A transmits a response corresponding to the received command to the communication device 10.

  As described above, the same effects as those of the first to fourth embodiments can be obtained. In addition, the IC card 20 can be configured with the nonvolatile memory 234A. That is, it is possible to extend the life without increasing the cost.

  All processes in the IC card system 1 can be executed by some software (applications). For this reason, these programs are installed in the communication device 10 through a computer-readable storage medium storing several programs for executing the above processing and control procedures, or these programs are installed via the communication device 10 in an IC. The above processing and control can be easily realized simply by writing to the card 20. For example, the communication device 10 can download the program via a network, store the downloaded program, and complete the installation of the program. Alternatively, the communication device 10 can read the program from the information storage medium, store the read program, and complete the installation of the program.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 ... Card system 10 ... Communication apparatus 11 ... CPU
12 ... ROM
13 ... RAM
14 ... Nonvolatile memory 15 ... Reader / writer 16 ... Display 17 ... Operation unit 18 ... Communication interface 20 ... Card 21 ... Main body 22A ... Module 22B ... Module 23A ... Chip 23B ... Chip 231A ... CPU
231B ... CPU
232A ... ROM
232B ROM
233A ... RAM
233B ... RAM
234A ... nonvolatile memory 234B ... nonvolatile memory 234A1 ... first nonvolatile memory 234A2 ... second nonvolatile memory 234B ... nonvolatile memory 235A ... communication unit 235B ... communication unit 236A ... power supply unit 236B ... power supply unit

Claims (10)

First and second memory areas;
A first communication unit for receiving a command;
Information is written to one of the memory areas selected from the first and second memory areas as a writing destination of information according to the processing of the command, and information is written to the selected memory area at the end of a series of writing A first processing unit for updating the information of the non-selected memory area based on:
An electronic device comprising: A first memory including the first memory area;
A second memory including the second memory area;
An electronic device according to claim 1. A first IC module including the first memory, the first communication unit, and the first processing unit;
A second IC module including the second memory, a second communication unit corresponding to the first communication unit, and a second processing unit corresponding to the first processing unit;
An electronic device according to claim 2. When the first processing unit selects the first memory from the first and second memories based on a count value of a first counter, the first processing unit writes information into the first memory,
When the second processing unit selects the second memory from the first and second memories based on the count value of the second counter synchronized with the first counter, the second processing unit stores the second memory in the second memory. 4. The electronic device according to claim 3, wherein information is written. The first processing unit updates the information in the first memory based on the information written in the second memory according to the end of a series of writing,
The electronic device according to claim 4, wherein the second processing unit updates information in the second memory based on information written in the first memory in response to the end of a series of writing. The first processing unit writes information to the first memory one or more times in one transaction process,
6. The electronic apparatus according to claim 5, wherein the second processing unit writes information to the second memory one or more times in one transaction process. The first processing unit updates the information in the first memory based on the information written in the second memory in response to the end of one transaction process by the second processing unit,
The second processing unit updates information in the second memory based on information written in the first memory in response to the end of one transaction processing by the first processing unit. Electronic equipment. The first IC module communicates with an external device through a first logical channel,
The electronic device according to claim 3, wherein the second IC module communicates with an external device through a second logical channel. The first IC module writes information to the first memory one or more times in one transaction based on the communication of the first logical channel,
9. The electronic device according to claim 8, wherein the second IC module writes information in the second memory one or more times in one transaction based on the communication of the second logical channel. The first IC module updates the information in the first memory based on the information written in the second memory in response to the end of one transaction by the second IC module,
10. The second IC module updates information in the second memory based on information written in the first memory in response to the end of one transaction by the first IC module. Electronic equipment.