JP2018098646A - Information transmission system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information transmission system of novel configuration.SOLUTION: A data server stores first data (handwritten document), and converts the first data into type data by character recognition using a neural network and stores the converted type data as second data when a transmitter transmits the first data from a terminal by a facsimile device or the like. When the transmitter corrects the first data (handwritten document) as third data and desires to replace the third data with the first data transmitted before, the transmitter transmits the third data (new handwritten document) from the terminal by the facsimile device or the like again. The data server extracts the first data having a high degree of matching with the third data and being data to be replaced from among stored reception data by pattern recognition using the neural network and replaces the first data with the third data.SELECTED DRAWING: Figure 1

Description

  One embodiment of the present invention relates to an information transmission system.

  The amount of data generated in the world is increasing day by day, and the load on the data server storing the data is increasing. In addition, a large amount of data can be transmitted in a short time by data transmission using the Internet. For example, Patent Document 1 discloses information transmission by a facsimile apparatus.

US Patent Application Publication No. 2008/0024833

  While computers produce enormous amounts of digital data, human-generated information still contains a lot of analog data, such as handwritten documents transmitted by facsimile machines. Digitizing such a handwritten document is important for realizing smooth communication between the sender and the receiver.

  When information is transmitted by a facsimile machine, there is a case where it is desired to replace data later for the convenience of the sender. However, by transmitting new data, the previous data and the new data coexist in the data server, and there arises a problem that the load on the data server increases as the data amount increases.

  An object of one embodiment of the present invention is to provide a novel information transmission system.

  Alternatively, one aspect of the present invention provides a novel information transmission system that can extract past data from received data stored in a data server without any contradiction, delete the past data, and replace it with new data. This is one of the issues.

  One embodiment of the present invention is an information transmission system for transmitting data from a transmission device to a reception device via a data server, and the transmission device has a function of transmitting first data or second data. The data server includes a character data generation circuit, a pattern recognition circuit, and a storage circuit; the character data generation circuit generates a third data based on the first data; and The memory circuit has a function of generating fourth data based on the second data, and the memory circuit stores at least one of the first data and the third data, and the second data and the fourth data. And the pattern recognition circuit compares the first data and the second data and has a matching area, the first data and the third data in the memory circuit are converted into the second data. And fourth data Has the function of replacing, the receiving apparatus has a function of displaying the third data or the fourth data, which is information transmission system.

  One embodiment of the present invention is an information transmission system for transmitting data from a transmission device to a reception device via a relay data server, and the transmission device transmits first data or second data. The transmission data server, the transmission data server has a character data generation circuit, a pattern recognition circuit, and a first storage circuit, and the relay data server has a second storage circuit, The character data generation circuit has a function of generating third data based on the first data and a function of generating fourth data based on the second data. The memory circuit and the second memory circuit have a function of storing at least one of the first data and the third data, and the second data and the fourth data. Data and second data In the case of having a matching region, the first data and the third data in the first memory circuit and the second memory circuit have a function of replacing the second data and the fourth data, The receiving device is an information transmission system having a function of displaying the third data or the fourth data.

  In one embodiment of the present invention, an information transmission system in which the first data and the second data include handwritten document data, and the third data and the fourth data include type data is preferable.

  In one embodiment of the present invention, the character data generation circuit and the pattern recognition circuit are preferably an information transmission system having a product-sum operation circuit that can be used in a neural network.

  In one embodiment of the present invention, an information transmission system is preferable in which the transmission device has a function of a facsimile device and the reception device has a function of a display device.

  In one embodiment of the present invention, each of the first memory circuit and the second memory circuit includes a memory element, the memory element includes a transistor and a capacitor, and the transistor includes a channel formation region. An information transmission system with an oxide semiconductor in the layer is preferred.

  Other aspects of the present invention are described in “DETAILED DESCRIPTION OF THE INVENTION” and “Drawings” described below.

  One embodiment of the present invention can provide a novel information transmission system.

  Alternatively, one aspect of the present invention provides a novel information transmission system that can extract past data from received data stored in a data server without any contradiction, delete the past data, and replace it with new data. be able to.

The figure for demonstrating the structure of an information transmission system. The figure for demonstrating the structure of an information transmission system. The figure for demonstrating the structure of an information transmission system. The figure for demonstrating the structure of an information transmission system. The figure for demonstrating the structure of an information transmission system. The figure for demonstrating the structure of an information transmission system. The figure for demonstrating the structure of an information transmission system. The figure for demonstrating the structure of an information transmission system. The figure for demonstrating the structure of the product-sum operation circuit which an information transmission system has. The figure for demonstrating the structure of the product-sum operation circuit which an information transmission system has. The figure for demonstrating the structure of the product-sum operation circuit which an information transmission system has. The figure which shows an example of a hierarchical neural network. The figure which shows an example of a hierarchical neural network. The figure which shows an example of a hierarchical neural network. 10A and 10B each illustrate a configuration example of a circuit. 3A and 3B illustrate a structure of a memory circuit included in an information transmission system. The figure for demonstrating the structure of the display apparatus which an information transmission system has. The figure for demonstrating the structure of the display apparatus which an information transmission system has.

  Hereinafter, one embodiment of the present invention will be described with reference to the drawings. However, one embodiment of the present invention can be implemented in many different modes, and it is easily understood by those skilled in the art that the modes and details can be variously changed without departing from the spirit and scope thereof. Is done. Accordingly, the present invention should not be construed as being limited to the following description.

  A configuration example of an information transmission system which is one embodiment of the present invention will be described. The information transmission system can be applied to transmission of information such as a handwritten document by facsimile.

<Configuration example 1>
FIG. 1A is a conceptual diagram for explaining a configuration example of an information transmission system. In FIG. 1A, the data transmission unit 10, the relay unit 20, and the reception unit 30 are broadly illustrated, and arrows indicate the flow of information from the transmission unit 10 side to the reception unit 30 via the relay unit 20. This is schematically shown. Information can be appropriately read as data.

  In the transmission unit 10, a sender 11, data 12, and a transmission device 13 are illustrated. The sender 11 is a user who transmits the data 12 as an example. The data 12 is, for example, handwritten document data or the handwritten document itself. For example, the transmission device 13 is a device capable of transmitting handwritten document data, specifically, a facsimile device (which may be abbreviated as FAX device or FAX), or a combination of functions such as a scanner and a telephone. Communication device.

  In the relay unit 20, a network 21 and a data server 22 are illustrated. The network 21 is, for example, a computer network such as the Internet, a LAN (Local Area Network), or a telephone line network, which is a base of World Wide Web (WWW). For example, the data server 22 has a function of storing the data 12 transmitted from the transmission unit 10 side via the network 21 and storing the data 12 by converting the data 12 into character data by character recognition using a neural network. . In addition, for example, when the data server 22 corrects the data 12 to be another data and wants to replace it with the previously transmitted data 12 (data of the handwritten document that has already been transmitted), the sender 11 revisits it. When another data (new handwritten document data (handwritten document data to be replaced)) is transmitted from the transmission device 13, the data is matched with the data to be replaced from the accumulated data 12 by pattern recognition using a neural network. It has a function of extracting data 12 to be replaced with a high degree and replacing the data 12 with the data to be replaced.

  The receiver 30 shows a receiver 31 and a display device 32. The receiver 31 is, for example, a user who receives print data or handwritten document data based on the data 12. For example, the display device 32 has a function of displaying type data or handwritten document data. In this case, it is preferable because data can be confirmed regardless of whether it is indoors or outdoors. The display device 32 may have a function of printing type data or handwritten document data on paper and outputting the data.

  FIG. 1B is a block diagram corresponding to the conceptual diagram of the information transmission system described in FIG. FIG. 1B illustrates the sender 11, the transmission device 13, the network 21, the data server 22, and the receiver 31 illustrated in FIG. The data server 22 includes a character data generation circuit 23, a pattern recognition circuit 24, and a storage circuit 25.

  The character data generation circuit 23 is a circuit for converting into character data by character recognition using a neural network or the like based on the data 12 which is the above-described handwritten document data (transmitted handwritten document data). That is, the character data generation circuit 23 has a function of generating print data based on handwritten document data, and a function of generating print data to be replaced based on new handwritten document data (handwritten document data to be replaced). Have

  The storage circuit 25 is a circuit for storing the converted type data and the data of the handwritten document that is the source of the converted type data. That is, the storage circuit 25 has a function of storing type data, type data to be replaced, handwritten document data, or handwritten document data to be replaced. Note that the memory element included in the memory circuit 25 includes a transistor and a capacitor, and the transistor is a transistor including an oxide semiconductor in a semiconductor layer including a channel formation region (hereinafter referred to as an OS transistor). preferable. The OS transistor has a very small leakage current flowing in the off state. Therefore, data can be stored by utilizing a characteristic that charges can be held by turning off the OS transistor. A structure of the memory circuit using the OS transistor will be described later.

  The pattern recognition circuit 24 is a circuit for comparing the data of the handwritten document with the data of the handwritten document to be replaced and extracting the matched document, that is, the data of the handwritten document to be replaced. That is, the pattern recognition circuit 24 compares the handwritten document data with the handwritten document data to replace the handwritten document data and the handwritten document data when the handwritten document data has a matching area. And the type data that is paired with the handwritten document.

  When transmitting handwritten document data with a transmission device such as FAX, considering the example of the transmitted handwritten document data and the example of the handwritten document that is to be replaced, a region that completely matches a part of the data is included. Can be mentioned. This is because it is inconvenient to rewrite everything from the beginning, and it is more convenient to add more. Therefore, by executing pattern matching as a figure, it is possible to extract a handwritten document that matches with high accuracy, that is, a replacement target document. The execution of pattern matching is also effective for character recognition when generating print data from handwritten document data. The presence or absence of the above-mentioned pattern matching can omit unnecessary execution of pattern matching by allowing the transmission unit to arbitrarily select replacement of the handwritten document transmitted earlier.

  For the pattern matching, for example, a convolutional neural network based on a neural network can be used. The neural network can be mounted on a data server provided on the transmission unit side in addition to the data server on the relay unit side. After learning by the neural network on the transmission unit side, the weighting coefficient can be transmitted to the data server on the relay unit side to configure the neural network of the data server. In addition, after learning with a neural network in the data server, the weighting coefficient can be transmitted to the transmitting unit side to configure the neural network in the data server. In the neural network, signal processing is performed by a product-sum operation using a weighting factor. The configuration of the product-sum operation circuit that performs the product-sum operation will be described later.

  When determining the degree of matching between handwritten documents, when comparing character data obtained after character recognition from handwritten document data, the degree of matching varies significantly depending on the position of the added sentence or figure. It is assumed that Therefore, a configuration in which pattern matching is executed with the data of the handwritten document before the print data is preferable. There is a method of using dependent data such as a FAX number on the transmission side for the purpose of limiting the handwritten document to be searched among the data of the handwritten document in the data server. In addition, it is also effective to transmit the information by adding it to the data of the handwritten document as information such as the transmission time from the transmission side. With such a configuration, it is possible to efficiently search for data of a handwritten document to be replaced.

  The information transmission system shown in FIGS. 1A and 1B can extract past data from received data stored in a data server without contradiction, delete this, and replace it with new data. Therefore, when information is transmitted by a facsimile machine, the problem that the load on the data server increases due to an increase in the amount of data is eliminated even if the data is to be replaced later for the convenience of the sender. be able to.

  Next, an operation example of the information transmission system shown in FIGS. 1A and 1B will be described with reference to the flowchart shown in FIG. In addition, FIGS. 3A and 3B and FIGS. 4A and 4B are schematic diagrams for supplementarily explaining the data flow in the information transmission system corresponding to each step shown in FIG. FIG.

  In the flowchart of FIG. 2, the above-described “handwritten document data” is simply illustrated as “data”. “Type data” is illustrated as “type data”. In addition, “handwritten document to be replaced” is illustrated as “update data”.

  Further, in the flowchart of FIG. 2, the area separated by the dotted line and the dotted line arrow is attached to facilitate understanding of the processing steps performed by the transmission unit 10, the relay unit 20, and the reception unit 30 in FIG. is there. In FIG. 2, steps S101, S104, and S105 are steps processed by the transmission unit 10, steps S102, S103, and S106 to S109 are steps processed by the relay unit 20, and step S110 is a step processed by the reception unit 30. It is.

  In step S101, data is transmitted. For example, handwritten character data is transmitted from the transmission unit 10 side to the relay unit 20 side by a transmission device such as FAX by the sender.

  In step S102, type data is generated. For example, the character data generation circuit 23 in the data server 22 converts handwritten character data into type data by character recognition using a neural network.

  In step S103, data and type data are stored. For example, the data transmitted to the relay unit 20 side and the type data converted by the character data generation circuit 23 are stored in the storage circuit 25.

  FIG. 3A is a schematic diagram for supplementarily explaining the data flow in the information transmission system corresponding to steps S101 to S103. The dotted arrows shown in FIG. 3A visualize the flow of transmission of data 12A and type data 14A in steps S101 to S103. The data 12A corresponds to the “handwritten document data” described above. In FIG. 3A, “abc−” illustrated by handwriting (cursive) is illustrated for easy understanding. The data 12A is transmitted to the character data generation circuit 23 of the data server 22 via the transmission device 13 and the network 21. The character data generation circuit 23 generates type data 14A. The type data 14A corresponds to the “type data” described above. In FIG. 3A, “abc−” illustrated in an existing font is illustrated for easy understanding. The data 12A and the type data 14A are stored in the storage circuit 25.

  In step S104, the data change is determined. For example, when transmitting data of handwritten characters from the transmission device 13 to the data server 22 again, it is possible to arbitrarily select whether or not there is data of handwritten characters that the sender wants to replace, so that the relay unit with the data server 22 can be selected. Judgment is made. If there is no handwritten character data to be replaced by the sender, the type data sent earlier is viewed. If there is handwritten character data to be replaced by the sender, that is, update data, the process proceeds to step S105.

  In step S105, update data is transmitted. For example, handwritten character data is transmitted from the transmission unit 10 side to the relay unit 20 side by a transmission device such as FAX by the sender.

  In step S106, pattern recognition is performed. For example, the handwritten character data to be replaced and the already transmitted handwritten character data stored in the storage circuit 25 are read out to the pattern recognition circuit 24 in the data server 22.

  In step S107, it is determined whether similar data is stored. For example, the pattern recognition circuit 24 in the data server 22 determines the degree of matching of handwritten characters by pattern matching using a neural network. The degree of matching may be determined by learning with a neural network. If the degree of coincidence is high, the process proceeds to step S108. If the degree of coincidence is low, the process proceeds to step S102 in order to perform the same processing as the previously stored data 12A and type data 14A.

  FIG. 3B is a schematic diagram for supplementarily explaining the data flow in the information transmission system corresponding to steps S104 to S107. The dotted arrows shown in FIG. 3B visualize the flow of transmission of data 12A and 12B in steps S104 to S107. The data 12B corresponds to the above-described “handwritten document to be replaced”, that is, “update data”. In FIG. 3 (B), “abcd−” illustrated by handwriting (cursive) is illustrated for easy understanding. That is, it is information with “d” added, and the sender 11 wants to replace the data with “d” added. The data 12B is transmitted to the pattern recognition circuit 24 of the data server 22 via the transmission device 13 and the network 21. The pattern recognition circuit 24 reads the data 12A from the storage circuit 25 and determines the degree of matching in order to identify similar data by pattern matching. In the example of FIG. 3B, it is assumed that only the added information “d” is different and the degree of matching is high. If the degree of coincidence is low, processing may be performed in the same manner as previously stored data 12A and type data 14A.

  In step S108, the data is updated. For example, the update data transmitted to the relay unit 20 side is stored in the storage circuit 25.

  In step S109, the type data is updated. For example, the update data transmitted to the relay unit 20 side is converted by the character data generation circuit 23, and new type data corresponding to the update data is stored in the storage circuit 25.

  FIG. 4A is a schematic diagram for supplementarily explaining the data flow in the information transmission system corresponding to steps S108 to S109. The dotted arrows shown in FIG. 4A visualize the flow of transmission of data 12B and type data 14B in steps S108 to S109. The data 12B determined to have a high degree of coincidence is transmitted to the character data generation circuit 23 of the data server 22 via the transmission device 13 and the network 21. The character data generation circuit 23 generates type data 14B. The type data 14B corresponds to the “type data” described above. In FIG. 4A, “abcd-” illustrated in an existing font is illustrated for easy understanding. The data 12B and the type data 14B are stored in the storage circuit 25 by overwriting the previously saved data 12A and type data 14A.

  In step S110, the type data is browsed. For example, the receiver 31 on the receiving side displays the updated data stored in the storage circuit 25 or the type data corresponding to the updated data, and confirms the updated information.

  FIG. 4B is a schematic diagram for supplementarily explaining the data flow in the information transmission system corresponding to step S110. The dotted line arrow shown in FIG. 4B visualizes the flow of the type data 14B in step S110. The data 14B, which is the type data corresponding to the replaced handwritten character data, is read by the receiver 31 on the receiving side and displayed on a display device or the like to confirm the information. If necessary, the receiver 31 can check the information by reading the data 14B and displaying it on a display device or the like.

  As described above, the information transmission system shown in FIGS. 1A and 1B extracts past data from the received data stored in the data server without contradiction by the operations described in FIGS. You can then delete it and replace it with new data. Therefore, when information is transmitted by a facsimile machine, the problem that the load on the data server increases due to an increase in the amount of data is eliminated even if the data is to be replaced later for the convenience of the sender. be able to.

<Configuration example 2>
FIG. 5A is a conceptual diagram for explaining another configuration example of the information transmission system. In FIG. 5A, similarly to FIG. 1A, data is roughly divided into a data transmission unit 10, a relay unit 20, and a reception unit 30, and an arrow passes through the relay unit 20 from the transmission unit 10 side. The flow of information to receiving part 30 is typically expressed. In addition, although the description which overlaps with the structural example 1 was suitably omitted in consideration of readability etc., the description of the said structural example 1 shall be used about the location to abbreviate | omit.

  In the transmitter 10, a sender 11, data 12, a transmitter 13, and a data server 15 are illustrated. As an example, the data server 15 stores the data 12 transmitted from the transmission unit 10 via the network 21, converts the data 12 into character data by character recognition using a neural network, and transmits the data. Has the function of In addition, for example, when the data server 15 corrects the data 12 into another data and wants to replace it with the previously transmitted data 12 (data of the transmitted handwritten document), the sender 11 again When another data (new handwritten document data (handwritten document data to be replaced)) is transmitted from the transmission device 13, the data is matched with the data to be replaced from the accumulated data 12 by pattern recognition using a neural network. It has a function of extracting data 12 to be replaced with a high degree, replacing the data 12 with data to be replaced, and a function of replacing transmitted type data.

  In the relay unit 20, a network 21 and a data server 22 are illustrated. For example, the data server 22 has a function of storing data 12 and type data transmitted from the transmission unit 10 side via the network 21.

  The receiver 30 shows a receiver 31 and a display device 32.

  FIG. 5B is a block diagram corresponding to the conceptual diagram of the information transmission system described in FIG. 5B illustrates the sender 11, the transmission device 13, the data server 15, the network 21, the data server 22, and the receiver 31 illustrated in FIG. 5A. The data server 15 includes a character data generation circuit 16, a pattern recognition circuit 17, an additional data generation circuit 18, and a storage circuit 19. The data server 22 has a storage circuit 25.

  The character data generation circuit 16 is a circuit for converting into character data by character recognition using a neural network or the like based on the data 12 which is the above-mentioned handwritten document data (transmitted handwritten document data). That is, the character data generation circuit 16 has a function of generating print data based on handwritten document data, and a function of generating print data to be replaced based on new handwritten document data (handwritten document data to be replaced). Have

  The storage circuits 19 and 25 are circuits for storing the converted type data and the original handwritten document data together. That is, the storage circuits 19 and 25 have a function of storing type data, type data to be replaced, handwritten document data, or handwritten document data to be replaced. Note that the memory element included in the memory circuits 19 and 25 includes a transistor and a capacitor, and the transistor is preferably an OS transistor. A structure of the memory circuit using the OS transistor will be described later.

  The pattern recognition circuit 17 is a circuit for comparing the data of the handwritten document with the data of the handwritten document to be replaced and extracting the matched document, that is, the data of the handwritten document to be replaced. That is, the pattern recognition circuit 17 compares the handwritten document data with the handwritten document data to be replaced, and has a matching area, the handwritten document data to replace the handwritten document data with the type data corresponding to the handwritten document. And the type data that is paired with the handwritten document.

  The additional data generation circuit 18 generates and gives additional data for identification when replacing the data 12 and / or type data transmitted from the transmission unit 10 side via the network 21 and stored in the storage circuit 25. Have For example, the additional data includes information data such as a transmission time. With such a configuration, it is possible to efficiently search for data of a handwritten document to be replaced.

  The information transmission system shown in FIGS. 5 (A) and 5 (B) extracts past data from the received data stored in the data servers 15 and 22 without contradiction, deletes this data, and replaces it with new data. Can do. Therefore, when information is transmitted by a facsimile machine, the problem that the load on the data server increases due to an increase in the amount of data is eliminated even if the data is to be replaced later for the convenience of the sender. be able to.

  Next, an operation example of the information transmission system shown in FIGS. 5A and 5B will be described with reference to the flowchart shown in FIG. In addition, FIGS. 7A and 7B and FIGS. 8A and 8B are schematic diagrams for supplementarily explaining the data flow in the information transmission system corresponding to each step shown in FIG. FIG.

  In the flowchart of FIG. 6, the “handwritten document data” described above is simply illustrated as “data”. “Type data” is illustrated as “type data”. In addition, “handwritten document to be replaced” is illustrated as “update data”. “Additional data” is illustrated as “tag data”.

  Further, in the flowchart of FIG. 6, the area separated by the dotted line and the dotted line arrow is attached to make it easy to understand the processing steps performed by the transmission unit 10, the relay unit 20, and the reception unit 30 in FIG. is there. In FIG. 6, steps S201 to S203 and S205 to S211 are steps processed by the transmission unit 10, steps S204 and S212 are steps processed by the relay unit 20, and step S213 is a step processed by the reception unit 30. .

  In step S201, type data is generated. For example, the character data generation circuit 16 in the data server 15 converts handwritten character data into type data by character recognition using a neural network.

  In step S202, data is stored. For example, it is stored in the storage circuit 19 in the data server 15.

  In step S203, type data is transmitted. For example, the print data is transmitted from the transmission unit 10 side to the relay unit 20 side.

  Step S204 stores type data. For example, the type data is stored in the storage circuit 25 in the data server 22.

  FIG. 7A is a schematic diagram for supplementarily explaining the data flow in the information transmission system corresponding to steps S201 to S204. The dotted line arrows shown in FIG. 7A visualize the flow of transmission of data 12A and type data 14A in steps S201 to S204. The data 12A is transmitted to the character data generation circuit 16 of the data server 15. The character data generation circuit 16 generates type data 14A. Data 12A and type data 14A are stored in storage circuit 19. The type data 14A is stored in the storage circuit 25. The storage circuit 25 may store the data 12A in accordance with the type data 14A.

  In step S205, the data change is determined. For example, when transmitting data of handwritten characters from the transmission device 13 to the data server 22 again, the data server 15 makes a determination by arbitrarily selecting whether or not there is handwritten character data that the sender wants to replace. Is called. If there is no handwritten character data to be replaced by the sender, the type data sent earlier is viewed. If there is handwritten character data to be replaced by the sender, that is, update data, the process proceeds to step S206.

  In step S206, pattern recognition is performed. For example, the handwritten character data to be replaced and the already transmitted handwritten character data stored in the storage circuit 19 are read out to the pattern recognition circuit 17 in the data server 15.

  In step S207, it is determined whether similar data is stored. For example, the pattern recognition circuit 17 in the data server 15 determines the degree of matching of handwritten characters by pattern matching using a neural network. The degree of matching may be determined by learning with a neural network. If the degree of coincidence is high, the process proceeds to step S208. If the degree of coincidence is low, the process proceeds to step S201 in order to perform the same processing as the previously stored data 12A and type data 14A.

  FIG. 7B is a schematic diagram for supplementarily explaining the data flow in the information transmission system corresponding to steps S205 to S207. The dotted arrows shown in FIG. 7B visualize the flow of transmission of data 12A and 12B in steps S205 to S207. The data 12B is transmitted to the pattern recognition circuit 17 of the data server 15. The pattern recognition circuit 17 reads the data 12A from the storage circuit 19 and determines the degree of matching in order to identify similar data by pattern matching. In the example of FIG. 7B, it is assumed that only the added information “d” is different and the degree of matching is high. If the degree of coincidence is low, processing may be performed in the same manner as previously stored data 12A and type data 14A.

  In step S208, update data is transmitted. For example, the data 12A stored in the storage circuit 19 in the data server 15 is updated to the data 12B.

  In step S209, the type data is updated. For example, the update data is converted by the character data generation circuit 16, and new type data corresponding to the update data is stored in the storage circuit 19.

  In step S210, tag data is generated. For example, tag data corresponding to data to be replaced among data stored in the storage circuit 25 in the data server 22 is generated.

  In step S211, type data and tag data are transmitted. For example, it is transmitted from the transmission unit 10 side to the relay unit 20 side via the network 21.

  In step S212, the type data is updated. For example, new type data corresponding to the update data transmitted to the relay unit 20 side is stored in the storage circuit 25.

  FIG. 8A is a schematic diagram for supplementarily explaining the data flow in the information transmission system corresponding to steps S208 to S212. The dotted arrows shown in FIG. 8A visualize the flow of transmission of data 12B and type data 14B in steps S208 to S212. The data 12B determined to have a high degree of coincidence is transmitted to the character data generation circuit 16 of the data server 15. The character data generation circuit 16 generates type data 14B. The data 12B and the type data 14B are stored in the storage circuit 19 by overwriting the previously saved data 12A and type data 14A. The type data 14B is attached with the tag data of the additional data generation circuit 18 and transmitted to the storage circuit 25 of the data server 22, and the type data 14A corresponding to the tag data is replaced with the type data 14B and stored.

  In step S213, type data is browsed. For example, the receiver 31 on the receiving side displays the type data corresponding to the update data stored in the storage circuit 25 and confirms the updated information.

  FIG. 8B is a schematic diagram for supplementarily explaining the data flow in the information transmission system corresponding to step S213. The dotted line arrow shown in FIG. 8B is a visualization of the flow of type data 14B in step S213. The data 14B, which is the type data corresponding to the replaced handwritten character data, is read by the receiver 31 on the receiving side and displayed on a display device or the like to confirm the information. If necessary, the receiver 31 can check the information by reading the data 14B and displaying it on a display device or the like.

  As described above, the information transmission system shown in FIGS. 5A and 5B extracts past data from the received data stored in the data server without contradiction by the operation described in FIGS. You can then delete it and replace it with new data. Therefore, when information is transmitted by a facsimile machine, the problem that the load on the data server increases due to an increase in the amount of data is eliminated even if the data is to be replaced later for the convenience of the sender. be able to.

<Configuration example of product-sum operation circuit applicable to character data generation circuit and pattern recognition circuit>
FIG. 9 shows an example of the configuration of a product-sum operation circuit used for character recognition or pattern matching using a neural network in the character data generation circuit and the pattern recognition circuit. The product-sum operation circuit 100 illustrated in FIG. 9 includes a storage circuit 101, a reference storage circuit 102, a current source circuit 103, a current sink circuit 104, and a current source circuit 105.

  The memory circuit 101 includes a memory cell MC exemplified by a memory cell MC [i, j] and a memory cell MC [i + 1, j]. Each memory cell MC includes an element having a function of converting an input potential into a current. As an element having the above function, for example, an active element such as a transistor can be used. FIG. 9 illustrates a case where each memory cell MC includes a transistor Tr1.

  A first analog potential is input to the memory cell MC from the wiring WD exemplified by the wiring WD [j]. The memory cell MC has a function of generating a first analog current corresponding to the first analog potential. Specifically, the drain current of the transistor Tr1 obtained when the first analog potential is supplied to the gate of the transistor Tr1 can be used as the first analog current. Hereinafter, the current flowing through the memory cell MC [i, j] is I [i, j], and the current flowing through the memory cell MC [i + 1, j] is I [i + 1, j].

  Note that when the transistor Tr1 operates in the saturation region, the drain current does not depend on the voltage between the source and the drain, but is controlled by the difference between the gate voltage and the threshold voltage. Therefore, it is desirable to operate the transistor Tr1 in the saturation region. In order to operate the transistor Tr1 in the saturation region, it is assumed that the gate voltage and the voltage between the source and the drain are appropriately set to a voltage within a range in which the transistor Tr1 operates in the saturation region.

  Specifically, in the product-sum operation circuit 100 illustrated in FIG. 9, the first analog potential Vx [i, j] or the first analog potential Vx [i] from the wiring WD [j] to the memory cell MC [i, j]. , J] is input. The memory cell MC [i, j] has a function of generating a first analog current corresponding to the first analog potential Vx [i, j]. That is, in this case, the current I [i, j] of the memory cell MC [i, j] corresponds to the first analog current.

  Specifically, in the product-sum operation circuit 100 illustrated in FIG. 9, the first analog potential Vx [i + 1, j] or the first analog potential Vx is connected to the memory cell MC [i + 1, j] from the wiring WD [j]. A potential corresponding to [i + 1, j] is input. The memory cell MC [i + 1, j] has a function of generating a first analog current corresponding to the first analog potential Vx [i + 1, j]. That is, in this case, the current I [i + 1, j] of the memory cell MC [i + 1, j] corresponds to the first analog current.

  The memory cell MC has a function of holding the first analog potential. That is, it can be said that the memory cell MC has a function of holding the first analog current corresponding to the first analog potential by holding the first analog potential.

  In addition, the second analog potential is input to the memory cell MC from the wiring RW exemplified by the wiring RW [i] and the wiring RW [i + 1]. The memory cell MC has a function of adding the second analog potential or a potential corresponding to the second analog potential to the already held first analog potential, and a third analog potential obtained by the addition. Holding function. The memory cell MC has a function of generating a second analog current corresponding to the third analog potential. That is, it can be said that the memory cell MC has a function of holding the second analog current corresponding to the third analog potential by holding the third analog potential.

  Specifically, in the product-sum operation circuit 100 illustrated in FIG. 9, the second analog potential Vw [i, j] is input to the memory cell MC [i, j] from the wiring RW [i]. The memory cell MC [i, j] has a function of holding a third analog potential corresponding to the first analog potential Vx [i, j] and the second analog potential Vw [i, j]. The memory cell MC [i, j] has a function of generating a second analog current corresponding to the third analog potential. That is, in this case, the current I [i, j] of the memory cell MC [i, j] corresponds to the second analog current.

  In the product-sum operation circuit 100 illustrated in FIG. 9, the second analog potential Vw [i + 1, j] is input to the memory cell MC [i + 1, j] from the wiring RW [i + 1]. The memory cell MC [i + 1, j] has a function of holding a third analog potential corresponding to the first analog potential Vx [i + 1, j] and the second analog potential Vw [i + 1, j]. The memory cell MC [i + 1, j] has a function of generating a second analog current corresponding to the third analog potential. That is, in this case, the current I [i + 1, j] of the memory cell MC [i + 1, j] corresponds to the second analog current.

  The current I [i, j] flows between the wiring BL [j] and the wiring VR [j] through the memory cell MC [i, j]. The current I [i + 1, j] flows between the wiring BL [j] and the wiring VR [j] through the memory cell MC [i + 1, j]. Therefore, a current I [j] corresponding to the sum of the current I [i, j] and the current I [i + 1, j] is passed through the memory cell MC [i, j] and the memory cell MC [i + 1, j]. It flows between the wiring BL [j] and the wiring VR [j].

  The reference memory circuit 102 includes a memory cell MCR exemplified by a memory cell MCR [i] and a memory cell MCR [i + 1]. A first reference potential VPR is input to the memory cell MCR from the wiring WDREF. The memory cell MCR has a function of generating a first reference current corresponding to the first reference potential VPR. Hereinafter, the current flowing through the memory cell MCR [i] is referred to as IREF [i], and the current flowing through the memory cell MCR [i + 1] is referred to as IREF [i + 1].

  Specifically, in the product-sum operation circuit 100 illustrated in FIG. 9, the first reference potential VPR is input to the memory cell MCR [i] from the wiring WDREF [i]. The memory cell MCR [i] has a function of generating a first reference current corresponding to the first reference potential VPR. That is, in this case, the current IREF [i] of the memory cell MCR [i] corresponds to the first reference current.

  In the product-sum operation circuit 100 illustrated in FIG. 9, the first reference potential VPR is input to the memory cell MCR [i + 1] from the wiring WDREF. The memory cell MCR [i + 1] has a function of generating a first reference current corresponding to the first reference potential VPR. That is, in this case, the current IREF [i + 1] of the memory cell MCR [i + 1] corresponds to the first reference current.

  The memory cell MCR has a function of holding the first reference potential VPR. That is, it can be said that the memory cell MCR has a function of holding the first reference current corresponding to the first reference potential VPR by holding the first reference potential VPR.

  In addition, the second analog potential is input to the memory cell MCR from the wiring RW exemplified by the wiring RW [i] and the wiring RW [i + 1]. The memory cell MCR adds the second analog potential or a potential corresponding to the second analog potential to the already held first reference potential VPR, and holds the second reference potential obtained by the addition. It has the function to do. The memory cell MCR has a function of generating a second reference current corresponding to the second reference potential. That is, it can be said that the memory cell MCR has a function of holding the second reference potential corresponding to the second reference potential by holding the second reference potential.

  Specifically, in the product-sum operation circuit 100 illustrated in FIG. 9, the second analog potential Vw [i, j] is input to the memory cell MCR [i] from the wiring RW [i]. The memory cell MCR [i] has a function of holding a second reference potential corresponding to the first reference potential VPR and the second analog potential Vw [i, j]. The memory cell MCR [i] has a function of generating a second reference current corresponding to the second reference potential. That is, in this case, the current IREF [i] of the memory cell MCR [i] corresponds to the second reference current.

  In the product-sum operation circuit 100 illustrated in FIG. 9, the second analog potential Vw [i + 1, j] is input to the memory cell MCR [i + 1] from the wiring RW [i + 1]. The memory cell MCR [i + 1] has a function of holding a second reference potential corresponding to the first reference potential VPR and the second analog potential Vw [i + 1, j]. The memory cell MCR [i + 1] has a function of generating a second reference current corresponding to the second reference potential. That is, in this case, the current IREF [i + 1] of the memory cell MCR [i + 1] corresponds to the second reference current.

  Then, the current IREF [i] flows between the wiring BLREF and the wiring VRREF through the memory cell MCR [i]. The current IREF [i + 1] flows between the wiring BLREF and the wiring VRREF through the memory cell MCR [i + 1]. Therefore, the current IREF corresponding to the sum of the current IREF [i] and the current IREF [i + 1] flows between the wiring BLREF and the wiring VRREF via the memory cell MCR [i] and the memory cell MCR [i + 1]. Become.

  The current source circuit 105 has a function of supplying a current having the same value as the current IREF flowing through the wiring BLREF or a current corresponding to the current IREF to the wiring BL. When setting an offset current, which will be described later, a current flowing between the wiring BL [j] and the wiring VR [j] through the memory cell MC [i, j] and the memory cell MC [i + 1, j]. When I [j] is different from the current IREF flowing between the wiring BLREF and the wiring VRREF via the memory cell MCR [i] and the memory cell MCR [i + 1], the difference current is the current source circuit 103 or the current sink circuit 104. Flowing into.

  Specifically, when the current I [j] is larger than the current IREF, the current source circuit 103 has a function of generating a current ΔI [j] corresponding to the difference between the current I [j] and the current IREF. The current source circuit 103 has a function of supplying the generated current ΔI [j] to the wiring BL [j]. That is, it can be said that the current source circuit 103 has a function of holding the current ΔI [j].

  When the current I [j] is smaller than the current IREF, the current sink circuit 104 has a function of generating a current ΔI [j] corresponding to the difference between the current I [j] and the current IREF. The current sink circuit 104 has a function of drawing the generated current ΔI [j] from the wiring BL [j]. That is, it can be said that the current sink circuit 104 has a function of holding the current ΔI [j].

  Next, an example of the operation of the product-sum operation circuit 100 illustrated in FIG. 9 will be described.

  First, a potential corresponding to the first analog potential is stored in the memory cell MC [i, j]. Specifically, a potential VPR−Vx [i, j] obtained by subtracting the first analog potential Vx [i, j] from the first reference potential VPR is set to the memory cell MC [i] via the wiring WD [j]. , J]. In the memory cell MC [i, j], the potential VPR−Vx [i, j] is held. In the memory cell MC [i, j], a current I [i, j] corresponding to the potential VPR−Vx [i, j] is generated. For example, the first reference potential VPR is a high level potential higher than the ground potential. Specifically, it is desirable that the potential is higher than the ground potential and is approximately equal to or lower than the high-level potential VDD supplied to the current source circuit 105.

  Further, the first reference potential VPR is stored in the memory cell MCR [i]. Specifically, the potential VPR is input to the memory cell MCR [i] through the wiring WDREF. In the memory cell MCR [i], the potential VPR is held. In the memory cell MCR [i], a current IREF [i] corresponding to the potential VPR is generated.

  In addition, a potential corresponding to the first analog potential is stored in the memory cell MC [i + 1, j]. Specifically, the potential VPR−Vx [i + 1, j] obtained by subtracting the first analog potential Vx [i + 1, j] from the first reference potential VPR is connected to the memory cell MC [i + 1] via the wiring WD [j]. , J]. In the memory cell MC [i + 1, j], the potential VPR−Vx [i + 1, j] is held. Further, in the memory cell MC [i + 1, j], a current I [i + 1, j] corresponding to the potential VPR−Vx [i + 1, j] is generated.

  In addition, the first reference potential VPR is stored in the memory cell MCR [i + 1]. Specifically, the potential VPR is input to the memory cell MCR [i + 1] through the wiring WDREF. In the Mori cell MCR [i + 1], the potential VPR is held. In the memory cell MCR [i + 1], a current IREF [i + 1] corresponding to the potential VPR is generated.

  In the above operation, the wiring RW [i] and the wiring RW [i + 1] are set to the reference potential. For example, a ground potential, a low-level potential VSS lower than the reference potential, or the like can be used as the reference potential. Alternatively, when a potential between the potential VSS and the potential VDD is used as the reference potential, the potential of the wiring RW can be higher than the ground potential even if the second analog potential Vw is positive or negative, so that signal generation is facilitated. This is preferable because product operation for positive and negative potentials can be performed.

  Through the above operation, currents that are combined with currents generated in the memory cells MC connected to the wiring BL [j] flow through the wiring BL [j]. Specifically, in FIG. 9, the current I [i, j] generated in the memory cell MC [i, j] is combined with the current I [i + 1, j] generated in the memory cell MC [i + 1, j]. Current I [j] flows. Further, by the above operation, currents that are combined with currents generated in the memory cells MCR connected to the wiring BLREF flow through the wiring BLREF. Specifically, in FIG. 9, a current IREF that is a combination of the current IREF [i] generated in the memory cell MCR [i] and the current IREF [i + 1] generated in the memory cell MCR [i + 1] flows.

  Next, from the difference between the current I [j] obtained by the first analog potential and the current IREF obtained by the first reference potential, with the potentials of the wiring RW [i] and the wiring RW [i + 1] being the reference potential. The obtained offset current Ioffset [j] is held in the current source circuit 103 or the current sink circuit 104.

  Specifically, when the current I [j] is larger than the current IREF, the current source circuit 103 supplies the current Ioffset [j] to the wiring BL [j]. That is, the current ICM [j] flowing through the current source circuit 103 corresponds to the current Ioffset [j]. The value of the current ICM [j] is held in the current source circuit 103. On the other hand, when the current I [j] is smaller than the current IREF, the current sink circuit 104 draws the current Ioffset [j] from the wiring BL [j]. That is, the current ICP [j] flowing through the current sink circuit 104 corresponds to the current Ioffset [j]. The value of the current ICP [j] is held in the current sink circuit 104.

  Then, according to the second analog potential or the second analog potential so as to be added to the first analog potential already held in the memory cell MC [i, j] or the potential according to the first analog potential. The stored potential is stored in the memory cell MC [i, j]. Specifically, by setting the potential of the wiring RW [i] to a potential higher by Vw [i] than the reference potential, the second analog potential Vw [i] is stored in the memory via the wiring RW [i]. Input to cell MC [i, j]. In the memory cell MC [i, j], the potential VPR−Vx [i, j] + Vw [i] is held. In the memory cell MC [i, j], a current I [i, j] corresponding to the potential VPR−Vx [i, j] + Vw [i] is generated.

  Further, according to the second analog potential or the second analog potential so as to be added to the first analog potential already held in the memory cell MC [i + 1, j] or the potential according to the first analog potential. The stored potential is stored in the memory cell MC [i + 1, j]. Specifically, by setting the potential of the wiring RW [i + 1] higher by Vw [i + 1] than the reference potential, the second analog potential Vw [i + 1] is stored in the memory through the wiring RW [i + 1]. It is input to the cell MC [i + 1, j]. In the memory cell MC [i + 1, j], the potential VPR−Vx [i + 1, j] + Vw [i + 1] is held. In the memory cell MC [i + 1, j], a current I [i + 1, j] corresponding to the potential VPR−Vx [i + 1, j] + Vw [i + 1] is generated.

  Note that in the case where the transistor Tr1 that operates in the saturation region is used as an element that converts potential into current, the potential of the wiring RW [i] is Vw [i], and the potential of the wiring RW [i + 1] is Vw [i + 1]. Assuming that the drain current of the transistor Tr1 included in the memory cell MC [i, j] corresponds to the current I [i, j], the second analog current is expressed by the following Expression 1. Note that k is a coefficient and Vth is a threshold voltage of the transistor Tr1.

I [i, j] = k (Vw [i] −Vth + VPR−Vx [i, j]) ² (1)

  Further, since the drain current of the transistor Tr1 included in the memory cell MCR [i] corresponds to the current IREF [i], the second reference current is expressed by the following Expression 2.

IREF [i] = k (Vw [i] −Vth + VPR) ² (2)

  The current I [j] corresponding to the sum of the current I [i, j] flowing through the memory cell MC [i, j] and the current I [i + 1, j] flowing through the memory cell MC [i + 1, j] is: I [j] = ΣiI [i, j], and the current IREF corresponding to the sum of the current IREF [i] flowing through the memory cell MCR [i] and the current IREF [i + 1] flowing through the memory cell MCR [i + 1] is , IREF = ΣiIREF [i], and the current ΔI [j] corresponding to the difference is expressed by the following Equation 3.

  ΔI [j] = IREF−I [j] = ΣiIREF [i] −ΣiI [i, j] (3)

  From Equation 1, Equation 2, and Equation 3, current ΔI [j] is derived as in Equation 4 below.

ΔI [j]
= Σi {k (Vw [i] −Vth + VPR) ² −k (Vw [i] −Vth + VPR−Vx [i, j]) ² }
= 2kΣi (Vw [i] · Vx [i, j]) − 2kΣi (Vth−VPR) · Vx [i, j] −kΣiVx [i, j] ² (4)

  In Equation 4, the term represented by 2kΣi (Vw [i] · Vx [i, j]) is the product of the first analog potential Vx [i, j] and the second analog potential Vw [i], This corresponds to the sum of the product of one analog potential Vx [i + 1, j] and the second analog potential Vw [i + 1].

  Further, Ioffset [j] is when the potential of the wiring RW [i] is all set as the reference potential, that is, when the second analog potential Vw [i] is 0 and the second analog potential Vw [i + 1] is 0. If the current ΔI [j] is, then the following equation 5 is derived from the equation 4.

Ioffset [j] = − 2kΣi (Vth−VPR) · Vx [i, j] −kΣiVx [i, j] ² (5)

  Therefore, from Expressions 3 to 5, 2kΣi (Vw [i] · Vx [i, j]) corresponding to the product sum of the first analog current and the second analog current is expressed by Expression 6 below. I understand that

  2kΣi (Vw [i] · Vx [i, j]) = IREF−I [j] −Ioffset [j] (6)

  When the sum of currents flowing through the memory cell MC is current I [j], the sum of currents flowing through the memory cell MCR is current IREF, and the current flowing through the current source circuit 103 or the current sink circuit 104 is current Ioffset [j]. When the potential of the wiring RW [i] is Vw [i] and the potential of the wiring RW [i + 1] is Vw [i + 1], the current Iout [j] that flows out of the wiring BL [j] is IREF−I [j] −. Ioffset [j]. From Expression 6, the current Iout [j] is 2kΣi (Vw [i] · Vx [i, j]), and the first analog potential Vx [i, j] and the second analog potential Vw [i] are It can be seen that this corresponds to the sum of the product and the product of the second analog potential Vx [i + 1, j] and the second analog potential Vw [i + 1].

  Note that the transistor Tr1 is desirably operated in a saturation region, but even if the operation region of the transistor Tr1 is different from an ideal saturation region, the first analog potential Vx [i, j] and the second analog potential are A current corresponding to the sum of the product of Vw [i] and the product of the second analog potential Vx [i + 1, j] and the second analog potential Vw [i + 1] is obtained without any problem with accuracy within a desired range. If it can, the transistor Tr1 can be regarded as operating in the saturation region.

  With the configuration of the product-sum operation circuit shown in FIG. 9, the operation process can be executed without converting it into digital data, so that the circuit scale of the semiconductor device can be reduced. Alternatively, by using the configuration of the product-sum operation circuit shown in FIG. 9, the operation process can be executed without being converted into digital data, so that the time required for the operation process can be reduced. Alternatively, the configuration of the product-sum operation circuit illustrated in FIG. 9 can reduce the power consumption of the semiconductor device while suppressing the time required for the operation processing.

  Next, examples of specific structures of the memory circuit 101, the reference memory circuit 102, the current source circuit 103, the current sink circuit 104, and the current source circuit 105 will be described with reference to FIGS.

  FIG. 10 shows, as an example, a specific circuit configuration and connection relationship between an arbitrary memory cell MC of 2 rows and 2 columns and an arbitrary memory cell MCR of 2 rows and 1 column. Specifically, in FIG. 10, the memory cell MC [i, j] in the i-th row and j-th column, the memory cell MC [i + 1, j] in the i + 1-th row and j-th column, and the memory cell MC [i in the i-th row j + 1-th column. , J + 1] and the memory cell MC [i + 1, j + 1] in the (i + 1) th row and j + 1th column. Specifically, FIG. 10 illustrates the memory cell MCR [i] in the i-th row and the memory cell MCR [i + 1] in the i + 1-th row.

  The memory cell MC [i, j] in the i-th row, the memory cell MC [i, j + 1], and the memory cell MCR [i] are connected to the wiring RW [i] and the wiring WW [i]. The memory cell MC [i + 1, j] in the i + 1th row, the memory cell MC [i + 1, j + 1], and the memory cell MCR [i + 1] are connected to the wiring RW [i + 1] and the wiring WW [i + 1]. Yes.

  The memory cell MC [i, j] in the j-th column and the memory cell MC [i + 1, j] are connected to the wiring WD [j], the wiring VR [j], and the wiring BL [j]. The memory cell MC [i, j + 1] in the j + 1 column and the memory cell MC [i + 1, j + 1] are connected to the wiring WD [j + 1], the wiring VR [j + 1], and the wiring BL [j + 1]. . The memory cell MCR [i] and the memory cell MCR [i + 1] in the (i + 1) th row are connected to the wiring WDREF, the wiring VRREF, and the wiring BLREF.

  Each memory cell MC and each memory cell MCR includes a transistor Tr1, a transistor Tr2, and a capacitor C1. The transistor Tr2 has a function of controlling input of the first analog potential to the memory cell MC or the memory cell MCR. The transistor Tr1 has a function of generating an analog current in accordance with the potential input to the gate. The capacitor C1 has a second analog potential or a potential corresponding to the second analog potential to the first analog potential or the potential corresponding to the first analog potential held in the memory cell MC or the memory cell MCR. Has the function of adding.

  Specifically, in the memory cell MC illustrated in FIG. 10, the transistor Tr1 has a gate connected to the wiring WW, one of the source and the drain connected to the wiring WD, and the other of the source and the drain connected to the gate of the transistor Tr2. ing. In the transistor Tr2, one of a source and a drain is connected to the wiring VR, and the other of the source and the drain is connected to the wiring BL. In the capacitor C1, the first electrode is connected to the wiring RW, and the second electrode is connected to the gate of the transistor Tr2.

  In the memory cell MCR shown in FIG. 10, the transistor Tr1 has a gate connected to the wiring WW, one of the source and the drain connected to the wiring WDREF, and the other of the source and the drain connected to the gate of the transistor Tr2. . In the transistor Tr2, one of a source and a drain is connected to the wiring VRREF, and the other of the source and the drain is connected to the wiring BLREF. In the capacitor C1, the first electrode is connected to the wiring RW, and the second electrode is connected to the gate of the transistor Tr2.

  In the memory cell MC, when the gate of the transistor Tr1 is a node N, in the memory cell MC, the first analog potential is input to the node N through the transistor Tr2. Then, when the transistor Tr2 is turned off, the node N is in a floating state. The node N holds the first analog potential or the potential corresponding to the first analog potential. In the memory cell MC, when the node N is in a floating state, the second analog potential input to the first electrode of the capacitor C1 is applied to the node N. With the above operation, the node N has a potential obtained by adding the second analog potential or the potential corresponding to the second analog potential to the potential corresponding to the first analog potential or the first analog potential. Become.

  Note that since the potential of the first electrode of the capacitor C1 is applied to the node N via the capacitor C1, in practice, the amount of change in the potential of the first electrode is directly reflected in the amount of change in the potential of the node N. It is not done. Specifically, by multiplying the amount of change in potential of the first electrode by a coupling coefficient that is uniquely determined from the capacitance value of the capacitive element C1, the capacitance value of the gate capacitance of the transistor Tr1, and the capacitance value of the parasitic capacitance. The amount of change in the potential of the node N can be accurately calculated. Hereinafter, in order to make the description easy to understand, it is assumed that the change amount of the potential of the first electrode is reflected in the change amount of the potential of the node N.

  The drain current of the transistor Tr1 is determined according to the potential of the node N. Therefore, when the potential of the node N is held by turning off the transistor Tr2, the value of the drain current of the transistor Tr1 is also held. The drain current reflects the first analog potential and the second analog potential.

  Further, when the gate of the transistor Tr1 in the memory cell MCR is the node NREF, in the memory cell MCR, a first reference potential or a potential corresponding to the first reference potential is input to the node NREF through the transistor Tr2, and then the transistor When Tr2 is turned off, the node NREF enters a floating state, and the first reference potential or a potential corresponding to the first reference potential is held at the node NREF. In the memory cell MCR, when the node NREF is in a floating state, the second analog potential input to the first electrode of the capacitor C1 is applied to the node NREF. Through the above operation, the node NREF has the potential obtained by adding the second analog potential or the potential corresponding to the second analog potential to the potential corresponding to the first reference potential or the first reference potential. Become.

  The drain current of the transistor Tr1 is determined according to the potential of the node NREF. Therefore, when the potential of the node NREF is held by turning off the transistor Tr2, the value of the drain current of the transistor Tr1 is also held. The drain current reflects the first reference potential and the second analog potential.

  If the drain current flowing through the transistor Tr2 of the memory cell MC [i, j] is current I [i, j], and the drain current flowing through the transistor Tr2 of the memory cell MC [i + 1, j] is current I [i + 1, j]. The sum of the currents supplied from the wiring BL [j] to the memory cell MC [i, j] and the memory cell MC [i + 1, j] is the current I [j]. The drain current flowing through the transistor Tr2 of the memory cell MC [i, j + 1] is defined as a current I [i, j + 1], and the drain current flowing through the transistor Tr2 of the memory cell MC [i + 1, j + 1] is defined as a current I [i + 1, j + 1]. Then, a sum of currents supplied from the wiring BL [j + 1] to the memory cell MC [i, j + 1] and the memory cell MC [i + 1, j + 1] is a current I [j + 1]. Further, when the drain current flowing through the transistor Tr2 of the memory cell MCR [i] is current IREF [i] and the drain current flowing through the transistor Tr2 of the memory cell MCR [i + 1] is current IREF [i + 1], the memory cell is connected to the wiring BLREF. The sum of the currents supplied to MCR [i] and memory cell MCR [i + 1] is current IREF.

  The current source circuit 103 illustrated in FIG. 10 includes a current source circuit 103 [j] corresponding to the memory cell MC in the jth column and a current source circuit 103 [j + 1] corresponding to the memory cell MC in the j + 1th column. . The current sink circuit 104 shown in FIG. 10 includes a current sink circuit 104 [j] corresponding to the memory cell MC in the jth column and a current sink circuit 104 [j + 1] corresponding to the memory cell MC in the j + 1th column. Have.

  The current source circuit 103 [j] and the current sink circuit 104 [j] are connected to the wiring BL [j]. In addition, the current source circuit 103 [j + 1] and the current sink circuit 104 [j + 1] are connected to the wiring BL [j + 1].

  The current source circuit 105 is connected to the wiring BL [j], the wiring BL [j + 1], and the wiring BLREF. The current source circuit 105 has a function of supplying the current IREF to the wiring BLREF and a function of supplying the same current as the current IREF or a current corresponding to the current IREF to each of the wiring BL [j] and the wiring BL [j + 1]. Have

  Specifically, the current source circuit 103 [j] and the current source circuit 103 [j + 1] each include transistors Tr7 to Tr9 and a capacitor C3. When setting the offset current, in the current source circuit 103 [j], the transistor Tr7 has a current corresponding to the difference between the current I [j] and the current IREF when the current I [j] is larger than the current IREF. It has a function of generating ICM [j]. In the current source circuit 103 [j + 1], the transistor Tr7 generates a current ICM [j + 1] corresponding to the difference between the current I [j + 1] and the current IREF when the current I [j + 1] is larger than the current IREF. It has a function. The current ICM [j] and the current ICM [j + 1] are supplied from the current source circuit 103 [j] and the current source circuit 103 [j + 1] to the wiring BL [j] and the wiring BL [j + 1].

  In the current source circuit 103 [j] and the current source circuit 103 [j + 1], in the transistor Tr7, one of the source and the drain is connected to the corresponding wiring BL, and the other of the source and the drain is supplied with a predetermined potential. Connected to wiring. In the transistor Tr8, one of the source and the drain is connected to the wiring BL, and the other of the source and the drain is connected to the gate of the transistor Tr7. In the transistor Tr9, one of the source and the drain is connected to the gate of the transistor Tr7, and the other of the source and the drain is connected to a wiring to which a predetermined potential is supplied. In the capacitor C3, the first electrode is connected to the gate of the transistor Tr7, and the second electrode is connected to a wiring to which a predetermined potential is supplied.

  The gate of the transistor Tr8 is connected to the wiring OSM, and the gate of the transistor Tr9 is connected to the wiring ORM.

  Note that FIG. 10 illustrates a case where the transistor Tr7 is a p-channel type and the transistors Tr8 and Tr9 are n-channel type.

  The current sink circuit 104 [j] and the current sink circuit 104 [j + 1] include transistors Tr4 to Tr6 and a capacitor C4, respectively. When setting the offset current, in the current sink circuit 104 [j], the transistor Tr4 has a current corresponding to the difference between the current I [j] and the current IREF when the current I [j] is smaller than the current IREF. It has a function of generating ICP [j]. In the current sink circuit 104 [j + 1], the transistor Tr4 generates a current ICP [j + 1] corresponding to the difference between the current I [j + 1] and the current IREF when the current I [j + 1] is smaller than the current IREF. It has a function. The current ICP [j] and the current ICP [j + 1] are drawn from the wiring BL [j] and the wiring BL [j + 1] to the current sink circuit 104 [j] and the current sink circuit 104 [j + 1].

  Note that the current ICM [j] and the current ICP [j] correspond to Ioffset [j]. Note that the current ICM [j + 1] and the current ICP [j + 1] correspond to Ioffset [j + 1].

  In the current sink circuit 104 [j] and the current sink circuit 104 [j + 1], in the transistor Tr4, one of the source and the drain is connected to the corresponding wiring BL, and the other of the source and the drain is supplied with a predetermined potential. Connected to the wiring. In the transistor Tr5, one of the source and the drain is connected to the wiring BL, and the other of the source and the drain is connected to the gate of the transistor Tr4. In the transistor Tr6, one of the source and the drain is connected to the gate of the transistor Tr4, and the other of the source and the drain is connected to a wiring to which a predetermined potential is supplied. In the capacitor C4, the first electrode is connected to the gate of the transistor Tr4, and the second electrode is connected to a wiring to which a predetermined potential is supplied.

  The gate of the transistor Tr5 is connected to the wiring OSP, and the gate of the transistor Tr6 is connected to the wiring ORP.

  Note that FIG. 10 illustrates the case where the transistors Tr4 to Tr6 are n-channel type.

  The current source circuit 105 includes a transistor Tr10 corresponding to the wiring BL and a transistor Tr11 corresponding to the wiring BLREF. Specifically, the current source circuit 105 illustrated in FIG. 10 includes, as the transistor Tr10, a transistor Tr10 [j] corresponding to the wiring BL [j] and a transistor Tr10 [j + 1] corresponding to the wiring BL [j + 1]. Is illustrated.

  The gate of the transistor Tr10 is connected to the gate of the transistor Tr11. In the transistor Tr10, one of the source and the drain is connected to the corresponding wiring BL, and the other of the source and the drain is connected to a wiring to which a predetermined potential is supplied. In the transistor Tr11, one of a source and a drain is connected to the wiring BLREF, and the other of the source and the drain is connected to a wiring to which a predetermined potential is supplied.

  The transistor Tr10 and the transistor Tr11 have the same polarity. FIG. 10 illustrates a case where both the transistor Tr10 and the transistor Tr11 have a p-channel type.

  The drain current of the transistor Tr11 corresponds to the current IREF. Since the transistor Tr10 and the transistor Tr11 have a function as a current mirror circuit, the drain current of the transistor Tr10 has almost the same value as the drain current of the transistor Tr11 or a value corresponding to the drain current of the transistor Tr11.

  Next, an example of a specific operation of the product-sum operation circuit 100 will be described with reference to FIG.

  11 corresponds to an example of a timing chart illustrating operations of the memory cell MC, the memory cell MCR, the current source circuit 103, the current sink circuit 104, and the current source circuit 105 illustrated in FIG. In FIG. 11, the operation of storing the first analog current in the memory cell MC and the memory cell MCR is performed from time T01 to time T04. From time T05 to time T10, an operation of setting an offset current Ioffset in the current source circuit 103 and the current sink circuit 104 is performed. From time T11 to time T16, an operation of acquiring data corresponding to the product-sum value of the first analog current and the second analog current is performed.

  Note that a low-level potential is supplied to the power supply line VR [j] and the power supply line VR [j + 1]. In addition, all the wirings having a predetermined potential connected to the current source circuit 103 are supplied with the high-level potential VDD. In addition, all the wirings having a predetermined potential connected to the current sink circuit 104 are supplied with the low-level potential VSS. In addition, all the wirings having a predetermined potential connected to the current source circuit 105 are supplied with the high-level potential VDD.

  The transistors Tr1, Tr4, Tr7, Tr10 [j], Tr10 [j + 1], and Tr11 are assumed to operate in the saturation region.

  First, from time T01 to time T02, a high-level potential is applied to the wiring WW [i], and a low-level potential is applied to the wiring WW [i + 1]. Through the above operation, the transistor Tr2 is turned on in the memory cell MC [i, j], the memory cell MC [i, j + 1], and the memory cell MCR [i] illustrated in FIG. In addition, the transistor Tr2 is kept off in the memory cell MC [i + 1, j], the memory cell MC [i + 1, j + 1], and the memory cell MCR [i + 1].

  Further, from time T01 to time T02, the potential obtained by subtracting the first analog potential from the first reference potential VPR is applied to the wiring WD [j] and the wiring WD [j + 1] illustrated in FIG. Specifically, the potential VPR-Vx [i, j] is applied to the wiring WD [j], and the potential VPR-Vx [i, j + 1] is applied to the wiring WD [j + 1]. The wiring WDREF is supplied with the first reference potential VPR, and the wiring RW [i] and the wiring RW [i + 1] have a potential between the potential VSS and the potential VDD as a reference potential, for example, a potential (VDD + VSS) / 2. Given.

  Therefore, the potential VPR−Vx [i, j] is applied to the node N [i, j] of the memory cell MC [i, j] illustrated in FIG. 10 through the transistor Tr2, and the memory cell MC [i, j + 1] is supplied. Node N [i, j + 1] is supplied with the potential VPR-Vx [i, j + 1] through the transistor Tr2, and the node NREF [i] of the memory cell MCR [i] is supplied with the potential VPR through the transistor Tr2. Given.

  When the time T02 ends, the potential applied to the wiring WW [i] illustrated in FIG. 10 changes from the high level to the low level, the memory cell MC [i, j], the memory cell MC [i, j + 1], and the memory cell MCR. In [i], the transistor Tr2 is turned off. Through the above operation, the node N [i, j] holds the potential VPR−Vx [i, j], the node N [i, j + 1] holds the potential VPR−Vx [i, j + 1], and the node NREF [I] holds the potential VPR.

  Next, in time T03 to time T04, the potential of the wiring WW [i] illustrated in FIG. 10 is maintained at a low level, and a high-level potential is applied to the wiring WW [i + 1]. Through the above operation, the transistor Tr2 is turned on in the memory cell MC [i + 1, j], the memory cell MC [i + 1, j + 1], and the memory cell MCR [i + 1] illustrated in FIG. Further, the transistor Tr2 is kept off in the memory cell MC [i, j], the memory cell MC [i, j + 1], and the memory cell MCR [i].

  From time T03 to time T04, a potential obtained by subtracting the first analog potential from the first reference potential VPR is supplied to the wiring WD [j] and the wiring WD [j + 1] illustrated in FIG. Specifically, the potential VPR−Vx [i + 1, j] is applied to the wiring WD [j], and the potential VPR−Vx [i + 1, j + 1] is applied to the wiring WD [j + 1]. The wiring WDREF is supplied with the first reference potential VPR, and the wiring RW [i] and the wiring RW [i + 1] have a potential between the potential VSS and the potential VDD as a reference potential, for example, a potential (VDD + VSS) / 2. Given.

  Accordingly, the node N [i + 1, j] of the memory cell MC [i + 1, j] illustrated in FIG. 10 is supplied with the potential VPR−Vx [i + 1, j] through the transistor Tr2, and the memory cell MC [i + 1, j + 1]. Node N [i + 1, j + 1] is supplied with the potential VPR-Vx [i + 1, j + 1] via the transistor Tr2, and the node NREF [i + 1] of the memory cell MCR [i + 1] is supplied with the potential VPR via the transistor Tr2. Given.

  When the time T04 ends, the potential applied to the wiring WW [i + 1] illustrated in FIG. 10 changes from a high level to a low level, and the memory cell MC [i + 1, j], the memory cell MC [i + 1, j + 1], and the memory cell MCR. In [i + 1], the transistor Tr2 is turned off. Through the above operation, the node N [i + 1, j] holds the potential VPR−Vx [i + 1, j], the node N [i + 1, j + 1] holds the potential VPR−Vx [i + 1, j + 1], and the node NREF [I + 1] holds the potential VPR.

  Next, at time T05 to time T06, a high-level potential is applied to the wiring ORP and the wiring ORM illustrated in FIG. In the current source circuit 103 [j] and the current source circuit 103 [j + 1] illustrated in FIG. 10, when a high-level potential is applied to the wiring ORM, the transistor Tr9 is turned on, and the potential VDD is applied to the gate of the transistor Tr7. To reset. In addition, in the current sink circuit 104 [j] and the current sink circuit 104 [j + 1] illustrated in FIG. 10, when a high-level potential is applied to the wiring ORP, the transistor Tr6 is turned on, and the gate of the transistor Tr4 has a potential VSS. Is reset when given.

  When the time T06 ends, the potentials applied to the wiring ORP and the wiring ORM illustrated in FIG. 10 change from a high level to a low level, and the transistor Tr9 is turned off in the current source circuit 103 [j] and the current source circuit 103 [j + 1]. Thus, the transistor Tr6 is turned off in the current sink circuit 104 [j] and the current sink circuit 104 [j + 1]. With the above operation, the potential VDD is held at the gate of the transistor Tr7 in the current source circuit 103 [j] and the current source circuit 103 [j + 1], and the transistor Tr4 in the current sink circuit 104 [j] and the current sink circuit 104 [j + 1]. The potential VSS is held at the gate.

  Next, at time T07 to time T08, a high-level potential is applied to the wiring OSP illustrated in FIG. Further, a potential between the potential VSS and the potential VDD, for example, a potential (VDD + VSS) / 2 is supplied as a reference potential to the wiring RW [i] and the wiring RW [i + 1] illustrated in FIG. When the high-level potential is applied to the wiring OSP, the transistor Tr5 is turned on in the current sink circuit 104 [j] and the current sink circuit 104 [j + 1].

  When I [j] flowing through the wiring BL [j] is smaller than the current IREF flowing through the wiring BLREF, that is, when ΔI [j] is positive, the transistor Tr1 of the memory cell MC [i, j] illustrated in FIG. This means that the sum of the current that can be drawn and the current that can be drawn by the transistor Tr1 of the memory cell MC [i + 1, j] is smaller than the drain current of the transistor Tr10 [j]. Therefore, when the current ΔI [j] is positive and the transistor Tr5 is turned on in the current sink circuit 104 [j], part of the drain current of the transistor Tr10 [j] flows into the gate of the transistor Tr4, and the potential of the gate Begins to rise. When the drain current of the transistor Tr4 becomes substantially equal to the current ΔI [j], the potential of the gate of the transistor Tr4 converges to a predetermined value. At this time, the gate potential of the transistor Tr4 corresponds to a potential at which the drain current of the transistor Tr4 becomes the current ΔI [j], that is, Ioffset [j] (= ICP [j]). That is, it can be said that the transistor Tr4 of the current sink circuit 104 [j] is set to a current source that can flow the current ICP [j].

  Similarly, when I [j + 1] flowing through the wiring BL [j + 1] is smaller than the current IREF flowing through the wiring BLREF, that is, when the current ΔI [j + 1] is positive, the transistor Tr5 is turned on in the current sink circuit 104 [j + 1]. Then, part of the drain current of the transistor Tr10 [j + 1] flows into the gate of the transistor Tr4, and the potential of the gate starts to rise. When the drain current of the transistor Tr4 becomes substantially equal to the current ΔI [j + 1], the gate potential of the transistor Tr4 converges to a predetermined value. The potential of the gate of the transistor Tr4 at this time corresponds to a potential at which the drain current of the transistor Tr4 becomes the current ΔI [j + 1], that is, Ioffset [j + 1] (= ICP [j + 1]). That is, it can be said that the transistor Tr4 of the current sink circuit 104 [j + 1] is set to a current source that can flow the current ICP [j + 1].

  When the time T08 ends, the potential applied to the wiring OSP illustrated in FIG. 10 changes from a high level to a low level, and the transistor Tr5 is turned off in the current sink circuit 104 [j] and the current sink circuit 104 [j + 1]. With the above operation, the potential of the gate of the transistor Tr4 is maintained. Therefore, the current sink circuit 104 [j] maintains the state set as a current source capable of flowing the current ICP [j], and the current sink circuit 104 [j + 1] is set as a current source capable of flowing the current ICP [j + 1]. Maintain the state.

  Next, at time T09 to time T10, a high-level potential is applied to the wiring OSM illustrated in FIG. Further, a potential between the potential VSS and the potential VDD, for example, a potential (VDD + VSS) / 2 is supplied as a reference potential to the wiring RW [i] and the wiring RW [i + 1] illustrated in FIG. When the high-level potential is applied to the wiring OSM, the transistor Tr8 is turned on in the current source circuit 103 [j] and the current source circuit 103 [j + 1].

  When I [j] flowing through the wiring BL [j] is larger than the current IREF flowing through the wiring BLREF, that is, when ΔI [j] is negative, the transistor Tr1 of the memory cell MC [i, j] illustrated in FIG. This means that the sum of the current that can be drawn and the current that can be drawn by the transistor Tr1 of the memory cell MC [i + 1, j] is larger than the drain current of the transistor Tr10 [j]. Therefore, when the current ΔI [j] is negative and the transistor Tr8 is turned on in the current source circuit 103 [j], current flows from the gate of the transistor Tr7 to the wiring BL [j], and the potential of the gate starts to decrease. . When the drain current of the transistor Tr7 becomes substantially equal to the current ΔI [j], the potential of the gate of the transistor Tr7 converges to a predetermined value. At this time, the gate potential of the transistor Tr7 corresponds to a potential at which the drain current of the transistor Tr7 becomes a current ΔI [j], that is, Ioffset [j] (= ICM [j]). That is, it can be said that the transistor Tr7 of the current source circuit 103 [j] is set to a current source that can flow the current ICM [j].

  Similarly, when I [j + 1] flowing through the wiring BL [j + 1] is larger than the current IREF flowing through the wiring BLREF, that is, when the current ΔI [j + 1] is negative, the transistor Tr8 is turned on in the current source circuit 103 [j + 1]. Then, current flows from the gate of the transistor Tr7 to the wiring BL [j + 1], and the potential of the gate starts to drop. When the drain current of the transistor Tr7 becomes substantially equal to the absolute value of the current ΔI [j + 1], the potential of the gate of the transistor Tr7 converges to a predetermined value. The potential of the gate of the transistor Tr7 at this time corresponds to a potential at which the drain current of the transistor Tr7 is equal to the current ΔI [j + 1], that is, the absolute value of Ioffset [j + 1] (= ICM [j + 1]). That is, it can be said that the transistor Tr7 of the current source circuit 103 [j + 1] is set to be a current source through which the current ICM [j + 1] can flow.

  When the time T08 ends, the potential applied to the wiring OSM illustrated in FIG. 10 changes from a high level to a low level, and the transistor Tr8 is turned off in the current source circuit 103 [j] and the current source circuit 103 [j + 1]. With the above operation, the potential of the gate of the transistor Tr7 is maintained. Therefore, the current source circuit 103 [j] maintains the state set as a current source that can flow the current ICM [j], and the current source circuit 103 [j + 1] is set as a current source that can flow the current ICM [j + 1]. Maintain the state.

  Note that in the current sink circuit 104 [j] and the current sink circuit 104 [j + 1], the transistor Tr4 has a function of drawing current. Therefore, when the current I [j] flowing through the wiring BL [j] is larger than the current IREF flowing through the wiring BLREF from time T07 to time T08 and ΔI [j] is negative, or the current I flowing through the wiring BL [j + 1] When [j + 1] is larger than the current IREF flowing through the wiring BLREF and ΔI [j + 1] is negative, the current sink circuit 104 [j] or the current sink circuit 104 [j + 1] has no excess or shortage, and the wiring BL [j] or the wiring BL [ It may be difficult to supply current to j + 1]. In this case, in order to balance the current flowing through the wiring BL [j] or the wiring BL [j + 1] and the current flowing through the wiring BLREF, the transistor Tr1 of the memory cell MC, the current sink circuit 104 [j], or the current sink It may be difficult for the transistor Tr4 of the circuit 104 [j + 1] and the transistor Tr10 [j] or Tr10 [j + 1] to operate in the saturation region.

  Even in the case where ΔI [j] is negative from time T07 to time T08, in order to ensure the operation in the saturation region of the transistor Tr1, Tr4, Tr10 [j], or Tr10 [j + 1], the transistor from time T05 to time T06 Instead of resetting the gate of Tr7 to the potential VDD, the gate potential of the transistor Tr7 may be set to such a level that a predetermined drain current can be obtained. With the above structure, since current is supplied from the transistor Tr7 in addition to the drain current of the transistor Tr10 [j] or Tr10 [j + 1], a current that cannot be drawn in the transistor Tr1 can be drawn to some extent in the transistor Tr4. The operation in the saturation region of the transistors Tr1, Tr4, Tr10 [j] or Tr10 [j + 1] can be ensured.

  Note that at time T09 to time T10, when I [j] flowing through the wiring BL [j] is smaller than the current IREF flowing through the wiring BLREF, that is, when ΔI [j] is positive, current sinking is performed from time T07 to time T08. Since the circuit 104 [j] is already set as a current source capable of flowing the current ICP [j], the potential of the gate of the transistor Tr7 remains substantially the potential VDD in the current source circuit 103 [j]. Similarly, when I [j + 1] flowing through the wiring BL [j + 1] is smaller than the current IREF flowing through the wiring BLREF, that is, when ΔI [j + 1] is positive, the current sink circuit 104 [j + 1] is switched from time T07 to time T08. Since the current source is already set to a current source through which the current ICP [j + 1] can flow, the potential of the gate of the transistor Tr7 remains substantially at the potential VDD in the current source circuit 103 [j + 1].

  Next, at time T11 to time T12, the second analog potential Vw [i] is applied to the wiring RW [i] illustrated in FIG. The wiring RW [i + 1] is still supplied with a potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2 as the reference potential. Specifically, the potential of the wiring RW [i] is higher by a potential difference Vw [i] than the potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2. For easy understanding, it is assumed that the potential of the wiring RW [i] is the potential Vw [i].

  When it is assumed that when the wiring RW [i] becomes the potential Vw [i], the amount of change in the potential of the first electrode of the capacitor C1 is substantially reflected in the amount of change in the potential of the node N, the memory illustrated in FIG. The potential of the node N in the cell MC [i, j] is VPR−Vx [i, j] + Vw [i], and the potential of the node N in the memory cell MC [i, j + 1] is VPR−Vx [i, j + 1] + Vw. [I]. From the above equation 6, the product sum of the first analog current and the second analog current corresponding to the memory cell MC [i, j] is the current obtained by subtracting Ioffset [j] from the current ΔI [j]. In other words, it is reflected in the current Iout [j] flowing out from the wiring BL [j]. The product sum of the first analog current and the second analog current corresponding to the memory cell MC [i, j + 1] is a current obtained by subtracting Ioffset [j + 1] from the current ΔI [j + 1], that is, the wiring BL [ It can be seen that the current Iout [j + 1] flowing out from j + 1] is reflected.

  When the time T12 ends, the wiring RW [i] is again supplied with a potential between the potential VSS and the potential VDD which is the reference potential, for example, the potential (VDD + VSS) / 2.

  Next, at time T13 to time T14, the second analog potential Vw [i + 1] is applied to the wiring RW [i + 1] illustrated in FIG. The wiring RW [i] is still supplied with a potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2 as the reference potential. Specifically, the potential of the wiring RW [i + 1] is higher by a potential difference Vw [i + 1] than the potential between the reference potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2. For ease of explanation, it is assumed that the potential of the wiring RW [i + 1] is the potential Vw [i + 1].

  When it is assumed that when the wiring RW [i + 1] becomes the potential Vw [i + 1], the amount of change in the potential of the first electrode of the capacitor C1 is substantially reflected in the amount of change in the potential of the node N. The potential of the node N in the cell MC [i + 1, j] is VPR−Vx [i + 1, j] + Vw [i + 1], and the potential of the node N in the memory cell MC [i + 1, j + 1] is VPR−Vx [i + 1, j + 1] + Vw. [I + 1]. From Equation 6 above, the first and second product-sum values corresponding to the memory cell MC [i + 1, j] are obtained by subtracting Ioffset [j] from the current ΔI [j], that is, Iout [ j]. The product sum of the first analog current and the second analog current corresponding to the memory cell MC [i + 1, j + 1] is a current obtained by subtracting Ioffset [j + 1] from the current ΔI [j + 1], that is, Iout [j + 1]. ] Is reflected in the

  When the time T12 ends, the wiring RW [i + 1] is again supplied with a potential between the potential VSS which is the reference potential and the potential VDD, for example, the potential (VDD + VSS) / 2.

  Next, at time T15 to time T16, the second analog potential Vw [i] is supplied to the wiring RW [i] illustrated in FIG. 10, and the second analog potential Vw [i + 1] is supplied to the wiring RW [i + 1]. . Specifically, the potential of the wiring RW [i] is higher by a potential difference Vw [i] than a potential between the reference potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2, and the wiring RW [i] The potential of (i + 1) is higher than the potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2 by a potential difference Vw [i + 1]. Further, it is assumed that the potential of the wiring RW [i] is the potential Vw [i] and the potential of the wiring RW [i + 1] is the potential Vw [i + 1].

  When it is assumed that when the wiring RW [i] becomes the potential Vw [i], the amount of change in the potential of the first electrode of the capacitor C1 is substantially reflected in the amount of change in the potential of the node N, the memory illustrated in FIG. The potential of the node N in the cell MC [i, j] is VPR−Vx [i, j] + Vw [i], and the potential of the node N in the memory cell MC [i, j + 1] is VPR−Vx [i, j + 1] + Vw. [I]. Further, when it is assumed that when the wiring RW [i + 1] becomes the potential Vw [i + 1], the amount of change in the potential of the first electrode of the capacitor C1 is substantially reflected in the amount of change in the potential of the node N. FIG. The potential of the node N in the memory cell MC [i + 1, j] shown is VPR−Vx [i + 1, j] + Vw [i + 1], and the potential of the node N in the memory cell MC [i + 1, j + 1] is VPR−Vx [i + 1, j + 1. ] + Vw [i + 1].

  From Equation 6 above, the first and second product sum values corresponding to the memory cell MC [i, j] and the memory cell MC [i + 1, j] are obtained from the current ΔI [j] to Ioffset [j]. It can be seen that the current is subtracted from the current Iout [j]. The first and second product sum values corresponding to the memory cell MC [i, j + 1] and the memory cell MC [i + 1, j + 1] are currents obtained by subtracting Ioffset [j + 1] from the current ΔI [j + 1], that is, It can be seen that the current Iout [j + 1] is reflected.

  When the time T16 ends, the wiring RW [i] and the wiring RW [i + 1] are again supplied with a potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2.

  With the above configuration, the product-sum operation can be performed with a small circuit scale. In addition, with the above configuration, the product-sum operation can be performed at high speed. In addition, with the above configuration, the product-sum operation can be performed with low power consumption.

  Note that the circuit configuration of the product-sum operation circuit described with reference to FIGS. 9 to 11 is merely an example, and any configuration can be employed as long as one embodiment of the present invention can be realized.

  Note that as the transistor Tr2, Tr5, Tr6, Tr8, or Tr9, a transistor with extremely low off-state current is preferably used. By using a transistor with extremely low off-state current as the transistor Tr2, the potential of the node N can be held for a long time. Further, by using transistors with extremely low off-state current for the transistors Tr5 and Tr6, the potential of the gate of the transistor Tr4 can be held for a long time. Further, by using transistors with extremely low off-state current for the transistors Tr8 and Tr9, the potential of the gate of the transistor Tr7 can be held for a long time.

In order to reduce the off-state current of the transistor, for example, the channel formation region may be formed using a semiconductor with a wide energy gap. The energy gap of the semiconductor is preferably 2.5 eV or more, 2.7 eV or more, or 3 eV or more. As such a semiconductor material, an oxide semiconductor can be given. A transistor including an oxide semiconductor in a channel formation region may be used as the transistors Tr2, Tr5, Tr6, Tr8, or Tr9. The leakage current of the OS transistor normalized by the channel width can be 10 × 10 ⁻²¹ A / μm (10 zept A / μm) or less when the source drain voltage is 10 V and room temperature (about 25 ° C.). is there. The leakage current of the OS transistor applied to the switches SW2 and SW3 is 1 × 10 ⁻¹⁸ A or less, 1 × 10 ⁻²¹ A or less, or 1 × 10 ⁻²⁴ A or less at room temperature (about 25 ° C.). preferable. Alternatively, the leakage current is preferably 1 × 10 ⁻¹⁵ A or less, or 1 × 10 ⁻¹⁸ A or less, or 1 × 10 ⁻²¹ A or less at 85 ° C.

  An oxide semiconductor is a semiconductor with a large energy gap, difficulty in excitation of electrons, and a large effective mass of holes. For this reason, a transistor including an oxide semiconductor in a channel formation region may hardly undergo avalanche collapse or the like as compared with a general transistor using silicon or the like. By suppressing hot carrier deterioration caused by avalanche collapse, a transistor including an oxide semiconductor in a channel formation region has a high drain breakdown voltage, and can be driven with a high drain voltage.

  The oxide semiconductor included in the channel formation region of the transistor is preferably an oxide semiconductor including at least one of indium (In) and zinc (Zn). As such an oxide semiconductor, an In oxide, a Zn oxide, an In—Zn oxide, an In—M—Zn oxide (the element M includes Ga, Al, Ti, Y, Zr, La, Ce, and Nd). Or Hf) is typical. These oxide semiconductors reduce an impurity such as hydrogen that serves as an electron donor (donor) and reduce oxygen vacancies to make the oxide semiconductor an i-type semiconductor (intrinsic semiconductor), or to an i-type semiconductor. It can be as close as possible. Such an oxide semiconductor can be referred to as a highly purified oxide semiconductor.

The channel formation region is preferably formed using an oxide semiconductor with low carrier density. For example, the carrier density of the oxide semiconductor is preferably less than 8 × 10 ¹¹ / cm ^{3 and} 1 × 10 ⁻⁹ / cm ³ or more. The carrier density is preferably less than 1 × 10 ¹¹ / cm ^{3, and} more preferably less than 1 × 10 ¹⁰ / cm ³ .

<Configuration example of neural network applicable to character data generation circuit and pattern recognition circuit>
A hierarchical neural network will be described as one type of neural network applicable to the character data generation circuit and the pattern recognition circuit.

  FIG. 12 is a diagram illustrating an example of a hierarchical neural network. The (k−1) -th layer (k is an integer of 2 or more) has P neurons (P is an integer of 1 or more), and the k-th layer has Q neurons (Q is The (k + 1) th layer has R neurons (R is an integer of 1 or more).

The product of the output signal z _p ^(k−1) and the weight coefficient w _qp ^(k) of the p-th neuron of the (k−1) -th layer (p is an integer of 1 or more and P or less) is the k-th layer. The q-th neuron (q is an integer between 1 and Q), and the output signal z _q ^(k) of the ^k- th neuron in the k-th layer and the weight coefficient w _rq ^{(k + 1)} Assume that the product is input to the r-th neuron in the (k + 1) -th layer (r is an integer of 1 to R), and the output signal of the r-th neuron in the (k + 1) -th layer is expressed as z _r ^{(k + 1)} To do.

  At this time, the total sum of signals input to the k-th neuron in the k-th layer is expressed by the following equation (D1).

The output signal z _q ^(k) from the q-th neuron in the k-th layer is defined by the following equation (D2).

The function f (u _q ^(k) ) is a neuron output function, and a step function, a linear ramp function, a sigmoid function, or the like can be used. The product-sum operation of equation (D1) can be realized by the product-sum operation circuit described above. Note that the calculation of the equation (D2) can be realized by a circuit 411 illustrated in FIG.

  Note that the output function of the neurons may be the same or different in all the neurons. In addition, the output function of the neuron may be the same or different for each layer.

  Here, consider a hierarchical neural network including all L layers shown in FIG. 13 (that is, k here is an integer of 2 or more and (L−1) or less). The first layer is an input layer of the hierarchical neural network, the Lth layer is an output layer of the hierarchical neural network, and the second to (L-1) th layers are hidden layers.

  The first layer (input layer) has P neurons, and the kth layer (hidden layer) has Q [k] neurons (Q [k] is an integer equal to or greater than 1). The L layer (output layer) has R neurons.

The output signal of the s [1] neuron in the first layer (s [1] is an integer between 1 and P) is z _{s [1]} ^(1), and the s [k] neuron in the kth layer. The output signal (s [k] is an integer between 1 and Q [k]) is z _{s [k]} ^(k), and the s [L] neuron (s [L] is 1 in the Lth layer. The output signal is an integer less than or equal to R.) z _{s [L]} ^(L) .

The output signal z _{s [k−1} ] of the s [k−1] th neuron (s [k−1] is an integer of 1 to Q [k−1]) in the (k−1) th layer. _] Product _{k s [k]} ^{(k )} and weight coefficient w _{s [k] s [k−1]} ^(k) are input to the s [k] neuron in the k-th layer. It is assumed that the output signal z _{s [L−} ] of the s [L−1] neuron (s [L−1] is an integer of 1 to Q [L−1]) in the (L−1) th layer. _1] ^(L−1) and the weight coefficient w _{s [L] s [L−1]} ^(L) and the product u _{s [L]} ^(L) are input to the s [L] neuron in the Lth layer. Shall be.

  Next, supervised learning will be described. Supervised learning means that when the output result differs from the desired result (sometimes referred to as teacher data or teacher signal) in the function of the above-described hierarchical neural network, An operation for updating the weighting coefficient based on the output result and the desired result.

  As a specific example of supervised learning, a learning method using a back propagation error method will be described. FIG. 14 is a diagram for explaining a learning method using the back propagation error method. The back propagation error method is a method of changing the weighting coefficient so that the error between the output of the hierarchical neural network and the teacher data becomes small.

For example, assume that input data is input to the s [1] neuron in the first layer, and output data z _{s [L]} ^(L) is output from the s [L] neuron in the Lth layer. Here, when the teacher signal for the output data z _{s [L]} ^(L) is t _{s [L]} , the error energy E is determined by the output data z _{s [L]} ^(L) and the teacher signal t _{s [L]} . Can be represented.

For the error energy E, the update amount of the weight coefficient w _{s [k] s [k−1]} ^(k) of the s [k] neuron in the k-th layer is expressed as ∂E / ∂w _{s [k] s [k −1] By} setting ^(k) , the weighting factor can be newly changed. Here, if the error δ _{s [k]} ^(k) of the output value z _{s [k]} ^(k) of the s [k] neuron in the k-th layer is defined as ∂E / ∂u _{s [k]} ^(k) , Δ _{s [k]} ^(k) and ∂E / ∂w _{s [k] s [k−1]} ^(k) can be expressed by the following equations (D3) and (D4), respectively.

f ′ (u _{s [k]} ^(k) ) is a derivative of the output function of the neuron circuit. Note that the calculation of Expression (D3) can be realized by a circuit 413 illustrated in FIG. Moreover, the calculation of Formula (D4) is realizable by the circuit 414 shown in FIG.16 (C), for example. The derivative of the output function can be realized, for example, by connecting an arithmetic circuit corresponding to a desired derivative to the output terminal of the operational amplifier.

Further, for example, the calculation of the part of Σw _{s [k + 1] · s [k]} ^{(k + 1)} · δ _{s [k + 1]} ^{(k + 1) in} the equation (D3) can be realized by the product-sum operation circuit described above.

Here, when the (k + 1) th layer is the output layer, that is, when the (k + 1) th layer is the Lth layer, δ _{s [L]} ^(L) and ∂E / ∂w _{s [L] s [L -1]} ^(L) can be represented by the following formulas (D5) and (D6), respectively.

  The calculation of Expression (D5) can be realized by a circuit 415 illustrated in FIG. Further, the calculation of Expression (D6) can be realized by a circuit 414 illustrated in FIG.

That is, the errors δ _{s [k]} ^(k) and δ _{s [L]} ^(L) of all the neuron circuits can be obtained from the equations (D1) to (D6). The update of the weighting coefficient is set based on the errors δ _{s [k]} ^(k) , δ _{s [L]} ^(L), desired parameters, and the like.

  As described above, the hierarchical neural network to which supervised learning is applied can be calculated by using the circuits shown in FIGS. 9 and 10 and the product-sum operation circuit described above.

Specifically, in the circuits shown in FIGS. 9 and 10, the first analog data is used as a weighting factor, and a plurality of second analog data is associated with the neuron output, so that the weighted sum operation of each neuron output is performed in parallel. The data corresponding to the result of the weighting calculation, that is, the synaptic input can be acquired as the output signal. Specifically, the weight coefficients w _{s [k] · 1} ^{(k) to} w _s of the s [k] neuron in the k-th layer are assigned to the memory cells AM [1, j] to AM [m, j]. _{[K] · Q [k−1]} ^(k) is stored as the first analog data, and the output signal z ₁ of each neuron of the (k−1) th layer is respectively connected to the wiring RW [1] to the wiring RW [m]. _By supplying _{s [k]} ^{(k-1) to} zQ _{[k-1] .s [k]} ^(k-1) as the second analog data, the s [k] neuron in the kth layer is supplied. The sum total u _{s [k]} ^(k) of the input signals can be calculated. That is, the product-sum operation shown in Expression (D1) can be realized by the product-sum operation circuit.

Further, when updating the weighting coefficient by supervised learning, the memory cell AM [1, j] to memory cell AM [m, j] are transferred from the kth layer s [k] neuron to the (k + 1) th layer. The weighting factors w _{1 · s [k]} ^{(k + 1) to} w _{Q [k + 1] s [k]} ^{(k + 1)} applied when signals are sent to the respective neurons are stored as first analog data, and wirings RW [1] to RW [1] to When the errors δ ₁ ^{(k + 1) to} δ _{Q [k + 1]} ^{(k + 1)} of each neuron of the ^{(k + 1)} -th layer are supplied as the second analog data to the wiring RW [m], Σw _{s [k + 1] · The value of s [k]} ^{(k + 1)} · δ _{s [k + 1]} ^{(k + 1)} can be obtained from the differential current ΔI _B [j] flowing in the wiring B [j]. That is, a part of the calculation shown in Expression (D3) can be realized by the product-sum calculation circuit.

<Configuration Example of Memory Cell Applicable to Memory Circuit>
An example of the circuit configuration of the memory cell used for the memory circuits 19 and 25 is shown in FIG. 16A to 16F, a configuration example of a memory cell that can be applied to the memory circuits 19 and 25 described above will be described.

  FIG. 16A is a block diagram for explaining a configuration example of the memory circuits 19 and 25. In the block diagram of FIG. 16A, the memory cell array 90, the word line driver circuit 91, and the bit line driver circuit 92 are illustrated.

  The memory cell array 90 includes memory cells MC provided in a matrix of m rows and n columns (m and n are natural numbers). The memory cell MC is connected to the word lines WL_1 to WL_m and the bit lines BL_1 to BL_n. The memory cell MC includes a bit line and a word line, a source line for flowing current, a wiring for applying a voltage to the back gate of the transistor, or a capacitance line for setting one electrode of the capacitor to a fixed potential. Or the like.

  The word line driving circuit 91 is a circuit that outputs a signal for selecting the memory cell MC in each row. The word lines WL_1 to WL_m may have separate word lines for writing and reading.

  The bit line driving circuit 92 is a circuit for writing data to the memory cells MC in each column or reading data from the memory cells MC. The bit lines BL_1 to BL_n may have different bit lines for writing and reading.

  FIGS. 16B to 16F illustrate examples of circuit configurations that can be taken by the memory cell MC described with reference to FIG.

  A memory cell MC_A illustrated in FIG. 16B includes a transistor OS1 and a capacitor 93. The transistor OS1 is a transistor having an oxide semiconductor in a semiconductor layer (OS transistor). An OS transistor has a characteristic that leakage current (off current) in a non-conduction state is extremely low as compared with a transistor having silicon in a semiconductor layer (Si transistor). Therefore, the charge corresponding to the data can be held in the charge holding node SN by turning off the transistor OS1. Therefore, the refresh rate of data held in the charge holding node SN can be reduced.

  A memory cell MC_B illustrated in FIG. 16C includes a transistor OS2 and a capacitor 93. The transistor OS2 is an OS transistor. The difference from the transistor OS1 in FIG. 16B is that the gate and the back gate are connected and the voltage of the word line WL is applied from both. With such a structure, the amount of current flowing between the source and the drain when the transistor OS2 is turned on can be increased.

  A memory cell MC_C illustrated in FIG. 16D includes a transistor OS3 and a capacitor 93. The transistor OS3 is an OS transistor. A difference from the transistor OS1 in FIG. 16B is that a back gate and a back gate line BGL are connected and a voltage different from that of the gate is applied to the back gate. With such a structure, the threshold voltage of the transistor OS3 can be controlled to control the amount of current flowing between the source and the drain.

  A memory cell MC_D illustrated in FIG. 16E includes a transistor OS1, a transistor M1, and a capacitor 93. One of the source and the drain of the transistor OS1 is connected to the write bit line WBL. The other of the source and the drain of the transistor OS1 is connected to the gate of the transistor M1 and one electrode of the capacitor 93. The gate of the transistor OS1 is connected to the write word line WWL. The other electrode of the capacitor 93 is connected to the read word line RWL. One of the source and the drain of the transistor M1 is connected to the read bit line RBL. The other of the source and the drain of the transistor M1 is connected to the source line SL. The transistor M1 is a p-channel transistor, but may be an n-channel transistor. By setting the transistor OS1 in a non-conductive state, the charge corresponding to the data can be held in the charge holding node SN. The transistor M1 is a transistor (Si transistor) having silicon in a channel formation region. Note that the transistor OS1 can have a structure similar to that of the above-described transistors OS2 and OS3.

  A memory cell MC_E illustrated in FIG. 16F includes a transistor OS1, a transistor M1, a transistor M2, and a capacitor 93. One of the source and the drain of the transistor OS1 is connected to the write bit line WBL. The other of the source and the drain of the transistor OS1 is connected to the gate of the transistor M1 and one electrode of the capacitor 93. The gate of the transistor OS1 is connected to the write word line WWL. The other electrode of the capacitor 93 is connected to the capacitor line CL. One of the source and the drain of the transistor M1 is connected to one of the source and the drain of the transistor M2. The other of the source and the drain of the transistor M1 is connected to the source line SL. The gate of the transistor M2 is connected to the read word line RWL. The other of the source and the drain of the transistor M2 is connected to the read bit line RBL. The transistor M2 is a p-channel transistor, but may be an n-channel transistor. By setting the transistor OS1 in a non-conductive state, the charge corresponding to the data can be held in the charge holding node SN. The transistor M2 is a Si transistor. Note that the transistor OS1 can have a structure similar to that of the above-described transistors OS2 and OS3.

  Note that the structure of the memory cell illustrated in FIGS. 16B to 16F is particularly effective when data stored in the memory circuit is increased. Compared to the case where the memory cells of the memory circuit are configured by SRAM (Static RAM), the configuration having one to three memory cells can suppress an increase in circuit area. In particular, the structure of the memory cell shown in FIGS. 16B to 16D is effective in suppressing an increase in circuit area.

  The OS transistor has a smaller variation in transistor characteristics when the operating temperature rises than that of the Si transistor. Therefore, it is possible to provide a memory circuit that can perform operation in a temperature range that can withstand in-vehicle specifications such as an automobile more reliably.

  Note that the circuit configurations illustrated in FIGS. 16B to 16F are merely examples, and any configuration can be employed as long as one embodiment of the present invention can be realized.

<Example of Circuit Configuration Applicable to Display Device>
An example of a circuit configuration in the display unit of the display device 32 is shown in FIG. FIG. 14 illustrates an example of a circuit configuration that can be applied to the sub-pixels included in the display portion described above.

  FIG. 17 is a block diagram illustrating a configuration example of a display device.

  A display device 500 illustrated in FIG. 17 includes a driver circuit 541, a driver circuit 542A, a driver circuit 542B, and a display portion 543. Note that the drive circuit 541, the drive circuit 542A, and the drive circuit 542B may be collectively referred to as a “drive circuit” or a “peripheral drive circuit”.

  The driver circuit 542A and the driver circuit 542B can function as a scan line driver circuit, for example. In addition, the drive circuit 541 can function as a signal line driver circuit, for example. Note that only one of the drive circuit 542A and the drive circuit 542B may be used. In addition, some circuit may be provided at a position facing the driving circuit 541 with the display portion 543 interposed therebetween.

  In addition, in the display device 500 illustrated in FIG. 17, each of the display devices 500 is substantially parallel to the p wirings 544 that are arranged substantially in parallel and whose potential is controlled by the drive circuit 542A and / or the drive circuit 542B. And q wirings 545 whose potentials are controlled by the drive circuit 541. Further, the display portion 543 includes a plurality of subpixels 546 arranged in a matrix. The sub-pixel 546 includes a pixel circuit and a display element.

  Further, full color display can be realized by causing the three sub-pixels 546 to function as one pixel. Each of the three subpixels 546 controls the transmittance, reflectance, light emission amount, etc. of red light, green light, or blue light. Note that the color of light controlled by the three sub-pixels 546 is not limited to a combination of red, green, and blue, and may be yellow, cyan, and magenta.

  In addition, a sub-pixel 546 that controls white light may be added to a pixel that controls red light, green light, and blue light, and the four sub-pixels 546 may function together as one pixel. By adding a sub-pixel 546 that controls white light, the luminance of the display region can be increased. Further, by increasing the number of sub-pixels 546 that function as one pixel and appropriately using red, green, blue, yellow, cyan, and magenta, the reproducible color gamut can be expanded.

  When the pixels are arranged in a matrix of 1920 × 1080, a display device portion 540 that can display at a resolution of so-called full high vision (also referred to as “2K resolution”, “2K1K”, “2K”, and the like) can be realized. . Further, for example, when pixels are arranged in a 3840 × 2160 matrix, a display device 540 that can display at a resolution of so-called ultra high vision (also referred to as “4K resolution”, “4K2K”, “4K”, etc.) is realized. can do. In addition, for example, when pixels are arranged in a 7680 × 4320 matrix, a display device portion 540 that can display at a resolution of so-called Super Hi-Vision (also referred to as “8K resolution”, “8K4K”, “8K”, etc.) is realized. can do. By increasing the number of pixels, it is also possible to realize the display device portion 540 that can display at a resolution of 16K or 32K.

  The g-th wiring 544_g (g is a natural number greater than or equal to 1 and less than or equal to p) is a plurality of subpixels 546 arranged in p rows and q columns (p and q are both natural numbers greater than or equal to 1) in the display portion 543. Among these, q sub-pixels 546 arranged in g rows are electrically connected. Further, the h-th column wiring 545_h (h is a natural number of 1 or more and q or less) is connected to p sub-pixels 546 arranged in the h column among the sub-pixels 546 arranged in the p row and the q column. Electrically connected.

  The display device 500 can use various modes or have various display elements. Examples of display elements include EL (electroluminescence) elements (organic EL elements, inorganic EL elements, or EL elements including organic and inorganic substances), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (Transistor that emits light in response to current), electron-emitting device, liquid crystal device, electronic ink, electrophoretic device, grating light valve (GLV), display device using MEMS (micro electro mechanical system), digital micromirror Some display devices using devices (DMD), DMS (digital micro shutter), etc. have display media whose contrast, brightness, reflectance, transmittance, etc. change due to electrical or magnetic action. . Further, quantum dots may be used as the display element.

  Next, an example of a pixel circuit included in the sub-pixel will be described.

  As described above, the pixel circuit of the display portion 543 has one type of a liquid crystal element, a light emitting element, and the like as a display element, and the configuration of the pixel circuit of the display portion 543 differs depending on the type of the display element.

  For example, FIG. 18A illustrates an example of a pixel circuit in the case where a liquid crystal element is used as the display element of the display portion 543. The pixel circuit 201 includes a transistor Tr1, a capacitor element C1, and a liquid crystal element LD.

  The first terminal of the transistor Tr1 is electrically connected to the wiring SL, the second terminal of the transistor Tr1 is electrically connected to the first terminal of the liquid crystal element LD, and the gate of the transistor Tr1 is electrically connected to the wiring GL1. It is connected to the. The first terminal of the capacitor C1 is electrically connected to the wiring CSL, and the second terminal of the capacitor C1 is electrically connected to the first terminal of the liquid crystal element LD. The second terminal of the liquid crystal element LD is electrically connected to the wiring VCOM1.

  The wiring SL functions as a signal line that supplies an image signal to the pixel circuit 201. The wiring GL2 functions as a scanning line for selecting the pixel circuit 201. The wiring CSL functions as a capacitor wiring for holding the potential of the first terminal of the capacitor C1, in other words, the potential of the first terminal of the liquid crystal element LD. The wiring VCOM1 is a wiring for applying a fixed potential such as 0 V or a GND potential as a common potential to the second terminal of the liquid crystal element LD.

  For example, FIG. 18B illustrates an example of a pixel circuit in the case where a light-emitting element is used as the display element of the display portion 543. The light-emitting element is an organic EL (Electro Luminescence) element. The pixel circuit 202 includes a transistor Tr2, a transistor Tr3, a capacitor C2, and a light emitting element ED.

  The first terminal of the transistor Tr2 is electrically connected to the wiring DL, the second terminal of the transistor Tr2 is electrically connected to the gate of the transistor Tr3, and the gate of the transistor Tr2 is electrically connected to the wiring GL2. ing. The first terminal of the transistor Tr3 is electrically connected to the first terminal of the light emitting element ED, and the second terminal of the transistor Tr3 is electrically connected to the wiring AL. The first terminal of the capacitor C2 is electrically connected to the second terminal of the transistor Tr3, and the second terminal of the capacitor C2 is electrically connected to the gate of the transistor Tr3. The second terminal of the light emitting element ED is electrically connected to the wiring VCOM2.

  The wiring DL functions as a signal line that supplies an image signal to the pixel circuit 202. The wiring GL2 functions as a scanning line for selecting the pixel circuit 202. The wiring AL functions as a current supply line for supplying a current to the light emitting element ED. The wiring VCOM2 is a wiring for applying a fixed potential such as 0 V or a GND potential as a common potential to the second terminal of the light emitting element ED.

  The capacitor C2 has a function of holding a voltage between the second terminal of the transistor Tr3 and the gate of the transistor Tr3. Thereby, the on-current flowing through the transistor Tr3 can be kept constant. Note that when the parasitic capacitance between the second terminal of the transistor Tr3 and the gate of the transistor Tr3 is large, the capacitor C2 is not necessarily provided.

  In the case where a light-emitting element is used as the display element of the display portion 543, a structure of the pixel circuit 203 illustrated in FIG. 18C which is different from the structure of the pixel circuit 202 may be employed.

  The pixel circuit 203 has a structure in which a back gate is provided in the transistor Tr3 included in the pixel circuit 202. The back gate of the transistor Tr3 is electrically connected to the gate of the transistor Tr3. With such a configuration, the on-current flowing through the transistor Tr3 can be increased.

  In the case where a light-emitting element is used as the display element of the display portion 543, the structure of the pixel circuit 204 illustrated in FIG. 18D may be employed as a structure different from that of the pixel circuit 202 and the pixel circuit 203.

  The pixel circuit 204 has a structure in which a back gate is provided in the transistor Tr3 included in the pixel circuit 202. The back gate of the transistor Tr3 is electrically connected to the first terminal of the transistor Tr3. With such a configuration, a shift in threshold voltage of the transistor Tr3 can be suppressed. Therefore, the reliability of the transistor Tr3 can be improved.

  In the case where a light-emitting element is used as the display element of the display portion 543, the structure of the pixel circuit 205 illustrated in FIG. 18E may be employed as a structure different from that of the pixel circuits 202 to 204.

  The pixel circuit 205 includes transistors Tr2 to Tr4, a capacitor C3, and a light emitting element ED.

  The first terminal of the transistor Tr2 is electrically connected to the wiring DL, the second terminal of the transistor Tr2 is electrically connected to the gate of the transistor Tr3, and the gate of the transistor Tr2 is electrically connected to the wiring ML. The back gate of the transistor Tr2 is electrically connected to the wiring GL3. The first terminal of the transistor Tr3 is electrically connected to the first terminal of the light-emitting element ED, the second terminal of the transistor Tr3 is electrically connected to the wiring AL, and the gate of the transistor Tr3 is the back gate of the transistor Tr3. And are electrically connected. The first terminal of the transistor Tr4 is electrically connected to the first terminal of the light-emitting element ED, the second terminal of the transistor Tr4 is electrically connected to the wiring ML, and the gate of the transistor Tr4 is electrically connected to the wiring ML. The back gate of the transistor Tr4 is electrically connected to the wiring GL3. The first terminal of the capacitor C3 is electrically connected to the gate of the transistor Tr3, and the second terminal of the capacitor C3 is electrically connected to the first terminal of the transistor Tr3. The second terminal of the light emitting element ED is electrically connected to the wiring VCOM2.

  The wiring DL functions as a signal line that supplies an image signal to the pixel circuit 205. The wiring GL3 functions as a wiring for applying a constant potential in order to control the threshold voltages of the transistors Tr2 and Tr4. The wiring ML is a wiring for applying a constant potential to the gate of the transistor Tr2, the second terminal of the transistor Tr4, and the gate of the transistor Tr4, and functions as a scanning line for selecting the pixel circuit 202. For the wiring AL and the wiring VCOM2, the description of the wiring AL and the wiring VCOM2 of the pixel circuit 202 is referred to.

  With such a structure, variation in luminance of the plurality of light-emitting elements ED included in the display portion 543 can be corrected by controlling threshold voltages of the transistors Tr2 and Tr4. Therefore, by applying the pixel circuit 205 to the display portion 543, the display device 500 with favorable display quality can be provided.

<Additional notes regarding the description of this specification>
In this specification and the like, the ordinal numbers “first”, “second”, and “third” are given to avoid confusion between components. Therefore, the number of components is not limited. Further, the order of the components is not limited.

  In the present specification and the like, in the block diagram, components are classified by function and shown as blocks independent of each other. However, in an actual circuit or the like, it is difficult to separate the components for each function, and there may be a case where a plurality of functions are involved in one circuit or a case where one function is involved over a plurality of circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification, and can be appropriately rephrased depending on the situation.

  Note that in the drawings, the same element, an element having a similar function, an element of the same material, an element formed at the same time, or the like may be denoted by the same reference numeral, and repeated description thereof may be omitted.

  In this specification and the like, when describing a connection relation of a transistor, one of a source and a drain is referred to as “one of a source and a drain” (or a first electrode or a first terminal), and the source and the drain The other is referred to as “the other of the source and the drain” (or the second electrode or the second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the names of the source and the drain of the transistor can be appropriately rephrased depending on the situation, such as a source (drain) terminal or a source (drain) electrode.

  In this specification and the like, voltage and potential can be described as appropriate. The voltage is a potential difference from a reference potential. For example, when the reference potential is a ground potential (ground potential), the voltage can be rephrased as a potential. The ground potential does not necessarily mean 0V. Note that the potential is relative, and the potential applied to the wiring or the like may be changed depending on the reference potential.

  In this specification and the like, a switch refers to a switch that is in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether or not to pass current. Alternatively, the switch refers to a switch having a function of selecting and switching a current flow path.

  As an example, an electrical switch or a mechanical switch can be used. That is, the switch is not limited to a specific one as long as it can control the current.

  Note that in the case where a transistor is used as the switch, the “conducting state” of the transistor means a state where the source and the drain of the transistor can be regarded as being electrically short-circuited. In addition, the “non-conducting state” of a transistor refers to a state where the source and drain of the transistor can be regarded as being electrically cut off. Note that when a transistor is operated as a simple switch, the polarity (conductivity type) of the transistor is not particularly limited.

  In this specification and the like, “A and B are connected” includes not only those in which A and B are directly connected but also those that are connected. Here, “A and B are connected” means that when there is an object having some electrical action between A and B, it is possible to send and receive electrical signals between A and B. Say.

BL_n bit line BL_1 bit line C1 capacitive element C2 capacitive element C3 capacitive element C4 capacitive element GL1 wiring GL2 wiring GL3 wiring M1 transistor M2 transistor OS1 transistor OS2 transistor OS3 transistor SW2 switch T01 time T02 time T03 time T04 time T05 time T06 time T07 time T08 Time T09 Time T10 Time T11 Time T12 Time T13 Time T14 Time T15 Time T16 Time Tr1 Transistor Tr2 Transistor Tr3 Transistor Tr4 Transistor Tr5 Transistor Tr6 Transistor Tr7 Transistor Tr8 Transistor Tr9 Transistor Tr10 Transistor Tr11 Transistor VCOM1 Line WL_WL Line 10 Transmission unit 11 Sender 12 Data 12A Data 12B Data 13 Transmission device 14A Data 14B Data 15 Data server 16 Character data generation circuit 17 Pattern recognition circuit 18 Additional data generation circuit 19 Storage circuit 20 Relay unit 21 Network 22 Data server 23 Character data generation Circuit 24 Pattern recognition circuit 25 Storage circuit 30 Receiver 31 Receiver 32 Display device 90 Memory cell array 91 Word line drive circuit 92 Bit line drive circuit 93 Capacitance element 100 Multiply-add operation circuit 101 Storage circuit 102 Reference storage circuit 103 Current source circuit 104 current sink circuit 105 current source circuit 201 pixel circuit 202 pixel circuit 203 pixel circuit 204 pixel circuit 205 pixel circuit 500 display device 540 display device unit 541 drive circuit 542A drive circuit 542B drive circuit 5 3 display 544 lines 544_g wiring 545 lines 545_h wiring 546 subpixels

Claims (10)

An information transmission system for transmitting data from a transmission device to a reception device via a data server,
The transmission device has a function of transmitting the first data or the second data,
The data server includes a character data generation circuit, a pattern recognition circuit, and a storage circuit.
The character data generation circuit has a function of generating third data based on the first data, and a function of generating fourth data based on the second data;
The storage circuit has a function of storing at least one of the first data, the third data, the second data, and the fourth data;
The pattern recognition circuit compares the first data and the third data with the second data when the first data and the second data are compared and has a matching area. A function to replace the data and the fourth data;
The information receiving system, wherein the receiving device has a function of displaying the third data or the fourth data. In claim 1,
The first data and the second data include handwritten document data,
The information transmission system, wherein the third data and the fourth data include type data. In claim 1 or 2,
The information transmission system, wherein the character data generation circuit and the pattern recognition circuit have a product-sum operation circuit that can be used in a neural network. In any one of Claims 1 thru | or 3,
The transmitter has a function of a facsimile machine,
The information receiving system, wherein the receiving device has a function of a display device. In any one of Claims 1 thru | or 4,
The memory circuit includes a memory element,
The memory element includes a transistor and a capacitor,
The transistor has an oxide semiconductor in a semiconductor layer having a channel formation region. An information transmission system for transmitting data from a transmission device to a reception device via a relay data server,
The transmission device includes a function of transmitting the first data or the second data, a data server for transmission,
The transmission data server includes a character data generation circuit, a pattern recognition circuit, and a first storage circuit,
The data server for relay includes a second storage circuit;
The character data generation circuit has a function of generating third data based on the first data, and a function of generating fourth data based on the second data;
The first memory circuit and the second memory circuit have a function of storing at least one of the first data and the third data, and the second data and the fourth data. ,
The pattern recognition circuit compares the first data and the second data, and has a region that matches, the first data in the first memory circuit and the second memory circuit, and A function of replacing the third data with the second data and the fourth data;
The information receiving system, wherein the receiving device has a function of displaying the third data or the fourth data. In claim 6,
The first data and the second data include handwritten document data,
The information transmission system, wherein the third data and the fourth data include type data. In claim 6 or 7,
The information transmission system, wherein the character data generation circuit and the pattern recognition circuit have a product-sum operation circuit that can be used in a neural network. In any one of Claims 6 thru | or 8,
The transmitter has a function of a facsimile machine,
The information receiving system, wherein the receiving device has a function of a display device. In any one of Claims 6 thru | or 9,
The first memory circuit and the second memory circuit each have a memory element;
The memory element includes a transistor and a capacitor,
The transistor has an oxide semiconductor in a semiconductor layer having a channel formation region.

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