JP2018093095A - Memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory device capable of independently driving a memory cell with high accuracy.SOLUTION: A memory device includes first wiring that extends in a first direction, second wiring that extends in a second direction that crosses the first direction, third wiring that is arranged in the first direction when viewed from the second wiring and that extends in the second direction, and first resistance change film provided between the first wiring and the second wiring and between the first wiring and the third wiring. The first resistance change film has two or more layers the compositions of which are different from each other. At least two layers out of the two or more layers are arranged between the second wiring and the third wiring in the first direction.SELECTED DRAWING: Figure 2

Description

  Embodiments described herein relate generally to a storage device.

  In recent years, a memory device in which a resistance change film is connected between two types of wirings extending in directions orthogonal to each other has been proposed. As a result, two-terminal memory cells can be integrated three-dimensionally, and the capacity can be increased. In such a memory device, it becomes a problem to drive each memory cell independently with high accuracy.

JP 2014-49745 A

  An object of the embodiment is to provide a memory device that can independently drive a memory cell with high accuracy.

  The storage device according to the embodiment includes a first wiring extending in a first direction, a second wiring extending in a second direction intersecting the first direction, and the first wiring as viewed from the second wiring. A third wiring disposed and extending in the second direction; a first resistance change film provided between the first wiring and the second wiring; and between the first wiring and the third wiring. And comprising. The first resistance change film includes two or more layers having different compositions. At least two of the two or more layers are disposed between the second wiring and the third wiring in the first direction.

1 is a perspective view showing a storage device according to a first embodiment. 1 is a cross-sectional view showing a memory cell of a memory device according to a first embodiment. It is a figure which shows the reset operation | movement of the memory | storage device which concerns on 1st Embodiment. It is sectional drawing which shows the memory cell of the memory | storage device which concerns on a comparative example. (A) And (b) is a figure which shows the simulation result of the electron density distribution in a barrier layer, (a) shows 1st Embodiment, (b) shows a comparative example. FIG. 6 is a graph comparing the magnitude of current flowing through each word line during a reset operation, with the horizontal axis representing the voltage between the bit line and the word line and the vertical axis representing the absolute value of the current flowing through the word line. . It is sectional drawing which shows the memory cell of the memory | storage device which concerns on 2nd Embodiment. It is sectional drawing which shows the memory cell of the memory | storage device which concerns on 3rd Embodiment. It is sectional drawing which shows the memory cell of the memory | storage device which concerns on 4th Embodiment. It is sectional drawing which shows the memory cell of the memory | storage device which concerns on 5th Embodiment. (A) And (b) is sectional drawing which shows the manufacturing method of the memory | storage device which concerns on 6th Embodiment. (A) And (b) is sectional drawing which shows the manufacturing method of the memory | storage device which concerns on 6th Embodiment. (A) And (b) is sectional drawing which shows the manufacturing method of the memory | storage device which concerns on 7th Embodiment. It is sectional drawing which shows the manufacturing method of the memory | storage device which concerns on 7th Embodiment. (A) And (b) is sectional drawing which shows the manufacturing method of the memory | storage device which concerns on 8th Embodiment. (A) And (b) is sectional drawing which shows the manufacturing method of the memory | storage device which concerns on 8th Embodiment.

(First embodiment)
FIG. 1 is a perspective view showing a storage device according to the present embodiment.
FIG. 2 is a cross-sectional view showing the memory cell of the memory device according to the present embodiment.

  As shown in FIG. 1, in the storage device 1 according to the present embodiment, a plurality of global bit lines 11 are provided. The global bit line 11 is formed by, for example, an upper layer portion of a silicon substrate (not shown) partitioned by an element isolation insulator (not shown), or an insulating film (not shown) on the silicon substrate. , And polysilicon is deposited thereon.

  Hereinafter, in this specification, an XYZ orthogonal coordinate system is adopted. The direction in which the global bit line 11 extends is defined as “X direction”, and the arrangement direction of the global bit line 11 is defined as “Y direction”. A direction perpendicular to the X direction and the Y direction is referred to as a “Z direction”. One of the Z directions is also referred to as “up” and the other is also referred to as “down”, but this expression is for convenience and is independent of the direction of gravity.

  A plurality of silicon members 12 are provided on each global bit line 11. As viewed from the Z direction, the silicon members 12 are arranged in a matrix along the X direction and the Y direction. The shape of each silicon member 12 is a rectangular parallelepiped with the Z direction as the longitudinal direction. The lower ends 12 a of the plurality of silicon members 12 arranged in a line along the X direction are commonly connected to one global bit line 11.

In each silicon member 12, n ^{+ -type} portion 13, p ^{− -type} portion 14, and n ^{+ -type} portion 15 are arranged in this order along the Z direction from the bottom, that is, from the global bit line 11 side to the top. ing. Note that the relationship between the n-type and the p-type may be reversed.

Between the silicon members 12 in the X direction, two gate electrodes 16 extending in the Y direction are provided. The gate electrode 16 is made of, for example, polysilicon. When viewed from the X direction, the gate electrode 16 overlaps the upper portion of the n ^{+ -type} portion 13, the entire p ^{− -type} portion 14, and the lower portion of the n ^{+ -type} portion 15.

A gate insulating film 17 made of, for example, silicon oxide is provided between the silicon member 12 and the gate electrode 16. The silicon member 12 including the n ^{+ -type} portion 13, the p ^{− -type} portion 14 and the n ^{+ -type} portion 15, the gate insulating film 17, and the pair of gate electrodes 16 sandwiching the silicon member 12 constitute, for example, an n-channel TFT 19. Has been. The TFT 19 is a switching element that switches between current conduction and interruption.

  On the silicon member 12, a local bit line 21 made of, for example, titanium nitride (TiN) is provided. The local bit line 21 extends in the Z direction, and its shape is, for example, a quadrangular prism. That is, the longitudinal direction of the local bit line 21 is the Z direction, and the length of the local bit line 21 in the Z direction is longer than the length in the X direction and the length in the Y direction.

  The lower end 21 a of the local bit line 21 is connected to the upper end 12 b of the silicon member 12. Since each local bit line 21 is disposed immediately above each silicon member 12, a plurality of local bit lines 21 are arranged in a matrix along the X direction and the Y direction in the entire storage device 1.

  A resistance change film 22 is provided on both side surfaces 21 c of the local bit line 21 facing the X direction. The resistance change film 22 is a film whose resistance state changes according to an applied voltage or current.

  A plurality of word lines 23 extending in the Y direction are provided between the local bit lines 21 adjacent in the X direction, and are arranged apart from each other in the Z direction. When viewed from the Y direction, the word lines 23 are arranged in a matrix along the X direction and the Z direction. The word line 23 is made of, for example, titanium nitride (TiN). The resistance change film 22 is connected between the local bit line 21 and the word line 23.

  Thus, a memory cell MC is configured via the resistance change film 22 at each intersection between the local bit line 21 and the word line 23. The memory cells MC are arranged in a three-dimensional matrix along the X direction, the Y direction, and the Z direction.

  As shown in FIG. 2, an interlayer insulating film 24 made of, for example, silicon oxide (SiO) is provided between the word lines 23 in the Z direction. Thereby, the word lines 23 and the interlayer insulating films 24 are alternately arranged along the Z direction. The distance between the interlayer insulating film 24 and the local bit line 21 is longer than the distance between the word line 23 and the local bit line 21. For this reason, a recess 25 is formed between adjacent word lines 23 in the Z direction.

  In the resistance change film 22, a low resistance layer (switch layer) 26 and a barrier layer 27 are laminated. The low resistance layer 26 is disposed on the local bit line 21 side, and the barrier layer 27 is disposed on the word line 23 side. That is, the low resistance layer 26 is disposed between the local bit line 21 and the barrier layer 27, and the barrier layer 27 is disposed between the low resistance layer 26 and the word line 23. The resistivity of the barrier layer 27 is higher than the resistivity of the low resistance layer 26.

  The low resistance layer 26 is made of, for example, a metal oxide, and is made of, for example, titanium oxide (TiO) or tungsten oxide (WO). The thickness of the low resistance layer 26 is, for example, about 6 nm. The low resistance layer 26 includes a main body portion 26b extending in the Z direction along the local bit line 21, and a convex portion extending from the main body portion 26b in the X direction and projecting into a space between adjacent word lines 23 in the Z direction. 26a is provided.

  The barrier layer 27 is made of, for example, amorphous silicon (aSi) or hafnium oxide (HfO). In the barrier layer 27, when an electric field is applied along the thickness direction (X direction), a tunnel current flows. The thickness of the barrier layer 27 is, for example, about 5 nm.

  The portion 27 b of the barrier layer 27 is disposed along the inner surface of the recess 25. Therefore, a recess 27 a reflecting the recess 25 is formed on the surface of the barrier layer 27 on the local bit line 21 side. And the convex part 26a of the low resistance layer 26 has entered into the concave part 27a. A portion 27b that covers the tip of the convex portion 26a of the low resistance layer 26 and the tip of the convex portion 26a in the barrier layer 27 is disposed between the word lines 23 adjacent in the Z direction. In other words, the barrier layer 27 covers the two surfaces of the convex portion 26a facing both sides in the Z direction and the front end surface of the convex portion 26a. Therefore, a part of the resistance change film 22 is disposed between the word lines 23 adjacent in the Z direction.

Next, the operation of the storage device according to this embodiment will be described.
FIG. 3 is a diagram illustrating a reset operation of the storage device according to the present embodiment.
As shown in FIG. 1, during the reset operation, a drive circuit (not shown) of the storage device 1 applies a positive write potential V _pgm to the selected global bit line 11. Further, an on potential is applied to the selected gate electrode 16 to make the TFT 19 conductive. As a result, the write potential V _pgm is applied to the selected local bit line 21 via the TFT 19. On the other hand, the drive circuit applies the ground potential (0 V) to the selected word line 23 and applies the potential (V _pgm / 2) to the non-selected word line 23.

As a result, as shown in FIG. 3, a voltage (V _pgm −0) is applied between the selected local bit line 21 and the selected word line 23s. For this reason, electrons gather in the portion 27 s disposed between the selected local bit line 21 and the selected word line 23 s in the barrier layer 27, and a tunnel electron current 31 flows. As a result, the resistance value of the portion 22s disposed between the local bit line 21 and the selected word line 23s in the resistance change film 22 increases. On the other hand, since only the voltage (V _pgm -V _pgm / 2) is applied between the selected local bit line 21 and the non-selected word line 23n, the tunnel current does not substantially flow.

  Further, the potential of the convex portion 26 a of the low resistance layer 26 is lowered and electrons are discharged, and the depletion layer 32 is formed starting from the interface with the barrier layer 27. For this reason, the electric field from the local bit line 21 is not so much applied to the portion 27b disposed in the recess 25 in the barrier layer 27, and electrons are not collected much. For this reason, the leakage current between the selected word line 23s and the non-selected word line 23n is suppressed.

Next, the effect of this embodiment will be described.
As described above, in the memory device 1 according to the present embodiment, the depletion layer 32 is formed at the tip of the convex portion 26a of the low resistance layer 26 at the time of reset, so that the portion disposed in the concave portion 25 in the barrier layer 27 In this case, the electric field of the local bit line 21 is difficult to reach. As a result, leakage current between the word lines 23 via the barrier layer 27 can be suppressed. Thereby, the memory cell MC can be driven independently with high accuracy.

(Comparative example)
Next, a comparative example will be described.
FIG. 4 is a cross-sectional view showing a memory cell of the memory device according to this comparative example.

  As shown in FIG. 4, in the memory device 101 according to this comparative example, the end surface of the word line 23 facing the local bit line 21 and the end surface of the interlayer insulating film 24 facing the local bit line 21 constitute substantially the same plane. doing. Therefore, the resistance change film 22 is formed flat along the Z direction, and does not enter between adjacent word lines 23 in the Z direction.

In the memory device 101, when 0 V is applied to the selected word line 23 s, a potential (V _pgm / 2) is applied to the unselected word line 23 n, and a write potential V _pgm is applied to the local bit line 21, the barrier layer 27 Electrons collect near the interface with the low-resistance layer 26 in FIG. As a result, the parasitic transistor 110 having the selected word line 23s as a source electrode, the non-selected word line 23n as a drain electrode, the low resistance layer 26 as a gate electrode, and the barrier layer 27 as a body is formed. An electron current 111 flows from 23s toward the unselected word line 23n. As a result, a leak current flows between the selected word line 23s and the non-selected word line 23n.

5A and 5B are diagrams showing simulation results of the electron density distribution in the barrier layer, where FIG. 5A shows the first embodiment and FIG. 5B shows a comparative example.
In FIG. 6, the horizontal axis represents the voltage between the bit line and the word line, and the vertical axis represents the absolute value of the current flowing through the word line, and the magnitude of the current flowing through each word line during the reset operation is compared. FIG. The horizontal axis in FIG. 6 is a linear axis, and the vertical axis is a logarithmic axis.

  As shown in FIG. 5A, in the memory device 1 according to the first embodiment described above, the electron density of the portion 27s arranged between the local bit line 21 and the selected word line 23s in the barrier layer 27 is shown. Was high. On the other hand, the electron density of the portion 27b disposed in the recess 25 in the barrier layer 27 was low. For this reason, the leakage current between the selected word line 23s and the non-selected word line 23n is suppressed.

  On the other hand, as shown in FIG. 5B, in the memory device 101 according to the comparative example, the electron density of the portion 27c between the low resistance layer 26 and the interlayer insulating film 24 in the barrier layer 27 is the barrier. The electron density of the portion 27 s between the low resistance layer 26 and the word line 23 in the layer 27 was higher. Thereby, it was estimated that a parasitic transistor having the barrier layer 27 as a body was formed.

  Further, as shown in FIG. 6, in the memory device according to the comparative example, the magnitude of the current flowing through the non-selected word line at the time of reset was about 1/10 of the magnitude of the current flowing through the selected word line. . In contrast, in the memory device according to the first embodiment, the magnitude of the current flowing through the non-selected word line at the time of reset is about 1/100 of the magnitude of the current flowing through the selected word line. Therefore, the first embodiment has a smaller leakage current than the comparative example.

(Second Embodiment)
Next, a second embodiment will be described.
FIG. 7 is a cross-sectional view showing a memory cell of the memory device according to this embodiment.

  As shown in FIG. 7, in the memory device 2 according to the present embodiment, an interface layer 28 is provided between the low resistance layer 26 and the barrier layer 27 of the resistance change film 22. The resistivity of the interface layer 28 is higher than the resistivity of the barrier layer 27. The interface layer 28 is made of, for example, aluminum oxide (AlO) or silicon oxide (SiO). The thickness of the interface layer 28 is thinner than the thickness of the low resistance layer 26 and the thickness of the barrier layer 27, for example, 0.5 nm. In the storage device 2, the tip of the convex portion 26 a of the low resistance layer 26, the portion of the barrier layer 27 covering the tip of the convex portion 26 a, and the tip of the convex portion 26 a in the interface layer 28 and the barrier layer 27. The portion arranged between them is arranged between adjacent word lines 23 in the Z direction. At the time of resetting and setting, a tunnel current flows through the interface layer 28 in the thickness direction, so that a current flows between the local bit line 21 and the word line 23.

In the present embodiment, since the interface layer 28 is provided between the low resistance layer 26 and the barrier layer 27, it is possible to effectively suppress mutual diffusion and reaction between the low resistance layer 26 and the barrier layer 27. it can. For example, when the low resistance layer 26 is formed of titanium oxide (TiO) and the barrier layer 27 is formed of amorphous silicon (aSi), titanium silicide is interposed between the low resistance layer 26 and the barrier layer 27. Formation of (TiSi) can be suppressed.
Other configurations, operations, and effects of the present embodiment are the same as those of the first embodiment.

(Third embodiment)
Next, a third embodiment will be described.
FIG. 8 is a cross-sectional view showing a memory cell of the memory device according to this embodiment.

  As shown in FIG. 8, the memory device 3 according to the present embodiment has an interlayer insulating film 24, a word line 23, and a barrier compared to the memory device 2 according to the second embodiment (see FIG. 7). The difference is that the metal oxide layer 29 is provided between the word line 23 and the barrier layer 27 arranged along the X direction. A portion of the interlayer insulating film 24 extending between the word line 23 and the barrier layer 27 is defined as an extending portion 24a. The metal oxide layer 29 is made of a metal oxide contained in the word line 23. For example, when the word line 23 is formed of titanium nitride (TiN), the metal oxide layer 29 is formed of titanium oxide (TiO).

According to the present embodiment, since the extended portion 24a of the interlayer insulating film 24 is disposed between the word line 23 and the barrier layer 27, the leak current flowing from the Z direction into the word line 23 is more effectively prevented. Can be suppressed.
Configurations, operations, and effects other than those described above in the present embodiment are the same as those in the second embodiment described above.

(Fourth embodiment)
Next, a fourth embodiment will be described.
FIG. 9 is a cross-sectional view showing a memory cell of the memory device according to the present embodiment.

  As shown in FIG. 9, the storage device 4 according to the present embodiment is different from the storage device 3 according to the third embodiment described above (see FIG. 8) in the low resistance layer 26 with the protrusions 26 a (FIG. 8). Reference point) is not provided, and the insulating member 30 is provided. The insulating member 30 is made of an insulating material, for example, silicon oxide (SiO). Instead of the insulating member 30, a gap may be formed. The insulating member 30 is disposed between the interface layer 28 in the Z direction, and is disposed between the interface layer 28 and the low resistance layer 26 in the X direction. A part of the insulating member 30 is disposed between adjacent word lines 23 in the Z direction. The interface layer 28 and the barrier layer 27 include two surfaces facing the both sides in the Z direction of the insulating member 30 and a surface facing the interlayer insulating film 24 of the insulating member 30, that is, a surface opposite to the local bit line 21. Covering. On the other hand, the low resistance layer 26 is not disposed between adjacent word lines 23 in the Z direction.

In the memory device 4 according to this embodiment, since the insulating member 30 is provided between the word lines 23 adjacent in the Z direction, the leakage current between the word lines 23 can be suppressed. Since the insulating member 30 is insulative, the current can be cut off even if the depletion layer is not formed. Therefore, the leak current between the word lines 23 can be suppressed not only at the time of resetting but also at the time of setting when a potential higher than that of the local bit line 21 is applied to the selected word line 23.
Configurations, operations, and effects other than those described above in the present embodiment are the same as those in the third embodiment described above.

(Fifth embodiment)
Next, a fifth embodiment will be described.
FIG. 10 is a cross-sectional view showing a memory cell of the memory device according to this embodiment.

  As shown in FIG. 10, in the storage device 5 according to the present embodiment, both the convex portion 26 a and the insulating member 30 are provided between the word lines 23 adjacent in the Z direction. On the other hand, the extension 24a (see FIG. 9) and the metal oxide layer 29 (see FIG. 9) of the interlayer insulating film 24 are not provided. Further, the interface layer 28 is disposed between the low resistance layer 26 and the barrier layer 27 and between the low resistance layer 26 and the insulating member 30. Thereby, between the adjacent word lines 23 in the Z direction, the interlayer insulating film 24 including the extended portion 24a, a part of the barrier layer 27, the insulating member 30, a part of the interface layer 28, and the low resistance layer 26 protrude. A part of the portion 26a is arranged.

According to this embodiment, the same effect as that of the fourth embodiment can be obtained.
Configurations, operations, and effects other than those described above in the present embodiment are the same as those in the fourth embodiment described above.

(Sixth embodiment)
Next, a sixth embodiment will be described.
The present embodiment is an embodiment of a method for manufacturing a storage device.
FIGS. 11A and 11B and FIGS. 12A and 12B are cross-sectional views illustrating the method for manufacturing the memory device according to the present embodiment.

First, as shown in FIG. 1, a plurality of global bit lines 11 extending in the X direction are formed by a normal method.
Next, as shown in FIG. 11A, the silicon member 12, the electrode film 41, the gate insulating film 17, and the gate electrode 16 extending in the Y direction are formed, and the space between them is filled with an interlayer insulating film 40.
Next, the interlayer insulating film 24 and the word line 23 are alternately stacked to form a stacked body 42. The interlayer insulating film 24 is formed by, for example, silicon oxide (SiO), and the word line 23 is formed by, for example, titanium nitride (TiN). Next, a trench 43 extending in the Y direction is formed in the stacked body 42. The trench 43 is formed at a position connecting the region directly above the silicon member 12. Thereby, the word line 23 is processed into a wiring shape extending in the Y direction.

  Next, as shown in FIG. 11B, the portion of the interlayer insulating film 24 exposed on the inner surface of the trench 43 is recessed. As a result, a recess 25 is formed between adjacent word lines 23 in the Z direction.

  Next, as shown in FIG. 12A, for example, amorphous silicon (aSi) or hafnium oxide (HfO) is deposited to form the barrier layer 27 on the inner surface of the recess 25 and the trench 43. When amorphous silicon is deposited, the exposed surface of the word line 23 may be oxidized to form a metal oxide layer 29 (see FIG. 8) made of titanium oxide (TiO). Next, for example, aluminum oxide (AlO) is deposited to form the interface layer 28 on the barrier layer 27.

  Next, as shown in FIG. 12B, anisotropic etching is performed to remove portions of the interface layer 28 and the barrier layer 27 that are disposed on the bottom surface of the trench 43, thereby exposing the electrode film 41. . Next, for example, a metal oxide such as titanium oxide (TiO) or tungsten oxide (WO) is deposited to form the low resistance layer 26. At this time, the low resistance layer 26 fills the recess 25 and is formed on the inner surface of the trench 43, but does not completely fill the trench 43. The low resistance layer 26 is connected to the electrode film 41. Next, for example, titanium nitride (TiN) is deposited to form the local bit line 21 in the trench 43.

  Next, a line-and-space mask (not shown) extending in the X direction is formed on the laminate 42 and anisotropic etching is performed to divide the local bit line 21 and the low resistance layer 26 in the Y direction. To do. Next, an insulating member (not shown) is embedded in the space after the local bit line 21 and the low resistance layer 26 are removed. Thereby, the storage device is manufactured.

  According to the present embodiment, the storage device 2 according to the second embodiment (see FIG. 7), the storage device 3 according to the third embodiment (see FIG. 8), or a storage device similar to these is manufactured. Is done.

  In the present embodiment, the example in which the interface layer 28 is formed by depositing aluminum oxide in the step shown in FIG. 12A is shown, but the present invention is not limited to this. For example, when the barrier layer 27 is formed of amorphous silicon (aSi) and titanium oxide (TiO) is deposited as the low resistance layer 26, silicon oxide (SiO 2) is interposed between the barrier layer 27 and the low resistance layer 26. ) Is naturally formed. Further, if the low resistance layer 26 is formed on the barrier layer 27 in a non-oxidizing atmosphere, the interface layer 28 is not formed, and the memory device similar to the first embodiment described above or a similar device is manufactured.

(Seventh embodiment)
Next, a seventh embodiment will be described.
13A, 13B, and 14 are cross-sectional views illustrating a method for manufacturing the memory device according to the present embodiment.

  First, the steps shown in FIGS. 11A to 12A are performed. However, in the step shown in FIG. 11B, when recessing the interlayer insulating film 24, a part of the interlayer insulating film 24 is left on the upper surface and the lower surface of the word line 23, thereby extending the extended portion 24a (FIG. 9). Reference).

  Next, as shown in FIG. 13A, an insulating film 30f is formed on the inner surface of the trench 43 by oxidizing the surface of the barrier layer 27 made of amorphous silicon or depositing silicon oxide. . The insulating film 30f is formed so as to fill the recess 25.

  Next, as shown in FIG. 13B, the insulating film 30f is etched. Thereby, a portion of the insulating film 30f formed on the inner surface of the trench 43 is removed. On the other hand, a portion of the insulating film 30f formed in the recess 25 is left as the insulating member 30. Next, portions of the interface layer 28 and the barrier layer 27 that are disposed on the bottom surface of the trench 43 are removed.

  Next, as shown in FIG. 14, the low resistance layer 26 and the local bit line 21 are formed. The subsequent steps are the same as those in the sixth embodiment described above. In this way, the storage device is manufactured.

  According to the present embodiment, the storage device 4 (see FIG. 9) according to the above-described fourth embodiment or a storage device similar thereto is manufactured.

(Eighth embodiment)
Next, an eighth embodiment will be described.
FIGS. 15A and 15B and FIGS. 16A and 16B are cross-sectional views illustrating the method for manufacturing the memory device according to this embodiment.

First, the steps shown in FIGS. 11A and 11B are performed.
Next, as shown in FIG. 15A, for example, amorphous silicon (aSi) is deposited to form the barrier layer 27 on the inner surfaces of the recess 25 and the trench 43. Next, the insulating film 30f is formed on the inner surface of the trench 43 by oxidizing the surface of the barrier layer 27 or depositing silicon oxide. The insulating film 30f is formed so as to fill the recess 25.

  Next, as shown in FIG. 15B, the insulating film 30f is etched. Thus, the entire portion formed on the inner surface of the trench 43 and the portion formed near the opening in the recess 25 are removed from the insulating film 30f. On the other hand, a portion of the insulating film 30f formed in the inner portion of the recess 25 is left to form the insulating member 30.

  Next, as illustrated in FIG. 16A, for example, aluminum oxide (AlO) is deposited to form the interface layer 28 on the barrier layer 27 and the insulating member 30.

Next, as shown in FIG. 16B, portions of the interface layer 28 and the barrier layer 27 that are disposed on the bottom surface of the trench 43 are removed.
Next, the low resistance layer 26 and the local bit line 21 are formed. The subsequent steps are the same as those in the sixth embodiment described above. In this way, the storage device is manufactured.

  According to the present embodiment, the storage device 5 (see FIG. 10) according to the fifth embodiment described above or a storage device similar thereto is manufactured.

  According to the embodiment described above, it is possible to realize a memory device that can drive memory cells accurately and independently.

  As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and the equivalents thereof.

1,2,3,4,5: storage device, 11: a global bit line, 12: silicon member, 12a: lower end, 12b: upper end, 13: ^{n +} form part, 14: p ^- form part, 15: ^{n +} 16: Gate electrode, 17: Gate insulating film, 19: TFT, 21: Local bit line, 21a: Lower end, 21c: Side surface, 22: Resistance change film, 22s: Part, 23: Word line, 23n: Non Selected word line, 23s: Selected word line, 24: Interlayer insulating film, 24a: Extension part, 25: Concave part, 26: Low resistance layer, 26a: Convex part, 26b: Main part, 27: Barrier layer, 27a: Concave part 27b: part, 27c: part, 27s: part, 28: interface layer, 29: metal oxide layer, 30: insulating member, 30f: insulating film, 31: tunneling electron current, 32: depletion layer, 40: interlayer insulating film , 41: electrode film, 42: lamination , 43: trench, 101: storage unit, 110: parasitic transistor, 111: electron current, MC: Memory cell

Claims (20)

A first wiring extending in a first direction;
A second wiring extending in a second direction intersecting the first direction;
A third wiring disposed in the first direction and extending in the second direction as viewed from the second wiring;
A first resistance change film provided between the first wiring and the second wiring and between the first wiring and the third wiring;
With
The first variable resistance film has two or more layers having different compositions.
A storage device in which at least two of the two or more layers are arranged between the second wiring and the third wiring in the first direction. One of the two or more layers is a first layer containing a metal oxide,
The other one of the two or more layers is disposed between the first layer and the second wiring and between the first layer and the third wiring, and includes a second layer containing silicon. Layer,
The first layer is
A main body extending in the first direction;
A convex portion protruding from the main body,
Have
The second layer covers two surfaces of the convex portion facing both sides of the first direction, and a tip surface of the convex portion,
2. The storage device according to claim 1, wherein a portion covering the tip of the convex portion and the tip of the second layer is disposed between the second wiring and the third wiring in the first direction. A first insulating film provided between the second wiring and the third wiring;
The first insulating film is
A first extension extending between the second wiring and the second layer;
A second extension extending between the third wiring and the second layer;
The storage device according to claim 2. The first variable resistance film has three or more layers having different compositions from each other,
One of the three or more layers is a first layer containing a metal oxide,
The other one of the three or more layers is disposed between the first layer and the second wiring and between the first layer and the third wiring, and includes a second layer containing silicon. Layer,
The other one of the three or more layers is a third layer that is disposed between the first layer and the second layer and is made of an insulating material.
The second layer covers two surfaces of the third layer facing both sides of the first direction and a surface facing the opposite side of the first layer;
A part of the third layer and a part of the second layer covering the part of the third layer are disposed between the second wiring and the third wiring in the first direction. Item 4. The storage device according to Item 1.   The storage device according to claim 4, wherein the first layer is not disposed between the second wiring and the third wiring in the first direction. The first variable resistance film has three or more layers having different compositions from each other,
One of the three or more layers is a first layer containing a metal oxide,
The other one of the three or more layers is disposed between the first layer and the second wiring and between the first layer and the third wiring, and includes a second layer containing silicon. Layer,
One of the three or more layers is a third layer made of an insulating material,
The first layer is
A main body extending in the first direction;
A protrusion protruding from the main body and disposed between the main body and the third layer;
Have
The second layer has two surfaces facing the both sides in the first direction in the convex portion, two surfaces facing the both sides in the first direction in the third layer, and the convex in the third layer. Cover the surface facing the other side,
A part of the convex part, the third layer, and a part of the second layer that covers the part of the convex part and the third layer are the second wiring and the third wiring in the first direction. The storage device according to claim 1, which is disposed between the storage devices. Another one of the three or more layers is disposed between the first layer and the second layer, and the resistivity is higher than the resistivity of the first layer and the resistivity of the second layer. Is a high fourth layer,
The storage device according to claim 2, wherein a part of the fourth layer is also disposed between the second wiring and the third wiring in the first direction. One of the two or more layers is a first layer extending in the first direction,
The other one of the two or more layers is a second layer disposed between the first layer and the second wiring and between the first layer and the third wiring. The storage device according to claim 1.   The memory device according to claim 8, wherein the first layer includes a metal oxide.   The memory device according to claim 9, wherein the metal oxide is titanium oxide or tungsten oxide.   The memory device according to claim 8, wherein the second layer includes silicon, silicon oxide, or hafnium oxide. The first variable resistance film has three or more layers having different compositions from each other,
Another one of the three or more layers is disposed between the first layer and the second layer, and the resistivity is higher than the resistivity of the first layer and the resistivity of the second layer. The storage device according to any one of claims 8 to 11, which is a higher third layer.   The memory device according to claim 12, wherein the third layer includes aluminum oxide or silicon oxide.   The storage device according to claim 12, wherein the third layer is thinner than the first layer and thinner than the second layer.   The part of the first layer and the part of the second layer are arranged between the second wiring and the third wiring in the first direction. The storage device according to one. The first layer is
A main body extending in the first direction;
A convex portion protruding from the main body portion into a space between the second wiring and the third wiring;
Have
The storage device according to claim 15, wherein the second layer covers two surfaces of the convex portion facing both sides of the first direction and a tip surface of the convex portion. The first variable resistance film has three or more layers having different compositions from each other,
One of the three or more layers is a fourth layer made of an insulating material,
15. The device according to claim 8, wherein a part of the second layer and at least a part of the fourth layer are arranged between the second wiring and the third wiring in the first direction. The storage device according to any one of the above. A fourth wiring extending in a direction crossing the first direction;
A first semiconductor member connected between the first wiring and the fourth wiring;
A fifth wiring extending in a direction intersecting the direction in which the fourth wiring extends;
A second insulating film provided between the first semiconductor member and the fifth wiring;
The storage device according to claim 1, further comprising: A sixth wiring extending in the first direction;
A second resistance change film provided between the sixth wiring and the second wiring and between the sixth wiring and the third wiring;
A second semiconductor member connected between the sixth wiring and the fourth wiring;
A seventh wiring extending in a direction intersecting the direction in which the fourth wiring extends;
A third insulating film provided between the second semiconductor member and the seventh wiring;
The storage device according to claim 18, further comprising: The fourth wiring extends in a third direction intersecting a plane including the first direction and the second direction;
The storage device according to claim 18, wherein the fifth wiring extends in the second direction.