JP2018085753A - Level shift circuit, electrooptical device, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a level shift circuit that has a small circuit occupation area and a low power consumption, and that can operate at a high speed.SOLUTION: A level shift circuit 10 comprises: an input part IN to which a value between a first potential Vand a second potential Vis inputted; a first output part OUT1 from which a value between a third potential Vand a fourth potential Vis outputted; a first capacitive element and a second capacitive element electrically series-connected between the input part IN and a fifth power supply part EP5 supplied with a fifth potential V; and a first inverter circuit INV1 supplied with the third potential Vand the fourth potential V. A connection point between the first capacitive element and the second capacitive element and an input node of the first inverter circuit INV1 are electrically connected with each other. An output node of the first inverter circuit INV1 is the first output part OUT1. Thereby, a level shift circuit that has a small occupation area and a low power consumption, and that can operate at a high speed, can be achieved.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a level shift circuit, an electro-optical device, and an electronic apparatus.

  In an electronic apparatus having a display function, a transmissive electro-optical device or a reflective electro-optical device is used. Light is irradiated to these electro-optical devices, and transmitted light or reflected light modulated by the electro-optical device becomes a display image, or is projected on a screen to become a projection image. A liquid crystal device is known as an electro-optical device used in such an electronic apparatus, which forms an image using the dielectric anisotropy of liquid crystal and the optical rotation of light in a liquid crystal layer. .

  In general, a relatively high voltage is required to drive an electro-optical device. On the other hand, an external control circuit that supplies a clock signal, a control signal, and the like as a driving reference to the electro-optical device is configured by a semiconductor integrated circuit, and the amplitude of the logic signal is about 1.8V to about 5V. The voltage is low. Therefore, the electro-optical device is generally provided with an amplitude conversion circuit (hereinafter referred to as a level shift circuit) that converts a low-amplitude logic signal from a semiconductor integrated circuit into a high-amplitude logic signal. An example of the level shift circuit is described in Patent Document 1. FIG. 1 of Patent Document 1 describes a level shift circuit based on a capacitive coupling operation.

JP 2003-110419 A

  However, the level shift circuit described in Patent Literature 1 includes a potential control circuit based on signal feedback, and thus has a problem that the circuit occupies a large area. The level shift circuit described in Patent Document 1 uses an offset voltage generation circuit in which an input node and an output node of an inverter circuit are self-connected. The offset voltage generation circuit always has a through current between power supplies. Because of the continuous generation of power, there was a problem of high power consumption. Further, in the liquid crystal device, the amount of data is increased with the increase in definition of a display image, but on the other hand, high-speed driving is necessary from the viewpoint of improvement of moving image display characteristics and three-dimensional display driving. For this reason, high-speed operation of the level shift circuit is strongly demanded, but the level shift circuit described in Patent Document 1 has a problem that high-speed driving is difficult. In other words, the conventional level shift circuit has a problem that it is difficult to realize high-speed operation with low power consumption in a circuit having a small occupation area (or a circuit having a small circuit scale).

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

Application Example 1 A level shift circuit according to this application example includes an input unit to which an input signal having a value between the first potential and the second potential is input, and between the third potential and the fourth potential. A first capacitive element and a second capacitive element that are electrically connected in series between the first output section that outputs the output signal that is a value, and the fifth power supply section that is supplied with the input section and the fifth potential And a first inverter circuit to which a third potential and a fourth potential are supplied, and a connection point between the first capacitor element and the second capacitor element and an input node of the first inverter circuit are electrically connected It is connected, The output node of a 1st inverter circuit is a 1st output part, It is characterized by the above-mentioned.
According to this configuration, the first capacitor element and the second capacitor element form a potential converter, and the connection point between the first capacitor element and the second capacitor element is the output node of the potential converter (the first inverter circuit of the first inverter circuit). Input node). In the potential converter, the potential of the input node of the first inverter circuit is determined by capacitive coupling between the first capacitor element and the second capacitor element. In other words, in accordance with the input signal, the potential conversion is performed by redistributing the charges at the output node of the potential conversion unit (the input node of the first inverter circuit), so that the level shift circuit capable of high-speed operation is provided. Can be realized. In addition, since the electric charge at the output node of the potential converter is stored, it is possible to reduce power consumption in the level shift circuit without generating extra current such as through current. Furthermore, since the level shift circuit has a small circuit scale, the occupied area can be reduced. In other words, a level shift circuit having a small occupation area, low power consumption, and capable of high-speed operation can be realized.

Application Example 2 In the level shift circuit according to Application Example 1, the first capacitor element includes a first capacitor first electrode and a first capacitor second electrode, and the second capacitor element includes a second capacitor first electrode. And the second capacitor second electrode, the first capacitor first electrode is electrically connected to the fifth power supply unit, the second capacitor second electrode is electrically connected to the input unit, and the first capacitor first electrode The two electrodes and the second capacitor first electrode are preferably electrically connected to form a connection point.
According to this configuration, the first capacitive element and the second capacitive element can constitute a capacitively coupled potential converter.

Application Example 3 The level shift circuit according to Application Example 1 or 2 includes a second inverter circuit and a second output unit, and the output node of the first inverter circuit and the input node of the second inverter circuit are electrically connected. It is preferable that the output node of the second inverter circuit is the second output unit.
A high-amplitude signal (first output signal) obtained by inverting the logic of the input signal is output from the first output unit. On the other hand, according to this configuration, the second output unit can output a high-amplitude signal (second output signal) having the same logic as the input signal. Further, the second output signal can be made closer to the third potential or the fourth potential than the amplitude of the first output signal. That is, the amplitude of the second output signal can be made larger than the amplitude of the first output signal.

Application Example 4 In the level shift circuit according to any one of Application Examples 1 to 3, the first inverter circuit includes a third power supply unit to which a third potential is supplied and a fourth power source to which a fourth potential is supplied. An N-type transistor and a P-type transistor are connected in series with the power supply unit, and the first potential is V ₁ , the second potential is V ₂ , the third potential is V ₃ , the fourth potential is V ₄ , 5 potential is V ₅ , the capacitance value of the first capacitor element is C ₁ , the capacitance value of the second capacitor element is C ₂ , the capacitance value of the N-type transistor is C _N , the capacitance value of the P-type transistor is C _P , When the logical threshold voltage of the inverter circuit is represented by V _T , it is preferable to satisfy the relational expression of Expression 1 and Expression 2.


The potential at the output node (input node of the first inverter circuit) of the potential converter is referred to as an intermediate potential, the intermediate potential when the input signal is the first potential V ₁ is named the sixth potential V _6, and the input signal is the second potential. The intermediate potential at the time of the potential V ₂ is named as a seventh potential V ₇ . The first inverter circuit has a logical threshold potential (V ₃ + V _T ). According to this configuration, when the input signal is the first potential V ₁ , the sixth potential V _{6 is set} to the logical threshold potential of the first inverter circuit. (V ₃ + V _T) lower than the input signal during a second potential V ₂ may be higher than the seventh potential V ₇ logic threshold potential of the first inverter circuit (V ₃ + V _T) . Therefore, when the input signal is the first potential V ₁ , a signal having a potential value between the logic threshold potential (V ₃ + V _T ) and the fourth potential V ₄ is output from the output node of the first inverter circuit. When the input signal is the second potential V ₂ , a signal having a potential value between the third potential V ₃ and the logic threshold potential (V ₃ + V _T ) can be output. That is, with a simple circuit configuration, it is possible to correctly convert an input signal into a high-amplitude logic signal at high speed with low power consumption.

Application Example 5 In the level shift circuit according to any one of Application Examples 1 to 3, the first inverter circuit includes a third power supply unit to which a third potential is supplied and a fourth power source to which a fourth potential is supplied. An N-type transistor and a resistance element are connected in series between the power supply unit, the first potential is V ₁ , the second potential is V ₂ , the third potential is V ₃ , the fourth potential is V ₄ , and the fifth element The potential is V ₅ , the capacitance value of the first capacitive element is C ₁ , the capacitance value of the second capacitive element is C ₂ , the capacitance value of the N-type transistor is C _N , and the logical threshold voltage of the first inverter circuit is V _T. It is preferable to satisfy the relational expression between Expression 3 and Expression 4.


The potential at the output node (input node of the first inverter circuit) of the potential converter is referred to as an intermediate potential, the intermediate potential when the input signal is the first potential V ₁ is named the sixth potential V _6, and the input signal is the second potential. The intermediate potential at the time of the potential V ₂ is named as a seventh potential V ₇ . The first inverter circuit has a logical threshold potential (V ₃ + V _T ). According to this configuration, when the input signal is the first potential V ₁ , the sixth potential V _{6 is set} to the logical threshold potential of the first inverter circuit. (V ₃ + V _T) lower than the input signal during a second potential V ₂ may be higher than the seventh potential V ₇ logic threshold potential of the first inverter circuit (V ₃ + V _T) . Therefore, when the input signal is the first potential V ₁ , a signal having a potential value between the logic threshold potential (V ₃ + V _T ) and the fourth potential V ₄ is output from the output node of the first inverter circuit. When the input signal is the second potential V ₂ , a signal having a potential value between the third potential V ₃ and the logic threshold potential (V ₃ + V _T ) can be output. That is, with a simple circuit configuration, it is possible to correctly convert an input signal into a high-amplitude logic signal at high speed with low power consumption.

Application Example 6 In the level shift circuit according to any one of Application Examples 1 to 3, the first inverter circuit includes a third power supply unit to which a third potential is supplied and a fourth power source to which a fourth potential is supplied. A resistor element and a P-type transistor connected in series with the power supply unit are provided. The first potential is V ₁ , the second potential is V ₂ , the third potential is V ₃ , the fourth potential is V ₄ , The potential is V ₅ , the capacitance value of the first capacitance element is C ₁ , the capacitance value of the second capacitance element is C ₂ , the capacitance value of the P-type transistor is C _P , and the logical threshold voltage of the first inverter circuit is V _T. It is preferable to satisfy the relational expression between Formula 5 and Formula 6.


The potential at the output node (input node of the first inverter circuit) of the potential converter is referred to as an intermediate potential, the intermediate potential when the input signal is the first potential V ₁ is named the sixth potential V _6, and the input signal is the second potential. The intermediate potential at the time of the potential V ₂ is named as a seventh potential V ₇ . The first inverter circuit has a logical threshold potential (V ₃ + V _T ). According to this configuration, when the input signal is the first potential V ₁ , the sixth potential V _{6 is set} to the logical threshold potential of the first inverter circuit. (V ₃ + V _T) lower than the input signal during a second potential V ₂ may be higher than the seventh potential V ₇ logic threshold potential of the first inverter circuit (V ₃ + V _T) . Therefore, when the input signal is the first potential V ₁ , a signal having a potential value between the logic threshold potential (V ₃ + V _T ) and the fourth potential V ₄ is output from the output node of the first inverter circuit. When the input signal is the second potential V ₂ , a signal having a potential value between the third potential V ₃ and the logic threshold potential (V ₃ + V _T ) can be output. That is, with a simple circuit configuration, it is possible to correctly convert an input signal into a high-amplitude logic signal at high speed with low power consumption.

Application Example 7 In the level shift circuit according to any one of Application Examples 1 to 6, it is preferable that the fourth potential and the fifth potential are equal.
The third potential V ₃ , the fourth potential V _4, and the fifth potential V ₅ are high-voltage power supplies, but according to this configuration, the number of high-voltage power supplies can be reduced.

Application Example 8 An electro-optical device according to this application example includes the level shift circuit according to any one of Application Examples 1 to 7.
According to this configuration, it is possible to realize an electro-optical device that can be driven at high speed with low power consumption by narrowing the peripheral region located on the outer periphery of the display region. In other words, a high-quality display can be performed on an electro-optical device that has a wide display area ratio relative to the entire electro-optical device and is excellent in design.

Application Example 9 An electronic apparatus according to this application example includes the electro-optical device according to Application Example 8 described above.
According to this configuration, it is possible to realize an electronic apparatus including an electro-optical device that has excellent design, low power consumption, and high-quality display.

The figure explaining the level shift circuit. The figure explaining the inverter circuit used for a level shift circuit. The equivalent circuit diagram in the 1st node of a level shift circuit. FIG. 6 is a potential relationship diagram illustrating the operation principle of the level shift circuit. The figure which verified the function of the level shift circuit. The figure which verified the function of the level shift circuit. FIG. 2 is a schematic plan view showing a circuit block configuration of an electro-optical device. FIG. 3 is a schematic cross-sectional view of a liquid crystal device. FIG. 3 is an equivalent circuit diagram illustrating an electrical configuration of the liquid crystal device. 10A and 10B each illustrate an electronic device. FIG. 6 is a circuit configuration diagram illustrating a level shift circuit according to a second embodiment. FIG. 5 is a circuit configuration diagram illustrating a level shift circuit according to a third embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the scale of each layer and each member is made different from the actual scale so that each layer and each member can be recognized.

(Embodiment 1)
"Circuit function"
1A and 1B are diagrams illustrating a level shift circuit according to the first embodiment, where FIG. 1A is a circuit configuration diagram and FIG. 1B is a potential relationship diagram. First, the function of the level shift circuit 10 according to the first embodiment will be described with reference to FIG.

  As shown in FIG. 1A, the level shift circuit 10 according to this embodiment includes an input unit IN to which an input signal is input, a potential conversion unit 18, a buffer unit 13, and an output from which an output signal is output. And a section. The buffer unit 13 includes a first inverter circuit INV1 and a second inverter circuit INV2. The output unit includes a first output unit OUT1 and a second output unit OUT2. A first output signal is output from the first output unit OUT1, and a second output signal is output from the second output unit OUT2. . The first output signal is a high-amplitude signal obtained by inverting the logic of the input signal, and the second output signal is a high-amplitude signal having the same logic as the input signal. The level shift circuit 10 is a circuit that converts a logic signal from a low voltage system circuit (not shown) into a logic signal suitable for a high voltage system circuit (not shown). As an output signal, the first output signal or the second output is used. Signals or these signals are further improved in driving capability by other inverter circuits or buffer circuits.

Input signal to the level shift circuit 10 includes a low-voltage circuit (e.g., configured the external control circuit in the semiconductor integrated circuit) is produced by, as shown in FIG. 1 (b), the first electric potential V ₁ The value is between the second potential V ₂ . The first potential V ₁ is _one of two power supply potentials (positive power supply potential and negative power supply potential) used in the low voltage system circuit, and the second potential V ₂ is two power supply potentials used in the low voltage system circuit. The other of (positive power supply potential and negative power supply potential). In the present embodiment, the first potential V ₁ is the negative power supply potential of the low voltage system circuit (referred to as the low voltage system negative power supply potential V _SS ), and the second potential V ₂ is the positive power supply potential (low voltage of the low voltage system circuit). Voltage system positive power supply potential V _DD ). The input signal has at least logic 0 and logic 1. In this embodiment, the input signal corresponding to logic 0 is the first potential V ₁ or a potential close to the first potential V ₁ , and at least the first This is a potential that is a value on the first potential V ₁ side of the average potential of the first potential V ₁ and the second potential V ₂ . Similarly, the input signal corresponding to the logic 1 is the second potential V ₂ or a potential close to the second potential V ₂ , and is at least more than the average potential of the first potential V ₁ and the second potential V _2. This is a potential that is a value on the second potential V ₂ side. In many cases, the amplitude of the logic signal in the low-voltage circuit (low-amplitude logic signal, potential difference between the first potential V ₁ and the second potential V ₂ ) is about 1.8V to about 5V.

The potential converter 18 converts the first potential V ₁ to the sixth potential V ₆ , converts the second potential V ₂ to the seventh potential V ₇ , and outputs it to the output node of the potential converter 18. That is, an input signal having a value between the first potential V ₁ and the second potential V ₂ is converted into an intermediate signal having a value between the sixth potential V ₆ and the seventh potential V ₇ . In the present embodiment, the intermediate signal corresponding to the logic 0 input signal is the sixth potential V ₆ or a potential close to the sixth potential V ₆ , and the intermediate signal corresponding to the logic 1 input signal is the seventh potential V ₇ or a potential close to the seventh potential V _7. In this example, the sixth potential V ₆ is a lower potential (referred to as an intermediate low potential V _ML ) among the intermediate signals at the output node of the potential converter 18, and the seventh potential V ₇ is the potential converter 18. The higher potential of the intermediate signals at the output node (referred to as intermediate high potential V _MH ).

The output node of the potential conversion unit 18 and the input node of the buffer unit 13 are electrically connected, and the output from the potential conversion unit 18 is input to the buffer unit 13. Hereinafter, the output node of the potential converter 18 and the input node of the buffer unit 13 are referred to as a first node (NODE1). The buffer unit 13 converts the sixth potential V ₆ input to the buffer unit 13 to the third potential V ₃ or a potential close to the third potential V ₃ , and converts the seventh potential V ₇ to the fourth potential V ₄ or the fourth potential V ₄ . 4 into a potential close to the potential V _4, and outputs the value to become the output signal between the output node of the buffer unit 13 and the third electric potential V ₃ and the fourth electric potential V _4. The output node of the buffer unit 13 is the second output unit OUT2 of the level shift circuit 10, and this node is referred to as a third node (NODE3). Note that the output node (first output unit OUT1) of the first inverter circuit INV1 constituting the buffer unit 13 may be the first output unit OUT1 of the level shift circuit 10, and this node is the second node (NODE2). Called. The output section of the level shift circuit 10 can be either the first output section OUT1 or the second output section OUT2. Either one can be selected as appropriate in accordance with a high voltage circuit to which a high amplitude signal is supplied from the level shift circuit 10.

The third potential V ₃ is one of two power supply potentials (positive power supply potential and negative power supply potential) used in the high voltage system circuit, and the fourth potential V ₄ is two power supply potentials used in the high voltage system circuit. The other of (positive power supply potential and negative power supply potential). In the present embodiment, the third potential V ₃ is a negative power supply potential of the high voltage system circuit (referred to as a high voltage system negative power supply potential V _LL ), and the fourth potential V ₄ is a positive power supply potential (high voltage system circuit of the high voltage system circuit). Voltage system positive power supply potential V _HH ). Like the input signal, the output signal has at least logic 0 and logic 1. In this embodiment, the output signal corresponding to logic 0 is the third potential V ₃ or the third potential V ₃ . The potential is close, and is a potential that is at least a value on the third potential V ₃ side of the average potential of the third potential V ₃ and the fourth potential V ₄ . Similarly, the output signal corresponding to logic 1 is the fourth potential V ₄ or a potential close to the fourth potential V ₄ , and is at least higher than the average potential of the third potential V ₃ and the fourth potential V _4. This is a potential that is a value on the fourth potential V ₄ side. The amplitude of the logic signal in the high voltage system circuit (potential difference between the third potential V ₃ and the fourth potential V ₄ ) is the amplitude of the logic signal in the low voltage system circuit (potential difference between the first potential V ₁ and the second potential V _2). ) And may be set to about 5 V to 50 V in the electro-optical device. In the present embodiment, as an example, the amplitude of the logic signal in the low voltage system circuit (potential difference between the first potential V ₁ and the second potential V ₂ ) is 5 V or 3.3 V, and the logic signal in the high voltage system circuit The amplitude (high amplitude logic signal, potential difference between the third potential V ₃ and the fourth potential V ₄ ) is 10V. In the present embodiment, the low voltage system negative power supply potential V _SS and the high voltage system negative power supply potential V _LL are equal, and both are set to the reference potential (V _SS = V _LL = 0V). Note that the low voltage system negative power supply potential V _SS and the high voltage system negative power supply potential V _LL may be different from each other or may not be the reference potential.

As described above, in the buffer unit 13, the intermediate signal having a value between the sixth potential V ₆ and the seventh potential V ₇ has a value between the third potential V ₃ and the fourth potential V ₄ . It is converted into an output signal or a second output signal. The buffer unit 13 has a logic threshold voltage V _T. When the third potential V ₃ is supplied as the negative power supply potential and the fourth potential V ₄ is supplied as the positive power supply potential to the buffer unit 13, the logical threshold potential of the buffer unit 13 is the third potential V ₃ and the logical threshold value. It is the sum (V ₃ + V _T ) with the voltage V _T. The sixth potential V _{6 at} the first node (NODE1) is a value between the logic threshold potential (V ₃ + V _T ) and the third potential V _3, and the seventh potential V ₇ is the logic threshold potential (V ₃ + V _T ) and the fourth potential V ₄ . As a result, the intermediate low potential V _ML (sixth potential V ₆ ) that is on the third potential V ₃ side of the logic threshold potential (V ₃ + V _T ) V ₃ + V _T ) is a value on the fourth potential V ₄ side, and the intermediate high potential V _MH (seventh) is a value on the fourth potential V ₄ side of the logic threshold potential (V ₃ + V _T ). The potential V ₇ ) is set to a value on the third potential V ₃ side with respect to the logical threshold potential (V ₃ + V _T ) at the second node (NODE2). Further, the third node (NODE3), both are close to the sixth potential V ₆ Gayori third potential V _3, is a value close to the seventh potential V ₇ Gayori fourth potential V _4. As described above, the second output unit OUT2 of the buffer unit 13 applies the intermediate signal (sixth potential V ₆ ) having a value closer to the third potential V ₃ than the logical threshold potential (V ₃ + V _T ) to the third potential V. ₃ is a circuit having a function of bringing the intermediate signal (seventh potential V ₇ ) having a value closer to the fourth potential V ₄ than the logical threshold potential (V ₃ + V _T ) closer to the fourth potential V ₄ .

The fifth potential V ₅ supplied to the potential converter 18 includes an intermediate low potential V _ML (sixth potential V ₆ ) and an intermediate high potential V _MH (seventh potential V ₇ ) as a logical threshold potential (V ₃ + V _T ) may be adjusted as appropriate. In this way, the level shift circuit 10 can be operated reliably. Alternatively, the fourth potential V ₄ and the fifth potential V ₅ may be made equal. The third potential V ₃ , the fourth potential V _4, and the fifth potential V ₅ are high-voltage power supplies. By doing so, the number of high-voltage power supplies can be reduced.

Thus, in the level shift circuit 10, the second output in which an input signal having a value between the first potential V ₁ and the second potential V ₂ has a value between the third potential V ₃ and the fourth potential V ₄ is used. Proper amplitude conversion to signal. Strictly as described above, for the sake of convenience of explanation, the input signal takes the first potential V ₁ when it is logic 0 and takes the second potential V ₂ when it is logic 1. Shall. Similarly, it is assumed that the intermediate signal takes the sixth potential V ₆ when the logic is 0 and takes the seventh potential V ₇ when the logic is 1. The second output signal is assumed to take the third potential V ₃ when the logic is 0 and the fourth potential V ₄ when the logic is 1. Note that the relationship between logic 0 and logic 1 may be reversed. More specifically, when a logic 0, the input signal takes a second potential V _2, the intermediate signal takes the seventh potential V _7, the output signal takes a fourth potential V _4, when the logic 1, The input signal may take the first potential V ₁ , the intermediate signal may take the sixth potential V ₆ , and the output signal may take the third potential V ₃ .

"Circuit configuration"
2A and 2B are diagrams illustrating an inverter circuit used in the level shift circuit, where FIG. 2A is a CMOS inverter circuit, FIG. 2B is an N-type inverter circuit, and FIG. 2C is a P-type inverter circuit. Next, the configuration of the level shift circuit 10 will be described with reference to FIGS.

As shown in FIG. 1A, the potential converter 18 includes a first capacitor element and a second capacitor element. The first capacitive element and the second capacitive element are connected between the fifth power supply unit EP5 to which the fifth potential V ₅ (in this embodiment, the high voltage system second positive power supply potential V _{HH ′} ) is supplied and the input unit IN. Are connected in series, and a connection point between the first capacitor and the second capacitor is an output node of the potential converter 18 (first node (NODE1)). Specifically, the first capacitor element has a first capacitor first electrode 11, a first capacitor second electrode 12, and a dielectric film sandwiched between them, and the second capacitor element is a second capacitor first electrode. 21, a second capacitor second electrode 22, and a dielectric film sandwiched between them, the first capacitor first electrode 11 is electrically connected to the fifth power supply unit EP 5, and the second capacitor second electrode 22 Are electrically connected to the input section IN, and the first capacitor second electrode 12 and the second capacitor first electrode 21 are electrically connected to form a connection point (first node (NODE1)). That is, the first capacitive element and the second capacitive element constitute a capacitively coupled potential converter 18. Since the output node (first node (NODE1)) of the potential converter 18 is electrically connected to the input node of the first inverter circuit INV1, in the potential converter 18, the first capacitor element, the second capacitor element, Thus, the potential of the input node of the first inverter circuit INV1 is determined according to the input signal.

  In this specification, the term “terminal 1 and terminal 2 are electrically connected” means that a resistor element or a switching element is used in addition to the case where terminal 1 and terminal 2 are directly connected by wiring. Including the case of being connected through That is, even if the potential at the terminal 1 and the potential at the terminal 2 are slightly different, the terminal 1 and the terminal 2 are electrically connected if they have the same meaning on the circuit. Therefore, for example, even when a switching element for stopping or functioning the potential conversion unit 18 is provided between the first capacitor first electrode 11 and the fifth power supply unit EP5, the switching element is in the ON state. Since the first capacitor first electrode 11 and the fifth power supply unit EP5 are in a conductive state, both are electrically connected.

  In the conventional circuit as described in Patent Document 1, in order to generate the intermediate potential, the conductance of the transistor is changed, and a stable point of the source / drain current is searched. On the other hand, in the potential conversion unit 18 of the level shift circuit 10, it is not necessary to find a stable point of the source / drain current, and the charge at the first node (NODE1) is redistributed according to the input signal. In this way, potential conversion is performed, so that high speed operation is possible. Further, in the circuit described in Patent Document 1, a through current is always generated. However, in the level shift circuit 10, since the electric charge at the first node (NODE1) is stored, an extra current such as a through current is stored. Therefore, low power consumption can be achieved. Further, since the level shift circuit 10 has a small circuit scale, the occupied area can be reduced. In other words, the level shift circuit 10 has a small occupation area, low power consumption, and high speed operation.

  The buffer unit 13 includes a first inverter circuit INV1 and a second inverter circuit INV2, and these are electrically connected in series between the first node (NODE1) and the third node (NODE3). That is, the first node (NODE1) is an input node of the first inverter circuit INV1, and the output node of the first inverter circuit INV1 and the input node of the second inverter circuit INV2 are electrically connected to each other to form the second node (NODE2). ), And the output node of the second inverter circuit INV2 is the third node (NODE3). The output node (second node (NODE2)) of the first inverter circuit INV1 is the first output unit OUT1 of the level shift circuit 10, and the output node (third node (NODE3)) of the second inverter circuit INV2 is the level shift circuit. 10 is the second output unit OUT2. The first output signal output from the first output unit OUT1 is a high-amplitude signal obtained by inverting the logic of the input signal. On the other hand, the second output signal output from the second output unit OUT2 is a high-amplitude signal having the same logic as the input signal.

A third potential V ₃ and a fourth potential V ₄ are supplied to the first inverter circuit INV1 and the second inverter circuit INV2. With such a configuration, the buffer unit 13 can be configured with a simple configuration of two inverter circuits. Further, the sixth potential V ₆ and the seventh potential V ₇ , which are potentials near the middle between the third potential V ₃ and the fourth potential V ₄ , are substantially equal to the third potential V ₃ in the second output unit OUT2. The fourth potential V ₄ can be set. That is, the amplitude of the second output signal can be made closer to the potential difference between the third potential V ₃ and the fourth potential V ₄ than the amplitude of the first output signal. Therefore, the amplitude of the second output signal is larger than the amplitude of the first output signal.

In the present embodiment, CMOS inverter circuits are used for the first inverter circuit INV1 and the second inverter circuit INV2. As shown in FIG. 2 (a), CMOS inverter circuit, N type between the fourth power supply unit EP4 which a third power supply unit EP3 the third potential V ₃ is supplied fourth potential V ₄ is supplied A transistor TrN and a P-type transistor TrP are connected in series. The gate of the N-type transistor TrN and the P-type transistor TrP is an input node INV-IN of the inverter circuit, and the drain of the N-type transistor TrN and the drain of the P-type transistor TrP are electrically connected, and the output node of the inverter circuit INV-OUT. The source of the N-type transistor TrN is electrically connected to the third power supply unit EP3, and the source of the P-type transistor TrP is electrically connected to the fourth power supply unit EP4.

In the case of the above configuration, the logic threshold voltage (V ₃ + V _T) of the buffer unit 13 is a logic threshold potential of the first inverter circuit _{INV1 (V 3 + V T)} . In general, the logic threshold potential of an inverter circuit is a potential at which the inverter circuit distinguishes between logic 1 and logic 0. That is, if the input to the inverter circuit is higher than the logical threshold potential, the output from the inverter circuit is lower than the logical threshold potential, and if the input to the inverter circuit is lower than the logical threshold potential, the inverter It is the logical threshold potential of the inverter circuit that makes the output from the circuit higher than the logical threshold potential. Therefore, in this embodiment, when a signal having a potential lower than the logical threshold potential (V ₃ + V _T ) is input to the input node of the first inverter circuit INV1, the logical threshold potential is output from the output node of the first inverter circuit INV1. A signal having a potential higher than (V ₃ + V _T ) and lower than the high voltage system positive power supply potential V _HH is output. Similarly, when the high potential of the signal than the logic threshold voltage (V ₃ + V _T) to the input node of the first inverter circuit INV1 is input, the logic threshold potential from the output node of the first inverter circuit INV1 (V ₃ + V A signal having a potential lower than _T ) and equal to or higher than the high voltage system negative power supply potential _VLL is output.

  The configuration of the buffer unit 13 is not limited to the above, and any configuration may be used as long as it functions as the buffer unit 13. Further, another buffer circuit, an inverter circuit, or the like may be provided after the buffer unit 13. As will be described later, in the present embodiment, for the verification of the level shift circuit 10, the output (second output signal) from the second inverter circuit INV2 is viewed.

"Principle and Verification"
FIG. 3 is an equivalent circuit diagram at the first node of the level shift circuit according to the present embodiment. 4A and 4B are potential relation diagrams illustrating the operation principle of the level shift circuit. FIG. 4A shows a case where the logic threshold potential is between the third potential and the fourth potential, and FIG. 4B shows a case where the logic threshold potential is the sixth potential. And the seventh potential. FIG. 5 is a diagram verifying the function of the level shift circuit according to the present embodiment. FIG. 6 is a diagram in which the function of the level shift circuit according to this embodiment is verified. Next, the principle of the level shift circuit 10 according to the present embodiment will be described with reference to FIGS. 3 to 6 and its function will be verified.

In the level shift circuit 10, the sixth potential V ₆ (intermediate low potential V _ML ) is lower than the logical threshold potential (V ₃ + V _T ) of the first inverter circuit INV1, and the seventh potential V ₇ (intermediate high potential V _MH ). Is higher than the logical threshold potential (V ₃ + V _T ) of the first inverter circuit INV1, the capacitance value C ₁ of the first capacitor element, the capacitance value C ₂ of the second capacitor element, and the first inverter circuit INV1. The transistor capacitance value C _p of the P-type transistor TrP constituting the first inverter circuit INV1, the transistor capacitance value C _N of the N-type transistor TrN constituting the first inverter circuit INV1, and the fifth potential V ₅ are set (in the following description, these are set) Is abbreviated as parameter group). In other words, when the input signal V _IN (see FIG. 3) to the level shift circuit 10 is the first potential V ₁ (low voltage system negative power supply potential V _SS ), the first output unit OUT1 receives the logical threshold potential (V ₃ + V _T ) and the fourth potential V ₄ (high voltage system positive power supply potential V _HH ), the first output signal is output, and the input signal V _IN to the level shift circuit 10 is the second potential. At the time of V ₂ (low voltage system positive power supply potential V _DD ), the first output part OUT1 generates a logic threshold potential (V ₃ + V _T ) and a third potential V ₃ (high voltage system negative power supply potential V _LL ). The parameter group needs to be set so that an output signal having a potential value between them is output. This will be described below.

First, an equivalent circuit in the first node (NODE1) will be described. In the state of the input signal V _IN is a second potential V ₂ (low-voltage positive power supply potential V _DD) to the level shift circuit 10, the intermediate voltage V _M at the seventh potential V ₇ (intermediate high potential V _MH), P Since the type transistor TrP is substantially in the off state, the potential of the channel formation region of the P type transistor TrP matches the source potential. Therefore, as shown in FIG. 3, the transistor capacitance value C _p of the P-type transistor TrP can be regarded as a capacitance value having one end connected to the fourth potential V ₄ (high voltage system positive power supply potential V _HH ). On the other hand, since the N-type transistor TrN is in the ON state, the drain potential and the source potential of the N-type transistor TrN are substantially equal, and an N-type channel is formed in the channel formation region. Therefore, as shown in FIG. 3, the transistor capacitance value C _N of the N-type transistor TrN can be regarded as a capacitance value having one end connected to the third potential V ₃ (high voltage system negative power supply potential V _LL ). The same principle works when the input signal is the first potential V ₁ (low voltage system negative power supply potential V _SS ), and the equivalent circuit at the first node (NODE 1) at that time is the same equivalent circuit as FIG. However, in this case, the input signal V _IN is at the first potential V ₁ (low-voltage negative power supply potential V _SS), the intermediate voltage V _M is the sixth potential V ₆ (intermediate low potential V _ML). The transistor capacitance value is a value obtained by dividing the product of the dielectric constant of vacuum, the relative dielectric constant of the gate insulating film, and the gate area of the transistor (the product of the length and width of the channel formation region) by the thickness of the gate insulating film. It is.

In the equivalent circuit shown in FIG. 3, when the input signal V _IN is the second potential V ₂ (low voltage system positive power supply potential V _DD ), the seventh potential V ₇ (intermediate high potential V _MH ) is expressed by Equation 7. The

Similarly, when the input signal V _IN is the first potential V ₁ (low voltage system negative power supply potential V _SS ), the sixth potential V ₆ (intermediate low potential V _ML ) is expressed by Equation 8.

Accordingly, when the input signal V _IN is the second potential V ₂ (low voltage system positive power supply potential V _DD ), the seventh potential V ₇ (intermediate high potential V _MH ) is the logic threshold potential (V) of the first inverter circuit INV1. _The condition that becomes higher than ₃ + V _T ) is expressed by Equation 9.

  From Equations 7 and 9, the first relational expression that the parameter group must satisfy is Equation 10.

On the other hand, when the input signal is the first potential V ₁ (low voltage system negative power supply potential V _SS ), the sixth potential V ₆ (intermediate low potential V _ML ) is the logic threshold potential (V ₃ + V) of the first inverter circuit INV1. _The condition that becomes lower than _T ) is expressed by Equation 11.

  From Equation 8 and Equation 11, the second relational expression that the parameter group must satisfy is Equation 12.

Parameter group (capacitance value C ₁ of the first capacitive element, a capacitance value C ₂ of the second capacitive element, and the transistor capacitance C _p of the P-type transistor TrP constituting the first inverter circuit INV1, the first inverter circuit INV1 The transistor capacitance value C _N of the N-type transistor TrN and the fifth potential V ₅ ) are set so as to satisfy Expressions 10 and 12. Equation 10 is organized as Equation 13.

  Similarly, Equation 12 is organized as Equation 14.

Equations 13 and 14 are conditions that the parameter group of the level shift circuit 10 should satisfy. When the parameter group satisfies the relationship between Formula 13 and Formula 14, when the input signal V _IN to the level shift circuit 10 is the first potential V ₁ , the sixth potential V _{6 is set} to the logical threshold of the first inverter circuit INV1. lower than the potential (V ₃ + V _T), the input signal V _iN is in the second potential V ₂ is higher than the logical threshold potential of the seventh potential V ₇ first inverter circuit INV1 (V ₃ + V _T) I can do it. Therefore, from the output node of the first inverter circuit INV1, when the input signal is the first potential V ₁ , the first potential that is between the logic threshold potential (V ₃ + V _T ) and the fourth potential V ₄ is obtained. An output signal can be output. When the input signal is the second potential V _2, a first output signal having a potential value between the third potential V ₃ and the logical threshold potential (V ₃ + V _T ) is output. I can do it. That is, with a simple circuit configuration, it is possible to correctly convert an input signal into a high amplitude logic signal at low speed and with low power consumption.

When the third potential V ₃ (high voltage system negative power supply potential V _LL ) is equal to the first potential V ₁ (low voltage system negative power supply potential V _SS ) and these are used as reference potentials (V _LL = V _SS = 0) ), Equation 13 becomes Equation 15.

  Similarly, Expression 14 becomes Expression 16.

As shown in FIG. 4A, the logic threshold potential (V ₃ + V _T ) of the first inverter circuit INV1 is set to the third potential V ₃ (high voltage system negative power supply potential V _LL ) and the fourth potential V ₄ (high voltage). When set at the center of the potential difference from the system positive power supply potential V _HH ) (V _T = (V ₄ −V ₃ ) / 2), Equation 13 becomes Equation 17.

  At this time, similarly, the mathematical expression 14 becomes the mathematical expression 18.

Further, at this time, the third potential V ₃ (high voltage system negative power supply potential V _LL ) and the first potential V ₁ (low voltage system negative power supply potential V _SS ) are equal and are used as reference potentials (V _LL = V _SS = 0), and Equation 17 becomes Equation 19.

  Similarly, Expression 18 becomes Expression 20.

On the other hand, as shown in FIG. 4B, the seventh potential V ₇ (intermediate high potential V _MH ) and the sixth potential V ₆ (intermediate low potential V _ML ) are the logical threshold potentials (V) of the first inverter circuit INV1. _{In order} to achieve symmetry with ₃ + V _T ) between them, the relationship of Equation 21 needs to be satisfied.

  When formula 21 is rearranged, formula 22 is obtained.

When the parameter group satisfies Formula 13, Formula 14, and Formula 22, the seventh potential V ₇ (intermediate high potential V _MH ) and the sixth potential V ₆ (intermediate low potential V _ML ) are the logic of the first inverter circuit INV1. Since the threshold potential (V ₃ + V _T ) is symmetrical, the level shift circuit 10 operates extremely stably.

In some cases, the fourth potential V ₄ and the fifth potential V ₅ are set equal to each other, the number of high-voltage power supplies is reduced, and a simple power supply configuration is desired. In this case, in Formula 13, Formula 14, and Formula 22, V ₄ = V ₅ , and the capacitance value C ₁ of the first capacitive element and the capacitance value of the second capacitive element are satisfied so as to satisfy these relational expressions. C ₂ , the transistor capacitance value C _p of the P-type transistor TrP constituting the first inverter circuit INV1, and the transistor capacitance value C _N of the N-type transistor TrN constituting the first inverter circuit INV1 are set. However, due to manufacturing errors, the capacitance value C ₁ of the first capacitive element, the capacitance value C ₂ of the second capacitive element of the actually manufactured circuit, and the transistor capacitance of the P-type transistor TrP constituting the first inverter circuit INV1 Equation 13 and Equation 14 and Equation 14 in which V ₄ = V ₅ under the condition that the value C _p and the transistor capacitance value C _N of the N-type transistor TrN constituting the first inverter circuit INV1 are V ₄ = V ₅ 22 may not be satisfied. In such a case, if the fifth potential V ₅ is shifted from the fourth potential V ₄ and finely adjusted so as to satisfy Equation 13, Equation 14, and Equation 22, the level shift circuit 10 operates correctly. .

Further, the logic threshold potential (V ₃ + V _T ) of the first inverter circuit INV1 is set to the third potential V ₃ (high voltage system negative power supply potential V _LL ) and the fourth potential V ₄ (high voltage system positive power supply potential V _HH ). Is set to the center of the potential difference (V _T = (V _HH −V _LL ) / 2), Equation 22 becomes Equation 23.

Further, at this time, the third potential V ₃ (high voltage system negative power supply potential V _LL ) and the first potential V ₁ (low voltage system negative power supply potential V _SS ) are equal and are used as reference potentials (V _LL = V _SS = 0), and Expression 23 becomes Expression 24.

Further, when the fourth potential V ₄ (high voltage system positive power supply potential V _HH ) and the fifth potential V ₅ (V _{HH ′} ) are equal, Equation 22 and Equation 23, and Equation 24 are Equation 25 and Equation 24, respectively. 26 and Equation 27.

After all, the design procedure of the level shift circuit 10 is as follows.
First, the logic threshold potential (V ₃ + V _T ) of the inverter circuit used in the high voltage system circuit and the level shift circuit 10 is set to the third potential V ₃ (high voltage system negative power supply potential V _LL ) and the fourth potential V ₄ (high The length L _N of the N-type transistor TrN constituting the inverter circuit so as to be the center of the potential difference from the voltage system positive power supply potential V _HH (so that V _T = (V ₄ −V ₃ ) / 2). And the ratio of width W _N (W _N / L _N ) and the ratio (W _P / L _P ) of the length L _P and the width W _P of the P-type transistor TrP constituting the inverter circuit. This, V of the N-type transistor _{TrN gs = V ds = V T} -V 3 = V 4 / and the source drain current when the 2-3V _3/2, V a P-type transistor TrP _gs = V _ds = V _{T -V 4 = -V 4/2-} V 3 / source drain current when the 2 and, stipulated and W _N / L _N as equal and W _P / L _P.

Next, assuming that the fourth potential V ₄ (high voltage system positive power supply potential V _HH ) and the fifth potential V ₅ (V _{HH ′} ) are equal, the parameter group is expressed by Equation 13, Equation 14, and Equation 26. Set to meet.

When the level shift circuit 10 thus designed is actually manufactured and the operation margin is narrow or does not operate, the fifth potential V ₅ (V _{HH ′} ) is set to the fourth potential. By shifting from the potential V ₄ (high voltage system positive power supply potential V _HH ), the parameter group satisfies Equation 13, Equation 14, and Equation 22. By doing so, the level shift circuit 10 functions correctly even if there are some manufacturing errors.

<Example 1>
Next, the function of the level shift circuit 10 according to the present embodiment will be verified with reference to FIG. In this embodiment, the various potentials are V ₁ = 0V, V ₂ = 5V, V ₃ = 0V, V ₄ = 10V, V ₅ = 10V. The thickness of the gate insulating film of the P-type transistor TrP constituting the first inverter circuit INV1 is 75 nm, the length is L _P = 5 μm, the width is W _P = 10 μm, and the transistor capacitance value of the _P -type transistor TrP is C _P = 0.023 pF. The gate insulating film of the N-type transistor TrN has a thickness of 75 nm, a length of L _N = 3 μm, a width of W _N = 5 μm, and a transistor capacitance value of the _N -type transistor TrN is C _N = 0.0069 pF. As a result, the logical threshold voltage of the first inverter circuit INV1 is V _T = 5V. The thickness of the dielectric film of the first capacitive element is 75 nm, the length is L ₁ = 109 μm, the width is W ₁ = 10 μm, and the capacitance value of the first capacitive element is C ₁ = 0.5 pF. The thickness of the dielectric film of the second capacitor element is 75 nm, the length is L ₂ = 217 μm, the width is W ₂ = 10 μm, and the capacitance value of the second capacitor element is C ₂ = 1 pF. The gate insulating film of the N-type transistor TrN, the gate insulating film of the P-type transistor TrP, the dielectric film of the first capacitor element, and the dielectric film of the second capacitor element are silicon oxide films, and the relative dielectric constant is 3 .9.

These parameter groups satisfy Expression 13 and Expression 14, and the level shift circuit 10 operates correctly and at high speed as shown in FIG. The seventh potential obtained by substituting the values of the parameter group of Example 1 into Equation 7 is V ₇ = 6.69 V, which is equal to the intermediate high potential V _MH of the first node indicated by NODE 1 in FIG. I'm doing it. Further, the sixth potential obtained by substituting the values of the parameter group of Example 1 into Equation 8 is V ₆ = 3.42 V, which is equal to the intermediate low potential V _ML of the first node indicated by NODE 1 in FIG. I'm doing it. In FIG. 5, NODE1 starts from 0V in order to realize an initial state of charge distribution by the first capacitor element and the second capacitor element. In other words, the result of the simulation including the power-on sequence.

<Example 2>
Next, the function of the level shift circuit 10 according to the present embodiment will be verified with reference to FIG. In this embodiment, the various potentials are V ₁ = 0V, V ₂ = 3.3V, V ₃ = 0V, V ₄ = 10V, V ₅ = 10V. The thickness of the gate insulating film of the P-type transistor TrP constituting the first inverter circuit INV1 is 75 nm, the length is L _P = 4 μm, the width is W _P = 2.5 μm, and the transistor capacitance value of the P-type transistor TrP is C _P = 0.0046 pF. The gate insulating film thickness of the N-type transistor TrN is 75 nm, the length is L _N = 3.2 μm, the width is W _N = 2.5 μm, and the transistor capacitance value of the _N -type transistor TrN is C _N = 0. 00368 pF. As a result, the logical threshold voltage of the first inverter circuit INV1 is V _T = 5V. The thickness of the dielectric film of the first capacitor element is 75 nm, the length is L ₁ = 125 μm, the width is W ₁ = 10 μm, and the capacitance value of the first capacitor element is C ₁ = 0.575 pF. The thickness of the dielectric film of the second capacitor element is 75 nm, the length is L ₂ = 187 μm, the width is W ₂ = 10 μm, and the capacitance value of the second capacitor element is C ₂ = 0.860 pF. The gate insulating film of the N-type transistor TrN, the gate insulating film of the P-type transistor TrP, the dielectric film of the first capacitor element, and the dielectric film of the second capacitor element are silicon oxide films, and the relative dielectric constant is 3 .9.

These parameter groups satisfy Expression 13, Expression 14, and Expression 22, and the level shift circuit 10 operates correctly and at high speed as shown in FIG. The seventh potential obtained by substituting the parameter group values of Example 2 into Equation 7 is V ₇ = 5.98 V, which is equal to the intermediate high potential V _MH of the first node indicated by NODE 1 in FIG. I'm doing it. Further, the sixth potential obtained by substituting the parameter group values of Example 2 into Equation 8 is V ₆ = 4.02 V, which is equal to the intermediate low potential V _ML of the first node indicated by NODE 1 in FIG. I'm doing it. In FIG. 6, NODE 1 starts from 0 V in order to realize the initial state of charge distribution by the first capacitor element and the second capacitor element. In other words, the power-on sequence is included. It is a result of simulation.

"Electro-optical device"
FIG. 7 is a schematic plan view illustrating a circuit block configuration of the electro-optical device according to the first embodiment. The circuit block configuration of the electro-optical device will be described below with reference to FIG.

  The level shift circuit 10 described above is used in an electro-optical device or the like. An example of the electro-optical device is the liquid crystal device 100, which is an active matrix electro-optical device using a thin film transistor element (pixel transistor) 46 as a switching element of the pixel 35 (see FIG. 9). As shown in FIG. 7, the liquid crystal device 100 includes at least a display area 34, a signal line driving circuit 36, a scanning line driving circuit 38, an external connection terminal 37, and a level shift circuit 10. The signal line driving circuit 36, the scanning line driving circuit 38, the external connection terminal 37, and the level shift circuit 10 are configured by pixel transistors 46.

  In the display area 34, pixels 35 are provided in a matrix. The pixel 35 is an area specified by the intersecting scanning line 16 (see FIG. 9) and the signal line 17 (see FIG. 9), and one pixel 35 extends from one scanning line 16 to the adjacent scanning line 16. And an area from one signal line 17 to the adjacent signal line 17. A signal line driving circuit 36 and a scanning line driving circuit 38 are formed in an area outside the display area 34. The scanning line driving circuit 38 is formed along two sides adjacent to the display area 34.

An external control circuit (not shown) including a semiconductor integrated circuit is electrically connected to the external connection terminal 37. The semiconductor integrated circuit is a low-voltage circuit, and therefore the logic signal supplied to the external connection terminal 37 is a low-amplitude signal and has a value between the first potential V ₁ and the second potential V ₂ . On the other hand, the logic signal used in the signal line driving circuit 36 and the scanning line driving circuit 38 is a high-amplitude signal and has a value between the third potential V ₃ and the fourth potential V ₄ . For this purpose, the electro-optical device includes a level shift circuit 10 for each signal between the external connection terminal 37 and these circuits.

  An X-side clock signal CLX, signal line drive circuit data DTX, and the like are supplied from the external connection terminal 37 to the signal line drive circuit 36. Similarly, the Y-side clock signal CLY, data DTY for the scanning line driving circuit, and the like are supplied from the external connection terminal 37 to the scanning line driving circuit 38. A level shift circuit 10 is arranged for each signal between the external connection terminal 37 and the signal line drive circuit 36 and between the external connection terminal 37 and the scanning line drive circuit 38, and thereby, from the external control circuit. The supplied low amplitude logic signal is converted into a high amplitude logic signal. For example, the low-amplitude Y-side clock signal CLY is converted into a high-amplitude Y-side clock signal CLYLS by the level shift circuit 10, and the data DTY for the low-amplitude scanning line driving circuit is converted by the level shifting circuit 10 to the high-amplitude scanning line driving circuit. Is converted into data DTYLS. The low-amplitude X-side clock signal CLX is converted into a high-amplitude X-side clock signal CLXLS by the level shift circuit 10, and the data DTX for the low-amplitude signal line driving circuit is converted by the level shift circuit 10 to the high-amplitude signal line driving circuit. Is converted into data DTXLS. The same applies to other signals. In FIG. 7, not all the wirings and all the external connection terminals are drawn, but only representative wirings are drawn for easy understanding.

  FIG. 8 is a schematic cross-sectional view of the liquid crystal device. Hereinafter, a cross-sectional structure of the liquid crystal device will be described with reference to FIG. In addition, in the following forms, when “on XX” is described, when placed on XX, or placed on XX via other components Or, when a part is arranged on OO and a part is arranged through another component, it represents.

  In the liquid crystal device 100, an element substrate 24 and a counter substrate 23 constituting a pair of substrates are bonded together by a sealing material 14 arranged in a substantially rectangular frame shape in plan view. The liquid crystal device 100 has a configuration in which a liquid crystal layer 15 is enclosed in a region surrounded by a sealing material 14. As the liquid crystal layer 15, for example, a liquid crystal material having a positive dielectric anisotropy is used. In the liquid crystal device 100, a light-shielding film 33 having a rectangular frame shape made of a light-shielding material is formed on the counter substrate 23 along the vicinity of the inner periphery of the sealing material 14, and an area inside the light-shielding film 33 is a display area. 34. The light shielding film 33 is made of, for example, aluminum (Al), which is a light shielding material. Further, as described above, the light shielding film 33 is formed in the display region 34 so as to partition the outer periphery of the display region 34 on the counter substrate 23 side. The scanning line 16 and the signal line 17 are provided facing each other.

  As shown in FIG. 8, a plurality of pixel electrodes 42 are formed on the element substrate 24 on the liquid crystal layer 15 side, and a first alignment film 43 is formed so as to cover the pixel electrodes 42. The pixel electrode 42 is a conductive film made of a transparent conductive material such as indium tin oxide (ITO). On the other hand, a lattice-shaped light shielding film 33 is formed on the counter substrate 23 on the liquid crystal layer 15 side, and a flat solid common electrode 27 is formed thereon. A second alignment film 44 is formed on the common electrode 27. The common electrode 27 is a conductive film made of a transparent conductive material such as ITO.

  The liquid crystal device 100 is of a transmissive type, and is used with polarizing plates (not shown) or the like arranged on the light incident side and the light emitting side of the element substrate 24 and the counter substrate 23, respectively. The configuration of the liquid crystal device 100 is not limited to this, and may be a reflective type or a transflective type.

  FIG. 9 is an equivalent circuit diagram showing an electrical configuration of the liquid crystal device. Hereinafter, the electrical configuration of the liquid crystal device will be described with reference to FIG.

  As shown in FIG. 9, the liquid crystal device 100 includes a plurality of pixels 35 that constitute the display region 34. Each pixel 35 is provided with a pixel electrode 42. Further, a pixel transistor 46 is formed in the pixel 35.

  The pixel transistor 46 is a switching element that controls energization of the pixel electrode 42. The signal line 17 is electrically connected to the source side of the pixel transistor 46. For example, image signals S1, S2,..., Sn are supplied to each signal line 17 from the signal line driving circuit.

  Further, the scanning line 16 is electrically connected to the gate side of the pixel transistor 46. For example, scanning signals G1, G2,..., Gm are supplied to the scanning lines 16 in a pulsed manner from the scanning line driving circuit 38 at a predetermined timing. Further, the pixel electrode 42 is electrically connected to the drain side of the pixel transistor 46.

  The image signals S1, S2,... Supplied from the signal line 17 are turned on by the pixel transistors 46 serving as switching elements being turned on for a certain period by the scanning signals G1, G2,. Sn are written into the pixel 35 through the pixel electrode 42 at a predetermined timing.

  Image signals S1, S2,..., Sn written in the pixel 35 are held for a certain period by a liquid crystal capacitor formed between the pixel electrode 42 and the common electrode 27 (see FIG. 8). Note that a storage capacitor 48 is formed by the pixel electrode 42 and the capacitor line 47 in order to suppress a decrease in the potential of the stored image signals S1, S2,..., Sn due to leakage current.

  When a voltage signal is applied to the liquid crystal layer 15, the alignment state of the liquid crystal molecules changes depending on the applied voltage level. Thereby, the light incident on the liquid crystal layer 15 is modulated to generate image light.

  In the present embodiment, the liquid crystal device 100 has been described as the electro-optical device. However, other electro-optical devices include electrophoretic display devices and organic EL devices. In the present embodiment, the level shift circuit 10 is configured by a thin film transistor element. However, the level shift circuit 10 may be configured by a semiconductor integrated circuit (IC circuit) formed on a semiconductor substrate. Examples of a semiconductor substrate suitable for the level shift circuit 10 include a silicon carbide substrate in addition to a silicon substrate.

"Electronics"
FIG. 10 is a diagram for explaining an electronic apparatus according to this embodiment. Next, the electronic apparatus of this embodiment will be described with reference to FIG. FIGS. 10A to 10C are perspective views showing the configuration of an electronic apparatus provided with the above-described liquid crystal device.

  As shown in FIG. 10A, a mobile personal computer 2000 including the liquid crystal device 100 includes the liquid crystal device 100 and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002.

  Subsequently, as shown in FIG. 10B, the cellular phone 3000 including the liquid crystal device 100 includes a plurality of operation buttons 3001, scroll buttons 3002, and the liquid crystal device 100 as a display unit. By operating the scroll button 3002, the screen displayed on the liquid crystal device 100 is scrolled.

  Subsequently, as shown in FIG. 10C, a personal digital assistant (PDA) 4000 having the liquid crystal device 100 includes a plurality of operation buttons 4001, a power switch 4002, and the liquid crystal device 100 as a display unit. Is provided. When the operation button 4001 is operated, various types of information such as an address book and a schedule book are displayed on the liquid crystal device 100.

  As electronic devices on which the liquid crystal device 100 is mounted, in addition to the one shown in FIG. 10, a pico projector, a head-up display, a smartphone, a head-mounted display, an EVF (Electrical View Finder), a small projector, a mobile computer, a digital The present invention can be used for various electronic devices such as cameras, digital video cameras, displays, in-vehicle devices, audio devices, exposure apparatuses, and lighting devices.

  As described above in detail, according to the present embodiment, the following effects can be obtained. First, it is possible to realize the level shift circuit 10 having a small occupation area, low power consumption, and capable of high speed operation. As a result, it is possible to realize an electro-optical device that narrows the peripheral region located on the outer periphery of the display region 34 and that is driven at high speed with low power consumption. That is, a high-quality display can be performed on the electro-optical device having a large design ratio and a high ratio of the display area 34 to the entire electro-optical device. In addition, it is possible to realize an electronic apparatus including an electro-optical device that is excellent in design, low power consumption, and capable of high-quality display. Furthermore, since high-speed operation is possible, a large amount of information per unit time can be handled, and high-definition display can be supported.

(Embodiment 2)
"Form 1 with reset transistor"
FIG. 11 is a circuit configuration diagram illustrating a level shift circuit according to the second embodiment. Hereinafter, the configuration of the level shift circuit 10 according to the present embodiment will be described with reference to FIG. In addition, about the component same as Embodiment 1, the same code | symbol is attached | subjected and the overlapping description is abbreviate | omitted.

  This embodiment (FIG. 11) is different from the first embodiment (FIG. 1A) in that a reset transistor 19 is provided. Other configurations are almost the same as those of the first embodiment. As described in the first embodiment (FIG. 1), the electric charge of the first node (NODE1) is stored in principle, but actually, the level shift circuit 10 has a leakage current that flows through the gate insulating film and the dielectric film. There is a risk that the amount of charge gradually changes during operation. If the amount of charge at the first node (NODE1) changes significantly, the level shift circuit 10 may not operate correctly. The level shift circuit 10 of this embodiment is provided with a reset transistor 19 in order to eliminate this fear.

One of the source and drain of the reset transistor 19 is electrically connected to the first node (NODE1), and the other is connected to the power source. In the present embodiment, the other of the source and drain is set to the ground potential V _Grd . In the present embodiment, the low voltage system negative power supply potential V _SS , the high voltage system negative power supply potential V _LL, and the ground potential V _Grd are equal (V _SS = V _LL = V _Grd ). A reset signal Rst is supplied to the gate of the reset transistor 19. If the reset signal Rst is active, the reset transistor 19 is turned on to reset the first node (NODE1) to the ground potential. On the other hand, if the reset signal Rst is inactive, the reset transistor 19 is turned off to cut off the first node (NODE1) and the power source. In the present embodiment, the reset transistor 19 is an N-type transistor TrN, and the fourth potential V ₄ is supplied as the active reset signal Rst, and the third potential V ₃ is supplied as the inactive reset signal Rst. The reset transistor 19 may be a P-type transistor TrP, and the third potential V ₃ may be supplied as the active reset signal Rst and the fourth potential V ₄ may be supplied as the inactive reset signal Rst.

First, prior to power-on such as supply of the second potential V ₂ , the fourth potential V ₄ , the fifth potential V _5, etc., the reset signal Rst is activated to reset the first node (NODE 1) to the ground potential. Next, the reset signal Rst is deactivated, and the first node (NODE1) and the power source are shut off. Thereafter, the first potential V ₁ to the fifth potential V ₅ are respectively supplied from the first power supply unit to the fifth power supply unit EP5, and then an input signal is input to the input unit IN.

  Even with such a configuration, the same effects as those of the first embodiment can be obtained, and the level shift circuit 10 can be operated correctly.

(Embodiment 3)
"Form 2 with reset transistor"
FIG. 12 is a circuit configuration diagram illustrating a level shift circuit according to the third embodiment. Hereinafter, the configuration of the level shift circuit 10 according to the present embodiment will be described with reference to FIG. In addition, about the component same as Embodiment 2, the same code | symbol is attached | subjected and the overlapping description is abbreviate | omitted.

This embodiment (FIG. 12) differs from the second embodiment (FIG. 11) in the connection form of the reset transistor 19. Other configurations are almost the same as those of the second embodiment. In the second embodiment (FIG. 11), the ground potential is supplied to the other of the source and drain. In contrast, in this embodiment, the reset potential V _RST is supplied to the other of the source and drain of the reset transistor 19. Other configurations are almost the same as those of the second embodiment.

One of the source and drain of the reset transistor 19 is electrically connected to the first node (NODE1), and the other is connected to the reset power supply unit. A reset potential V _RST is supplied to the reset power supply unit. A reset signal Rst is supplied to the gate of the reset transistor 19. The reset signal Rst that turns on the reset transistor 19 is referred to as an active reset signal V _A. Also, refer to the reset signal Rst to reset transistor 19 is turned off and the inactive reset signal V _NA.

The reset potential V _RST is the high reset potential V _RSTH (V _RST = V _RSTH ) if the input signal is the second potential V ₂ , and the low reset potential if the input signal is the first potential V _1. V _RSTL (V _RST = V _RSTL ). The high reset potential V _RSTH is expressed by Equation 28.

Further, the low reset potential V _RSTL is expressed by Equation 29.

In the formulas 28 and Equation 29, C _R is the transistor capacitance of the reset transistor 19. In this embodiment, since the reset transistor 19 is an N-type transistor TrN, the active reset signal V _{A is set} to the high voltage system positive power supply potential V _HH (V _A = V _HH ), and the inactive reset signal V _{NA is set} to the high voltage. The system negative power supply potential V _LL is preferable (V _NA = V _LL ).

If the input signal is the second potential V ₂ after turning on the power to supply the first potential V ₁ to the fifth potential V ₅ from the first power source to the fifth power source EP 5, respectively, The reset potential V _RST is set to the high reset potential V _RSTH (V _RST = V _RSTH ) described in Equation 28, the active reset signal V _A is supplied to the gate of the reset transistor 19, and the first node ( _NODE1 ) is set to V _RSTH . Reset.

If the input signal is the first potential V ₁ after the power supply for supplying the first potential V ₁ to the fifth potential V ₅ from the first power supply unit to the fifth power supply unit EP5, respectively, the reset potential V _{RST Is set to} the low reset potential V _RSTL (V _RST = V _RSTL ) described in Expression 29, the active reset signal V _A is supplied to the gate of the reset transistor 19, and the first node (NODE 1) is reset to V _RSTL .

Thereafter, an inactive reset signal _VNA is supplied to the gate of the reset transistor 19 to turn off the reset transistor 19. Then, due to capacitive coupling, the first node (NODE1) becomes the intermediate high potential V _MH if the input signal is the second potential V ₂ , and the intermediate low potential V _ML if the input signal is the first potential V _1. Become. Thereafter, the level shift circuit 10 is operated with the reset transistor 19 closed (while the inactive reset signal _VNA is supplied to the gate of the reset transistor 19). The reset operation described above may be introduced from time to time during the operation of the level shift circuit 10.

  Even with such a configuration, the same effects as those of the first embodiment can be obtained, and further, the level shift circuit 10 can be operated correctly even when continuously used for a long time.

(Embodiment 4)
"Inverter circuit is N-type"
FIG. 2B is a diagram illustrating an inverter circuit used in the level shift circuit according to the fourth embodiment. Hereinafter, the configuration of the level shift circuit 10 according to the present embodiment will be described with reference to FIG. In addition, about the component same as Embodiment 1 thru | or 3, the same code | symbol is attached | subjected and the overlapping description is abbreviate | omitted.

  The present embodiment (FIG. 2B) differs from the first embodiment (FIG. 2A) in the configuration of the inverter circuit. Other configurations are almost the same as those of the first to third embodiments. In the first embodiment, a CMOS inverter circuit is used. On the other hand, in this embodiment, an N-type inverter circuit is used. Other configurations are almost the same as those of the first to third embodiments.

In the level shift circuit 10 of the present embodiment, an N-type inverter circuit is used for both the first inverter circuit INV1 and the second inverter circuit INV2. The N-type inverter circuit, is connected in series with N-type transistor TrN and the resistance element between the fourth power supply unit EP4 which a third power supply unit EP3 the third potential V ₃ is supplied fourth potential V ₄ is supplied Has been. Specifically, the gate of the N-type transistor TrN is the input node INV-IN of the inverter circuit, and the drain of the N-type transistor TrN and one terminal of the resistance element are electrically connected, and the output node INV of the inverter circuit -OUT. The source of the N-type transistor TrN is electrically connected to the third power supply unit EP3, and the other terminal of the resistance element is electrically connected to the fourth power supply unit EP4.

The relationship to be satisfied by the parameter group is the same as that in the first embodiment, and is a relational expression in which the transistor capacitance value of the P-type transistor TrP is zero (C _P = 0) in the equation appearing in the first embodiment. Therefore, for example, Expression 13 becomes Expression 30, and it is preferable that the other parameter groups excluding the transistor capacitance value of the P-type transistor TrP satisfy the relational expression of Expression 30.

  Similarly, for example, Expression 14 becomes Expression 31, and it is preferable that the other parameter groups excluding the transistor capacitance value of the P-type transistor TrP satisfy the relational expression of Expression 31.

  Even with such a configuration, the same effects as those of the first to third embodiments can be obtained. In addition, the level shift circuit 10 can be realized without using the P-type transistor TrP. Therefore, the level shift circuit 10 can be realized by an amorphous silicon thin film transistor, an oxide thin film transistor, or the like, which has a difficult CMOS structure. An oxide containing zinc or tin is used for a semiconductor layer of the oxide thin film transistor.

(Embodiment 5)
"Inverter circuit is P type"
FIG. 2C illustrates an inverter circuit used in the level shift circuit according to the fifth embodiment. Hereinafter, the configuration of the level shift circuit 10 according to the present embodiment will be described with reference to FIG. In addition, about the component same as Embodiment 1 thru | or 3, the same code | symbol is attached | subjected and the overlapping description is abbreviate | omitted.

  The present embodiment (FIG. 2C) differs from the first embodiment (FIG. 2A) in the configuration of the inverter circuit. Other configurations are almost the same as those of the first to third embodiments. In the first embodiment, a CMOS inverter circuit is used. In contrast, in this embodiment, a P-type inverter circuit is used. Other configurations are almost the same as those of the first to third embodiments.

In the level shift circuit 10 of the present embodiment, a P-type inverter circuit is used for both the first inverter circuit INV1 and the second inverter circuit INV2. The P-type inverter circuit, a third resistive element and the P-type transistor TrP is serially connected between the power supply portion EP3 and fourth power supply unit EP4 fourth potential V ₄ is supplied to the third potential V ₃ is supplied Has been. Specifically, the gate of the P-type transistor TrP is an input node INV-IN of the inverter circuit, and the drain of the P-type transistor TrP and one terminal of the resistance element are electrically connected to each other, and the output node INV of the inverter circuit -OUT. The source of the P-type transistor TrP is electrically connected to the fourth power supply unit EP4, and the other terminal of the resistance element is electrically connected to the third power supply unit EP3.

The relationship to be satisfied by the parameter group is the same as that in the first embodiment, and is a relational expression in which the transistor capacitance value of the N-type transistor TrN is zero (C _N = 0) in the equation appearing in the first embodiment. Therefore, for example, Expression 13 becomes Expression 32, and it is preferable that the other parameter groups excluding the transistor capacitance value of the N-type transistor TrN satisfy the relational expression of Expression 32.

  Similarly, for example, Expression 14 becomes Expression 33, and it is preferable that the other parameter groups excluding the transistor capacitance value of the N-type transistor TrN satisfy the relational expression of Expression 33.

  Even with such a configuration, the same effects as those of the first to third embodiments can be obtained. In addition, the level shift circuit 10 can be realized without using the N-type transistor TrN. Therefore, the level shift circuit 10 can be realized by an organic thin film transistor having a difficult CMOS structure. The semiconductor layer of the organic thin film transistor includes poly (9,9-dioctylfluorene-codithiophene) (F8T2), poly (3-hexylthiophene) (P3HT), poly [5,5′-bis (3-dodecyl- 2tinyl) -2,2′-bithiophene] (PQT-12), PBTTTT, pentacene, and other organic substances are used.

  The present invention is not limited to the above-described embodiment, and various changes and improvements can be added to the above-described embodiment.

EP3 ... third power supply unit, EP4 ... fourth power supply unit, EP5 ... fifth power supply unit, IN ... input unit, INV1 ... first inverter circuit, INV2 ... second inverter circuit, OUT1 ... first output unit, OUT2 ... first Two outputs, TrN ... N-type transistor, TrP ... P-type transistor, Rst ... Reset signal, V ₁ ... first potential, V ₂ ... second potential, V ₃ ... third potential, V ₄ ... fourth potential, V ₅ ... 5th potential, V ₆ ... 6th potential, V ₇ ... 7th potential, V _T ... logic threshold voltage, V _A ... active reset signal, V _NA ... inactive reset signal, V _RSTH ... high reset potential, V _RSTL : Low reset potential, 10: Level shift circuit, 11: First capacitor first electrode, 12: First capacitor second electrode, 13: Buffer part, 14: Sealing material, 15 ... Liquid crystal layer, 16 ... Scanning line, 17 ... signal line, 18 ... potential conversion 19, a reset transistor, 21, a second capacitor first electrode, 22, a second capacitor second electrode, 23, an opposing substrate, 24, an element substrate, 27, a common electrode, 33, a light shielding film, 34, a display area, 35 ... Pixel, 36 ... Signal line drive circuit, 37 ... External connection terminal, 38 ... Scan line drive circuit, 42 ... Pixel electrode, 43 ... First alignment film, 44 ... Second alignment film, 46 ... Pixel transistor, 47 ... Capacitance line, 48... Holding capacity, 100.

Claims (9)

An input unit to which an input signal having a value between the first potential and the second potential is input;
A first output unit that outputs an output signal having a value between the third potential and the fourth potential;
A first capacitive element and a second capacitive element electrically connected in series between the input part and a fifth power supply part to which a fifth potential is supplied;
A first inverter circuit to which the third potential and the fourth potential are supplied,
A connection point between the first capacitive element and the second capacitive element and an input node of the first inverter circuit are electrically connected,
An output node of the first inverter circuit is the first output unit. The first capacitor element has a first capacitor first electrode and a first capacitor second electrode,
The second capacitor element has a second capacitor first electrode and a second capacitor second electrode,
The first capacitor first electrode is electrically connected to the fifth power source;
The second capacitor second electrode is electrically connected to the input unit;
2. The level shift circuit according to claim 1, wherein the first capacitor second electrode and the second capacitor first electrode are electrically connected to serve as the connection point. A second inverter circuit and a second output unit;
The output node of the first inverter circuit and the input node of the second inverter circuit are electrically connected,
The level shift circuit according to claim 1, wherein an output node of the second inverter circuit is the second output unit. The first inverter circuit includes an N-type transistor and a P-type transistor connected in series between a third power supply unit to which the third potential is supplied and a fourth power supply unit to which the fourth potential is supplied. ,
The first potential is V ₁ , the second potential is V ₂ , the third potential is V ₃ , the fourth potential is V ₄ , the fifth potential is V ₅ , and the capacitance value of the first capacitor element is C ₁ , the capacitance value of the second capacitor element is C ₂ ,
When the capacitance value of the N-type transistor is represented by C _N , the capacitance value of the P-type transistor is represented by C _P , and the logical threshold voltage of the first inverter circuit is represented by V _T , the relationship between Formula 1 and Formula 2 The level shift circuit according to any one of claims 1 to 3, wherein the expression is satisfied.

The first inverter circuit includes an N-type transistor and a resistance element connected in series between a third power supply unit to which the third potential is supplied and a fourth power supply unit to which the fourth potential is supplied,
The first potential is V ₁ , the second potential is V ₂ , the third potential is V ₃ , the fourth potential is V ₄ , the fifth potential is V ₅ , and the capacitance value of the first capacitor element is C ₁ , the capacitance value of the second capacitor element is C ₂ ,
2. The relational expression of Formula 3 and Formula 4 is satisfied when the capacitance value of the N-type transistor is represented by C _N and the logical threshold voltage of the first inverter circuit is represented by V _T. The level shift circuit as described in any one of thru | or 3.

The first inverter circuit includes a resistance element and a P-type transistor connected in series between a third power supply unit to which the third potential is supplied and a fourth power supply unit to which the fourth potential is supplied,
The first potential is V ₁ , the second potential is V ₂ , the third potential is V ₃ , the fourth potential is V ₄ , the fifth potential is V ₅ , and the capacitance value of the first capacitor element is C ₁ , the capacitance value of the second capacitor element is C ₂ ,
2. The relational expression of Formula 5 and Formula 6 is satisfied when the capacitance value of the P-type transistor is represented by C _P and the logical threshold voltage of the first inverter circuit is represented by V _T. The level shift circuit as described in any one of thru | or 3.

  The level shift circuit according to claim 1, wherein the fourth potential is equal to the fifth potential.   An electro-optical device comprising the level shift circuit according to claim 1.   An electronic apparatus comprising the electro-optical device according to claim 8.