JP2018084932A - Control circuit, control method thereof and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a circuit increases in size due to the necessity of a plurality of counters, the number of which corresponds to the number of restoration requests which can be issued, for circuits to which the clock supply is stopped.SOLUTION: A control circuit includes: control means; first generation means which generates a supply request for requesting clock supply; first measurement means which starts measurement of a first period in response to generation of the supply request and generates a first signal for ordering clock supply after the first period; second generation means which generates a stop request for requesting stop of clock supply; second measurement means which starts measurement of a second period in response to generation of another supply request during the measurement of the first period by the first measurement means; and third generation means which generates a second signal for ordering the stop of clock supply in response to generation of the stop request if the second period has elapsed, and restricts generation of the second signal during the measurement of the second period by the second measurement means.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a control circuit that performs power saving control of an image processing apparatus, a control method thereof, and a program.

  Improvements in the degree of integration and processing power of semiconductor integrated circuits in recent years have led to an increase in power consumption, and measures to reduce power consumption are essential. The clock of the target circuit, called clock gating, is stopped and power is reduced. There is a way to reduce this.

  The clock gating control method is roughly divided into two. One is a method of controlling clock supply / stop by software when the use / non-use of a clock gating target circuit is statically known. The other is a method that is implemented in hardware in order to perform clock gating control more finely.

  As a method for controlling clock gating by hardware, there is a method disclosed in Patent Document 1. In the method of Patent Document 1, the occurrence of some event trigger is detected and the time difference is set because there is a time difference from the generation of the clock control request of the target circuit until the target circuit is actually operable. Control to supply clock and power. For example, in Patent Document 1, an interval at which a slave device accepts a transfer is predicted, and the slave clock is stopped from the completion of the transfer until the next transfer occurs, so that the next transaction can be processed in time. A technique for restoring the power state is disclosed.

  However, in the case where the clock of the clock gating target circuit is supplied with a time lag after measurement for a certain time after the request for returning the clock gating target circuit is generated, the following technique is applied. There was a problem like this. In the technique of Patent Document 1, clock control is performed with a time difference using only one counter. However, when applied to a case where a plurality of clock gating target circuit return requests are generated in a short time, a single counter cannot perform flag management for clock control for all return requests. It is.

  On the other hand, as a solution to the above problem, the prior art of performing clock stop processing using a plurality of counters for a plurality of different clock control request events that occur in parallel as shown in Patent Document 2 There are ways to use technology. That is, when the method of Patent Document 2 is applied, each of a plurality of counters corresponding to a plurality of return requests performs flag management for clock control for all the return requests.

Japanese Patent No. 4837780 Japanese Patent Publication No. 06-048454

  However, in the methods of Patent Document 1 and Patent Document 2, only the maximum number of return requests (for example, the maximum number of standings) that can be issued to the clock gating target circuit with respect to the clock gating target circuit. Multiple counters are required. There is a problem that the circuit scale for power control including clock supply becomes large.

  The present invention has been made in view of the above problems, and realizes power control including control of clock supply with a small circuit scale even when a plurality of return requests are generated for a clock gating target circuit. An object is to provide a circuit. It is another object of the present invention to provide a control method and program for the control circuit.

  In order to solve the above problems, a control circuit according to the present invention has the following configuration. Control means for supplying a clock to the target circuit or stopping the clock supply to the target circuit, and generating a supply request for requesting the clock supply to the target circuit before the target circuit starts predetermined processing When the supply request is generated by the first generation unit and the first generation unit, measurement of the first time is started, and after the first time has elapsed, a first signal instructing clock supply is generated First measurement means for outputting to the control means; second generation means for generating a stop request for requesting stop of clock supply to the target circuit after the target circuit has completed the predetermined processing; and When a supply request is newly generated by the first generation unit while the first measurement unit is measuring the first time, the second measurement unit starts measuring the second time, and the second Over time When the stop request is generated by the second generation means, a second signal instructing to stop the clock supply to the target circuit is generated and output to the control means. When the measuring means is measuring the second time, it has a third generating means for restricting the generation of the second signal, and the control means receives the first signal, A control circuit that controls to stop the clock supply to the target circuit when the clock is supplied to the target circuit and the second signal is received.

  According to the present invention, power control including clock supply can be realized with a small circuit scale even when a plurality of return requests are generated for a clock gating target circuit.

1 is a configuration example of an image processing system-on-chip 100 according to a first embodiment. It is a structural example of the image processing module 11 of 1st Embodiment. 3 is a configuration example of a Write DMAC clock enable control module 303 according to the first embodiment. It is an operation | movement flowchart of the clock enable production | generation counter 400 of 1st Embodiment. It is an operation | movement flowchart of the clock stop request | requirement mask period counter 401 of 1st Embodiment. It is a wave form diagram of a clock stop process when the single transfer of 1st Embodiment is issued. FIG. 6 is a waveform diagram of clock stop processing when two continuous transfers are issued at a sufficiently long interval according to the first embodiment. It is a wave form diagram of a clock stop process in case two continuous transfers are issued at a short interval of case 1 of a 1st embodiment. It is a wave form chart of clock stop processing when two continuous transfers are issued at a short interval of case 2 of a 1st embodiment. FIG. 6 is a waveform diagram of clock stop processing when three continuous transfers are issued at short intervals according to the first embodiment. It is an example of a structure of WriteDMAC clock enable control module 303 of 2nd Embodiment. It is a wave form diagram of a clock stop process when two continuous transfers are issued at a short interval of the second embodiment. It is a structural example of the clock enable generation counter 400 of 3rd Embodiment. It is an operation | movement flowchart of the division | segmentation clock enable generation counter A700 of 3rd Embodiment. It is an operation | movement flowchart of the division | segmentation clock enable generation counter B701 of 3rd Embodiment. It is an operation | movement flowchart of the division | segmentation clock enable generation counter D703 of 3rd Embodiment. It is a wave form diagram of a clock stop process when two continuous transfers are issued at a short interval of a 3rd embodiment. It is a wave form diagram when 350 cycles (minimum value) are required for the image processing calculation of 4th Embodiment. It is a wave form diagram in case 400 cycles (median value) are required for the image processing calculation of 4th Embodiment. It is a wave form diagram when the image processing calculation of 4th Embodiment requires 450 cycles (maximum value). It is an example of a structure of WriteDMAC clock enable control module 303 of 5th Embodiment. It is a structural example of the count object time measurement circuit 901 of 5th Embodiment. FIG. 10 is an operation flowchart of a count target time measuring circuit 901 and a measurement mode switching circuit 900 according to the fifth embodiment.

  Hereinafter, a control circuit according to an embodiment of the present invention will be described in detail with reference to the drawings. In addition, the following embodiment is an illustration and does not limit the scope of the present invention.

(First embodiment)
[Device configuration example]
The block diagram of FIG. 1 shows a configuration example of the image processing system-on-chip 100 of the present embodiment.

  The system-on-chip 100 for image processing includes a CPU 10 that performs information processing, an image processing module 11 that performs image processing, and a supply module 21 that controls supply / non-supply of a clock of the image processing module 11. The system-on-chip 100 for image processing is a system-on-chip that constitutes the image processing apparatus of the present embodiment.

  In the present embodiment, the supply module 21 will be described in detail by taking an example of controlling the supply / stop of the clock of the Write DMAC 302 to save power of the Write DMAC 302, but the present invention is not limited to this. The supply module 21 may control not only supply / stop of the clock of the Write DMAC 302 but also power supply or stop of the power supply of the Write DMAC 302. Further, the supply module 21 may control to change the clock frequency of the Write DMAC 302 or to change the power supply voltage of the Write DMAC 302. The system-on-chip 100 includes a bus module 30 that is connected to each module (not shown), manages data transfer, a DRAM 200 that is a volatile temporary storage device, and a MEMC 20 that is a memory controller that controls the DRAM 200. The image processing system-on-chip 100 includes a clock generator that generates a clock signal to each module, a reset generator that generates a reset signal, and the like, which are omitted in FIG.

[Configuration Example of Image Processing Module 11]
The block diagram of FIG. 2 shows a configuration example of the image processing module 11 of the present embodiment. The image processing module 11 includes a ReadDMAC 300, an arithmetic circuit 301 in the image processing module, a Write DMAC 302, and a Write DMAC clock enable control module 303. The Write DMAC clock enable control module 303 is a control circuit that performs power saving control in this embodiment.

  Hereinafter, the operation of each module in the image processing module 11 will be described along a basic data processing flow.

  First, the ReadDMAC 300 issues a read request to the MEMC 20 via the bus module 30 and reads data in a predetermined address area on the DRAM 200. The ReadDMAC 300 transfers the data received from the DRAM 200 to the arithmetic circuit 301 in the image processing module. At the start timing of this data transfer, the ReadDMAC internal bus data transfer generation signal (pulse signal) is asserted.

  Next, the arithmetic circuit 301 performs predetermined arithmetic processing such as image processing arithmetic on the input data transferred from the ReadDMAC 300. It is assumed that a predetermined calculation process such as an image processing calculation in the calculation circuit 301 requires 400 cycles. When the processing of the arithmetic circuit 301 in the image processing module is completed, the arithmetic circuit 301 transfers data subjected to image processing to the Write DMAC 302.

  The Write DMAC 302 receives the output data from the arithmetic circuit 301, issues a write request to the MEMC 20 via the bus module 30, and writes the data in a predetermined address area on the DRAM 200. At the timing when this data writing is completed, the Write DMAC external bus data transfer completion signal (pulse signal) is asserted. The signal indicating the write DMAC operating state is always asserted while the write DMAC 302 is operating, and is always negated during the non-operating period.

  The Write DMAC clock enable control module 303 can transmit a write DMAC 302 clock control instruction signal to the supply module 21 in accordance with the data processing status in the image processing module 11. In this embodiment, the Write DMAC 302 is a clock gating target circuit that is controlled by the supply module 21 to supply a clock. In the present embodiment, the Write DMAC 302 is described as an example of a clock gating target circuit. However, the circuit is not limited to the Write DMAC 302 as long as the circuit performs a predetermined process.

[Configuration Example of Write DMAC Clock Enable Control Module 303]
The block diagram of FIG. 3 shows an example of the configuration of the Write DMAC clock enable control module 303 of this embodiment.

  The Write DMAC clock enable control module 303 includes a clock enable generation counter 400, a clock stop request mask period counter 401, a clock enable negate instruction generation circuit 403, and a clock enable control circuit 402. The measurement target of the clock enable generation counter 400 that is the first measurement unit is the first predetermined time 500, and the measurement target of the clock stop request mask period counter 401 that is the second measurement unit is the second predetermined time 501. In the present embodiment, measurement of the first predetermined time 500 and the second predetermined time 501 is realized by measuring the set number of clocks. In the present embodiment, for the sake of simplicity, description will be made assuming that the clock frequencies of the clock enable generation counter 400, the clock stop request mask period counter 401, and the Write DMAC 302 are the same. However, the clock frequencies of these counters and Write DMAC 302 may be operating at different frequencies. For example, by setting the frequency of these counters to ½ of the clock frequency of Write DMAC 302, the accuracy of clock control is reduced, but when measuring the same period, the number of FFs constituting the counter is halved. be able to. Then, the circuit scale of the counter is about ½, the circuit scale is ½, and the frequency is ½, so that the operation power of the counter can be reduced to about ¼. In addition, the first measurement unit and the second measurement unit are not limited to the counter as long as they are circuits that measure time (number of cycles), and may be configured by registers, for example.

  In the present embodiment, as shown in FIG. 2, the Write DMAC 302 has been described as an example of a clock gating target circuit. However, the present embodiment can be applied to any circuit that performs predetermined processing. If there are a plurality of clock gating target circuits, one set of the clock enable generation counter 400 and the clock stop request mask period counter 401 may be prepared for each clock gating target circuit. Since the relationship among each clock gating target circuit, the clock enable generation counter 400, and the clock stop request mask period counter 401 is the same, detailed description thereof is omitted.

  The Write DMAC clock enable control module 303 includes a Write DMAC clock supply request signal generation circuit 304 (first generation circuit) and a Write DMAC clock stop request signal generation circuit 305 (second generation circuit). These two modules receive a signal requesting the Write DMAC clock enable control module 303 to supply a clock to the Write DMAC 302 or to stop the clock supply.

  Details of the operation of these modules will be described in the following flowchart and explanation of operation using waveforms.

[Operation Flow of Clock Enable Generation Counter 400]
FIG. 4 shows a flowchart of the operation flow of the clock enable generation counter 400 of this embodiment.

  First, in step S11, the clock enable generation counter 400 is in a non-count state. In step S12, the clock enable generation counter 400 determines whether or not the Write DMAC clock supply request signal has a value of 1 every cycle. When the Write DMAC clock supply request signal is 0, the clock enable generation counter 400 continues the non-count state in step S11. If the Write DMAC clock supply request signal is 1, the process proceeds to step S13, and the clock enable generation counter 400 shifts to the count state. Then, in the next cycle, in step S14, the clock enable generation counter 400 sets the value of the clock enable generation counter 400 to 1. Thereafter, in step S15, the clock enable generation counter 400 determines whether or not the value of the clock enable generation counter 400 is equal to the value of the first predetermined time 500 every cycle. If the value of the clock enable generation counter 400 is not equal to the value of the first predetermined time 500, in step S16, the clock enable generation counter 400 increments the value and performs the determination of step S15 again in the next cycle. If the value of the clock enable generation counter 400 is equal to the value of the first predetermined time 500, the clock enable generation counter 400 changes the value of the clock enable assert instruction signal (first signal) to 1 in step S17. Then, the clock enable generation counter 400 returns to the non-count state in step S11.

[Operation Flow of Clock Stop Request Mask Period Counter 401]
FIG. 5 shows a flowchart of the operation flow of the clock stop request mask period counter 401 of this embodiment.

  First, in step S21, the clock stop request mask period counter 401 is in a non-count state. In step S22, the clock stop request mask period counter 401 determines whether or not the Write DMAC clock supply request signal has a value of 1 every cycle. When the Write DMAC clock supply request signal is 0, the clock stop request mask period counter 401 continues the non-count state of step S21. When the Write DMAC clock supply request signal is 1, the clock stop request mask period counter 401 proceeds to the next step S23 in the same cycle as step S22.

  In step S23, the clock stop request mask period counter 401 determines whether or not the clock enable generation counter 400 is in a count state. When the clock enable generation counter 400 is not in the count state, the clock stop request mask period counter 401 continues the non-count state in step S21. When the clock enable generation counter 400 is in the count state, the clock stop request mask period counter 401 shifts to the count state in step S24. In step S25, in the same cycle as step S24, the clock stop request mask period counter 401 starts to invalidate the Write DMAC clock stop request signal. Specifically, in the count state of the clock stop request mask period counter 401, the clock stop request mask period counter 401 outputs a signal indicating that counting is in progress to the clock enable negate instruction generation circuit 403. When receiving the signal indicating that the clock stop request mask period counter 401 is counting, the clock enable negate instruction generation circuit 403 limits the generation of the clock enable negate instruction signal so as not to output the clock enable negate instruction signal. Since the generation of the clock enable negate instruction signal is limited, even when the Write DMAC clock stop request signal is generated, the clock enable negate instruction signal is not generated, and the Write DMAC clock stop request signal is invalidated.

  In step S26, in the next cycle, the clock stop request mask period counter 401 sets the value of the clock stop request mask period counter 401 to 1. In step S27, in the same cycle as step S26, the clock stop request mask period counter 401 determines whether or not the Write DMAC clock supply request signal has a value of 1. When the Write DMAC clock supply request signal is 1, by returning to step S26 in the next cycle, the clock stop request mask period counter 401 sets the value to 1 again and resets the counter value. This is because when the Write DMAC clock supply request signal is asserted while the clock stop request mask period counter 401 is in the count state, the counter count period is extended and the counter is reused many times. When the Write DMAC clock supply request signal is 0, the process proceeds to the next step S28 in the same cycle as step S27.

  In step S28, the clock stop request mask period counter 401 determines whether or not the value of the clock stop request mask period counter 401 is equal to the second predetermined time 501. If the value of the clock stop request mask period counter 401 is not equal to the second predetermined time 501, the clock stop request mask period counter 401 increments the value by 1 in step S29, and the determination in step S27 is performed again in the next cycle. In step S30, if the value of the clock stop request mask period counter 401 is equal to the second predetermined time 501, the clock stop request mask period counter 401 ends the invalidation of the Write DMAC clock stop request signal. Then, the clock stop request mask period counter 401 returns to the non-count state in step S21.

When Single Transfer Is Issued FIG. 6 illustrates the data processing of the image processing module 11 and the write DMAC 302 clock stop processing when a single transfer is issued in this embodiment, using waveforms.

  First, the ReadDMAC 300 issues a read request to the MEMC 20 via the bus module 30 and reads data in a predetermined address area on the DRAM 200 (T0). At this time, the ReadDMAC external bus data transfer completion signal is asserted (T0). The ReadDMAC 300 transfers the data received from the DRAM 200 to the arithmetic processing module 301 in the image processing module (T2). At this time, the ReadDMAC internal bus data transfer generation signal is asserted (T2). At the same time, the Write DMAC clock supply request signal generation circuit 304 asserts the Write DMAC clock supply request signal (T2).

  In response to the assertion of the Write DMAC clock supply request signal, the clock enable generation counter 400 performs time measurement for a first predetermined time 500 from time T3 (T3 → T397). In the present embodiment, the first predetermined time 500 is 395 cycles. Further, the signal indicating that the clock enable generation counter is counting (not shown in FIG. 6) shown in FIG. 3 is asserted during the period when the clock enable generation counter 400 is counting (T3 → T397) and is not counting. Is negated. In the cycle in which the clock enable generation counter 400 in FIG. 6 is counting, the signal indicating that the clock enable generation counter is counting is always asserted.

  Next, the arithmetic circuit 301 in the image processing module performs image processing arithmetic on the data transferred from the ReadDMAC 300 (T3 → T402). It is assumed that the image processing calculation in the image processing module internal calculation circuit 301 requires 400 cycles.

  At T397, the time measurement of the first predetermined time 500 of the clock enable generation counter 400 is completed, and the clock enable assert instruction signal is asserted to the clock enable control circuit 402.

  It is assumed that the clock of the Write DMAC 302 is supplied and the Write DMAC 302 actually starts operating after five cycles after the assertion of the clock enable assert instruction signal. At T402, the write DMAC 302 clock is supplied, and the operation of the write DMAC 302 is started.

  In T402, the processing in the image processing module arithmetic circuit 301 is completed, and the image processing module arithmetic circuit 301 transfers the data subjected to the image processing to the Write DMAC 302 (T402).

  The Write DMAC 302 receives the output data from the arithmetic circuit 301 in the image processing module, then issues a write request to the MEMC 20 via the bus module 30, and writes the data in a predetermined address area on the DRAM 200 (T408). At this time, the Write DMAC external bus data transfer completion signal is asserted (T408). At the same time, the Write DMAC clock stop request signal generation circuit 305 asserts the Write DMAC clock stop request signal (T408). Further, while the Write DMAC 302 is performing data processing (T403 → T408), the signal (not shown in FIG. 6) indicating the Write DMAC operation state shown in FIG. 3 is asserted. In FIG. 6, in the cycle in which the Write DMAC operation state is in operation, the signal indicating the Write DMAC operation state is always asserted.

  When the data transfer between the Write DMAC 302 and the MEMC 20 is completed, there is no transfer information in the Write DMAC 302, and the Write DMAC 302 can be placed in a clock stop state. Therefore, at the time T408, simultaneously with the completion of the data transfer between the Write DMAC 302 and the MEMC 20, the Write DMAC clock stop request signal generation circuit 305 asserts the Write DMAC clock stop request signal. At the same time, the clock enable negate instruction generation circuit 403 (third generation circuit) asserts a clock enable negate instruction signal (second signal) output to the clock enable control circuit 402. That is, the clock enable negate instruction generation circuit 403 generates a clock enable negate instruction signal and outputs it to the clock enable control circuit 402.

  It is assumed that the clock of the Write DMAC 302 is stopped and the Write DMAC 302 actually stops operating after five cycles after the assertion of the clock enable negate instruction signal. At T413, the clock of the Write DMAC 302 is stopped, and the operation of the Write DMAC 302 is stopped.

  In FIG. 6, the clock stop request mask period counter 401 does not satisfy the counter activation requirement shown in FIG.

When two consecutive transfers are issued at a sufficiently long interval When two consecutive transfers are issued at a sufficiently long interval, the period during which the Write DMAC 302 between those transfers is not processing the transfer, The clock of the Write DMAC 302 can be stopped.

  The phrase “sufficiently long interval” means that the subsequent transfer is issued in a state where the clock enable generation counter 400 is not used by the preceding transfer, and the clock enable generation counter 400 can be used by the subsequent transfer. Means state.

  FIG. 7 illustrates the data processing of the image processing module 11 and the clock stop processing of the Write DMAC 302 when two continuous transfers are issued in this embodiment at sufficiently long intervals, using waveforms.

  In FIG. 7, it is assumed that transfer A is a preceding transfer and transfer B is a subsequent transfer.

  Since the processing content up to T408 of transfer A is the same processing as the description content of “when a single transfer is issued” in FIG. 6 described above, detailed description thereof is omitted. As a result of the completion of the transfer A process in the Write DMAC 302 at T408, the clock of the Write DMAC 302 is stopped at T413.

  At T418, transfer B is issued, ReadDMAC 300 issues a read request to MEMC 20, and reads data in a predetermined address area on DRAM 200. Then, the ReadDMAC 300 transfers the data received from the DRAM 200 to the in-image processing module arithmetic circuit 301 (T420). At the same time, the Write DMAC clock supply request signal generation circuit 304 asserts the Write DMAC clock supply request signal (T420).

  Then, the clock enable generation counter 400 asserts the clock enable assert instruction signal at T815 after the first predetermined time 500 (395 cycles) has elapsed from T421. Further, the write DMAC 302 clock is supplied to T820 after five cycles.

  As a result, the clock of the Write DMAC 302 is stopped during a period from T413 when the processing of the transfer A is completed and the clock of the Write DMAC 302 is stopped to T819 when the transfer B is issued and the clock of the Write DMAC 302 is supplied. During that period, the power of the Write DMAC 302 can be reduced.

  Further, at T831, the clock of the Write DMAC 302 stops with the completion of the transfer B processing in the Write DMAC 302.

  In FIG. 7, the clock stop request mask period counter 401 does not satisfy the activation requirement of the counter shown in FIG.

● When two consecutive transfers are issued at short intervals (Case 1)
When two consecutive transfers are issued at a short interval (case 1), the clock of the Write DMAC 302 is not stopped even during the period during which the Write DMAC 302 is not performing a transfer process.

  The phrase “short interval” means that the subsequent transfer is issued while the clock enable generation counter 400 is used by the preceding transfer, and the clock enable generation counter 400 cannot be used by the subsequent transfer. Means.

  In this embodiment, the clock stop request mask period counter 401 is used to invalidate the assertion of the Write DMAC clock stop request signal for a predetermined time from the occurrence of the subsequent transfer. By doing so, the transfer of the succeeding line is prevented from reaching the Write DMAC 302 when the clock of the Write DMAC 302 is stopped.

  FIG. 8 illustrates the data processing of the image processing module 11 and the clock stop processing of the Write DMAC 302 when two continuous transfers are issued at a short interval (case 1) in this embodiment, using waveforms.

  In FIG. 8, it is assumed that transfer A is a preceding transfer and transfer B is a subsequent transfer.

  Since the processing content up to T408 of transfer A is the same processing content as that described above in the case of “single transfer is issued”, detailed description thereof is omitted.

  At T8, transfer B is issued, ReadDMAC 300 issues a read request to MEMC 20, and reads data in a predetermined address area on DRAM 200. The ReadDMAC 300 transfers the data received from the DRAM 200 to the arithmetic processing module 301 in the image processing module (T10). At the same time, the Write DMAC clock supply request signal generation circuit 304 asserts the Write DMAC clock supply request signal (T10).

  However, at time T10 when the Write DMAC clock supply request signal for transfer B is asserted, the time measurement of the clock enable generation counter 400 for transfer A is being executed. Therefore, the time measurement of the clock enable generation counter 400 related to the transfer B cannot be performed at time T10.

  Since the Write DMAC clock supply request signal is newly asserted during the time measurement of the clock enable generation counter 400, the clock stop request mask period counter 401 starts its operation (T11). Specifically, the operation of this counter is started when the Write DMAC clock supply request signal is asserted during the assertion period (T11 → T410) of the signal indicating that the clock enable generation counter is counting (not shown in FIG. 8). (T11).

  The clock stop request mask period counter 401 performs time measurement for a second predetermined time 501 from time T11 (T11 → T410). In the present embodiment, the second predetermined time 501 is 400 cycles. Also, the signal indicating that the clock stop request mask period counter is being counted (not shown in FIG. 8) shown in FIG. 3 is asserted during the period (T11 → T410) during which the clock stop request mask period counter 401 is counting, The period being counted is negated. In the cycle in which the clock stop request mask period counter 401 is counting in FIG. 8, the signal indicating that the clock stop request mask period counter is being counted is always asserted.

  At T408, the processing of transfer A in the Write DMAC 302 is completed, and the Write DMAC clock stop request signal is asserted. However, at time T408, the clock stop request mask period counter 401 is measuring time by transfer B. Therefore, the clock enable negate instruction generation circuit 403 ignores the assertion of the Write DMAC clock stop request signal and does not assert the clock enable negate instruction signal. That is, the generation of the clock enable negate instruction signal is limited by a signal indicating that the clock stop request mask period counter 401 is measuring. Therefore, the write DMAC 302 clock stop request accompanying the completion of the transfer A processing is invalidated (T408). As a result, the clock of the Write DMAC 302 continues to be supplied even after T413 when the Write DMAC 302 is processing the transfer B.

  Specifically, the clock enable negate instruction generation circuit 403 is a period in which either the signal indicating that the clock stop request mask period counter is being counted or the signal indicating the Write DMAC operating state (not shown in FIG. 8) is not asserted. The following control is performed. The clock enable negate instruction generation circuit 403 ignores the assertion of the Write DMAC clock stop request signal during this period, restricts the generation of the clock enable negate instruction signal, and does not assert the clock enable negate instruction signal. The clock enable negate instruction generation circuit 403 is a mechanism for preventing the clock of the Write DMAC 302 from being inadvertently stopped when the Write DMAC 302 is operating. Note that the following configuration may be added to the first embodiment so that the clock is not stopped in the interval between the clocks of the Write DMAC 302 when it is supplied. The clock enable negate instruction signal is invalidated during the period from the assertion of the clock enable assert instruction signal until the Write DMAC starts operation.

  Thus, when the generation interval of transfer A and transfer B is short, the following can be said. Although the write DMAC 302 clock is not stopped between the two transfers, the transfer B can be prevented from reaching the write DMAC 302 when the write DMAC 302 clock is stopped.

  Thus, in this embodiment, clock control is performed using the two counters of the clock enable generation counter 400 and the clock stop request mask period counter 401, and the circuit scale required for clock control can be reduced. .

  Also, at T421, the write DMAC 302 clock stops upon completion of the transfer B processing in the Write DMAC 302.

● When two consecutive transfers are issued at short intervals (Case 2)
In FIG. 9, data processing of the image processing module 11 and clock stop processing of the Write DMAC 302 when two continuous transfers are issued at short intervals (case 2) will be described using waveforms.

  The phrase “short interval” means that the subsequent transfer is issued while the clock enable generation counter 400 is used by the preceding transfer, and the clock enable generation counter 400 cannot be used by the subsequent transfer. Means.

  In FIG. 9, it is assumed that transfer A is a preceding transfer and transfer B is a subsequent transfer.

  In FIG. 8, the interval between transfer A and transfer B is as short as 8 cycles, but in FIG. 9, the interval between transfer A and transfer B is 103 cycles. The transfer interval (103 cycles) in FIG. 9 is longer than the case (8 cycles) in FIG. 8, but is shorter than 395 cycles of the first predetermined time 500.

  9 is different from FIG. 8 only in that the interval between transfer A and transfer B is changed from 8 cycles to 103 cycles, and there is no difference in individual processing contents. Therefore, detailed description is omitted.

  In FIG. 9, the Write DMAC clock supply request signal is asserted by transfer B at T105, but the clock enable generation counter 400 is used by transfer A. Therefore, the clock stop request mask period counter 401 operates during a period from T106 to T410.

  At T408, the processing of the transfer A in the Write DMAC 302 is completed, and the Write DMAC clock stop request signal is asserted. However, at time T408, the clock stop request mask period counter 401 is measuring time by transfer B. Therefore, the clock enable negate instruction generation circuit 403 ignores the assertion of the Write DMAC clock stop request signal and does not assert the clock enable negate instruction signal.

  As a result, the clock of the Write DMAC 302 continues to be supplied during a period from T413 after the completion of the transfer A processing to T504 immediately before the transfer B reaches the Write DMAC 302. Therefore, although the write DMAC 302 clock is not stopped between two transfers, the transfer B can be prevented from reaching the write DMAC 302 when the write DMAC 302 clock is stopped.

FIG. 10 shows data processing by the image processing module 11 and clock stop processing by the Write DMAC 302 (first processing) when three consecutive transfers are issued at short intervals. Embodiment) will be described using waveforms.

  The phrase “short interval” means that the subsequent transfer is issued while the clock enable generation counter 400 is used by the preceding transfer, and the clock enable generation counter 400 cannot be used by the subsequent transfer. Means.

  In FIG. 10, the first transfer is transfer A, the second transfer is transfer B, and the third transfer is transfer C. The individual processing contents by the three transfers are the same as the explanation contents of FIG. 6 and FIG. 8, and the detailed explanation is omitted.

  When a transfer is issued at a short interval for 3 or more consecutive times, that is, when the Write DMAC clock supply request signal is asserted by the subsequent transfer during the time measurement of the clock stop request mask period counter 401 (T10), Perform the operation. The clock stop request mask period counter 401 resets the current value (T11), and again measures the time for the second predetermined time 501 (T11 → T410). As a result, even when three or more consecutive transfers are issued at short intervals, the measurement time of the clock stop request mask period counter 401 can be extended each time, and this counter can be reused. For this reason, even if a plurality of clock stop request mask period counters 401 are not prepared, it is possible to prevent a subsequent transfer from reaching the Write DMAC 302 when the clock of the Write DMAC 302 is stopped.

  At T412, the Write DMAC clock stop request signal is asserted with the completion of transfer B processing in the Write DMAC 302. At this time, the clock enable negate instruction signal is not asserted even though the clock stop request mask period counter 401 is not counted. This is because the Write DMAC is used by the transfer C at time T412, and the Write DMAC clock cannot be stopped at this time. Specifically, at T412, the Write DMAC 302 processes the transfer C, and a signal (not shown in FIG. 10) indicating the Write DMAC operating state is asserted. Therefore, the clock enable negate instruction generation circuit 403 ignores the assertion of the Write DMAC clock stop request signal and does not assert the clock enable negate instruction signal.

(Second Embodiment)
[Device configuration example]
In the second embodiment, only a part of the configuration of the configuration of the first embodiment is different. Therefore, the description of the same components as those in the first embodiment will be omitted, and portions in which the second embodiment is different from the first embodiment will be mainly described in detail.

  Since the basic configuration of the image processing module 11 of the second embodiment is the same as the basic configuration of the image processing module 11 of the first embodiment, the description thereof is omitted. The configuration of the Write DMAC clock enable control module 303 of this embodiment is different from that of the first embodiment, and the block diagram of FIG. 11 shows a configuration example of the Write DMAC clock enable control module 303 of this embodiment.

  In the second embodiment, in addition to the configuration of the first embodiment, a data stall state notifying unit 600 for notifying the occurrence of a data stall state of the arithmetic circuit 301 in the image processing module is provided. Further, the data stall state notifying unit 600 receives an arithmetic circuit internal state signal indicating the internal state of the arithmetic circuit 301 in the image processing module.

  The data stall state notifying means 600 confirms the state of the arithmetic circuit internal state signal to identify a period during which data processing stall occurs inside the arithmetic circuit 301 in the image processing module, and during that period, the data stall state Assert a notification signal.

  The clock enable generation counter 400 and the clock stop request mask period counter 401 can interrupt the time measurement of these counters while the data stall state notification signal is asserted. When the data processing stall is resolved and the data stall state notification signal is negated, the clock enable generation counter 400 and the clock stop request mask period counter 401 resume time measurement.

  Accordingly, even when the processing time in the image processing module 11 is delayed due to the occurrence of a data stall state, the clock control of the Write DMAC 302 can be performed correctly.

When two consecutive transfers are issued at short intervals FIG. 12 shows the data processing of the image processing module 11 and the clock stop processing of the Write DMAC 302 (second processing) when two consecutive transfers are issued at short intervals. Embodiment) will be described using waveforms.

  The phrase “short interval” means that the subsequent transfer is issued while the clock enable generation counter 400 is used by the preceding transfer, and the clock enable generation counter 400 cannot be used by the subsequent transfer. Means.

  In FIG. 12, it is assumed that transfer A is a preceding transfer and transfer B is a subsequent transfer.

  The individual processing contents by the two transfers are the same as the explanation contents of FIG. 6 and FIG. 8, and the detailed explanation is omitted.

  At T395, a data stall state of the arithmetic circuit 301 in the image processing module occurs, and assertion of the data stall state notification signal is started. The assertion of the data stall state notification signal occurs from T395 to T398. Accordingly, during the period from T396 to T399, the clock enable generation counter 400 and the clock stop request mask period counter 401 interrupt the time measurement and hold the current value. At time T399, the data stall state is canceled, and the data stall state notification signal is negated. As a result, the clock enable generation counter 400 and the clock stop request mask period counter 401 restart time measurement from T400.

  Although the present embodiment has been described in the form of a difference from the first embodiment, it is easily understood that the present embodiment can be implemented in combination with embodiments other than the first embodiment. I can do it.

(Third embodiment)
[Device configuration example]
In the third embodiment, only a part of the configuration of the configuration of the first embodiment is different. Therefore, description is abbreviate | omitted regarding the same component as 1st Embodiment, and the part from which 3rd Embodiment differs from 1st Embodiment is mainly demonstrated in detail.

  In the third embodiment, only the internal configuration of the clock enable generation counter 400 is different from that of the first embodiment. The block diagram of FIG. 13 shows a configuration example of the clock enable generation counter 400 of the third embodiment.

  In the third embodiment, among the configurations in the Write DMAC clock enable control module 303 of the first embodiment, the clock enable generation counter 400 is divided and configured with a plurality of counters connected in series. In the present embodiment, the clock enable generation counter 400 is divided into four counters. The divided counters are referred to as a divided clock enable generation counter A700, a divided clock enable generation counter B701, a divided clock enable generation counter C702, and a divided clock enable generation counter D703, respectively.

  The four counters thus divided measure a predetermined time A800, a predetermined time B801, a predetermined time C802, and a predetermined time D803, respectively. The total of the four predetermined times divided in this way is equal to the first predetermined time 500 of the first embodiment.

  At this time, the value of the predetermined time A800 in the first stage needs to be equal to or larger than the predetermined time B801, the predetermined time C802, and the predetermined time D803 in the subsequent stage. This is because, as will be described later, the clock stop request mask period counter 401 is operated only when the Write DMAC clock supply request signal is asserted during the time measurement of the divided clock enable generation counter A700 at the first stage.

  The operation of the four divided counters is as follows.

  First, when the Write DMAC clock supply request signal is asserted, the divided clock enable generation counter A700 starts measuring time for a predetermined time A800. When the time measurement of the divided clock enable generation counter A700 is completed, the divided clock enable generation counter B701 starts measuring the predetermined time B801.

  Similarly, when the time measurement of the divided clock enable generation counter B 701 is completed, the divided clock enable generation counter C 702 starts measuring the predetermined time C 802.

  Similarly, when the time measurement of the divided clock enable generation counter C702 is completed, the divided clock enable generation counter D703 starts measuring the predetermined time D803.

  Finally, when the time measurement of the divided clock enable generation counter D703 is completed, a clock enable assert instruction signal is asserted to the clock enable control circuit 402. Thereafter, the clock of the Write DMAC 302 is supplied, and the operation of the Write DMAC 302 is started.

  In the third embodiment, the clock stop request mask period counter 401 is operated only when the Write DMAC clock supply request signal is asserted while the first-stage divided clock enable generation counter A700 is measuring time. That is, in the third embodiment, the signal indicating that the clock enable generation counter is being counted is asserted while the first stage divided clock enable generation counter A700 is counting, and is negated during the non-counting period.

  On the other hand, in the first embodiment, if the Write DMAC clock supply request signal is asserted while the entire clock enable generation counter 400 is measuring time, the clock stop request mask period counter 401 is operated.

  In the example of the four-counter division of the third embodiment, the predetermined time A800 can be configured to be a value that is about ¼ of the first predetermined time 500. By dividing the clock enable generation counter 400, it is possible to stop the clock even between transfers with a shorter issuance interval compared to the case where the counter is not divided (first embodiment).

  The first predetermined time 500 of the first embodiment is 395 cycles, and in the example of the counter four division of the third embodiment, the divided measurement times are set as follows. The predetermined time A800 is 100 cycles, the predetermined time B801 is 100 cycles, the predetermined time C802 is 100 cycles, and the predetermined time D803 is 95 cycles.

  Therefore, in the first embodiment, when each transfer interval is 395 cycles or less, the write DMAC 302 clock does not stop between transfers. On the other hand, in the third embodiment, when each transfer interval is 100 cycles or less, the clock of the Write DMAC 302 is not stopped between transfers, and the time granularity at which the clock is stopped by counter division can be made finer.

[Operation Flow of Divided Clock Enable Generation Counter A700]
FIG. 14 shows a flowchart of the operation flow of the divided clock enable generation counter A700 of the third embodiment.

  First, in step S41, the divided clock enable generation counter A700 is in a non-count state. In step S42, the divided clock enable generation counter A700 determines whether or not the Write DMAC clock supply request signal has a value of 1 every cycle. When the Write DMAC clock supply request signal is 0, the divided clock enable generation counter A700 continues the non-count state of step S41. When the Write DMAC clock supply request signal is 1, the divided clock enable generation counter A700 shifts to the count state of step S43.

  In step S44, the divided clock enable generation counter A700 sets the value of the divided clock enable generation counter A700 to 1 in the next cycle. Thereafter, in step S45, the divided clock enable generation counter A700 determines whether or not the value of the divided clock enable generation counter A700 is equal to the value of the predetermined time A800 every cycle. If the value of the divided clock enable generation counter A700 is not equal to the value of the predetermined time A800, the divided clock enable generation counter A700 increments the value by 1 in step S46, and the determination in step S45 is performed again in the next cycle. If the value of the divided clock enable generation counter A700 is equal to the value of the predetermined time A800, in step S47, the divided clock enable generation counter A700 issues a start instruction for the divided clock enable generation counter B701, which is a subsequent counter. Then, the divided clock enable generation counter A700 returns to the non-count state in step S41.

  Even when the number of divisions of the clock enable generation counter 400 is changed from four, the operation description of FIG. 14 can be applied to the first-stage counter.

[Operation Flow of Divided Clock Enable Generation Counter B701]
FIG. 15 shows a flowchart of the operation flow of the divided clock enable generation counter B 701 of the third embodiment.

  First, in step S51, the divided clock enable generation counter B 701 is in a non-count state. In step S52, it is determined every cycle whether or not the count state of the divided clock enable generation counter A700, which is the preceding stage counter, is completed and the preceding stage counter has shifted from the counting state to the non-counting state. If the preceding counter has not shifted from the count state to the non-count state, the divided clock enable generation counter B 701 continues the non-count state in step S51. When the counter at the previous stage shifts from the count state to the non-count state, the divided clock enable generation counter B 701 shifts to the count state of step S53.

  In step S54, in the next cycle, the divided clock enable generation counter B701 sets the value of the divided clock enable generation counter B701 to 1. Thereafter, in step S55, the divided clock enable generation counter B701 determines whether or not the value of the divided clock enable generation counter B701 is equal to the value of the predetermined time B801 every cycle. If the value of the divided clock enable generation counter B 701 is not equal to the value of the predetermined time B 801, the divided clock enable generation counter B 701 increments the value by 1 in step S 56 and performs the determination of step S 55 again in the next cycle. If the value of the divided clock enable generation counter B 701 is equal to the value of the predetermined time B 801, in step S 57, the divided clock enable generation counter B 701 issues a start instruction for the divided clock enable generation counter C 702 which is a subsequent stage counter. Then, the divided clock enable generation counter B 701 returns to the non-count state in step S51.

  Even when the number of divisions of the clock enable generation counter 400 is changed from 4, the description of the operation of FIG. 15 can be applied to the middle stage counter excluding the first stage and the last stage. Since the operation flow of the divided clock enable generation counter C702 is the same as the operation flow of the divided clock enable generation counter B701, detailed description thereof is omitted.

[Operation Flow of Divided Clock Enable Generation Counter D703]
FIG. 16 shows a flowchart of the operation flow of the divided clock enable generation counter D703 of the third embodiment.

  First, in step S71, the divided clock enable generation counter D703 is in a non-counting state. Then, in step S72, it is determined every cycle whether or not the count state of the divided clock enable generation counter C702 that is the preceding stage counter is completed and the preceding stage counter has shifted from the counting state to the non-counting state. When the preceding counter has not shifted from the count state to the non-count state, the divided clock enable generation counter D703 continues the non-count state of step S71. When the preceding counter shifts from the count state to the non-count state, in step S73, the divided clock enable generation counter D703 shifts to the count state.

  In the next cycle, in step S74, the divided clock enable generation counter D703 sets the value of the divided clock enable generation counter D703 to 1. Thereafter, in step S75, the divided clock enable generation counter D703 determines whether or not the value of the divided clock enable generation counter D703 is equal to the value of the predetermined time D803 every cycle. If the value of the divided clock enable generation counter D703 is not equal to the value of the predetermined time D803, the divided clock enable generation counter D703 increments the value by 1 in step S76, and performs the determination of step S75 again in the next cycle. If the value of the divided clock enable generation counter D703 is equal to the value of the predetermined time D803, the divided clock enable generation counter D703 changes the value of the clock enable assert instruction signal to 1 in step S77. Then, the divided clock enable generation counter D703 returns to the non-count state in step S71.

  Even when the number of divisions of the clock enable generation counter 400 is changed from 4, the description of the operation of FIG. 16 can be applied to the last stage counter.

  The basic operation of the clock stop request mask period counter 401 of this embodiment is the same as the operation flow of the clock stop request mask period counter 401 of the first embodiment of FIG. Only the location will be described in detail.

  In step S23 of FIG. 5, it is determined whether or not the clock enable generation counter 400 is in the count state. Thereafter, the process proceeds to step S24 and the clock stop request mask period counter 401 is in the count state. On the other hand, in the present embodiment, it is determined whether or not the divided clock enable generation counter A700, which is the first stage counter of the divided clock enable generation counter 400, is in the count state.

  In the first embodiment, the first predetermined time 500 that is the measurement target of the entire clock enable generation counter 400 is 395 cycles. On the other hand, in the present embodiment, the divided first time A800 that is the measurement target of the divided clock enable generation counter A700 is 100 cycles. Therefore, by dividing the clock enable generation counter 400, the time granularity at which the clock stops between each transfer can be made finer.

When two continuous transfers are issued at short intervals but the clock stops FIG. 17 shows the image processing module 11 of the third embodiment when two continuous transfers are issued at short intervals. Data processing and write DMAC 302 clock stop processing will be described using waveforms.

  In FIG. 17, it is assumed that transfer A is a preceding transfer and transfer B is a subsequent transfer.

  In FIG. 17, transfer A and transfer B are issued at the same interval as the example of FIG. 9 of the first embodiment, and the timing at which each transfer is processed is the same in the examples of FIG. 17 and FIG. However, FIG. 9 is different in that the clock enable generation counter 400 having a single configuration is divided into four counters in FIG.

  For this reason, the following differences occur between FIG. 17 and FIG.

  At time T105 in FIG. 9, a new Write DMAC clock supply request signal is asserted while the clock enable generation counter 400 is measuring time. For this reason, the clock enable generation counter 400 cannot be operated for the transfer B, and the clock stop request mask period counter 401 starts operating. As a result, the clock of the Write DMAC 302 cannot be stopped between the transfer A and the transfer B from T413 to T504.

  On the other hand, at time T105 in FIG. 17, after the time measurement of the divided clock enable generation counter A700 is completed, a new Write DMAC clock supply request signal is asserted. Therefore, the divided clock enable generation counter A700 can be operated for the transfer B, and the clock stop request mask period counter 401 does not start the operation. As a result, the clock of the Write DMAC 302 can be stopped between the transfer A and the transfer B from T413 to T504.

  The generation of transfer B at time T105 in FIG. 17 causes the divided clock enable generation counter A700 to start counting from time T106, and the counting of the divided clock enable generation counter D703 is completed at T500 (not shown) after 394 cycles. . Then, a clock enable assert instruction signal is asserted to the clock enable control circuit 402. Further, at time T505 after five cycles, a clock is supplied to the Write DMAC 302 for which the clock supply has been stopped.

  Although the present embodiment has been described in the form of a difference from the first embodiment, it is easy to implement this embodiment together with embodiments other than the first embodiment. I understand.

(Fourth embodiment)
In the fourth embodiment, a method in which each counter sets an appropriate value in the same configuration as the first embodiment will be described.

  In the first embodiment, the clock enable generation counter 400 measures the first predetermined time 500 and the clock stop request mask period counter 401 measures the second predetermined time 501 so that the write DMAC 302 is controlled.

  In the present embodiment, an example of a method of setting appropriate values for the first predetermined time 500 and the second predetermined time 501 when the values of the times to be measured by these counters vary will be described.

  In the present embodiment, it is assumed that an image processing operation within the arithmetic circuit 301 in the image processing module requires a minimum of 350 cycles and a maximum of 450 cycles, and the processing time varies within this range. On the other hand, it is assumed that the write DMAC 302 is supplied with a clock and the write DMAC 302 actually starts operating after five cycles after the assertion of the clock enable assert instruction signal, as in the first embodiment.

  In this case, the time from when the Write DMAC clock supply request signal is asserted until the transfer reaches the Write DMAC 302 is a minimum of 350 cycles and a maximum of 450 cycles.

  On the other hand, considering the time difference (5 cycles) from the clock supply of the Write DMAC 302 to the start of the operation of the Write DMAC 302, the following can be said. That is, it is appropriate to set a minimum of 345 cycles and a maximum of 445 cycles from the assertion of the Write DMAC clock supply request signal to the assertion of the clock enable assert instruction signal.

  The clock enable generation counter 400 performs clock supply control of the Write DMAC 302.

  Therefore, from the viewpoint of reliable clock control, it is preferable to perform control so that the clock is supplied as soon as possible when the measurement target time of the counter fluctuates. Therefore, in the fourth embodiment, the first predetermined time 500 is set to 345 cycles, which is the minimum value of the time from the assertion of the Write DMAC clock supply request signal to the assertion of the clock enable assert instruction signal.

  On the other hand, the clock stop request mask period counter 401 is intended to prevent the transfer from reaching the Write DMAC 302 when the clock of the Write DMAC 302 is in a stopped state when the transfer occurs at a short interval. The clock stop request mask period counter 401 controls the write DMAC 302 so that the clock of the write DMAC 302 is not inadvertently stopped by invalidating the assertion of the write DMAC clock stop request signal for a predetermined time when transfer occurs at a short interval.

  Therefore, from the viewpoint of reliable clock control, when the time to be measured by this counter varies, it is preferable to perform control so that the clock of the Write DMAC 302 does not stop as long as possible. Therefore, in the fourth embodiment, the second predetermined time 501 is set to 450 cycles, which is the maximum value of the time from when the Write DMAC clock supply request signal is asserted until the transfer reaches the Write DMAC 302.

  Thus, when the value of the time to be measured by these counters fluctuates due to fluctuations in the data processing time, the following measures are effective. The minimum value among the fluctuation values is measured at the first predetermined time 500 to be measured by the clock enable generation counter 400, and the maximum value among the fluctuation values at the second predetermined time 501 to be measured by the clock stop request mask period counter 401. Is used.

  By doing so, the clock control of the Write DMAC 302 can be steadily performed so as to prevent the transfer from reaching the Write DMAC 302 when the clock of the Write DMAC 302 is stopped.

When the value of the time to be measured by the counter fluctuates In the following, in this embodiment, the waveform regarding the data processing of the image processing module 11 and the clock stop processing of the Write DMAC 302 when the value of the time to be measured by the counter fluctuates. Will be described.

  As described above, it is assumed that a minimum of 350 cycles and a maximum of 450 cycles are required for the image processing calculation in the calculation circuit 301 in the image processing module. In addition, a minimum value of 345 cycles is measured for the first predetermined time 500 to be measured by the clock enable generation counter 400, and a maximum value of 450 cycles is measured for the second predetermined time 501 to be measured by the clock stop request mask period counter 401. use.

  In the following, the operation in the case where 350 cycles (minimum value), 400 cycles (median value), and 450 cycles (maximum value) are required for the image processing calculation in the calculation circuit 301 in the image processing module will be individually described. .

When the image processing calculation requires 350 cycles (minimum value) FIG. 18 illustrates the processing when the image processing calculation according to the fourth embodiment requires 350 cycles (minimum value) using waveforms.

  In FIG. 18, it is assumed that transfer A is a preceding transfer and transfer B is a subsequent transfer.

  In FIG. 18, the clock enable generation counter 400 starts measuring time by the transfer A at T3, and the transfer A reaches the Write DMAC 302 at T352.

  Since the minimum value of 345 cycles is set for the first predetermined time 500 to be measured by the clock enable generation counter 400, a clock can be supplied to T352 when transfer A reaches the Write DMAC 302 at T352.

  Further, at T11, the clock stop request mask period counter 401 starts time measurement by transfer B, and transfer T arrives at the Write DMAC 302 at T360.

  Since the maximum 450 cycles is set as the second predetermined time 501 to be measured by the clock stop request mask period counter 401, the clock of the Write DMAC 302 is not stopped between the transfer A and the transfer B.

When the image processing calculation requires 400 cycles (median value) FIG. 19 illustrates the processing when the image processing calculation according to the fourth embodiment requires 400 cycles (median value) using waveforms.

  In FIG. 19, it is assumed that transfer A is a preceding transfer and transfer B is a subsequent transfer.

  In FIG. 19, the clock enable generation counter 400 starts measuring time by transfer A at T3, and transfer A arrives at the Write DMAC 302 at T402.

  Since the minimum value of 345 cycles is set at the first predetermined time 500 to be measured by the clock enable generation counter 400, the clock can be supplied to T352 before transfer A arrives at the Write DMAC 302 at T402. .

  Further, at T11, the clock stop request mask period counter 401 starts time measurement by the transfer B, and the transfer B reaches the Write DMAC 302 at T410.

  Since the maximum 450 cycles is set as the second predetermined time 501 to be measured by the clock stop request mask period counter 401, the clock of the Write DMAC 302 is not stopped between the transfer A and the transfer B.

When the image processing calculation requires 450 cycles (maximum value) FIG. 20 illustrates the processing when the image processing calculation according to the fourth embodiment requires 450 cycles (maximum value) using waveforms.

  In FIG. 20, it is assumed that transfer A is a preceding transfer and transfer B is a subsequent transfer.

  In FIG. 20, the clock enable generation counter 400 starts measuring time by the transfer A at T3, and the transfer A reaches the Write DMAC 302 at T452.

  Since the minimum value of 345 cycles is set at the first predetermined time 500 to be measured by the clock enable generation counter 400, the clock can be supplied to T352 before transfer A arrives at the Write DMAC 302 at T452. .

  Further, at T11, the clock stop request mask period counter 401 starts time measurement by the transfer B, and the transfer B reaches the Write DMAC 302 at T460.

  Since the maximum 450 cycles is set as the second predetermined time 501 to be measured by the clock stop request mask period counter 401, the clock of the Write DMAC 302 is not stopped between the transfer A and the transfer B.

Incorporation of Mechanism for Increasing Opportunity to Stop Clock In this embodiment, the clock stop request mask period counter 401 is controlled using the maximum value among the fluctuation values at the second predetermined time 501.

  For this reason, even if the Write DMAC clock stop request signal is asserted, the clock of the Write DMAC 302 may not stop because the clock stop request mask period counter 401 is counting. This phenomenon occurs at T366 in FIG. 18 and T416 in FIG.

  Therefore, in the fourth embodiment, it is possible to incorporate a mechanism for more actively sensing the non-operating state of the Write DMAC 302 and increasing the opportunity to stop the clock.

  In the fourth embodiment, when the clock stop request mask period counter 401 is in a non-counting state and the operation state of the Write DMAC 302 is not in operation, a process of always stopping the clock of the Write DMAC 302 may be performed.

  Further, the process of always stopping the clock of the Write DMAC 302 may be controlled by delaying the time by preparing a separate counter or the like.

  Furthermore, the following processing may be added in order to prevent the clock from being stopped in the interval between the write DMAC 302 clocks. During the period from the assertion of the clock enable assert instruction signal until the Write DMAC starts its operation, the clock of the Write DMAC 302 is not stopped.

  The first predetermined time 500 in the first embodiment is a time used for the clock enable generation counter 400 to perform supply control of the write DMAC 302 clock. In the first embodiment, a value of 395 cycles is used as an example of the first predetermined time 500. However, in the fifth embodiment, a method for calculating the optimal value of the first predetermined time 500 by calculation will be described. .

  By starting the clock supply of the Write DMAC 302 at the timing immediately before the transfer reaches the Write DMAC 302 and the processing of the Write DMAC 302 is started, the following effects can be expected. The clock stop period of the Write DMAC 302 can be lengthened, and the power saving effect of the Write DMAC 302 can be further enhanced.

  Therefore, it is desirable to set the following value as the first predetermined time 500.

  The first predetermined time 500 is calculated from the third predetermined time 1000 to the fourth predetermined time 1001, and if the third predetermined time 1000 is 400 cycles and the fourth predetermined time 1001 is 5 cycles, One predetermined time 500 is 395 cycles.

  The third predetermined time 1000 is a time from when the Write DMAC clock supply request signal is asserted until the transfer reaches the Write DMAC 302, and in the present embodiment, it is assumed to be 400 cycles. The fourth predetermined time 1001 is a time obtained by subtracting the time until the Write DMAC 302 is supplied with the clock of the Write DMAC 302 and actually starts the operation, and is assumed to be 5 cycles in this embodiment.

  Further, as the second predetermined time 501, it is desirable to set the following value from the viewpoint of preventing the write DMAC 302 from stopping when the subsequent transfer reaches the Write DMAC 302. That is, the second predetermined time 501 is desirably 400 cycles, which is the same as the third time 1000.

  Thus, by performing clock control as follows, the clock stop period of the Write DMAC 302 that is the clock gating target circuit can be lengthened, and the power saving effect of the Write DMAC 302 can be further enhanced.

  A value obtained by subtracting the time (fourth time 1001) required for the clock supply processing of the WriteDMAC 302 from the time (third time 1000) from when the transfer reaches the WriteDMAC 302 until the circuit is started to be used is a first predetermined value. Set to time 500.

  Further, in the case where the value of the third time 1000 fluctuates as in the fourth embodiment, it is desirable to set the following values from the viewpoint of reliably controlling the write DMAC 302 clock.

  That is, the first predetermined time 500 is calculated as the minimum value of the third time 1000 minus the fourth time 1001, and the third time 1000 is 350 cycles and the fourth time 1001 is 5 cycles. The first predetermined time 500 is 345 cycles.

  The second predetermined time 501 is 450 cycles, which is the same as the maximum value of the third time 1000.

  Although the present embodiment has been described in the form of a difference from the first embodiment, it is easy to implement this embodiment together with embodiments other than the first embodiment. I understand.

(Fifth embodiment)
In the fifth embodiment, only a part of the configuration of the configuration of the fourth embodiment is different. Therefore, the description of the same components as those in the fourth embodiment is omitted, and portions in which the present embodiment is different from the fourth embodiment will be mainly described in detail.

  In the fifth embodiment, regarding a first predetermined time 500 and a second predetermined time 501 that are measurement targets of each counter, a method of automatically measuring and determining these values on an actual machine will be described. This technique is applicable to the case where the measurement target time of each counter varies as in the fourth embodiment.

  Since the hardware configuration of the image processing module 11 of the present embodiment is the same as the hardware configuration of the image processing module 11 of the first embodiment, the description thereof is omitted. The configuration of the Write DMAC clock enable control module 303 of this embodiment is different from that of the first embodiment, and the block diagram of FIG. 21 shows a configuration example of the Write DMAC clock enable control module 303 of this embodiment.

  In this embodiment, in addition to the hardware configuration of the first embodiment, a measurement mode switching circuit 900 and a count target time measurement circuit 901 are provided. In addition, a Write DMAC internal bus data transfer generation signal and a measurement mode switching request signal are provided.

  The Write DMAC internal bus data transfer generation signal is asserted (pulse signal) when the processing circuit 301 in the image processing module completes the processing and starts transferring the data subjected to the image processing to the Write DMAC 302.

  The measurement mode switching circuit 900 performs ON / OFF switching of the count target time measurement mode when the measurement mode switching request signal is controlled by the CPU 10 or the like.

  The count target time measurement circuit 901 is switched by the measurement mode switching circuit 900. When the count target time measurement mode is ON, the count target time measurement circuit 901 sets the maximum value and the minimum value of the time required for the image processing calculation in the image processing module calculation circuit 301. taking measurement. This value is obtained by measuring the maximum value and the minimum value of the third time 1000 in the fifth embodiment. The third time 1000 is a time from when the Write DMAC clock supply request signal is asserted until the transfer reaches the Write DMAC 302.

  When the count target time measurement mode is ON, the clock enable generation counter 400 and the clock stop request mask period counter 401 can stop their operations. Similarly, when the count target time measurement mode is OFF, the count target time measurement circuit 901 can stop its operation. In addition, when the operation of these modules is stopped, the clock and power supply of these modules can be stopped to put these modules in a power saving state.

  After the count target time measurement circuit 901 measures the maximum value and the minimum value of the third time 1000, the count target time measurement mode is turned off. Then, the clock enable generation counter 400 and the clock stop request mask period counter 401 use the first predetermined time 500 and the second predetermined time using the maximum value and the minimum value of the third time 1000 measured by the counting target time measuring circuit 901. Time 501 is set.

  Assuming that the counting target time measuring circuit 901 obtains 450 cycles as the maximum value of the third time 1000 and 350 cycles as the minimum value of the third time 1000, the first predetermined time 500 and the second predetermined time 501 are as follows. You can set as follows.

  The first predetermined time 500 is calculated from the measured minimum value of the third time 1000 minus the fourth time 1001, and the third time 1000 is 350 cycles and the fourth time 1001 is 5 cycles. The first predetermined time 500 is 345 cycles.

  The second predetermined time 501 is 450 cycles, which is the same as the maximum value of the measured third time 1000.

The block diagram of FIG. 22 shows a configuration example of the count target time measuring circuit 901. The count target time measurement circuit 901 includes a count target time counter 902, a count target time minimum value storage circuit 903, and a count target time maximum value storage circuit 904. Detailed operations of these modules will be described with reference to the flowcharts shown below.
[Operation Flow of Count Target Time Measurement Circuit 901]
FIG. 23 shows a flowchart of the operation flow of the count target time measuring circuit 901 and the measurement mode switching circuit 900 of this embodiment.

  First, in step S101, the count target time measuring circuit 901 is in a non-operating state. In step S102, the count target time counter 902 determines whether the count target time measurement mode is ON. The ON / OFF control of the count target time measurement mode is performed when the measurement mode switching request signal of the measurement mode switching circuit 900 is controlled by the CPU 10 or the like and the value of the measurement mode switching instruction signal is changed. When the count target time measurement mode is OFF, the count target time measurement circuit 901 maintains the non-operation state of step S101. When the count target time measurement mode is ON, the count target time measurement circuit 901 proceeds to step S103, and the count target time measurement circuit 901 shifts to the operating state.

  Next, in step S104, the count target time counter 902 determines whether or not the Write DMAC clock supply request signal has a value of 1. If the Write DMAC clock supply request signal is 0, the value is determined again in step S104 in the next cycle. If the Write DMAC clock supply request signal is 1, the count target time counter 902 sets the value of the count target time counter 902 to 1 in the next cycle in step S105. Thereafter, in the same cycle, in step S106, the count target time counter 902 determines whether or not the Write DMAC internal bus data transfer generation signal has a value of 1. If the Write DMAC internal bus data transfer generation signal is 0, in step S107, the count target time counter 902 increments the value of the count target time counter by 1, and performs the determination in step S106 again in the next cycle. If the Write DMAC internal bus data transfer generation signal is 1, then in step S108, the count target time counter 902 determines whether or not the measurement by the count target time counter 902 is the first measurement.

  If the measurement by the count target time counter 902 is the first measurement, the count target time counter 902 copies the value of the count target time counter 902 to the count target time maximum value storage circuit 904 in step S109. In step S <b> 110, similarly, the count target time counter 902 copies the value of the count target time counter 902 to the count target time minimum value storage circuit 903. Thereafter, the process returns to step S104, and the count target time counter 902 starts the second measurement. If the measurement by the count target time counter 902 is not the first measurement in step S108, the process proceeds to the determination in step S111.

  In step S111, the count target time counter 902 determines whether the value of the count target time counter 902 exceeds the current value of the count target time maximum value storage circuit 904. When the value of the count target time counter 902 does not exceed the current value of the count target time maximum value storage circuit 904, the step of step S112 is skipped, and the count target time counter 902 performs the determination of step S113. When the value of the count target time counter 902 exceeds the current value of the count target time maximum value storage circuit 904, the process proceeds to step S112. In step S112, the count target time counter 902 copies the value of the count target time counter 902 to the count target time maximum value storage circuit 904, and then performs the determination in step S113.

  In step S113, the count target time counter 902 determines whether the value of the count target time counter 902 is less than the current value of the count target time minimum value storage circuit 903. When the value of the count target time counter 902 is not less than the current value of the count target time minimum value storage circuit 903, the step of step S114 is skipped, and the count target time counter 902 performs the determination of step S115. When the value of the count target time counter 902 is less than the current value of the count target time minimum value storage circuit 903, the process proceeds to step S114. In step S114, the count target time counter 902 copies the value of the count target time counter 902 to the count target time minimum value storage circuit 903, and then performs the determination of step S115.

  In step S115, the count target time counter 902 determines whether or not the count target time measurement mode is ON. When the count target time measurement mode is ON, the process returns to step S104, and the count target time counter 902 starts the next measurement. When the count target time measurement mode is OFF, in step S116, the count target time measurement circuit 901 returns to the non-operation state, and the measurement of the count target time is completed.

  Although the present embodiment has been described in the form of a difference from the fourth embodiment, it is easy to implement this embodiment together with embodiments other than the fourth embodiment. I understand.

  In the fourth embodiment, a method in which each counter sets an appropriate value in the same configuration as the first embodiment will be described.

(Sixth embodiment)
In the sixth embodiment, a method will be described in which each counter sets an appropriate value in the same configuration as the fourth embodiment or the fifth embodiment.

  In the fourth embodiment, the following measures are effective when the value of the time to be measured by the clock control counter fluctuates because the data processing time fluctuates. The minimum value among the fluctuation values is measured at the first predetermined time 500 to be measured by the clock enable generation counter 400, and the maximum value among the fluctuation values at the second predetermined time 501 to be measured by the clock stop request mask period counter 401. Is used.

  On the other hand, in the fourth embodiment, the value of the time to be measured by the counter varies, but if the tendency of the value variation is biased, the maximum value / minimum value are not necessarily used for control and more appropriate. You may let the counter measure the correct value.

  Specifically, the image processing calculation time (third time 1000) in the image processing module calculation circuit 301 fluctuates up to 350-450 cycles. .

375-425 cycles: probability of occurrence 90%.
425-450 cycle: occurrence probability 5%.
350-375 cycles: probability of occurrence 5%.

  In this case, instead of using the true maximum and minimum values (350 and 450 cycles, respectively) as the setting of the maximum and minimum values for the third time 1000, the maximum is set in consideration of the bias of time fluctuations. The controllability of the clock may be better if the value / minimum value is set.

  The true maximum value is 450 cycles, but the probability of occurrence is not more than a predetermined value (for example, 5% or less) and is not used. Similarly, the true minimum value is 350 cycles, but its occurrence probability is not more than a predetermined value (for example, 5% or less) and is not used. In the present embodiment, 425 cycles are used as the maximum value of the third time 1000, and 375 cycles are used as the minimum value of the third time 1000.

  In that case, the first predetermined time 500 and the second predetermined time 501 can be set as follows.

  The first predetermined time 500 is calculated from the minimum value of the third time 1000 minus the fourth time 1001, and the minimum value of the third time 1000 is 375 cycles, and the fourth time 1001 is 5 cycles. The first predetermined time 500 is 370 cycles.

  The second predetermined time 501 is 425 cycles, which is the same as the maximum value of the third time 1000.

  However, in the present embodiment, although the probability of occurrence is small, there is a case where the third time 1000 deviates from the set values of the first predetermined time 500 and the second predetermined time 501 (in this example, 425-450 cycles, And a period of 350-375 cycles).

  For this reason, in this embodiment, even if the transfer reaches the WriteDMAC 302 while the WriteDMAC 302 clock is stopped, a mechanism for supplying the WriteDMAC 302 clock without losing the transfer information can be incorporated. For example, there is a method of adopting a Valid-Ready type transfer protocol for the interface with the Write DMAC 302. In this case, while the Write DMAC 302 clock is stopped, an access penalty occurs by negating the Ready signal from the Write DMAC 302, but the transfer information can be prevented from being lost.

  Although the present embodiment has been described in the form of a difference from the fourth embodiment, the present embodiment can be implemented in combination with the embodiments described in the present specification other than the fourth embodiment. It can be easily understood.

(Other embodiments)
The present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in a computer of the system or apparatus read the program. It can also be realized by processing to be executed. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

10 CPU
11 Image processing module 20 MEMC
21 Supply module 30 Bus module 100 Image processing system on chip 200 DRAM
300 ReadDMAC
301 arithmetic circuit 302 Write DMAC
303 Write DMAC clock enable control module 304 Write DMAC clock supply request signal generation circuit 305 Write DMAC clock stop request signal generation circuit 400 Clock enable generation counter 401 Clock stop request mask period counter 402 Clock enable control circuit 403 Clock enable negate instruction generation circuit

Claims (18)

Control means for supplying a clock to the target circuit or stopping the clock supply to the target circuit;
First generation means for generating a supply request for requesting clock supply to the target circuit before the target circuit starts predetermined processing;
When the supply request is generated by the first generation unit, measurement of a first time is started, and after the first time has elapsed, a first signal instructing clock supply is generated and output to the control unit First measuring means to perform,
Second generation means for generating a stop request for requesting stop of clock supply to the target circuit after the target circuit has completed the predetermined processing;
When a supply request is newly generated by the first generation unit while the first measurement unit is measuring the first time, a second measurement unit starts measuring the second time;
When the stop request is generated by the second generation means after the second time has elapsed, a second signal is generated to instruct to stop the clock supply to the target circuit, and is sent to the control means. Output, and when the second measuring means is measuring the second time, has a third generating means for restricting the generation of the second signal,
The control means controls to supply a clock to the target circuit when receiving the first signal, and to stop supplying a clock to the target circuit when receiving the second signal. Control circuit.   When a supply request is generated by the first generation unit while the second measurement unit is measuring the second time, the second measurement unit resets the value of the second time that has already been measured. The control circuit according to claim 1, wherein the second time is newly measured. The first measuring means is constituted by a plurality of counters connected in series,
The second measuring unit measures the second time when a supply request is newly generated by the first generating unit while the first-stage counter of the plurality of counters is measuring the time. 3. The second time is not measured when a new supply request is generated by the first generation unit while the counter of the latter stage is measuring the time. 4. Control circuit.   4. The control circuit according to claim 3, wherein the total time measured by each of the plurality of counters is the first time. 5.   5. The control circuit according to claim 1, wherein each of the first measurement unit and the second measurement unit includes a counter. A target circuit; a control circuit according to any one of claims 1 to 5; and a supply unit that supplies a clock to the target circuit or stops a clock supply to the target circuit.
The control means controls the supply means to supply a clock to the target circuit when receiving the first signal, and stops supplying the clock to the target circuit when receiving the second signal. An image processing apparatus that controls the supply means. An arithmetic circuit that performs predetermined arithmetic processing on the transferred input data and outputs the output data of the arithmetic processing to the target circuit; and a transfer unit that transfers the input data to the arithmetic circuit; In addition,
The said 1st production | generation means produces | generates the supply request | requirement which requests | requires the clock supply to the said target circuit at the timing which the said transfer means starts the data transfer to the said arithmetic circuit. Image processing device. A signal indicating the internal state of the arithmetic circuit is received, a stall is confirmed in the arithmetic processing of the arithmetic circuit based on the received signal, and if the stall has occurred, a notification signal is sent to the first measuring means And a notification means for outputting to the second measurement means,
The image processing apparatus according to claim 7, wherein the first measurement unit and the second measurement unit interrupt time measurement while receiving the notification signal. The first time is set based on a minimum value of time from the start to the end of the arithmetic processing by the arithmetic circuit,
The image processing apparatus according to claim 8, wherein the second time is set based on a maximum value of a time from the start to the end of the arithmetic processing by the arithmetic circuit.   The image processing apparatus according to claim 9, further comprising a measuring unit that measures a maximum value and a minimum value of a time from the start to the end of the arithmetic processing by the arithmetic circuit. The first time is not set based on the minimum value having an occurrence probability of a predetermined value or less,
The image processing apparatus according to claim 9, wherein the second time is not set based on the maximum value having an occurrence probability equal to or less than a predetermined value. Further comprising storage means for storing output data of the arithmetic processing by the arithmetic circuit;
The image processing apparatus according to claim 6, wherein the target circuit transfers the output data of the arithmetic processing to the storage unit.   The image processing apparatus according to claim 6, wherein the target circuit is a Write DMAC. Control means for supplying power to the target circuit or stopping power supply to the target circuit;
First generation means for generating a supply request for requesting power supply to the target circuit before the target circuit starts predetermined processing;
When the supply request is generated by the first generation unit, measurement of a first time is started, and after the first time has elapsed, a first signal instructing power supply is generated and output to the control unit First measuring means to perform,
Second generation means for generating a stop request for requesting stop of power supply to the target circuit after the target circuit has completed the predetermined processing;
When a supply request is newly generated by the first generation unit while the first measurement unit is measuring the first time, a second measurement unit starts measuring the second time;
If the stop request is generated by the second generation means after the second time has elapsed, a second signal is generated to instruct the power supply to the target circuit to be stopped, and the control means is supplied to the control means. Output, and when the second measuring means is measuring the second time, has a third generating means for restricting the generation of the second signal,
The control means controls to supply power to the target circuit when receiving the first signal, and to stop supplying power to the target circuit when receiving the second signal. Control circuit. A control method of a control circuit having control means for supplying a clock to a target circuit or stopping a clock supply to the target circuit,
A first generation step of generating a supply request for requesting a clock supply to the target circuit before the target circuit starts a predetermined process;
When the supply request is generated in the first generation step, the first measuring unit starts measuring the first time, and after the first time has elapsed, generates a first signal instructing clock supply, A first measuring step for outputting to the control means;
A second generation step of generating a stop request for requesting the stop of the clock supply to the target circuit after the target circuit has completed the predetermined processing;
If a supply request is newly generated in the first generation step while the first measurement unit is measuring the first time in the first measurement step, the second measurement unit measures the second time. A second measuring step for starting
When the stop request is generated by the second generation unit after the second time has elapsed, the third generation unit generates a second signal instructing to stop the clock supply to the target circuit. A third generation step of outputting to the control means, and limiting the generation of the second signal when the second measurement means is measuring the second time in the second measurement step;
The control means has a control step of controlling to supply a clock to the target circuit when receiving the first signal and to stop supplying a clock to the target circuit when receiving the second signal. A method characterized by. A control method for a control circuit having control means for supplying power to a target circuit or stopping power supply to the target circuit,
A first generation step in which a first generation unit generates a supply request for requesting power supply to the target circuit before the target circuit starts a predetermined process;
When the supply request is generated in the first generation step, the first measurement unit starts measuring the first time, and after the first time has elapsed, generates a first signal instructing power supply, A first measuring step for outputting to the control means;
A second generation step of generating a stop request for requesting a stop of power supply to the target circuit after the target circuit has completed the predetermined processing;
If a supply request is newly generated in the first generation step while the first measurement unit is measuring the first time in the first measurement step, the second measurement unit measures the second time. A second measuring step for starting
After the second time has elapsed, when the stop request is generated by the second generation unit, the third generation unit generates a second signal instructing to stop power supply to the target circuit. A third generation step of outputting to the control means, and limiting the generation of the second signal when the second measurement means is measuring the second time in the second measurement step;
The control means includes a control step of controlling to supply power to the target circuit when receiving the first signal and to stop supplying power to the target circuit when receiving the second signal. A method characterized by. A control program for a control circuit having control means for supplying a clock to the target circuit or stopping the clock supply to the target circuit,
A first generation step for generating a supply request for requesting a clock supply to the target circuit before the target circuit starts a predetermined process;
When the supply request is generated in the first generation step, the first measuring unit starts measuring the first time, and generates a first signal instructing clock supply after the first time has elapsed. A first measurement step for outputting to the control means;
A second generation step of generating a stop request for requesting a stop of clock supply to the target circuit after the target circuit completes the predetermined processing;
If a supply request is newly generated in the first generation step while the first measurement unit is measuring the first time in the first measurement step, the second measurement unit A second measurement step for starting measurement;
When the stop request is generated by the second generation unit after the second time has elapsed, the third generation unit outputs the second signal instructing to stop the clock supply to the target circuit. A third generation step for restricting the generation of the second signal when the second measurement unit is measuring the second time in the second measurement step. ,
A control step for controlling to supply a clock to the target circuit when receiving the first signal and to stop supplying a clock to the target circuit when receiving the second signal;
A program that causes a computer to execute. A control program for a control circuit having control means for supplying power to a target circuit or stopping power supply to the target circuit,
A first generation step for generating a supply request for requesting power supply to the target circuit before the target circuit starts a predetermined process;
When the supply request is generated in the first generation step, the first measuring unit starts measuring the first time, and generates a first signal instructing power supply after the first time has elapsed. A first measurement step for outputting to the control means;
A second generation step of generating a stop request for requesting a stop of power supply to the target circuit after the target circuit has completed the predetermined processing;
If a supply request is newly generated in the first generation step while the first measurement unit is measuring the first time in the first measurement step, the second measurement unit A second measurement step for starting measurement;
When the stop request is generated by the second generation unit after the second time has elapsed, the third generation unit outputs the second signal instructing to stop power supply to the target circuit. A third generation step for restricting the generation of the second signal when the second measurement unit is measuring the second time in the second measurement step. ,
A control step for controlling to supply power to the target circuit when receiving the first signal and to stop power supply to the target circuit when receiving the second signal;
A program that causes a computer to execute.

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