JP2018073042A - Memory controller, memory control method, integrated circuit device and imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory controller capable of excellently performing memory control.SOLUTION: The memory controller includes a first arbitration unit for arbitrating transfer requests from a plurality of bus masters, and a second arbitration unit for arbitrating the plurality of transfer requests respectively arbitrated by the first arbitration unit, and the first arbitration unit outputs a new transfer request from a bus master to the second arbitration unit regardless of whether to permit a transfer request which has already been outputted to the second arbitration unit by the first arbitration unit.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a memory controller, a memory control method, an integrated circuit device, and an imaging device.

  As measures for reducing the cost of digital cameras, digital video cameras, and the like, miniaturization of LSI (Large-Scale Integration) mounted on these devices is being studied. On the other hand, there is a demand for higher performance and multi-function of these devices, and the number of functional blocks connected to a memory controller that controls memory such as SDRAM (Synchronous Dynamic Random Access Memory) tends to increase. The increase in the functional blocks connected to the memory controller causes local concentration of wiring around the memory controller, increases the circuit scale for securing the wiring area, and becomes an obstacle to downsizing of the LSI.

As a technique for solving such a problem, it is conceivable to use a multi-stage memory controller (see Patent Document 1). In a memory controller having a multi-stage configuration, a plurality of functional blocks serving as a bus master are connected to each of a plurality of sub-controllers, and the plurality of sub-controllers are connected to a main controller. If a multi-stage memory controller is used, local concentration of wiring can be prevented, which can contribute to miniaturization of the LSI.
Conventionally, a configuration is also known in which a transfer request from a bus master to a memory is arbitrated according to the priority of each bus master.

JP2012-123545A

  However, in a multi-stage memory controller, memory control may not always be performed satisfactorily.

  It is an object of the present invention to provide a memory controller, a memory control method, an integrated circuit device, and an imaging device that can perform good memory control.

  According to an aspect of the present invention, a first arbitration unit that arbitrates transfer requests from a plurality of bus masters, and a second arbitration unit that arbitrates transfer requests arbitrated by the plurality of first arbitration units, respectively. The first arbitration unit includes a new one from the bus master regardless of whether or not the transfer request already output by the first arbitration unit to the second arbitration unit is permitted. A memory controller is provided that outputs a transfer request to the second arbitration unit.

  According to the present invention, it is possible to provide a memory controller, a memory control method, an integrated circuit device, and an imaging device that can perform good memory control.

It is a block diagram which shows the imaging device provided with the memory controller by one Embodiment. It is a figure which shows the signal input / output between each functional block. It is a figure which shows the signal input / output between each functional block. It is a figure which shows the signal input / output between each functional block. It is a figure which shows the signal input / output between each functional block. It is a time chart which shows operation | movement of the memory controller in an address phase. It is a time chart which shows operation | movement of the memory controller in an address phase. It is a time chart which shows operation | movement of the memory controller in an address phase. It is a time chart which shows the example of operation | movement of the memory controller in a data phase. It is a figure which shows the memory controller by a reference example.

  First, before describing a memory controller according to an embodiment, a memory controller according to a reference example will be described. FIG. 5 is a diagram illustrating a memory controller according to a reference example. FIG. 5A is a block diagram illustrating a memory controller according to a reference example. As illustrated in FIG. 5A, the memory controller 507 according to the reference example includes sub arbitration units 509 a to 509 c and a main arbitration unit 512. It should be noted that reference numerals 509a to 509c are used when describing the individual sub-arbitration units, and reference numeral 509 is used when the general sub-arbitration units are described. A bus master 501a and a bus master 501b are connected to the sub arbitration unit 509a. A bus master 501c and a bus master 501d are connected to the sub arbitration unit 509b. A bus master 501e and a bus master 501f are connected to the sub arbitration unit 509c. Note that reference numerals 501a to 501f are used when describing individual bus masters, and reference numerals 501 are used when general bus masters are described. FIG. 5B is a diagram showing the priority of access to the memory 508 of the bus masters 501a to 501f. The smaller the numerical value of the priority shown in FIG. 5B, the higher the priority.

  When a bus master other than the bus master 501f, that is, the bus masters 501a to 501e, simultaneously outputs a signal requesting permission to transfer data to and from the memory 508, that is, a transfer request signal (REQ signal). Is assumed. Each sub arbitration unit 509 selects the REQ signal from the bus master 501 having the highest priority among the bus masters 501 outputting the REQ signal to the sub arbitration unit 509. Therefore, the sub arbitration unit 509a selects the REQ signal from the bus master 501a, the sub arbitration unit 509b selects the REQ signal from the bus master 501c, and the sub arbitration unit 509c selects the REQ signal from the bus master 501e. . The REQ signal selected by each sub arbitration unit 509 is output to the main arbitration unit 512. The main arbitration unit 512 selects the REQ signal from the bus master 501 having the highest priority among the bus masters 501 whose REQ signal has reached the main arbitration unit 512 via the sub arbitration unit 509. Therefore, the REQ signal from the bus master 501 a that reaches the main arbitration unit 512 via the sub arbitration unit 509 a is selected by the main arbitration unit 512. The main arbitration unit 512 issues a command corresponding to the access from the bus master 501a to the memory 508.

  Here, although the REQ signal from the bus master 501e having the lowest priority is transmitted to the main arbitration unit 512 via the sub arbitration unit 509c, the REQ signal is still permitted by the main arbitration unit 512. Assume a state that is not. In such a state, it is assumed that the REQ signal is output from the bus master 501f having the highest priority.

  At the timing when the REQ signal is output from the bus master 501f, the REQ signal from the bus master 501e is already output to the main arbitration unit 512 via the sub arbitration unit 509c. The sub-arbiter 509c cannot newly output the REQ signal from the bus master 501e, that is, the REQ signal from the bus master 501f until the transfer request is permitted by the main arbitrator 512. It has become.

  Since the priority of access from the bus master 501e is the lowest, as long as the bus masters 501a to 501d connected to the other sub arbitration units 509a and 509b continue to output REQ signals sequentially, the REQ signals from these bus masters 501a to 501d Takes precedence. Therefore, as long as the bus masters 501a to 501d connected to the other sub arbitration units 509a and 509b continuously output the REQ signal, the REQ signal from the bus master 501e is not permitted by the main arbitration unit 512. If the REQ signal from the bus master 501e is not permitted by the main arbitration unit 512, the REQ signal from the bus master 501f is not permitted by the main arbitration unit 512 even though the access priority from the bus master 501f is the highest.

  As described above, in the memory controller according to the reference example, although the REQ signal is from the bus master 501f having a high access priority, permission for the REQ signal may be significantly delayed, and the memory cannot be controlled well. There is a case.

  Embodiments of the present invention will be described below in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments.

[One Embodiment]
A memory controller, a memory control method, an integrated circuit device, and an imaging device according to an embodiment will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating an imaging apparatus having a memory controller according to the present embodiment. In FIG. 1, functional blocks necessary for explanation are extracted and shown.

  The imaging apparatus 150 according to the present embodiment includes an imaging device 100, an imaging processing unit 101a, an evaluation value generation unit 101b, a recognition processing unit 101c, a development processing unit 101d, a display control unit 101e, and an encoding processing unit 101f. And a recording medium control unit 101g. Furthermore, the imaging apparatus 150 according to the present embodiment includes the memory controller 108 and the memory 109 according to the present embodiment. For example, SDRAM (Synchronous Dynamic Random Access Memory) or the like is used as the memory 109, but other types of memory can also be used. A clock signal CLK (see FIGS. 3 and 4) generated by a clock generation unit (not shown) is appropriately input to these functional blocks constituting the imaging device 150, and these functional blocks are synchronized with the clock signal CLK. Operation is possible.

  The imaging processing unit 101a, the evaluation value generation unit 101b, the recognition processing unit 101c, the development processing unit 101d, the display control unit 101e, the encoding processing unit 101f, and the recording medium control unit 101g are integrated according to this embodiment. The circuit device 120 is provided. The memory controller 108 and the memory 109 are also provided in the integrated circuit device 120 according to the present embodiment. In the present embodiment, the integrated circuit device 120 is configured as a single semiconductor integrated circuit chip. The memory 109 is configured as a semiconductor integrated circuit chip different from the integrated circuit device 120.

  The imaging element (imaging sensor) 100 has a pixel array (not shown) in which a plurality of pixels (not shown) each including a photoelectric conversion unit (not shown) are arranged in a matrix, that is, in a matrix. ing. The image sensor 100 photoelectrically converts an optical image formed by an imaging optical system (not shown) by each photoelectric conversion unit, thereby generating image data. An image signal (image data) generated by the imaging element 100 is input to the imaging processing unit 101a. The imaging processing unit (image processing unit) 101 a performs image processing such as defective pixel correction on the image data, and writes the image data subjected to the image processing to the memory 109 via the memory controller 108.

  The evaluation value generation unit 101b reads the image data written in the memory 109 via the memory controller 108, and generates an evaluation value by analyzing color information in units of predetermined image areas. The evaluation value generation unit 101 b writes the generated evaluation value into the memory 109 via the memory controller 108. The recognition processing unit 101c reads the image data written in the memory 109 via the memory controller 108, and performs recognition processing such as face recognition and object recognition based on the image data. The recognition processing unit 101 c writes the result of the recognition processing in the memory 109 via the memory controller 108.

  The development processing unit 101d reads out the image data subjected to the image processing by the imaging processing unit 101a from the memory 109 via the memory controller 108, and performs processing such as filter processing, resizing processing, and format conversion. The development processing unit 101d writes the image data subjected to these processes to the memory 109 via the memory controller 108. The display control unit 101e reads out the image data processed by the development processing unit 101d from the memory 109 via the memory controller 108, and displays an image corresponding to the image data on a display unit (not shown). To control.

  The encoding processing unit 101f reads out the image data processed by the development processing unit 101d from the memory 109 via the memory controller 108. It is encoded by an encoding method such as H.264. The encoding processing unit 101 f writes the encoded image data into the memory 109 via the memory controller 108. The recording medium control unit 101g reads the image data encoded by the encoding processing unit 101f, that is, the encoded image data from the memory 109 via the memory controller 108. The recording medium control unit 101g writes the encoded image data on a recording medium such as an SD memory card (not shown).

  The imaging processing unit 101a, the evaluation value generation unit 101b, the recognition processing unit 101c, the development processing unit 101d, the display control unit 101e, the encoding processing unit 101f, and the recording medium control unit 101g transfer data to and from the memory 109. A signal requesting permission, that is, a transfer request signal is issued. These functional blocks are also called bus masters because they output a transfer request signal (transfer request, request), that is, a REQ signal, to the memory controller 108. Note that reference numerals 101a to 101g are used when describing individual bus masters, and reference numeral 101 is used when general bus masters are described.

  The memory controller 108 includes sub-arbitration units (sub-controllers, first arbitration units) 110a, 110b, and 110c, and a main arbitration unit (main controller, second arbitration unit) 113. Note that reference numerals 110a to 110c are used when describing individual sub-arbitration units, and reference numeral 110 is used when general sub-arbitration units are described. The memory controller 108 has an arbitration function for transfer requests from each bus master 101. The memory controller 108 also has a control function for the memory 109.

  The sub arbitration unit 110a arbitrates transfer requests from the imaging processing unit 101a, the evaluation value generation unit 101b, and the recognition processing unit 101c. The sub arbitration unit 110a performs the following processing when a transfer request is issued from the bus master 101 connected to the sub arbitration unit 110a, that is, when the REQ signal is asserted. That is, the sub arbitration unit 110a asserts the signal REQ_SUB0 (see FIG. 2A) output from the sub arbitration unit 110a to the main arbitration unit 113, and outputs the signal ADRS_SUB0 (see FIG. 2A). Read / write, that is, information indicating the data transfer direction, information indicating the address of the data transfer destination, information indicating the size of the data to be transferred, and the like are transmitted by the signal ADRS_SUB0. Also, information indicating which bus master 101 the signal REQ_SUB0 output from the sub arbitration unit 110a to the main arbitration unit 113, that is, the ID information of the bus master 101 is obtained by the signal ADRS_SUB0. Is transmitted. Incidentally, since a plurality of bus masters 101 are connected to the sub arbitration unit 110a, REQ signals from the plurality of bus masters 101 may be asserted at the same time. When REQ signals from a plurality of bus masters 101 connected to the sub arbitration unit 110a are asserted at the same time, the sub arbitration unit 110a performs an arbitration process as follows. That is, the sub arbitration unit 110 a selects the bus master 101 having the highest priority among the bus masters 101 that are asserting the REQ signal based on the priority set in advance for each bus master 101. Then, the sub arbitration unit 110a asserts the signal REQ_SUB0 output from the sub arbitration unit 110a to the main arbitration unit 113, and outputs the signal ADRS_SUB0. Information such as described above is transmitted by the signal ADRS_SUB0. When the transfer request from the bus master 101 is permitted by the main arbitration unit 113, the sub arbitration unit 110a confirms that the transfer request is permitted by the main arbitration unit 113 to the bus master 101 that has issued the transfer request. The indicated signal, that is, the ACK signal is output. The bus master 101 that has received the ACK signal (transfer permission signal) deasserts the REQ signal. Thereafter, the sub-arbitration unit 110a appropriately performs the arbitration process in the same manner as described above.

  Similarly to the sub arbitration unit 110a, the sub arbitration units 110b and 110c arbitrate transfer requests from the bus masters 101 connected to the sub arbitration units 110b and 110c, respectively. Specifically, the sub arbitration unit 110b arbitrates transfer requests from the development processing unit 101d and the display control unit 101e. The sub-arbiter 110c arbitrates transfer requests from the encoding processor 101f and the recording medium controller 101g. The sub-arbiter 110b outputs a signal REQ_SUB1 and a signal ADRS_SUB1 (see FIG. 2B), and the sub-arbiter 110c outputs a signal REQ_SUB2 and a signal ADRS_SUB2 (see FIG. 2C). When describing individual transfer request signals, that is, the signal REQ_SUB, the code REQ_SUB0 to REQ_SUB2 is used, and when the signal REQ_SUB in general is described, the code REQ_SUB is used. Further, when describing each signal ADRS_SUB, the code ADRS_SUB0 to ADRS_SUB2 is used, and when describing the signal ADRS_SUB in general, the code ADRS_SUB is used. The signal ADRS_SUB is transmitted by parallel transmission using a plurality of signal lines.

  Note that the combination of connections between the sub arbitration units 110a to 110c and the bus masters 101a to 101g is not limited to the above. For example, the arrangement locations of the respective bus masters 101a to 101g are set in consideration of terminal allocation, circuit scale, power consumption, data flow, and the like in the LSI. For example, the bus masters 101a to 101g are connected to the sub arbitration units 110a to 110c so that the wiring is short and not complicated. Accordingly, the combination of connections between the sub arbitration units 110a to 110c and the bus masters 101a to 101g differs depending on the configuration and specifications of the LSI.

  A signal corresponding to the REQ signal from the bus master 101, that is, a signal REQ_SUB is input from the sub arbitration unit 110 to the main arbitration unit 113. When the signal REQ_SUB is asserted, the main arbitration unit 113 permits data transfer to the bus master 101 that has issued the REQ signal that causes the signal REQ_SUB to be asserted, that is, accesses the memory 109. Permit as appropriate. When the main arbitration unit 113 permits the transfer request from the bus master 101, the main arbitration unit 113 asserts the signal REQ_SUB with a signal indicating that the transfer request is permitted, that is, an ACK signal. Output to the sub-arbiter 110. In addition, the main arbitration unit 113 outputs information indicating which bus master 101 is permitted to transfer, that is, ID information of the bus master 101 to the sub arbitration unit 110. Since a plurality of sub-arbitration units 110 are connected to the main arbitration unit 113, the signal REQ_SUB from the plurality of sub-arbitration units 110 may be asserted at the same time. When the signal REQ_SUB from the plurality of sub arbitration units 110 connected to the main arbitration unit 113 is asserted at the same time, the main arbitration unit 113 performs the following process. That is, the main arbitration unit 113 sets the bus master 101 having the highest priority among the bus masters 101 that have issued the transfer request that has caused the assertion of the signal REQ_SUB to the priority levels set in advance for the respective bus masters 101. Select based on. Then, the main arbitration unit 113 allows the selected bus master 101 to transfer data. Thereafter, the main arbitration unit 113 appropriately performs arbitration processing in the same manner as described above.

  FIG. 2 is a diagram showing signals input / output between the functional blocks. FIG. 2 shows some of the various functional blocks shown in FIG. Specifically, in FIG. 2A, an imaging processing unit 101a, an evaluation value generation unit 101b, a recognition processing unit 101c, a sub arbitration unit 110a, and a main arbitration unit 113 are extracted and shown. ing. In FIG. 2B, the development processing unit 101d, the display control unit 101e, the sub arbitration unit 110b, and the main arbitration unit 113 are extracted and shown. In FIG. 2C, an encoding processing unit 101f, a recording medium control unit 101g, a sub arbitration unit 110c, and a main arbitration unit 113 are extracted and shown. In FIG. 2D, the main arbitration unit 113 and the memory 109 are extracted and shown.

  As shown in FIGS. 2A to 2C, each of the bus masters 101a to 101g appropriately transmits signals REQ0 to REQ6, that is, a REQ signal (transfer request signal) to the sub arbitration units 110a to 110c. Output. Note that reference numerals REQ0 to REQ6 are used when describing individual transfer request signals, and the terms “REQ signal” and “transfer request signal” are used as appropriate when general transfer request signals are described. Each of the bus masters 101a to 101g outputs signals REQ1 to REQ6 and outputs signals ADRS0 to ADRS6 as appropriate to the sub arbitration units 110a to 110c. Read / write, that is, information indicating the data transfer direction, information indicating the address of the data transfer destination, information indicating the size of the data to be transferred, and the like are transmitted by signals ADRS0 to ADRS6. Note that these pieces of information transmitted from the bus master 101 to the sub arbitration unit 110 by the signals ADRS0 to ADRS6 are appropriately transmitted from the sub arbitration unit 110 to the main arbitration unit 113 by the signals ADRS_SUB0 to ADRS_SUB2. Signals ADRS0 to ADRS6 are transmitted by parallel transmission using a plurality of signal lines, respectively. The sub arbitration units 110a to 110c appropriately output signals ACK0 to ACK6 indicating that transfer requests from the bus masters 101a to 101g have been permitted by the main arbitration unit 113, that is, ACK signals, to the respective bus masters 101a to 101g. To do. The sub arbitration units 110a to 110c appropriately output signals WEN0 to WEN6 indicating that the sub arbitration units 110a to 110c are ready to receive write data to the respective bus masters 101a to 101g. The write data is data written to the memory 109. Each of the bus masters 101a to 101g appropriately outputs signals WVALID0 to WVALID6 indicating that the write data is valid data to the sub arbitration units 110a to 110c. Each of the bus masters 101a to 101g appropriately outputs the write data to the sub arbitration units 110a to 110c by signals WDATA0 to WDATA6. The signals WDATA0 to WDATA6 are transmitted by parallel transmission using a plurality of signal lines. The sub arbitration units 110a to 110c appropriately output signals RVALID0 to RVALID6 indicating that the data transmitted by the signals RDATA0 to RDATA6 is valid data to the respective bus masters 101a to 101g. The sub arbitration units 110a to 110c appropriately output the read data to the respective bus masters 101a to 101g by signals RDATA0 to RDATA6. Note that the read data is data read from the memory 109. The signals RDATA0 to RDATA6 are transmitted by parallel transmission using a plurality of signal lines. The sub arbitration units 110a to 110c appropriately output signals RLAST0 to RLAST6 indicating that the final read data is transmitted by the signals RDATA0 to RDATA6 to the respective bus masters 101a to 101g.

  Here, a data transfer method will be described taking data transfer between the imaging processing unit 101a and the sub-arbitration unit 110a as an example. In data transfer, first, the imaging processing unit 101a outputs a signal REQ0 and a signal ADRS0. As described above, read / write, that is, information indicating the data transfer direction, information indicating the address of the data transfer destination, information indicating the size of the data to be transferred, and the like are transmitted by the signal ADRS0. When the main arbitration unit 113 permits the transfer request from the imaging processing unit 101a, the sub arbitration unit 110a outputs a signal ACK0 to the imaging processing unit 101a. The signal ACK0 is output from the sub-arbitration unit 110a to the imaging processing unit 101a, so that the imaging processing unit 101a is notified that the signal REQ0 is permitted by the main arbitration unit 113. Thereafter, data transfer is started.

  Data is written to the memory 109 as follows. In other words, when data is written, after the signal ACK0 is output from the sub-arbitration unit 110a to the imaging processing unit 101a, the signal WEN0 indicating that preparation for reception of the write data is completed is output from the sub-arbitration unit 110a. The image is output to the imaging processing unit 101a. Upon receiving the signal WEN0, the imaging processing unit 101a outputs write data to the sub arbitration unit 110a by the signal WDATA0, and outputs a signal WVALID0 indicating that the write data is valid data to the sub arbitration unit 110a. The sub-arbiter 110a receives the write data within the period in which the signal WVALID0 is received as valid data. Thus, data is written into the memory 109.

  Reading data from the memory 109 is performed as follows. That is, when data is read, after the signal ACK0 is output from the sub arbitration unit 110a to the imaging processing unit 101a, the sub arbitration unit 110a outputs read data to the imaging processing unit 101a by the signal RDATA0. The sub-arbiter 110a outputs read data to the imaging processor 101a by the signal RDATA0 and outputs a signal RVALID0 indicating that the read data is valid to the imaging processor 101a. The imaging processing unit 101a receives, as valid data, read data within a period in which the signal RVALID0 is received. Further, when outputting the final read data, the sub arbitration unit 110a outputs the signal RLAST0 to notify the imaging processing unit 101a that the read data is the final read data.

  As described above, the sub-arbiter 110 appropriately asserts the signal REQ_SUB corresponding to the REQ signal and appropriately outputs the signal ADRS_SUB. Then, the main arbitration unit 113 appropriately permits the data transfer by the bus master 101 that has issued the transfer request as described above. When the main arbitration unit 113 permits data transfer by the bus master 101 that has issued the REQ signal, the main arbitration unit 113 outputs the signal ACK_SUB to the sub-arbitration unit 110 that has asserted the signal REQ_SUB corresponding to the REQ signal. In the description of the individual transfer permission signals, the codes ACK_SUB0 to ACK_SUB2 are used, and in the description of the transfer permission signals in general, the code ACK_SUB is used. The main arbitration unit 113 asserts the signal ACK_SUB and also transmits a signal ID_SUB indicating which of the plurality of bus masters 101 connected to the sub arbitration unit 110 is permitted to be transferred to the sub arbitration unit. Output to 110a. In addition, when describing each signal ID_SUB, code | symbol ID_SUB0-ID_SUB2 is used, and when signal ID_SUB general is demonstrated, code | symbol ID_SUB is used. The signal ID_SUB is transmitted by parallel transmission using a plurality of signal lines.

  After the transfer request is granted, data transfer, specifically, data writing to the memory 109 and data reading from the memory 109 are performed. For example, when writing is performed, signals WEN_SUB0 to WEN_SUB2 indicating that preparation for reception of write data is completed are appropriately output to the sub-arbitration units 110a to 110c. The main arbitration unit 113 appropriately outputs signals WID_SUB <b> 0 to WID_SUB <b> 2 indicating which of the bus masters 101 is ready to receive write data written to the sub arbitration unit 110 a. The signals WID_SUB0 to WID_SUB2 are transmitted by parallel transmission using a plurality of signal lines. The sub arbitration units 110a to 110c appropriately output the write data to the main arbitration unit 113 by signals WDATA_SUB0 to WDATA_SUB2, and perform the following processing. That is, the sub arbitration units 110a to 110c appropriately output signals WVALID_SUB0 to WVALID_SUB2 indicating that the write data is valid data to the main arbitration unit 113. The signals WDATA_SUB0 to WDATA_SUB2 are transmitted by parallel transmission using a plurality of signal lines.

  On the other hand, when reading is performed, signals RID_SUB0 to RID_SUB2 indicating which bus master 101 should be read data are appropriately output from the main arbitration unit 113 to the sub arbitration units 110a to 110c. The signals RID_SUB0 to RID_SUB2 are transmitted by parallel transmission using a plurality of signal lines. The main arbitration unit 113 appropriately outputs read data to the sub-arbitration unit 110a by signals RDATA_SUB0 to RDATA_SUB2. The signals RDATA_SUB0 to RDATA_SUB2 are transmitted by parallel transmission using a plurality of signal lines. Further, the main arbitration unit 113 appropriately outputs signals RVALID_SUB0 to RVALID_SUB2 indicating that the read data is valid data to the sub arbitration units 110a to 110c. The main arbitration unit 113 appropriately outputs signals RLAST_SUB0 to RLAST_SUB2 indicating that the final read data is output to the sub arbitration unit 110a.

  As shown in FIG. 2D, an address (address signal) and a command (command signal) are input from the main arbitration unit 113 to the memory 109. Here, a case where an address and a command are issued from the main arbitration unit 113 is shown, but an address and a command may be issued from a functional block provided separately from the main arbitration unit 113. In addition, data input / output is performed between the main arbitration unit 113 and the memory 109. Note that, here, a case where data is input / output between the main arbitration unit 113 and the memory 109 is shown, but data is transmitted between the functional block provided separately from the main arbitration unit 113 and the memory 109. May be input / output. The address, command, and data are each transmitted by parallel transmission using a plurality of signal lines.

  Communication performed between the bus master 101 and the sub arbitration unit 110 and communication performed between the sub arbitration unit 110 and the main arbitration unit 113 mainly include two phases. The first phase is a phase until the bus master 101 outputs a transfer request, specifically, a REQ signal, and the transfer request is permitted by the main arbitration unit 113, that is, an address phase. The second phase is a phase after the address phase and is a phase in which data transfer is performed, that is, a data phase. The data phase includes a data write phase in which data is written to the memory 109 and a data read phase in which data is read from the memory 109.

  FIG. 3 is a time chart showing the operation of the memory controller in the address phase. Here, a case where the priorities of the plurality of bus masters 101 connected to the sub arbitration unit 110a are set as follows will be described as an example. The bus master having the highest priority among the bus masters 101a to 101c is the imaging processing unit 101a. The bus master 101 with the second highest priority is the evaluation value generation unit 101b. The bus master 101 with the third highest priority is the recognition processing unit 101c. The priority of the bus master 101 is not limited to this, and can be set as appropriate.

  FIG. 3A shows a case where a transfer request is issued simultaneously from the evaluation value generation unit 101b and the recognition processing unit 101c at timing T0, and then a transfer request is issued from the imaging processing unit 101a at timing T7. Yes. Here, a case where a transfer request is not issued from the bus masters 101d to 101g other than the bus masters 101a to 101c will be described as an example.

  At timing T0, the evaluation value generation unit 101b issues a transfer request. Specifically, the evaluation value generation unit 101b asserts the REQ signal, that is, the signal REQ1. At timing T0, the recognition processing unit 101c issues a transfer request. Specifically, the recognition processing unit 101c asserts the REQ signal, that is, the signal REQ2. Evaluation value generation unit 101b issues a transfer request and transmits information A1 related to the transfer request to sub-arbitration unit 110a by signal ADRS1. In addition, the recognition processing unit 101c issues a transfer request and transmits information A2 related to the transfer request to the sub-arbiter 110a by a signal ADRS2. The information A1 and A2 include read / write, that is, information indicating the data transfer direction, information indicating the address of the data transfer destination, information indicating the size of the data to be transferred, and the like.

  Since transfer requests from the two bus masters 101b and 101c are issued simultaneously, the sub arbitration unit 110a sequentially selects these transfer requests according to the priority of the bus master 101. The bus master having the highest priority among the bus master 101b and the bus master 101c is the evaluation value generation unit 101b. Accordingly, the sub-arbitration unit 110a first selects a transfer request from the evaluation value generation unit 101b. The sub arbitration unit 110a asserts a signal REQ_SUB0 corresponding to the transfer request at timing T1, and transmits information A1 related to the transfer request to the main arbitration unit 113 by the signal ADRS_SUB0. The information A1 transmitted by the signal ADRS_SUB0 includes, in addition to read / write, that is, information indicating a data transfer direction, information indicating a data transfer destination address, and information indicating a size of data to be transferred. Such information is also included. That is, the information A1 transmitted by the signal ADRS_SUB0 includes information indicating that the signal REQ_SUB0 corresponds to the signal REQ1 from the evaluation value generation unit 101b. The main arbitration unit 113 can determine that the signal REQ_SUB0 corresponds to the signal REQ1 from the evaluation value generation unit 101b based on the information A1 transmitted by the signal ADRS_SUB0. In this way, a transfer request from the evaluation value generation unit 101b is transmitted to the main arbitration unit 113.

  When the transfer request from the evaluation value generation unit 101b is transmitted to the main arbitration unit 113, the bus master 101 that has issued the transfer request but has not been transmitted to the main arbitration unit 113 is the recognition processing unit. 101c only. Therefore, the sub arbitration unit 110a selects a transfer request from the recognition processing unit 101c. The sub arbitration unit 110a transmits the information A2 related to the transfer request from the recognition processing unit 101c to the main arbitration unit 113 by the signal ADRS_SUB0 while maintaining the assertion of the signal REQ_SUB0. The information A2 transmitted by the signal ADRS_SUB0 includes, in addition to read / write, that is, information indicating the data transfer direction, information indicating the address of the data transfer destination, and information indicating the size of the data to be transferred. Such information is also included. That is, information A2 transmitted by the signal ADRS_SUB0 includes information indicating that the signal REQ_SUB0 corresponds to the signal REQ2 from the recognition processing unit 101c. The main arbitration unit 113 can determine that the signal REQ_SUB0 corresponds to the signal REQ2 from the recognition processing unit 101c based on the information A2 transmitted by the signal ADRS_SUB0. In this way, the transfer request from the recognition processing unit 101 c is transmitted to the main arbitration unit 113. Thus, the sub arbitration unit 110a transmits the transfer request from the bus master 101c to the main arbitration unit 113 regardless of whether the transfer request from the bus master 101b is permitted by the main arbitration unit 113.

  At the stage when the transfer request from the evaluation value generation unit 101b is transmitted to the main arbitration unit 113, the transfer request from the recognition processing unit 101c is not transmitted to the main arbitration unit 113. Accordingly, at this stage, the main arbitration unit 113 receives a request from the evaluation value generation unit 101b on the condition that there is no particular problem with granting a transfer request from the evaluation value generation unit 101b. Permit transfer request. Specifically, the main arbitration unit 113 asserts the signal ACK_SUB0 at the timing T2. Also, the main arbitration unit 113 sends information I1 indicating that the bus master 101 to which the transfer request is permitted is the evaluation value generation unit 101b, that is, ID information of the evaluation value generation unit 101b, to the sub arbitration unit 110a by the signal ID_SUB0. introduce. Based on the assertion of the signal ACK_SUB0 and the information I1 indicated by the signal ID_SUB0, the sub arbitration unit 110a detects that the main arbitration unit 113 has permitted the transfer request from the evaluation value generation unit 101b. The sub arbiter 110a asserts the signal ACK1 transmitted from the sub arbiter 110a to the evaluation value generator 101b at timing T3. The evaluation value generation unit 101b can detect that the transfer request from the evaluation value generation unit 101b, that is, the signal REQ1 is permitted by the main arbitration unit 113 by detecting the assertion of the signal ACK1. The evaluation value generation unit 101b that has detected the signal ACK1 deasserts the signal REQ1 at timing T4. Further, the sub-arbiter 110a deasserts the signal ACK1 at the timing T4. In this way, the main arbitration unit 113 permits the transfer request from the evaluation value generation unit 101b.

  When the transfer request from the evaluation value generation unit 101b is granted to the main arbitration unit 113, the transfer request is received by the main arbitration unit 113, but the transfer request is not granted. Is only the recognition processing unit 101c. Accordingly, at this stage, the main arbitration unit 113 requests the transfer request from the recognition processing unit 101c on the condition that there is no particular problem with granting the transfer request from the recognition processing unit 101c. Permission. Specifically, the main arbitration unit 113 performs the following process while maintaining the assertion of the signal ACK_SUB0. That is, the main arbitration unit 113 transmits information I2 indicating that the bus master 101 to which the transfer request is permitted is the recognition processing unit 101c, that is, ID information of the recognition processing unit 101c, to the sub-arbitration unit 110a by the signal ID_SUB0. . The sub arbitration unit 110a detects that the transfer request from the recognition processing unit 101c is permitted by the main arbitration unit 113 based on the assertion of the signal ACK_SUB0 and the information I2 indicated by the signal ID_SUB0. The sub arbitration unit 110a asserts the signal ACK2 output from the sub arbitration unit 110a to the recognition processing unit 101c at timing T4. At T4, the main arbitration unit 113 deasserts the signal ACK_SUB0. The recognition processing unit 101c can detect that the transfer request from the recognition processing unit 101c, that is, the signal REQ2 is permitted by the main arbitration unit 113 by detecting the assertion of the signal ACK2. At timing T4, the main arbitration unit 113 deasserts the signal ACK_SUB0. The recognition processing unit 101c that has detected the signal ACK2 deasserts the signal REQ2 at timing T5. Further, at timing T5, the sub-arbiter 110a deasserts the signal ACK2.

  Thereafter, for example, at timing T7, the imaging processing unit 101a issues a transfer request. Specifically, the imaging processing unit 101a asserts the signal REQ0. The imaging processing unit 101a issues a transfer request and outputs information A0 related to the transfer request. The information A0 includes read / write, that is, information indicating the data transfer direction, information indicating the address of the data transfer destination, information indicating the size of the data to be transferred, and the like. The bus master 101 that asserts the REQ signal is only the imaging processing unit 101a. Accordingly, the sub-arbitration unit 110a selects the transfer request from the imaging processing unit 101a on the condition that there is no particular problem with selecting the transfer request from the imaging processing unit 101a. The sub arbitration unit 110a asserts the signal REQ_SUB0 corresponding to the transfer request at timing T8, and transmits information A0 related to the transfer request to the main arbitration unit 113 by the signal ADRS_SUB0. The information A0 transmitted by the signal ADRS_SUB0 includes, in addition to read / write, that is, information indicating the data transfer direction, information indicating the address of the data transfer destination, and information indicating the size of the data to be transferred. Such information is also included. That is, the information A0 transmitted by the signal ADRS_SUB0 includes information indicating that the signal REQ_SUB0 corresponds to the signal REQ0 from the imaging processing unit 101a. The main arbitration unit 113 determines that the signal REQ_SUB0 corresponds to the signal REQ0 from the imaging processing unit 101a based on the information A0 transmitted by the signal ADRS_SUB0. In this way, the transfer request from the imaging processing unit 101a is transmitted to the main arbitration unit 113.

  As described above, the signal REQ_SUB0 asserted at the timing T8 is in response to a transfer request from the imaging processing unit 101a. REQ_SUB corresponding to a transfer request other than the transfer request from the imaging processing unit 101a is not asserted at this stage. Accordingly, at this stage, the main arbitration unit 113 requests the transfer request from the imaging processing unit 101a on the condition that there is no particular problem with granting the transfer request from the imaging processing unit 101a. Permission. Specifically, the main arbitration unit 113 asserts the signal ACK_SUB0 at the timing T9. Further, the main arbitration unit 113 transmits information I0 indicating that the bus master 101 to which the transfer request is permitted is the imaging processing unit 101a, that is, ID information of the imaging processing unit 101a, to the sub-arbitration unit 110a by the signal ID_SUB0. . The sub arbitration unit 110a detects that the transfer request from the imaging processing unit 101a is permitted by the main arbitration unit 113 based on the assertion of the signal ACK_SUB0 and the information I0 indicated by the signal ID_SUB0. The sub arbitration unit 110a asserts the signal ACK0 output from the sub arbitration unit 110a to the imaging processing unit 101a at timing T10. Note that the main arbitration unit 113 deasserts the signal ACK_SUB0 at the timing T10. The imaging processing unit 101a can detect that the transfer request from the imaging processing unit 101a, that is, the signal REQ0 is permitted by the main arbitration unit 113 by detecting the assertion of the signal ACK0. The imaging processing unit 101a that has detected the signal ACK0 deasserts the signal REQ0 at timing T11. In addition, the sub arbitration unit 110a deasserts the signal ACK0 at the timing T11.

  In FIG. 3A, there is no contention between the transfer request from the bus master 101 connected to the sub arbitration unit 110a and the transfer request from the bus master 101 connected to the other sub arbitration units 110b and 110c. The case has been described as an example. However, there may be a conflict between a transfer request from the bus master 101 connected to the sub arbitration unit 110a and a transfer request from the bus master 101 connected to the other sub arbitration units 110b and 110c. When a transfer request from the bus master 101 connected to the sub arbitration unit 110a conflicts with a transfer request from the bus master 101 connected to the other sub arbitration units 110b and 110c, for example, FIG. As shown. In FIG. 3B, a transfer request is simultaneously issued from the evaluation value generation unit 101b, the recognition processing unit 101c, and the development processing unit 101d at timing T0, and thereafter, a transfer request is issued from the imaging processing unit 101a at timing T7. Shows the case. Here, a case where the priorities of the plurality of bus masters 101 connected to the sub arbitration unit 110 are set as follows will be described as an example. The bus master having the highest priority among the bus masters 101a to 101d is the imaging processing unit 101a. The bus master 101 with the second highest priority is the evaluation value generation unit 101b. The bus master 101 with the third highest priority is the recognition processing unit 101c. The bus master 101 with the fourth highest priority is the development processing unit 101d. The priority of the bus master 101 is not limited to this, and can be set as appropriate.

  At timing T0, the evaluation value generation unit 101b, the recognition processing unit 101c, and the development processing unit 101d each issue a transfer request. Specifically, the evaluation value generation unit 101b asserts the signal REQ1, the recognition processing unit 101c asserts the signal REQ2, and the development processing unit 101d asserts the signal REQ3. Evaluation value generation unit 101b issues a transfer request and transmits information A1 related to the transfer request to sub-arbitration unit 110a by signal ADRS1. In addition, the recognition processing unit 101c issues a transfer request and transmits information A2 related to the transfer request to the sub-arbiter 110a by a signal ADRS2. Further, the development processing unit 101d issues a transfer request and transmits information A3 related to the transfer request to the sub-arbitration unit 110b by a signal ADRS3. The information A1 to A3 includes read / write, that is, information indicating the data transfer direction, information indicating the address of the data transfer destination, information indicating the size of the data to be transferred, and the like.

  Since transfer requests from the two bus masters 101b and 101c are simultaneously transmitted to the sub arbitration unit 110a, the sub arbitration unit 110a appropriately selects these transfer requests according to the priority of the bus master 101. The bus master having the highest priority among the bus master 101b and the bus master 101c is the evaluation value generation unit 101b. Therefore, the sub arbitration unit 110a selects a transfer request from the evaluation value generation unit 101b. The sub arbitration unit 110a asserts a signal REQ_SUB0 corresponding to the transfer request at timing T1, and transmits information A1 related to the transfer request to the main arbitration unit 113 by the signal ADRS_SUB0. The information A1 transmitted by the signal ADRS_SUB0 includes, in addition to read / write, that is, information indicating a data transfer direction, information indicating a data transfer destination address, and information indicating a size of data to be transferred. Such information is also included. That is, the information A1 transmitted by the signal ADRS_SUB0 includes information indicating that the signal REQ_SUB0 corresponds to the signal REQ1 from the evaluation value generation unit 101b. The main arbitration unit 113 can determine that the signal REQ_SUB0 corresponds to the signal REQ1 from the evaluation value generation unit 101b based on the information A1 transmitted by the signal ADRS_SUB0. In this way, a transfer request from the evaluation value generation unit 101b is transmitted to the main arbitration unit 113.

  On the other hand, since the transfer request transmitted to the sub arbitration unit 110b is only the transfer request from the development processing unit 101d, the sub arbitration unit 110b selects the transfer request from the development processing unit 101d. The sub arbitration unit 110b asserts the signal REQ_SUB1 corresponding to the transfer request at timing T1, and transmits information A3 related to the transfer request to the main arbitration unit 113 by the signal ADRS_SUB1. The information A3 transmitted by the signal ADRS_SUB1 includes, in addition to read / write, that is, information indicating the data transfer direction, information indicating the address of the data transfer destination, and information indicating the size of the data to be transferred. Such information is also included. That is, information A3 transmitted by the signal ADRS_SUB1 includes information indicating that the signal REQ_SUB1 corresponds to the signal REQ3 from the development processing unit 101d. The main arbitration unit 113 can determine that the signal REQ_SUB1 corresponds to the signal REQ3 from the development processing unit 101d based on the information A3 transmitted by the signal ADRS_SUB1. In this way, a transfer request from the development processing unit 101d is transmitted to the main arbitration unit 113.

  At the stage where the transfer request from the evaluation value generation unit 101b and the transfer request from the development processing unit 101d are transmitted to the main arbitration unit 113, the transfer request from the recognition processing unit 101c is not transmitted to the main arbitration unit 113. The main arbitration unit 113 arbitrates the transfer request from the bus master 101 at this stage, that is, when the transfer request from the recognition processing unit 101c is not transmitted to the main arbitration unit 113 as follows. That is, the main arbitration unit 113 selects the bus master 101 having the highest priority among the bus masters 101 for which the main arbitration unit 113 has received the transfer request, based on the priority set in advance for each bus master 101. To do. At this stage, the transfer requests received by the main arbitration unit 113 are a transfer request from the evaluation value generation unit 101b and a transfer request from the development processing unit 101d. Among these bus masters 101, the bus master 101 having the highest priority is the evaluation value generation unit 101b. Therefore, the main arbitration unit 113 responds to the transfer request from the evaluation value generation unit 101b on the condition that there is no particular problem with respect to granting the transfer request from the evaluation value generation unit 101b. Permission. Specifically, the main arbitration unit 113 asserts the signal ACK_SUB0 at the timing T2. Also, the main arbitration unit 113 sends information I1 indicating that the bus master 101 to which the transfer request is permitted is the evaluation value generation unit 101b, that is, ID information of the evaluation value generation unit 101b, to the sub arbitration unit 110a by the signal ID_SUB0. introduce. Based on the assertion of the signal ACK_SUB0 and the information I1 indicated by the signal ID_SUB0, the sub arbitration unit 110a detects that the main arbitration unit 113 has permitted the transfer request from the evaluation value generation unit 101b. The sub arbiter 110a asserts the signal ACK1 transmitted from the sub arbiter 110a to the evaluation value generator 101b at timing T3. The evaluation value generation unit 101b can detect that the transfer request from the evaluation value generation unit 101b, that is, the signal REQ1 is permitted by the main arbitration unit 113 by detecting the assertion of the signal ACK1. The evaluation value generation unit 101b that has detected the signal ACK1 deasserts the signal REQ1 at timing T4. Further, the sub-arbiter 110a deasserts the signal ACK1 at the timing T4. In this way, the main arbitration unit 113 permits the transfer request from the evaluation value generation unit 101b.

  When the transfer request from the evaluation value generation unit 101b is transmitted to the main arbitration unit 113, the bus master 101 whose transfer request is not transmitted to the main arbitration unit 113 by the sub arbitration unit 110 is only the recognition processing unit 101c. Therefore, the sub arbitration unit 110a selects the transfer request from the recognition processing unit 101c at the timing T2. The sub arbitration unit 110a transmits the information A2 related to the transfer request from the recognition processing unit 101c to the main arbitration unit 113 by the signal ADRS_SUB0 while maintaining the assertion of the signal REQ_SUB0. The information A2 transmitted by the signal ADRS_SUB0 includes, in addition to read / write, that is, information indicating the data transfer direction, information indicating the address of the data transfer destination, and information indicating the size of the data to be transferred. Such information is also included. That is, information A2 transmitted by the signal ADRS_SUB0 includes information indicating that the signal REQ_SUB0 corresponds to the signal REQ2 from the recognition processing unit 101c. The main arbitration unit 113 can determine that the signal REQ_SUB0 corresponds to the signal REQ2 from the recognition processing unit 101c based on the information A2 transmitted by the signal ADRS_SUB0. In this way, the transfer request from the recognition processing unit 101 c is transmitted to the main arbitration unit 113. As described above, the sub arbitration unit 110a transmits the transfer request from the bus master 101c to the main arbitration unit 113 regardless of whether the transfer request from the bus masters 101b and 101d is permitted by the main arbitration unit 113.

  At the stage where permission for the transfer request from the evaluation value generation unit 101b is performed by the main arbitration unit 113, permission for the transfer request from the recognition processing unit 101c and the transfer request from the development processing unit 101d is granted to the main arbitration unit. 113 is not performed. Therefore, the main arbitration unit 113 arbitrates transfer requests from these bus masters 101b and 101d as follows. That is, the main arbitration unit 113 assigns the bus master 101 having the highest priority among the bus masters 101 that are not permitted for the transfer request even though the transfer request is received by the main arbitration unit 113. Select based on priority. At this stage, the bus master 101 that is not permitted for the transfer request although the transfer request is received by the main arbitration unit 113 is the recognition processing unit 101c and the development processing unit 101d. Of these bus masters 101c and 101d, the bus master 101 having the highest priority is the recognition processing unit 101c. Therefore, the main arbitration unit 113 permits the transfer request from the recognition processing unit 101c on the condition that there is no particular problem with the permission for the transfer request from the recognition processing unit 101c. I do. Specifically, the main arbitration unit 113 performs the following process while maintaining the assertion of the signal ACK_SUB0 at the timing T3. That is, the main arbitration unit 113 transmits information I2 indicating that the bus master 101 to which the transfer request is permitted is the recognition processing unit 101c, that is, ID information of the recognition processing unit 101c, to the sub-arbitration unit 110a by the signal ID_SUB0. . The sub arbitration unit 110a detects that the transfer request from the recognition processing unit 101c is permitted by the main arbitration unit 113 based on the assertion of the signal ACK_SUB0 and the information I2 indicated by the signal ID_SUB0. The sub arbitration unit 110a asserts the signal ACK2 transmitted from the sub arbitration unit 110a to the recognition processing unit 101c at timing T4. The recognition processing unit 101c can detect that the transfer request from the recognition processing unit 101c, that is, the signal REQ2 is permitted by the main arbitration unit 113 by detecting the assertion of the signal ACK2. The recognition processing unit 101c that has detected the signal ACK2 deasserts the signal REQ2 at timing T5. In addition, the sub arbitration unit 110a deasserts the signal ACK2 at the timing T5. In this way, the main arbitration unit 113 permits the transfer request from the recognition processing unit 101c.

  At the stage where the transfer request from the recognition processing unit 101c is permitted by the main arbitration unit 113, the transfer request from the development processing unit 101d is not permitted by the main arbitration unit 113. The bus master 101 that is not permitted for the transfer request even though the transfer request is received by the main arbitration unit 113 is only the development processing unit 101d at this stage. Therefore, the main arbitration unit 113 permits the transfer request from the development processing unit 101d on the condition that there is no particular problem with the permission for the transfer request from the development processing unit 101d. I do. Specifically, the main arbitration unit 113 asserts the signal ACK_SUB1 at timing T4. Further, the main arbitration unit 113 transmits information I3 indicating that the bus master 101 to which the transfer request is permitted is the development processing unit 101d, that is, ID information of the development processing unit 101d, to the sub arbitration unit 110b by the signal ID_SUB1. . The sub arbitration unit 110b detects that the transfer request from the development processing unit 101d has been permitted by the main arbitration unit 113 based on the assertion of the signal ACK_SUB1 and the information I3 indicated by the signal ID_SUB1. The sub arbitration unit 110b asserts a signal ACK3 transmitted from the sub arbitration unit 110b to the development processing unit 101d at timing T5. The development processing unit 101d can detect that the transfer request from the development processing unit 101d, that is, the signal REQ3 is permitted by the main arbitration unit 113 by detecting the assertion of the signal ACK3. The development processing unit 101d that has detected the signal ACK3 deasserts the signal REQ3 at timing T6. Further, the sub arbitration unit 110b deasserts the signal ACK3 at the timing T6. In this manner, the main arbitration unit 113 permits the transfer request from the development processing unit 101d.

  The operation after timing T7 in FIG. 3B is the same as the operation after timing T7 described above with reference to FIG.

  3A and 3B, an example has been described in which a transfer request issued from the bus master 101 at the timing T0 is quickly and sequentially permitted by the main arbitration unit 113. However, a transfer request issued from the bus master 101 may not be immediately permitted by the main arbitration unit 113. For example, when it is necessary for the main arbitration unit 113 to perform processing having a higher priority than the permission processing for the transfer request from the bus master 101, the main arbitration unit 113 promptly permits the transfer request issued from the bus master 101. Not done. Further, even when a large number of transfer requests are issued from the bus master 101 with a high priority, permission for the transfer requests from the bus master 101 with a low priority is not promptly performed. When the transfer request issued from the bus master 101 is not promptly permitted by the main arbitration unit 113, for example, as shown in FIG. FIG. 3C shows a state in which the transfer request issued from the evaluation value generation unit 101b and the recognition processing unit 101c at timing T0 is not permitted by the main arbitration unit 113, and is transferred from the imaging processing unit 101a. Shows when a request is issued. Here, the priority of the bus master 101 connected to the sub arbitration unit 110a is the same as described above. That is, the bus master having the highest priority among the bus masters 101a to 101c is the imaging processing unit 101a. The bus master 101 with the second highest priority is the evaluation value generation unit 101b. The bus master 101 with the third highest priority is the recognition processing unit 101c. The priority of the bus master 101 is not limited to this, and can be set as appropriate.

  At timing T0, the evaluation value generation unit 101b and the recognition processing unit 101c each issue a transfer request. Specifically, the evaluation value generation unit 101b asserts the signal REQ1, and the recognition processing unit 101c asserts the signal REQ2. Evaluation value generation unit 101b issues a transfer request and transmits information A1 related to the transfer request to sub-arbitration unit 110a by signal ADRS1. In addition, the recognition processing unit 101c issues a transfer request and transmits information A2 related to the transfer request to the sub-arbiter 110a by a signal ADRS2. The information A1 and A2 include read / write, that is, information indicating the data transfer direction, information indicating the address of the data transfer destination, information indicating the size of the data to be transferred, and the like.

  Since the transfer requests from the two bus masters 101b and 101c are simultaneously transmitted to the sub arbitration unit 110a, the sub arbitration unit 110a appropriately selects these transfer requests according to the priority of the bus master 101. The bus master having the highest priority among the bus master 101b and the bus master 101c is the evaluation value generation unit 101b. Therefore, first, at this stage, the sub-arbiter 110a selects a transfer request from the evaluation value generator 101b. The sub arbitration unit 110a asserts a signal REQ_SUB0 corresponding to the transfer request at timing T1, and transmits information A1 related to the transfer request to the main arbitration unit 113 by the signal ADRS_SUB0. The information A1 transmitted by the signal ADRS_SUB0 includes, in addition to read / write, that is, information indicating a data transfer direction, information indicating a data transfer destination address, and information indicating a size of data to be transferred. Such information is also included. That is, the information A1 transmitted by the signal ADRS_SUB0 includes information indicating that the signal REQ_SUB0 corresponds to the signal REQ1 from the evaluation value generation unit 101b. The main arbitration unit 113 can determine that the signal REQ_SUB0 corresponds to the signal REQ1 from the evaluation value generation unit 101b based on the information A1 transmitted by the signal ADRS_SUB0. In this way, the transfer request from the evaluation value generation unit 101b is transmitted to the main arbitration unit 113 by the sub arbitration unit 110a.

  When the transfer request from the evaluation value generation unit 101b is transmitted to the main arbitration unit 113 by the sub arbitration unit 110a, the bus master 101 whose transfer request is not transmitted to the main arbitration unit 113 by the sub arbitration unit 110a is the recognition processing unit 101c. Only. Accordingly, at this stage, the sub-arbiter 110a selects a transfer request from the recognition processor 101c. The sub arbitration unit 110a transmits the information A2 related to the transfer request from the recognition processing unit 101c to the main arbitration unit 113 by the signal ADRS_SUB0 while maintaining the assertion of the signal REQ_SUB0. The information A2 transmitted by the signal ADRS_SUB0 includes, in addition to read / write, that is, information indicating the data transfer direction, information indicating the address of the data transfer destination, and information indicating the size of the data to be transferred. Such information is also included. That is, information A2 transmitted by the signal ADRS_SUB0 includes information indicating that the signal REQ_SUB0 corresponds to the signal REQ2 from the recognition processing unit 101c. The main arbitration unit 113 can determine that the signal REQ_SUB0 corresponds to the signal REQ2 from the recognition processing unit 101c based on the information A2 transmitted by the signal ADRS_SUB0. Thus, the transfer request from the recognition processing unit 101c is transmitted to the main arbitration unit 113 by the sub arbitration unit 110a. Thus, the sub arbitration unit 110a transmits the transfer request from the bus master 101c to the main arbitration unit 113 regardless of whether the transfer request from the bus master 101b is permitted by the main arbitration unit 113.

  Although the transfer request from the bus master 101b and the transfer request from the bus master 101c are transmitted to the main arbitration unit 113, the transfer request issued from the bus masters 101b and 101c is not immediately permitted by the main arbitration unit 113. . Since the reason why such a phenomenon occurs is described above, it is omitted here.

  Thereafter, for example, at timing T7, the imaging processing unit 101a issues a transfer request. Specifically, the imaging processing unit 101a asserts the signal REQ0. The imaging processing unit 101a issues a transfer request and transmits information A0 related to the transfer request to the sub-arbiter 110a by a signal ADRS0. The information A0 includes read / write, that is, information indicating the data transfer direction, information indicating the address of the data transfer destination, information indicating the size of the data to be transferred, and the like.

  The sub arbitration unit 110a asserts the signal REQ_SUB0 corresponding to the transfer request at timing T8, and transmits information A0 related to the transfer request to the main arbitration unit 113 by the signal ADRS_SUB0. The information A0 transmitted by the signal ADRS_SUB0 includes, in addition to read / write, that is, information indicating the data transfer direction, information indicating the address of the data transfer destination, and information indicating the size of the data to be transferred. Such information is also included. That is, the information A0 transmitted by the signal ADRS_SUB0 includes information indicating that the signal REQ_SUB0 corresponds to the signal REQ0 from the imaging processing unit 101a. The main arbitration unit 113 can determine that the signal REQ_SUB0 corresponds to the signal REQ0 from the imaging processing unit 101a based on the information A0 transmitted by the signal ADRS_SUB0. In this way, the transfer request from the imaging processing unit 101a is transmitted to the main arbitration unit 113 by the sub arbitration unit 110a.

  At the stage when the transfer request from the imaging processing unit 101a is transmitted to the main arbitration unit 113 by the sub-arbitration unit 110a, permission for the transfer request from the imaging processing unit 101a, the evaluation value generation unit 101b, and the recognition processing unit 101c is permitted. It is not performed by the main arbitration unit 113. The main arbitration unit 113 arbitrates transfer requests from these bus masters 101a to 101c as follows. That is, the main arbitration unit 113 selects the bus master 101 having the highest priority among the bus masters 101 for which the main arbitration unit 113 has received the transfer request, based on the priority set in advance for each bus master 101. To do. At this stage, the transfer requests received by the main arbitration unit 113 are a transfer request from the imaging processing unit 101a, a transfer request from the evaluation value generation unit 101b, and a transfer request from the recognition processing unit 101c. Among these bus masters 101, the bus master 101 having the highest priority is the imaging processing unit 101a. Accordingly, the main arbitration unit 113 does not respond to a transfer request from the imaging processing unit 101a on the condition that there is no particular problem with granting a transfer request from the imaging processing unit 101a. Give permission. Specifically, the main arbitration unit 113 asserts the signal ACK_SUB0 at timing T10, for example. Further, the main arbitration unit 113 transmits information I0 indicating that the bus master 101 to which the transfer request is permitted is the imaging processing unit 101a, that is, ID information of the imaging processing unit 101a, to the sub-arbitration unit 110a by the signal ID_SUB0. . The sub arbitration unit 110a detects that the transfer request from the imaging processing unit 101a is permitted by the main arbitration unit 113 based on the assertion of the signal ACK_SUB0 and the information I0 indicated by the signal ID_SUB0. The sub arbitration unit 110a asserts the signal ACK0 transmitted from the sub arbitration unit 110a to the imaging processing unit 101a at timing T11. The imaging processing unit 101a can detect that the transfer request from the imaging processing unit 101a, that is, the signal REQ0 is permitted by the main arbitration unit 113 by detecting the assertion of the signal ACK0. The imaging processing unit 101a that has detected the signal ACK0 deasserts the signal REQ0 at timing T12. Further, the sub arbitration unit 110a deasserts the signal ACK0 at the timing T12. In this manner, the main arbitration unit 113 permits the transfer request from the imaging processing unit 101a.

  At the stage where permission for the transfer request from the imaging processing unit 101a is performed by the main arbitration unit 113, permission for the transfer request from the evaluation value generation unit 101b and the transfer request from the recognition processing unit 101c is granted to the main arbitration unit. 113 has not yet been performed. Therefore, the main arbitration unit 113 arbitrates transfer requests from these bus masters 101b and 101c as follows. That is, the main arbitration unit 113 assigns the bus master 101 having the highest priority among the bus masters 101 that are not yet permitted for the transfer request even though the transfer request is received by the main arbitration unit 113. Select based on priority. At this stage, the bus master 101 for which the transfer request has been received by the main arbitration unit 113 but has not yet been authorized is the evaluation value generation unit 101b and the recognition processing unit 101c. Among these bus masters 101b and 101c, the bus master 101 having the highest priority is the evaluation value generation unit 101b. Therefore, the main arbitration unit 113 responds to a transfer request from the evaluation value generation unit 101b on the condition that there is no particular problem with granting a transfer request from the evaluation value generation unit 101b. Permission is granted. Specifically, the main arbitration unit 113 performs the following process while maintaining the assertion of the signal ACK_SUB0 at the timing T11. That is, the main arbitration unit 113 sends the information I1 indicating that the bus master 101 to which the transfer request is permitted is the evaluation value generation unit 101b, that is, the ID information of the evaluation value generation unit 101b, to the sub arbitration unit 110a by the signal ID_SUB0. introduce. Based on the assertion of the signal ACK_SUB0 and the information I1 indicated by the signal ID_SUB0, the sub arbitration unit 110a detects that the main arbitration unit 113 has permitted the transfer request from the evaluation value generation unit 101b. The sub arbiter 110a asserts the signal ACK1 transmitted from the sub arbiter 110a to the evaluation value generator 101b at timing T12. The evaluation value generation unit 101b can detect that the transfer request from the evaluation value generation unit 101b, that is, the signal REQ1 is permitted by the main arbitration unit 113 by detecting the assertion of the signal ACK1. The evaluation value generator 101b that has detected the signal ACK1 deasserts the signal REQ1 at timing T13. In addition, the sub arbitration unit 110a deasserts the signal ACK1 at the timing T13. In this way, the main arbitration unit 113 permits the transfer request from the evaluation value generation unit 101b.

  At the stage where permission for the transfer request from the evaluation value generation unit 101b is performed, the bus master 101 that is not permitted for the transfer request even though the transfer request is received by the main arbitration unit 113, Only the recognition processing unit 101c. Therefore, the main arbitration unit 113 permits the transfer request from the recognition processing unit 101c on the condition that there is no particular problem with the permission for the transfer request from the recognition processing unit 101c. I do. Specifically, the main arbitration unit 113 performs the following process while maintaining the assertion of the signal ACK_SUB0 at the timing T12. That is, the main arbitration unit 113 transmits information I2 indicating that the bus master 101 to which the transfer request is permitted is the recognition processing unit 101c, that is, ID information of the recognition processing unit 101c, to the sub-arbitration unit 110a by the signal ID_SUB0. . The sub arbitration unit 110a detects that the transfer request from the recognition processing unit 101c is permitted by the main arbitration unit 113 based on the assertion of the signal ACK_SUB0 and the information I2 indicated by the signal ID_SUB0. The sub arbitration unit 110a asserts the signal ACK2 transmitted from the sub arbitration unit 110a to the recognition processing unit 101c at timing T13. The recognition processing unit 101c can detect that the transfer request from the recognition processing unit 101c, that is, the signal REQ2 is permitted by the main arbitration unit 113 by detecting the assertion of the signal ACK2. The recognition processing unit 101c that has detected the signal ACK2 deasserts the signal REQ2 at timing T14. In addition, the sub arbitration unit 110a deasserts the signal ACK2 at the timing T14. In this way, the main arbitration unit 113 permits the transfer request from the recognition processing unit 101c.

  As described above, in this embodiment, regardless of whether or not the transfer request from the bus master 101 is permitted by the main arbitration unit 113, the transfer request from the bus master 101 is sequentially transmitted to the main arbitration unit 113. Then, the main arbitration unit 113 sequentially grants the transfer requests that are not permitted even though the transfer request is received, based on the preset priority of the bus master 101.

  Next, the operation in the data phase will be described. FIG. 4 is a time chart showing an example of the operation in the data phase. 4A shows a time chart when data is written, and FIG. 4B shows a time chart when data is read. The data phase starts after the address phase. Here, a case where the data phase starts from timing T20 will be described as an example, but the present invention is not limited to this. Here, an example will be described in which the data acquired by the imaging processing unit 101a is written to the memory 109 and the data written in the memory 109 is read by the imaging processing unit 101a. Since data writing and reading are performed in the same manner by other bus masters 101, the description thereof is omitted here. Further, here, a case where data transfer for four bursts, that is, four cycles is performed will be described as an example, but the present invention is not limited to this.

  First, an operation when data is written to the memory 109 will be described with reference to FIG. At timing T20, the main arbitration unit 113 asserts the signal WEN_SUB0 output to the sub arbitration unit 110a. As described above, the signal WEN_SUB0 is a signal indicating that preparation for receiving write data is completed. Further, the main arbitration unit 113 sends information I0 indicating that preparation for reception of the write data from the imaging processing unit 101a, that is, ID information of the imaging processing unit 101a, to the sub-arbitration unit 110a. introduce. Based on the assertion of the signal WEN_SUB0 and the information I0 indicated by the signal WID_SUB0, the sub arbitration unit 110a detects that the main arbitration unit 113 has completed preparation for reception of the write data from the imaging processing unit 101a. . The main arbitration unit 113 deasserts the signal WEN_SUB at timing T21.

  At timing T21, the sub arbitration unit 110a asserts the signal WEN0 output from the sub arbitration unit 110a to the imaging processing unit 101a. As described above, the signal WEN0 is a signal indicating that the preparation for receiving the write data is completed in the sub-arbiter 110a. At timing T22, the sub arbitration unit 110a deasserts the signal WEN0.

  Within the period of timing T22 to T26, that is, within the period of 4 cycles, the imaging processing unit 101a asserts the signal WVALID0 output from the imaging processing unit 101a to the sub-arbitration unit 110a. The signal WVALID0 is a signal indicating that the write data is valid data. The imaging processing unit 101a asserts the signal WVALID0 and transmits the data D0 to D3 to the sub arbitration unit 110a by the signal WDATA0 within the period of the timings T22 to T26. The sub arbitration unit 110a deasserts the signal WVALID0 at timing T26. In this way, the data D0 to D3 are transmitted from the imaging processing unit 101a to the sub arbitration unit 110a.

  Within a period from timing T26 to T30, that is, within a period of four cycles, the sub arbitration unit 110a asserts the signal WVALID_SUB0 output from the sub arbitration unit 110a to the main arbitration unit 113. The signal WVALID_SUB0 is a signal indicating that the write data is valid. The sub arbitration unit 110 asserts the signal WVALID_SUB0 and transmits the data D0 to D3 to the main arbitration unit 113 by the signal WDATA_SUB0 within the period of the timings T26 to T30. Thus, the write data D0 to D3 are transmitted from the sub arbitration unit 110a to the main arbitration unit 113.

  The main arbitration unit 113 temporarily stores write data in a data buffer (not shown). Thereafter, the main arbitration unit 113 outputs the data temporarily stored in the data buffer to the memory 109 at a desired timing. Thus, the transfer of data from the imaging processing unit 101a to the memory 109 is completed.

Next, an operation for reading data from the memory 109 will be described with reference to FIG.
In a stage before the timing T20, the data read from the memory 109 is temporarily stored in the data buffer of the main arbitration unit 113. The main arbitration unit 113 asserts the signal RVALID_SUB0 output from the main arbitration unit 113 to the sub-arbitration unit 110a within the period of timing T20 to T24, that is, within the period of four cycles. The main arbitration unit 113 sequentially reads the data D0 to D3 temporarily stored in the data buffer, and sequentially transmits the read data D0 to D3 as read data to the sub arbitration unit 110a by the signal RDATA_SUB0. Further, the main arbitration unit 113 outputs information I0 indicating that the read data is data for a transfer request (read request) from the imaging processing unit 101a, that is, ID information of the imaging processing unit 101a as a signal. This is transmitted to the sub-arbiter 110a by RID_SUB0. Transmission of the information I0 by the signal RID_SUB0 is continued within the period of timing T20 to T24. At timing T23, the main arbitration unit 113 asserts the signal RLAST_SUB. The signal RLAST_SUB is a signal indicating that the final read data is output as described above. At timing T24, the main arbitration unit 113 deasserts the signal RVALID_SUB0 and the signal RLAST_SUB0. The sub arbitration unit 110a detects that the read data D0 to D3 transmitted in T20 to T24 is data for a transfer request (read request) from the imaging processing unit 101a, based on information I0 indicated by the signal RID_SUB. To do.

  Within the period of timing T24 to T28, that is, within the period of four cycles, the sub arbitration unit 110a asserts the signal RVALID0 output from the sub arbitration unit 110a to the imaging processing unit 101a. The signal RVALID0 is a signal indicating that the read data transmitted by the signal RDATA0 is valid data. The sub arbitration unit 110a sequentially outputs the read data D0 to D3 read from the memory 109 by the main arbitration unit 113 to the imaging processing unit 101a within the period of timing T20 to T24. At timing T27, the sub arbitration unit 110a asserts the signal RLAST0 output to the imaging processing unit 101a. The signal RLAST0 is a signal indicating that the final read data is transmitted as described above. At timing T28, the sub-arbiter 110a deasserts the signal RVALID0 and the signal RLAST0. Thus, the transfer of data from the memory 109 to the imaging processing unit 101a, that is, the reading of data from the memory 109 by the imaging processing unit 101a is completed.

  As described above, in this embodiment, the sub-arbiter 110 sends the transfer request from the bus master 101 to the main arbitrator 113 regardless of whether or not the main arbitrator 113 permits the transfer request from the bus master 101. Transmit sequentially. Then, the main arbitration unit 113 sequentially grants the transfer requests that are not permitted even though the transfer request is received according to the preset access priority of the bus master 101. Therefore, according to the present embodiment, it is possible to provide a memory controller that can perform good memory access.

[Modified Embodiment]
As mentioned above, although this invention was explained in full detail based on suitable embodiment, this invention is not limited to these embodiment, Various forms in the range which does not deviate from a summary are also contained in this invention.
For example, in the above-described embodiment, the case where the memory controller 108 according to the present embodiment is provided in the imaging device 150 has been described as an example, but the present invention is not limited to this. The memory controller 108 according to the present embodiment may be provided in any electronic device.
In the above embodiment, the case where the plurality of sub-arbitration units 110 and the main arbitration unit 113 are provided, that is, the two-stage memory controller 108 has been described as an example. However, the present invention is not limited to this. . A memory controller having three or more stages may be used.
In the above-described embodiment, the case where the number of bus masters 101 is seven, the number of sub arbitration units 110 is three, and the number of main arbitration units 113 is one has been described as an example. is not. The number of bus masters 101, the number of sub arbitration units 110, and the number of main arbitration units 113 can be set as appropriate.

  The present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in a computer of the system or apparatus read and execute the program This process can be realized. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

DESCRIPTION OF SYMBOLS 100 ... Image pick-up element 101a-101g ... Bus master 109 ... Memory 110a-110c ... Sub arbitration part 113 ... Main arbitration part 120 ... Integrated circuit device 150 ... Imaging device

Claims (12)

A first arbitration unit that arbitrates transfer requests to a memory from a plurality of bus masters;
A second arbitration unit that arbitrates transfer requests respectively arbitrated by a plurality of the first arbitration units;
The first arbitration unit determines whether a new transfer request from the bus master is issued regardless of whether or not the transfer request already output by the first arbitration unit to the second arbitration unit has been granted. Is output to the second arbitration unit.   The memory controller according to claim 1, wherein the first arbitration unit arbitrates the transfer request from the plurality of bus masters based on a predetermined priority.   The second arbitration unit outputs the transfer requests output from a plurality of the first arbitration units, including a plurality of transfer requests which are output from one of the first arbitration units and which are not permitted. The memory controller according to claim 1, wherein arbitration is performed based on a predetermined priority.   4. The memory controller according to claim 2, wherein the predetermined priority is a priority set in advance for each of the plurality of bus masters.   When the first arbitration unit transmits the transfer request from the bus master to the second arbitration unit, the first arbitration unit outputs a signal indicating the transfer request to the second arbitration unit, and 5. The memory controller according to claim 1, wherein a signal indicating whether the request is a transfer request from a bus master is output to the second arbitration unit. 6.   When permission for the transfer request is performed, the second arbitration unit outputs a signal indicating permission for the transfer request to the first arbitration unit, and 6. The memory controller according to claim 1, wherein a signal indicating whether the transfer request from the bus master is permitted is output to the first arbitration unit.   When writing the data from the bus master to the memory via the first arbitration unit and the second arbitration unit, the second arbitration unit prepares to receive data in the second arbitration unit. A signal indicating that the data is completed in the first arbitration unit, and a signal indicating which of the bus masters is ready to receive data from the second arbitration unit The memory controller according to any one of claims 1 to 6, wherein the memory controller is output to the first arbitration unit.   When the data written in the memory is read by the bus master via the second arbitration unit and the first arbitration unit, the second arbitration unit transfers the data to the first arbitration unit. 8. The memory according to claim 1, wherein a signal indicating to which bus master the data is to be read is output to the first arbitration unit. controller. Multiple bus masters,
A first arbitration unit that arbitrates transfer requests to the memory from the plurality of bus masters; and a second arbitration unit that arbitrates transfer requests respectively arbitrated by the plurality of first arbitration units, The arbitration unit sends a new transfer request from the bus master to the first arbitration unit regardless of whether or not the transfer request already output by the first arbitration unit to the second arbitration unit has been granted. And a memory controller that outputs to the arbitration unit. Multiple bus masters,
An image sensor that outputs an image signal to any of the plurality of bus masters;
A first arbitration unit that arbitrates transfer requests to the memory from the plurality of bus masters; and a second arbitration unit that arbitrates transfer requests respectively arbitrated by the plurality of first arbitration units; A memory controller that controls data transfer to and from the memory, wherein the first arbitration unit grants permission for a transfer request that the first arbitration unit has already output to the second arbitration unit. A memory controller that outputs a new transfer request from the bus master to the second arbitration unit, regardless of whether it has been performed;
Data from the bus master is written via the first arbitration unit and the second arbitration unit, and data is read to the bus master via the second arbitration unit and the first arbitration unit. An imaging apparatus comprising: the memory. Arbitrating a transfer request to a memory from a plurality of bus masters by a first arbitration unit;
A transfer request arbitrated by each of the plurality of first arbitration units is arbitrated by a second arbitration unit, and data transfer between the bus master and the memory is controlled according to the transfer request,
In the step of arbitrating the transfer requests from the plurality of bus masters by the first arbitration unit, the first arbitration unit uses the transfer request already output by the first arbitration unit to the second arbitration unit. A memory control method comprising: outputting a new transfer request from the bus master to the second arbitration unit regardless of whether or not permission is given. On the computer,
Arbitrating a transfer request to a memory from a plurality of bus masters by a first arbitration unit;
A transfer request arbitrated by each of the plurality of first arbitration units is arbitrated by a second arbitration unit, and a step of controlling data transfer between the bus master and the memory is executed according to the transfer request A program,
In the step of arbitrating the transfer requests from the plurality of bus masters by the first arbitration unit, the first arbitration unit uses the transfer request already output by the first arbitration unit to the second arbitration unit. Regardless of whether or not permission is given, a new transfer request from the bus master is output to the second arbitration unit.

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