JP2018067507A - Display and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display panel comprising: a substrate; a plurality of pixels each located on the substrate and having a transistor and a light emitting element; first wires located on the substrate and electrically connected to the transistors; and a pair of first connection pads covering both a first lateral face of the substrate and a second lateral face opposite to the first lateral face and electrically connected to the first wires.SOLUTION: A first lateral face and a second lateral face can have concave parts that are covered by a pair of first connection pads. Light emitting elements each have a pixel electrode and may share a counter electrode on the pixel electrode, and a display panel may have second wires that are located between adjacent pixels and electrically connected to the counter electrodes.SELECTED DRAWING: Figure 4

Description

  One embodiment of the present disclosure relates to a display device and a manufacturing method thereof.

  Typical examples of the display device include a liquid crystal display device having a display element such as a liquid crystal element or a light-emitting element in each pixel, an organic EL (Electroluminescence) display device, and the like. These display devices each have a liquid crystal element or an organic light emitting element (hereinafter also simply referred to as a light emitting element) in each of a plurality of pixels formed on a substrate. A liquid crystal element or a light-emitting element has a layer containing a liquid crystal or a light-emitting material between a pair of electrodes, and is driven by applying a voltage or supplying a current between the pair of electrodes.

  As one method for manufacturing a large display device, it is known to use a plurality of small and medium display panels such as an organic EL panel on which display elements are formed, and arrange these on a large substrate. A light-emitting device manufactured by this method is called a panel-bonded display device. For example, Patent Documents 1 to 4 disclose panel junction type display devices in which organic EL panels are arranged in a matrix on a substrate.

JP 2004-111320 A JP 2006-163325 A JP 2011-81945 A JP, 2014-157206, A

  One of the problems of the present disclosure is to provide a structure and a method for manufacturing a large display device such as a large display device on which a light emitting element is mounted at low cost. Alternatively, one of the problems of the present disclosure is to provide a structure and a method for manufacturing a large display device having a plurality of display panels and having high display quality.

  One embodiment of the present disclosure includes a substrate, a plurality of pixels located on the substrate and having a light emitting element, a first wiring located on the substrate and electrically connected to the light emitting element, and the substrate The display panel includes a first connection pad that covers the first side surface of the first connection pad and is electrically connected to the first wiring.

  The first side surface may have a recess that is covered by the first connection pad. The display panel may include a second connection pad that is electrically connected to the first wiring and covers a second side surface facing the first side surface. The first connection pad and the second connection pad can cover the first wiring. The substrate has a first side surface and a third side surface perpendicular to the second side surface, and a distance between the third side surface and the first connection pad is between the third side surface and the second connection pad. It may be different from the distance.

  The display panel further includes a second wiring that intersects the first wiring, and a third connection pad that is electrically connected to the second wiring and covers a third side surface perpendicular to the first side surface. be able to. The first wiring and the second wiring may be electrically connected to the light-emitting element through a transistor.

  One embodiment of the present disclosure includes a base substrate and a plurality of display panels positioned on the base substrate, and each of the plurality of display panels is positioned on the substrate and the plurality of light emitting elements. A pixel, a first wiring located on the substrate and electrically connected to the light-emitting element, and a first connection pad covering the first side surface of the substrate and electrically connected to the first wiring; A display device.

  The plurality of display panels may be arranged in a matrix of m rows and n columns. Here, m and n are natural numbers greater than 1. Moreover, m and n may be larger than 2, and the plurality of display panels may have the same structure.

  The base substrate has a plurality of wirings stacked on each other and a first conductive bump electrically connected to one of the plurality of wirings, and one first connection pad of the plurality of display panels is a first conductive pad. It may be electrically connected to the bump.

  In each of the plurality of display panels, the first side surface may have a recess that is covered with the first connection pad. Each of the plurality of display panels can have a second connection pad that is electrically connected to the first wiring and covers the second side surface facing the first side surface. The first connection pad and the second connection pad may cover the first wiring. The substrate has a first side surface and a third side surface perpendicular to the second side surface, and a distance between the third side surface and the first connection pad is between the third side surface and the second connection pad. It may be different from the distance.

  Each of the plurality of display panels includes a second wiring that intersects the first wiring, and a third connection pad that is electrically connected to the second wiring and covers a third side surface perpendicular to the first side surface. May further be included. The first wiring and the second wiring may be electrically connected to the light-emitting element through a transistor.

  Each of the plurality of display panels can have a third wiring between the first side surface and the pixel closest to the first side surface. In each of the plurality of display panels, the light emitting element has a pixel electrode. Alternatively, the counter electrode on the pixel electrode may be shared, and the third wiring may be electrically connected to the counter electrode.

  The first wirings of display panels adjacent to each other may be arranged to extend on different straight lines.

  The first side surface has a concave portion covered with the first connection pad, the first conductive bump is located in the concave portion, two adjacent display panels are in contact with each other, and the first conductive bump is sandwiched between them. it can.

The upper surface schematic diagram of the display apparatus of one embodiment of this indication. The cross-sectional schematic diagram of the display apparatus of one Embodiment of this indication. The upper surface schematic diagram of the display panel of the display apparatus of one embodiment of this indication. The side surface schematic diagram of the display panel of the display apparatus of one Embodiment of this indication. The upper surface schematic diagram of the base substrate of the display apparatus of one Embodiment of this indication. The cross-sectional schematic diagram of the base substrate of the display apparatus of one Embodiment of this indication. 1 is a schematic perspective view of a display device according to an embodiment of the present disclosure. The upper surface schematic diagram of the display panel of the display apparatus of one embodiment of this indication. 4A and 4B illustrate a method for manufacturing a display panel of a display device according to an embodiment of the present disclosure. 4A and 4B illustrate a method for manufacturing a display panel of a display device according to an embodiment of the present disclosure. 4A and 4B illustrate a method for manufacturing a display panel of a display device according to an embodiment of the present disclosure. 4A and 4B illustrate a method for manufacturing a display panel of a display device according to an embodiment of the present disclosure. 4A and 4B illustrate a method for manufacturing a display panel of a display device according to an embodiment of the present disclosure. 4A and 4B illustrate a method for manufacturing a display panel of a display device according to an embodiment of the present disclosure. 4A and 4B illustrate a method for manufacturing a display panel of a display device according to an embodiment of the present disclosure. 4A and 4B illustrate a method for manufacturing a display panel of a display device according to an embodiment of the present disclosure. 4A and 4B illustrate a method for manufacturing a display panel of a display device according to an embodiment of the present disclosure. 4A and 4B illustrate a method for manufacturing a display panel of a display device according to an embodiment of the present disclosure. The upper surface schematic diagram of the display panel of the display apparatus of one embodiment of this indication. The upper surface schematic diagram of the display panel of the display apparatus of one embodiment of this indication. The upper surface schematic diagram of the display panel of the display apparatus of one embodiment of this indication. The upper surface schematic diagram of the display panel of the display apparatus of one embodiment of this indication. 6 is a diagram illustrating a method for manufacturing a base substrate of a display device according to an embodiment of the present disclosure. FIG. 6 is a diagram illustrating a method for manufacturing a base substrate of a display device according to an embodiment of the present disclosure. FIG.

  Hereinafter, each embodiment of the present disclosure will be described with reference to the drawings. However, the present disclosure can be implemented in various modes without departing from the gist thereof, and is not construed as being limited to the description of the embodiments exemplified below.

  In order to clarify the description, the drawings may be schematically represented with respect to the width, thickness, shape, and the like of each part as compared to actual aspects, but are merely examples and limit the interpretation of the present disclosure. Not what you want. In the present specification and each drawing, elements having the same functions as those described with reference to the previous drawings may be denoted by the same reference numerals, and redundant description may be omitted.

  In the present specification and claims, in expressing a mode of disposing another structure on a certain structure, when simply describing “on top”, unless otherwise specified, It includes both the case where another structure is disposed immediately above and a case where another structure is disposed via another structure above a certain structure.

  In the present specification and claims, when a plurality of films are formed by processing a single film, the plurality of films may have different functions and roles. However, the plurality of films are derived from films formed as the same layer in the same process, and have the same layer structure and the same material. Therefore, these plural films are defined as existing in the same layer.

(First embodiment)
The structure of the display device 100 of this embodiment will be described with reference to FIGS. In the following description, the display device 100 is described as an active matrix organic EL display device, but the present embodiment can also be applied to a passive matrix display device. As the display element, either a liquid crystal element or a light emitting element may be used. In the case of using a light emitting element, the light emitting element may be an organic EL element or an inorganic EL element. The inorganic EL element may be an inorganic EL diode that is driven by a direct current, or a so-called genuine electroluminescence element that is driven by applying an alternating voltage.

[1. Overall structure]
FIG. 1 is a schematic top view of the display device 100, and FIG. 2 shows a schematic cross-sectional view along the chain line AA ′. As illustrated in FIG. 1, the display device 100 includes a base substrate 102 and a plurality of display panels 200 provided on the base substrate 102. In the display device 100 shown in FIG. 2, nine display panels 200 arranged in three rows and three columns are provided on the base substrate 102, but the number of display panels 200 is not limited, and the display panels 200 are provided on the base substrate 102. The display panel 200 can be provided in a matrix of m rows and n columns. Here, m and n are natural numbers larger than 1.

  A driving circuit can be provided over the base substrate 102. FIG. 1 shows an example in which two driving circuits 104 and 106 are provided. The display panels 200 are independently driven by the drive circuits 104 and / or 106. Note that the display device 100 is not necessarily provided with two driver circuits, and a single driver circuit may be provided over the base substrate 102. Alternatively, a driver circuit provided over a different substrate may be separately provided over the base substrate 102 without forming the driver circuit over the base substrate 102.

  As illustrated in FIG. 2, the display panel 200 includes a display region 206 having a plurality of pixels between a first substrate 202 and a second substrate 204 that are fixed to each other by a sealing material 210.

  The drive circuits 104 and 106 are provided on the base substrate 102 and covered with a sealing substrate 130 with a sealing material 134. The thickness of the sealing substrate 130 may be appropriately selected so that the second substrate 204 and the upper surface of the sealing substrate 130 are located in substantially the same plane.

  The drive circuits 104 and 106 are electrically connected to the display panel 200 through the wiring 108. As shown in FIG. 2, the wiring 108 can have a multilayer structure in the base substrate 102. For example, the uppermost wiring 108 a connects one of the plurality of display panels 200 to the drive circuit 104. On the other hand, the wiring 108b overlapping the wiring 108a connects the display panel 200 adjacent to the display panel 200 to which the wiring 108a is connected to the driving circuit 104. Similarly, the wiring 108c connects the display panel 200 adjacent to the display panel 200 to which the wiring 108b is connected to the driving circuit 106. The wirings 108a, 108b, and 108c are electrically connected to the corresponding display panels 200 by connection pads 208 provided on the side surfaces of the display panel 200 and conductive bumps 120 (described later) provided on the base substrate 102, respectively.

  Note that the number of layers and the stacked structure of the wiring 108 can be changed as appropriate depending on the number and arrangement of the display panels 200. One display panel 200 may be connected to both of the two drive circuits 104 and 106.

  The base substrate 102 is further provided with a plurality of wirings 110 extending to the side surface where the drive circuits 104 and 106 are not provided (FIG. 1). Like the wiring 108, the plurality of wirings 110 can have a stacked structure in the base substrate 102. For example, the wiring 110a provided in the uppermost layer of the wirings 110 illustrated in FIG. 2 can be electrically connected to the display panel 200 positioned in the second row. On the other hand, the wiring 110b positioned below the wiring 110a can be electrically connected to the display panel 200 positioned in the third row, for example. The wiring 110 is electrically connected to a connector 114 such as a flexible printed circuit board (FPC) at the end of the base substrate 102. A signal supplied from an external circuit (not shown) via the connector 114 is input to the display panel 200 through the wiring 110, and the pixels are controlled in conjunction with signals input from the drive circuits 104 and 106.

  The display device 100 can further include a wiring 112 that is electrically connected to the display panel 200. As will be described later, the wiring 112 is connected to one of the electrodes included in the pixel. The wiring 112 can also be arranged so as to extend to the side where the wiring 110 is provided, and is connected to an external circuit at the end of the base substrate 102.

[2. Display panel]
The structure of the display panel 200 will be described with reference to FIGS. 3 and 4 are schematic views of the upper surface and side surfaces of the display panel, respectively. The display panel 200 includes a plurality of pixels 214 on the first substrate 202. A region where the plurality of pixels 214 are provided corresponds to the display region 206 in FIG. The pixel 214 can be provided with a display element such as a light emitting element or a liquid crystal element which gives different colors, whereby full color display can be performed. For example, display elements that give red, green, or blue can be provided in the three pixels 214, respectively. Alternatively, a display element that gives white in all the pixels 214 may be used, and a full color display may be performed by extracting red, green, or blue for each pixel 214 using a color filter. The arrangement of the pixels 214 is not limited, and a stripe arrangement, a delta arrangement, a pen tile arrangement, or the like can be adopted. In the display device 100 shown in FIG. 3, the pixels 214 are arranged in a matrix.

  Various wirings for supplying a signal supplied via the wirings 108 and 110 to each pixel 214 are further provided on the first substrate 202. Although FIG. 3 shows an example in which three types of wirings 216, 218, and 220 are provided, the number of wirings is not limited, and four or more types of wirings may be provided. The wirings 216, 218, and 220 are electrically connected to a semiconductor element such as a transistor provided in each pixel 214, and function as, for example, a scanning line, a signal line, a current supply line, or the like.

  When this embodiment is applied to a passive matrix display device, for example, the wirings 216 and 220 of the wirings 216, 218, and 220 can be used as bit lines and word lines. In this case, the wirings 216 and 220 are connected to a pair of electrodes included in the light-emitting element without functioning as a transistor, or function as these electrodes.

  Each of the wirings 216, 218, and 220 is connected to a conductive connection pad on at least one side surface of the first substrate 202. Specifically, for example, the wiring 216 is electrically connected to the connection pad 208 on one of the side surfaces of the first substrate 202 (first side surface 222). The connection pad 208 is electrically connected to the driving circuit 104 or 106 via the wiring 108 provided on the base substrate 102. In the example illustrated in FIG. 3, the wiring 216 is connected to one of the connection pads 208 provided on the first side surface 222 and the second side surface 224 opposite to the first side surface 222. In FIG. 3, an example in which the odd-numbered wirings 216 are connected to the connection pads 208 provided on the first side surface 222 and the even-numbered wirings 216 are connected to the connection pads 208 provided on the second side surface 224. It is shown. In this case, the odd-numbered wirings 216 and the even-numbered wirings 216 may be connected to different drive circuits (104, 106). Note that connection pads 208 may be provided at both ends of all the wirings 216. Such a configuration will be described in a third embodiment.

  Similarly, the wirings 218 and 220 are also connected to the conductive connection pads 212 on the side surfaces (third side surface 226 and fourth side surface 228) perpendicular to the first side surface 222 and the second side surface 224. be able to. The connection pad 212 is electrically connected to an external circuit through the wiring 110 provided on the base substrate 102. In FIG. 3, both ends of the wirings 218 and 220 are connected to the connection pad 212. However, like the wiring 216, the display panel 200 is configured so that only one end is connected to the connection pad 212. Also good. Such a configuration will be described in a third embodiment.

  As shown in FIG. 3, when two connection pads are connected to one wiring, the positions of these connection pads may be shifted from each other. That is, the connection pad or the wiring can be configured so that the distance from the side surface parallel to the direction in which the wiring extends to the connection pad is different from each other. Specifically, for example, in the wiring 218 shown in FIG. 3, the distance from the first side surface 222 (or the second side surface 224), which is a side surface parallel to the extending direction, to the connection pad 212 may be different from each other. . Here, the wiring 218 has a bent structure, whereby the distances between the first side surface 222 and the connection pad 212 are different from each other. By arranging the connection pads 208 and 212 in this way, it is possible to prevent the corresponding wirings from being electrically connected to each other between the adjacent display panels 200 and to drive each display panel 200 independently. . The wirings 218 and 220 can have the same relationship with respect to the positional relationship between the pair of connection pads in one wiring.

  The display panel 200 can further include a wiring 230. The wiring 230 is electrically connected to one of the electrodes of the light emitting element 282 described later, for example, the counter electrode 250. At least one wiring 230 may be provided in one display panel 200, and may be provided between adjacent pixels 214. Alternatively, as shown in FIG. 3, it may be provided between any side surface of the first substrate 202 and the pixel 214 closest thereto. Like the wirings 216, 218, and 220, the wiring 230 is connected to the conductive connection pad 232 on either side of the first substrate 202, and is electrically connected to the wiring 112 provided on the base substrate 102 by the connection pad 232. Connected.

  In a region where the connection pads 208, 212, or 232 are formed, that is, on each side surface (first side surface 222, second side surface 224, third side surface 226, and fourth side surface 228) of the first substrate 202. A recess is formed. Then, as illustrated in FIG. 4, the recess is covered with the connection pads 208, 212, or 232.

  Among the pixels 214 of the display panel 200, the pixels 214 are arranged so that the distance between one side surface and the end of the pixel 214 closest to the side surface is ½ of the distance between the ends of adjacent pixels. Is preferred. More specifically, for example, the distance L1 between the end of the pixel 214 closest to the second side 224 and the second side 224 is between the ends of the pixels 214 adjacent in the direction orthogonal to the second side 224. The distance L2 is preferably ½ of the distance L2 (see FIG. 3). Similarly, the distance L3 between the end of the pixel 214 closest to the third side 226 and the third side 226 is 1 of the distance L4 between the ends of adjacent pixels in the direction orthogonal to the third side 226. / 2 is preferable. Thereby, the pixels 214 can be arranged at equal intervals over the plurality of display panels 200. As a result, a region between adjacent display panels 200 is not conspicuous and is difficult to be recognized by the user, and a high-quality image can be provided.

[3. Base substrate]
The structure of the base substrate 102 will be described with reference to FIGS. FIG. 5 is a schematic top view of the base substrate 102. For the sake of clarity, the wirings 108 and 110 are not shown in the region where the display panel 200 is installed. 6 is a schematic cross-sectional view taken along the chain line BB ′ of FIG.

  As shown in FIG. 5, the base substrate 102 overlaps the side surfaces (first side surface 222, second side surface 224, third side surface 226, and fourth side surface 228) of the display panel 200 installed thereon. A plurality of conductive bumps 120 are provided at the positions. The conductive bumps 120 can be arranged in a matrix. Each conductive bump 120 is connected to one of the connection pads 208, 212, and 232 of the corresponding one display panel 200. Therefore, the number of conductive bumps 120 connected to one display panel 200 is the same as the number of connection pads 208, 212, 232 provided on the wirings 216, 218, 220, 230. For example, if the display panel 200 has p wirings 216, q wirings 218, r wirings 220, and s wirings 230, each having one connection pad 208, 212, or 232, p + q + r + s wirings. The conductive bumps 120 are provided so that the conductive bumps 120 are connected to one display panel 200.

  The arrangement of the plurality of conductive bumps 120 connected to one display panel 200 can be the same. Thereby, the structure of the some display panel 200 can also be made the same. In this case, for example, when the display panel 200 is arranged in a matrix of m rows and n columns, the display panel 200 located in the first row, the m row, the first column, or the n column (hereinafter referred to as a peripheral panel). , As well as other display panels 200 (located in the 2nd to m-1th rows or the 2nd to n-1th columns) have the same structure. it can.

  As shown in FIG. 6, the base substrate 102 can include a so-called multilayer wiring board in which wirings are provided in multiple layers. Specifically, the base substrate 102 includes a plurality of insulating members 140 (140a, 140b, 140c, 140d, 140e, 140f, 140g) and a plurality of wiring layers (110a, 110b, 110c, 108a, 108b) sandwiched between them. ) Etc. The number and structure of the insulating members 140 and the wiring layers can be changed as appropriate depending on the number and arrangement pattern of the display panels 200.

The wiring 110 illustrated in FIG. 6 has a three-layer structure (110a, 110b, 110c), and is connected to the display panel 200 located in a different row. Similarly, the wiring 108 has a three-layer structure (108a, 108b) including one layer (not shown), and is connected to the display panel 200 located in a different column. Each of the wirings 108 and 110 is connected to the corresponding conductive bump 120 through a via 142 provided in the insulating member 140. The conductive bumps 120 are connected to corresponding wirings 216, 218, 220, and 230 via connection pads 208, 212, and 232 provided on the side surface of the display panel 200.
[4. Connection]

  FIG. 7 schematically shows a connection mode between the display panel 200 and the base substrate 102. Here, the second substrate 204 and the like of the display panel 200 are not illustrated. As shown in FIG. 7, the display panel 200 is disposed on the base substrate 102 so that the side surfaces of the conductive bumps 120 on the base substrate 102 are surrounded by the connection pads 208. The wiring of the display panel 200 (for example, the wiring 216 shown in FIG. 7) is connected to the wiring 108 in the base substrate 102 through the connection pad 208, the conductive bump 120, and the via 142, and is connected to the driving circuit 104, 106 or an external circuit. Various signals are supplied to each display panel 200. Thereby, each display panel 200 can be driven independently.

  As described above, a concave portion is provided on the side surface of the first substrate 202, and the connection pads 208, 212, and 232 are provided so as to cover the concave portion. Therefore, the connection pad also has a recess, and the display panel 200 is arranged so that the conductive bump 120 is located in the recess. Therefore, as shown in FIG. 2, the display panels 200 can be arranged so that the side surfaces of the adjacent display panels 200 (for example, the side surfaces of the first substrate 202) are in contact with each other. For this reason, it is not necessary to provide a gap between the adjacent display panels 200, and the joint between the display panels 200 can be made inconspicuous. As a result, a high quality image can be provided.

  Further, as described above, the display device 100 can be manufactured using the display panel 200 having the same structure. Accordingly, a large display panel can be formed at low cost, and the display device 100 having an arbitrary size can be provided only by changing the size of the base substrate 102 and the stacked structure of wirings provided there. Is possible.

(Second Embodiment)
In this embodiment, a method for manufacturing the display panel 200 will be described with reference to FIGS. 8 is a schematic top view of the pixel 214, and FIGS. 9 to 15 correspond to cross sections taken along chain lines EE ′ and FF ′ shown in FIG. 16 to 18 are schematic top views of the display panel 200. FIG. Description of the configuration described in the first embodiment may be omitted.

  As shown in FIG. 8, each pixel 214 includes a semiconductor element such as a transistor or a light emitting element. FIG. 8 illustrates an example in which two transistors 242 and 244 and a light-emitting element 282 are provided in one pixel 214. However, the number of transistors in each pixel 214 is not limited, and other semiconductor elements such as a capacitor element are provided. It may be provided.

  As illustrated in FIG. 8, the transistor 242 includes a semiconductor film 254. Part of the wiring 216 overlaps with the semiconductor film 254 and forms part of the gate electrode of the transistor 242. In other words, the wiring 216 is electrically connected to the gate electrode of the transistor 242. For example, the wiring 216 can supply a scan signal to the transistor 242. The wiring 218 forms part of the source / drain electrode of the transistor 242 and is electrically connected to the transistor 242. For example, the wiring 218 can supply a video signal to the transistor 242. The wiring 220 also forms part of the source / drain electrode of the transistor 244 and is electrically connected to the transistor 244. The wiring 220 can supply current to the pixel electrode 246 of the light-emitting element 282 through the transistor 244, for example.

  The light-emitting element 282 includes a pixel electrode 246 and a counter electrode 250 provided thereon, and an EL layer 280 described later is provided between the pixel electrode 246 and the counter electrode 250. As shown in FIG. 8, the counter electrode 250 is formed over a plurality of pixels 214. That is, the counter electrode 250 is shared by the plurality of pixels 214. Hereinafter, a method for manufacturing the display panel 200 will be specifically described.

  First, the base film 252 is formed over the first substrate 202 (FIG. 9A). The first substrate 202 has a function of supporting semiconductor elements such as the transistors 242 and 244 and the light-emitting element 282. Therefore, the first substrate 202 may be made of a material having heat resistance to process temperatures of various elements formed thereon and chemical stability to chemicals used in the process. Specifically, the first substrate 202 can include glass, quartz, plastic, ceramic, or the like.

  The base film 252 is one of arbitrary structures, and has a function of preventing impurities such as alkali metal from diffusing from the first substrate 202 to the transistors 242 and 244 and the like. The base film 252 can include an inorganic insulator such as silicon nitride, silicon oxide, silicon nitride oxide, or silicon oxynitride. The base film 252 can be formed to have a single layer or a stacked structure by applying a chemical vapor deposition method (CVD method), a sputtering method, or the like.

  Next, a semiconductor film 254 is formed over the base film 252. The semiconductor film 254 may include, for example, a group 14 element such as silicon or an oxide semiconductor. As the oxide semiconductor, a Group 13 element or a Group 14 element can be included. For example, a mixed oxide (IGO) of indium and gallium or a mixed oxide (IGZO) including indium, gallium, and zinc can be given. . In the case where the semiconductor film 254 contains silicon, the semiconductor film 254 may be formed by a CVD method using silane gas or the like as a raw material. The resulting amorphous silicon may be crystallized by heat treatment or irradiation with light such as a laser. In the case where the semiconductor film 254 includes an oxide semiconductor, the semiconductor film 254 can be formed by a sputtering method or the like.

  Next, a gate insulating film 256 is formed so as to cover the semiconductor film 254. The gate insulating film 256 may have a single-layer structure or a stacked structure, and can be formed by a method similar to that of the base film 252. Alternatively, an inorganic compound having a high dielectric constant such as hafnium oxide or hafnium silicate may be used.

  Subsequently, a wiring 216 is formed over the gate insulating film 256 by a sputtering method or a CVD method. At that time, part of the wiring 216 over which the semiconductor film 254 overlaps functions as the gate electrode 258 (FIG. 9B). At this time, the gate electrode 260 of the transistor 244 is also formed at the same time. Therefore, the wiring 216 and the gate electrode 260 exist in the same layer. The wiring 216 and the gate electrode 260 can be formed using a metal such as titanium, aluminum, copper, molybdenum, tungsten, or tantalum or an alloy thereof so as to have a single layer or a stacked structure. For example, a structure in which a metal having a relatively high melting point such as titanium, tungsten, or molybdenum and a metal having high conductivity such as aluminum or copper is sandwiched can be employed.

  Next, an interlayer film 262 is formed over the wiring 216 (gate electrode 258) (FIG. 9B). The interlayer film 262 may have a single-layer structure or a stacked structure, and can be formed by a method similar to that of the base film 252.

  Next, the interlayer film 262 and the gate insulating film 256 are etched to form openings that reach the semiconductor film 254 (FIG. 10A). The opening can be formed, for example, by performing plasma etching in a gas containing fluorine-containing hydrocarbon. At this time, the base film 252, the gate insulating film 256, and the interlayer film 262 in the region where the connection pads 208, 212, or 232 are formed can be removed (see the section F-F ′).

  Subsequently, a metal film is formed so as to cover the opening, and etching is performed to form the wiring 218 (FIG. 10B). Part of the wiring 218 overlapping with the semiconductor film 254 functions as a source / drain electrode of the transistor 242. At this time, source / drain electrodes overlapping the wiring 220 and the semiconductor film of the transistor 244 (see FIG. 8) and the source / drain electrodes 264 of the transistor 242 are also formed. The metal film can have a structure similar to that of the wiring 216 and can be formed using a method similar to the formation of the wiring 216. Through the above steps, the transistors 242 and 244 are formed. Note that in this disclosure, the structure of the transistors 242 and 244 is not limited, and may have either a top-gate structure or a bottom-gate structure. Further, there is no restriction on the vertical relationship between the semiconductor film and the source / drain electrodes.

  Next, a planarization film 266 is formed so as to cover the wirings 218 and 220 and the source / drain electrodes 264 (FIG. 11A). The planarization film 266 has a function of absorbing unevenness and inclination caused by the transistors 242 and 244 and other semiconductor elements to give a flat surface. The planarization film 266 can be formed using an organic insulator. Examples of organic insulators include polymer materials such as epoxy resins, acrylic resins, polyimides, polyamides, polyesters, polycarbonates, and polysiloxanes. Wet film formation methods such as spin coating, dip coating, ink jet, and printing Can be formed.

  Next, the planarization film 266 is etched to form an opening 248 that reaches one of the source / drain electrodes of the transistor 244 (see FIG. 8). At this time, the planarization film 266 in a region where the connection pads 208, 212, or 232 are formed may be removed (FIG. 11B). After that, a pixel electrode 246 is formed over the planarization film 266 by a sputtering method, a vapor deposition method, or the like so as to cover the opening 248 (FIGS. 8 and 12A). At this time, the wiring 230 is formed at the same time. The pixel electrode 246 can contain a light-transmitting conductive oxide, a metal, or the like. In the case where light obtained from the light-emitting element is extracted in a direction opposite to that of the first substrate 202, a metal such as aluminum or silver or an alloy thereof can be used for the pixel electrode 246. In this case, a laminated structure of the above metal or alloy and a light-transmitting conductive oxide, for example, a laminated structure in which a metal is sandwiched between conductive oxides (conductive oxide / silver / conductive oxide) is employed. May be. As the conductive oxide, indium-tin oxide (ITO) or indium-zinc oxide (IZO) can be used. The wiring 230 may have the same structure as the pixel electrode 246 or may be formed using only a metal included in the pixel electrode 246.

  Subsequently, a partition 268 is formed so as to cover an end portion of the pixel electrode 246 (FIG. 12B). The partition wall 268 can absorb a step due to the pixel electrode 246 and the like, and can electrically insulate the pixel electrodes 246 of the adjacent pixels 214 from each other. A partition 268 is an insulating film and can be formed by a wet film formation method using a material that can be used for the planarization film 266 such as an epoxy resin or an acrylic resin.

  Next, a through hole 270 is formed in the first substrate 202 in a region where the connection pads 208, 212, and 232 are formed (FIG. 13A). The through hole 270 may be formed by a physical method such as sandblasting or laser processing, dry etching such as reactive ion etching, or wet etching using hydrofluoric acid. Alternatively, the through hole 270 may be formed by forming a recess in the first substrate 202 using these methods, and then polishing the bottom surface of the first substrate 202. The shape of the through hole 270 is not limited, and the shape on the upper surface of the first substrate 202 may be any of a circle, an ellipse, and a polygon. In addition, the inner wall of the through hole 270 does not always need to be perpendicular to the upper surface of the first substrate 202, and the area of the through hole 270 in the plane parallel to the upper surface of the first substrate 202 is not necessarily constant. Good. A schematic top view of the display panel 200 at this stage is shown in FIG.

  Next, a conductive layer 272 is formed inside and around the through hole 270 (FIG. 13B). The conductive layer 272 can be formed by, for example, an evaporation method or a sputtering method. For the conductive layer 272, titanium, chromium, aluminum, copper, an alloy thereof, or the like can be used. Note that before the conductive layer 272 is formed, a region where the conductive layer 272 is formed may be coated with an insulating film containing, for example, silicon oxide. Further, as an arbitrary configuration, after the conductive layer 272 is formed, a conductive layer may be further formed by an evaporation method or the like. In this case, for example, a metal such as copper, silver, or gold can be used for the conductive layer.

  Next, a region where the connection pads 208, 212, or 232 are formed, that is, the inside and the periphery of the through hole 270 are covered with a mask. For example, a photosensitive film resist is formed on both surfaces of the first substrate 202, and the resist in and around the through hole 270 is removed by photolithography. In this state, power is supplied to the conductive layer 272 to perform electrolytic plating. Thus, connection pads 208, 212, and 232 are formed on the surface of the conductive layer 272 (FIG. 14A). The connection pads 208, 212, and 232 are formed so as to cover a part of the wirings 216, 218, 220, and 230. The connection pads 208, 212, and 232 can include, for example, copper, silver, gold, or the like. A schematic top view of the display panel 200 at this stage is shown in FIG. Although not shown, the electrolytic plating may be performed so that the connection pads 208, 212, and 232 fill the inside of the through hole 270.

  Next, a light emitting element 282 is formed. Specifically, an EL layer 280 is formed over the pixel electrode 246 and the partition 268 (FIG. 14B). In FIG. 14B, although the EL layer 280 is drawn as a single layer, the structure of the EL layer 280 is not limited. The EL layer 280 may be formed of a plurality of layers. For example, the EL layer 280 can be formed by appropriately combining a carrier injection layer, a carrier transport layer, a light emitting layer, a carrier blocking layer, an exciton blocking layer, and the like. The structure of the EL layer 280 may be different between adjacent pixels 214. For example, the EL layer 280 may be formed so that the light emitting layers are different between adjacent pixels 214 and the other layers have the same structure. Conversely, the same EL layer 280 may be used in all the pixels 214. The EL layer 280 can be formed by the above-described inkjet method, spin coating method, vapor deposition method, or the like. Note that a region where the EL layer 280 is not provided can be formed by covering with a metal mask.

  Subsequently, the counter electrode 250 is formed over the EL layer 280 (FIG. 14B). Thereby, the light emitting element 282 is formed. The counter electrode 250 is formed so that a part thereof is connected to the wiring 230. For the counter electrode 250, for example, a metal such as magnesium, silver, or aluminum, or an alloy thereof can be used. Alternatively, a conductive oxide such as ITO or IZO may be used. Alternatively, a layer containing the metal and a layer having a conductive oxide may be stacked. The counter electrode 250 can be formed by vapor deposition or sputtering. A region where the pixel electrode 246 and the EL layer 280 are in direct contact is a light emitting region of each pixel 214.

  Next, the second substrate 204 is bonded to the first substrate 202 with the sealant 210, and the light-emitting element 282 is sealed (FIG. 15A). Sealing may be performed in an atmosphere of an inert gas such as nitrogen. As the sealing material 210, a thermosetting resin or a photocurable resin can be used. The second substrate 204 can include materials that can be used in the first substrate 202. When sealing, a desiccant may be sealed between the first substrate 202 and the second substrate 204.

  Next, the first substrate 202 is cut along the through hole 270 (see the chain line in FIG. 17). Cutting may be performed using laser irradiation or a cutter. As a result, recesses are formed on the side surfaces of the first substrate 202, and connection pads 208, 212, and 232 that cover these are formed (FIG. 15B). A top view at this stage is shown in FIG.

  Through the above process, the display panel 200 can be manufactured. By disposing the display panel 200 on the base substrate 102 so as to dispose the conductive bumps 120 in the recesses of the connection pads 208, 212, and 232 (FIG. 7), the display device 100 can be manufactured.

(Third embodiment)
In this embodiment, a display panel having a structure different from that of the display panel 200 will be described with reference to FIGS. Description of the configurations described in the first and second embodiments may be omitted.

  The display panel 300 shown in FIG. 19 is different from the display panel 200 in that the connection pads 208 connected to all the wirings 216 are located on one side surface (first side surface 222 in FIG. 19). For example, when only one driving circuit is provided on the base substrate 102, the structure of the wiring provided in the base substrate 102 can be simplified by adopting such a structure.

  A display panel 302 shown in FIG. 20 is different from the display panel 300 in that a pair of connection pads 208 connected to one wiring 216 are displaced from each other. Specifically, in each wiring 216, the connection pad extends from the third side surface 226 (or the fourth side surface 228) that is a side surface parallel to the direction in which the wiring 216 extends (the direction perpendicular to the first side surface 222). The distances up to 208 are different from each other. Here, the wiring 216 has a bent structure. By arranging the connection pads 208 in this way, it is possible to prevent the wiring 216 from being electrically connected between the adjacent display panels 200.

  A display device 304 shown in FIG. 21 is different from the display panel 302 in that a pair of connection pads 212 connected to each of the wirings 218 and 220 coincide with each other. Specifically, in each of the wirings 218 and 220, the distance from the side surface (for example, the first side surface 222 or the second side surface 224) parallel to the direction in which these wirings extend to the connection pad 212 is the same. Although not shown, the connection pad 208 may have the same configuration.

  In this case, as shown in FIG. 22, by arranging a plurality of display panels 304 so that the adjacent display panels 304 are displaced from each other, it is possible to prevent connection of corresponding wirings between the adjacent display panels 304. it can. More specifically, the display panel 304 is arranged so that the wirings (for example, the wirings 218) of the display panels 304 adjacent to each other are positioned on different straight lines. The distance L5 between two straight lines formed by the corresponding wirings 218 of the display panels 304 adjacent to each other can be made smaller than the pitch of the pixels 214, and may be, for example, ½ of the pitch.

(Fourth embodiment)
In this embodiment, a method for manufacturing the base substrate 102 illustrated in FIGS. 5 and 6 will be described with reference to FIGS. 23 and 24 correspond to the cross section of FIG.

  First, the first layer wiring 110c is formed over the insulating member 140a (FIG. 23A). The insulating member 140a can include a material similar to that of the first substrate 202. When a polymer material is included, the polymer material may be selected from epoxy resin, polycarbonate, polyimide, phenol resin, and the like. Further, a reinforcing material such as glass fiber may be included in these polymer materials. Note that the insulating member 140a may be formed over a glass substrate, and then the wiring 110c may be formed. The wiring 110c can include a metal such as gold, silver, copper, and aluminum, or an alloy including these, and is formed by an electrolytic plating method, a sputtering method, a CVD method, a printing method, an inkjet method, a lamination method, or the like. Can do. When an inkjet method or a printing method is used, a metal paste in which the metal fine particles and the resin are mixed can be used.

  After that, the insulating member 140b is formed using the above-described polymer material (FIG. 23B). The insulating member 140b can be formed using a printing method, an inkjet method, a laminating method, a spin coating method, a dip coating method, or the like.

  Subsequently, similarly to the formation of the wiring 110c and the insulating member 140b, the wiring 108b, the insulating member 140c, and the like are sequentially formed (FIG. 23C).

  Next, the insulating member 140 is subjected to laser processing, dry etching such as reactive ion etching, or wet etching to form an opening 144 reaching each wiring layer (FIG. 24A).

  Subsequently, a via 142 is formed in the opening 144. The via 142 can be formed by an electrolytic plating method, and can include copper, silver, gold, aluminum, or an alloy thereof. The via 142 is preferably formed also on the upper surface of the uppermost insulating member 140g.

  Next, a metal paste is applied onto the via 142 using, for example, a printing method, heated and cured, and the conductive bump 120 is formed (FIG. 6).

  Through the above steps, the base substrate 102 can be manufactured. Thereafter, the display device 100 can be manufactured by arranging the required number of display panels 200 on the base substrate 102.

  Note that the driver circuits 104 and 106 formed over the base substrate 102 can be performed before the via 142 is formed or after the conductive bump 120 is formed, but a semiconductor film formed by metal dislocation from the conductive bump 120 or the via 142 is used. In order to prevent contamination, it is preferable to form the drive circuits 104 and 106 before the via 142 is formed. The driver circuits 104 and 106 include various semiconductor elements such as transistors, which can be formed by using a method for manufacturing the display panel 200. Alternatively, as described above, the drive circuits 104 and 106 may be formed on different substrates and fixed to the uppermost insulating member 140g.

  The embodiments described above as the embodiments of the present disclosure can be implemented in appropriate combination as long as they do not contradict each other. In addition, components that are appropriately added, deleted, or changed in design by those skilled in the art based on each embodiment are also included in the scope of the present disclosure as long as they include the gist of the present disclosure.

  Of course, other operational effects that are different from the operational effects provided by each of the above-described embodiments are obvious from the description of the present specification or can be easily predicted by those skilled in the art. It is understood that this disclosure provides.

  100: display device, 102: base substrate, 104: drive circuit, 106: drive circuit, 108: wiring, 108a: wiring, 108b: wiring, 108c: wiring, 110: wiring, 110a: wiring, 110b: wiring, 110c: Wiring: 112: wiring, 114: connector, 120: conductive bump, 130: sealing substrate, 134: sealing material, 140: insulating member, 140a: insulating member, 140b: insulating member, 140c: insulating member, 140d: insulating 140e: insulating member, 140f: insulating member, 140g: insulating member, 142: via, 144: opening, 200: display panel, 202: first substrate, 204: second substrate, 206: display region, 208: connection pad, 210: sealing material, 212: connection pad, 214: pixel, 216: wiring, 218: wiring, 220: wiring, 22 : First side, 224: second side, 226: third side, 228: fourth side, 230: wiring, 232: connection pad, 242: transistor, 244: transistor, 246: pixel electrode, 248 : Opening, 250: counter electrode, 252: base film, 254: semiconductor film, 256: gate insulating film, 258: gate electrode, 260: gate electrode, 262: interlayer film, 264: drain electrode, 266: flattening film 268: Partition, 270: Through hole, 272: Conductive layer, 280: EL layer, 282: Light emitting element, 300: Display panel, 302: Display panel, 304: Display panel

Claims (20)

A substrate,
A plurality of pixels located on the substrate and having a light emitting element;
A first wiring located on the substrate and electrically connected to the light emitting element;
A display panel having a first connection pad that covers a first side surface of the substrate and is electrically connected to the first wiring.   The display panel according to claim 1, wherein the first side surface has a recess that is covered with the first connection pad.   The display panel according to claim 1, wherein the first connection pad covers the first wiring.   The display panel according to claim 1, further comprising: a second connection pad that is electrically connected to the first wiring and covers a second side surface facing the first side surface. The substrate has a third side surface perpendicular to the first side surface and the second side surface;
The display panel according to claim 4, wherein a distance between the third side surface and the first connection pad is different from a distance between the third side surface and the second connection pad. A second wiring crossing the first wiring;
The display panel according to claim 1, further comprising a third connection pad that is electrically connected to the second wiring and covers a third side surface perpendicular to the first side surface.   The display panel according to claim 6, wherein the first wiring and the second wiring are electrically connected to the light emitting element through a transistor. A base substrate;
A plurality of display panels located on the base substrate;
Each of the plurality of display panels is
A substrate,
A plurality of pixels located on the substrate and having a light emitting element;
A first wiring located on the substrate and electrically connected to the light emitting element;
A display device having a first connection pad that covers a first side surface of the substrate and is electrically connected to the first wiring. The plurality of display panels are arranged in a matrix of m rows and n columns,
The display device according to claim 8, wherein m and n are natural numbers greater than one. M and n are greater than 2,
The display device according to claim 9, wherein the plurality of display panels have the same structure. The base substrate includes a plurality of wirings stacked on each other,
A first conductive bump electrically connected to one of the plurality of wirings;
The display device according to claim 9, wherein one first connection pad of the plurality of display panels is electrically connected to the first conductive bump.   9. The display device according to claim 8, wherein in each of the plurality of display panels, the first side surface has a concave portion covered with the first connection pad.   9. The display device according to claim 8, wherein each of the plurality of display panels includes a second connection pad that is electrically connected to the first wiring and covers a second side surface facing the first side surface. .   The display device according to claim 13, wherein in each of the plurality of display panels, the first connection pad and the second connection pad cover the first wiring. In each of the plurality of display panels,
The substrate has a third side surface perpendicular to the first side surface and the second side surface;
The display device according to claim 14, wherein a distance between the third side surface and the first connection pad is different from a distance between the third side surface and the second connection pad. Each of the plurality of display panels is
A second wiring crossing the first wiring;
The display device according to claim 8, further comprising a third connection pad that is electrically connected to the second wiring and covers a third side surface perpendicular to the first side surface. Each of the plurality of display panels has a third wiring between the first side surface and a pixel closest to the first side surface,
In each of the plurality of display panels,
The light emitting element has a pixel electrode, and shares a counter electrode on the pixel electrode;
The display device according to claim 8, wherein the third wiring is electrically connected to the counter electrode.   The display device according to claim 8, wherein the first wirings of display panels adjacent to each other are arranged to extend on different straight lines. The first side surface has a recess covered by the first connection pad,
The first conductive bump is located in the recess,
The display device according to claim 11, wherein two adjacent display panels are in contact with each other and sandwich the first conductive bump.   The display device according to claim 16, wherein the first wiring and the second wiring are electrically connected to the light emitting element through a transistor.

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