JP2018052321A - Interlocking data verification device and interlocking data-design verification system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide methods to verify whether a connection diagram is perfect or not after modification in a case the modification is applied through manual works to the connection diagram which is created by an interlocking data generation device.SOLUTION: A final connection diagram acquisition unit 51 of an interlocking data verification device 50 acquires a final connection diagram, extracts expressed contents of the diagram and informs a first verification unit 61 and a second verification unit 62 of the contents. The first verification unit 61 verifies that the interlocking data have conditions coincident with those specified by the interlocking diagram. The second verification unit 62 verifies rationality of the interlocking data.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an interlocking data verification device and an interlocking data design verification system for verifying that interlocking data used in an interlocking device that controls a traffic light or a switch is correctly created.

  In a railway signal system, an interlocking device is installed at a station serving as a base where a plurality of each field device such as a traffic light or a switch is installed to control each field device. The interlocking device changes the turning machine in a predetermined direction by the setting operation of the route, locks the turning machine, and permits traveling by displaying a progress indicator on the traffic light for the train. In addition, the train running status is grasped by the track circuit, the traffic lights are stopped and displayed in accordance with the train running, and the locks of the switchovers are unlocked. Furthermore, it has a function of giving a certain chain relationship between the devices so as not to hinder the course.

  An interlocking chart is used as a condition table indicating these functions (operating conditions). The interlocking chart is composed of a wiring schematic diagram indicating the alignment, facility installation location, and the like, and an interlocking table indicating the control conditions of the interlocking device. Generally, the interlocking device realizes a predetermined function by interlocking data created based on the interlocking chart.

  As one form of interlocking data, a method using a connection diagram is known, and a method of automatically creating a connection diagram from an interlocking diagram is also known (see, for example, Patent Document 1).

The connection diagram automatically created based on the linkage diagram covers the basic parts, but in order to obtain a connection diagram that is actually used, for example, the designer needs to make changes for the following reasons. There is.
(1) When a mechanical relay is used for an input / output portion with each device, it is necessary to provide an auxiliary relay because the relay contacts are insufficient. In this case, the designer adds a circuit for operating the auxiliary relay.
(2) In order to check that the operation of the auxiliary relay is correct, it is necessary to add a contact of the auxiliary relay to a predetermined circuit. For example, when the auxiliary relay of the signal control relay operates improperly, the designer adds a contact of the auxiliary relay to the display lock condition of the approach lock circuit so that the lock cannot be unlocked.
(3) In addition, the original relay contact is replaced with an auxiliary relay contact according to certain rules.

JP2013-001224A

  By the way, it is considered that the connection diagram automatically created as shown in Patent Document 1 operates as shown in the interlocking diagram if there is no error in the generation logic. However, the connection diagram that the designer has worked on may cause human error, and there is a possibility that the operation may not be performed in accordance with the interlocking chart. That is, a technique for verifying that there is no error in the interlocking data such as a connection diagram by some method is required.

  This invention is made | formed in view of such a condition, Comprising: It is providing the technique which solves the said subject.

The present invention is an interlocking data verification device for verifying interlocking data created based on an interlocking chart in which the operating conditions of the interlocking device in a railway signal system are described, and a name for extracting description contents from the interlocking data The extraction unit, the conversion table creation unit that converts the extracted description contents into a table-type linked conversion table, and the linked chart that is the basis of the linked data can be compared with the linked conversion table. And an output unit for outputting to.
Moreover, you may provide the comparison verification part which compares the said interlocking chart and the said interlocking conversion table, and discriminate | determines a difference.
Moreover, you may provide the condition collation part which performs verification by collation of the self-check condition about the said interlocking | linkage data.
Moreover, you may provide the excessive condition verification part which judges whether the excessive condition unrelated to the conditions described in the said interlocking chart is inserted in the said interlocking | linkage data.
The linkage data may be described by a connection diagram or a logical expression.
A linked data design verification system of the present invention includes the linked data verification apparatus described above and a linked data generation apparatus that creates the linked data based on the linked chart.

  ADVANTAGE OF THE INVENTION According to this invention, the technique which verifies the interlocking data produced based on the interlocking chart in which the operating condition of the interlocking device was described can be provided.

It is a block diagram which shows the outline | summary of the interlocking data design verification system based on embodiment. It is a chart figure explaining the outline of the processing by the interlocking data design verification system concerning an embodiment. It is a figure which shows the example of a connection diagram based on embodiment, the example of a name extraction definition, and the produced | generated interlocking conversion table. It is a figure which shows the example of a connection diagram based on embodiment, the example of a conversion definition, and the interlocking conversion table added. It is a figure which shows the interlocking chart based on embodiment, the example of a connection diagram, the example of an incorrect connection diagram in the case of correction, and the interlocking conversion table produced | generated based on the incorrect connection diagram. It is a figure which shows the example of a connection diagram based on embodiment, and the example of collation definition. It is a figure which shows the example of a connection diagram based on embodiment. It is a figure which shows the example of a connection diagram and logical expression based on embodiment.

  Next, modes for carrying out the present invention (hereinafter, simply referred to as “embodiments”) will be specifically described with reference to the drawings.

  FIG. 1 is a block diagram showing an outline of the linked data design verification system 10. FIG. 2 is a chart for explaining an outline of processing by the interlocking data design verification system 10.

  The linked data design verification system 10 includes a linked data generation device 30 and a linked data verification device 50. The interlocking data generation device 30 automatically creates a connection diagram A2 based on the interlocking chart A1. The connection diagram A2 is an assembly of a plurality of connection diagrams, and each connection diagram is given a circuit name such as “lever reaction circuit” or “signal control circuit”.

  As described above, an operator such as a designer may process the connection diagram A2 created by the interlocking data generation device 30. Therefore, when the operator such as the designer performs processing on the connection diagram A2 created by the connection data generation device 30, the connection data verification device 50 generates a connection diagram after processing (final connection diagram A3). Verify whether it is appropriate.

  Here, (1) verification that the interlocking data has the conditions as indicated in the interlocking chart (Verification 1_S10) and (2) verification to verify the rationality of the interlocking data (Verification 2_S20) can be executed. It has become.

  In order to execute these verifications, the interlocking data verification device 50 includes a final connection diagram acquisition unit 51, an output unit 52, a first verification unit 61, and a second verification unit 62. The final connection diagram acquisition unit 51 acquires the final connection diagram A3, extracts the description content, and notifies the first verification unit 61 and the second verification unit 62 of the description. For example, CAD data or paper-based data is used as the final connection diagram A3.

Next, the processing of the first verification unit 61 will be specifically described.
(1) About verification 1_S10 In verification 1_S10, tabular data (interlocking conversion table A4) is created using the final connection diagram A3 for operating the interlocking device and various definitions created in advance. By comparing the interlocking conversion table A4 and the interlocking chart, it is verified that the necessary conditions are included in the final connection diagram A3 without excess or deficiency.

  The first verification unit 61 includes a conversion table creation unit 63, a name extraction unit 64, and a comparison verification unit 66.

Verification (A): Creation of interlocking conversion table A4 As a first step, the name extraction unit 64 extracts basic names such as “route” and “turnover” provided at the station to be verified. To do. The conversion table creation unit 63 creates the basic part of the linked conversion table A4 based on the extraction result. The name extraction unit 64 has a function of extracting a name and a condition extraction and conversion function described later.

As an example of the “route” extraction method, a method using a signal control circuit will be described.
One signal control circuit is created for one route, and the operation of the coil that constitutes the circuit causes the traffic signal that permits the train to travel along that route, and the stop indication when it falls. Become. In the coil name, “HR”, which is a name for identification (hereinafter, “identification name”), is combined with a “course” name. For example, the coil name of the signal control circuit for the route “1RA” is “1RAHR”. Therefore, the route name can be extracted by removing the identification name “HR” from the coil name of the signal control circuit. By preparing a name extraction definition D1 in which a circuit name to be extracted, an identification name, and a type are described, a linked conversion table A4 can be generated based on the connection diagram (final connection diagram A3) and the name extraction definition D1.

  FIG. 3 shows an example of a connection diagram (final connection diagram A3), an example of a name extraction definition D1, and a generated interlocking conversion table A4. In the connection diagram of FIG. 3A, two circuits of 1RAHR and 1RBHR are described as examples of the signal control circuit. FIG. 3B shows an example of the name extraction definition D1 provided in the name extraction unit 64. The name extraction definition D1 describes “signal control circuit” as a circuit name to be extracted, “HR” as an identification name, and “course” as a type. In the linked conversion table A4 in FIG. 3C, only the column title of the first row is prepared as a template at the start of table creation, and rows are added by the processing described below.

  The name extraction unit 64 searches the connection diagram for the circuit name “signal control circuit” described in the name extraction definition D1, and identifies the coil name “1RAHR”. The name extraction unit 64 extracts the name “1RA” obtained by removing the identification name “HR” described in the name extraction definition D1 from the coil name. The conversion table creation unit 63 writes this name “1RA” in the name column of the interlocking conversion table A4. In addition, the type “course” described in the name extraction definition D1 is described in the type column of the interlock conversion table A4.

  As shown in FIG. 3A, since the coil name “1RBHR” is also present in the signal control circuit, by repeating the same processing, “1RB” in the name column and “ "Course" is written. By repeating the above processing, an interlocking conversion table A4 as shown in FIG. 3C is generated.

  The extraction of the route name is not limited to the “signal control circuit”, and other circuits such as a “lever reaction circuit” can be used, and can be dealt with by rewriting the name extraction definition D1. Similarly, the name extraction definition D1 may be created so as to use the “tip lock circuit” or the like for the name of the tipping machine, and the name extraction definition D1 is appropriately changed for other types as well. Extraction is possible.

Verification (B): Entry of conditions in each column of interlocking conversion table As the second stage, it is described in a predetermined column (locking column, signal control column, path locking column, approaching locking column, etc.) of interlocking conversion table A4. Extract the condition name.

As an example, a procedure for extracting “orbital conditions” described in the “signal control field” will be described.
In the signal control circuit provided for each route, a trajectory condition for making the traffic signal for that route stop is displayed. The contact name as the track condition is a name obtained by adding “R” to the “track circuit” name, and the contact form is a saddle contact (contact configured when the relay operates). Therefore, the track condition can be extracted from the contact name and contact form included in the signal control circuit.

  FIG. 4 shows an example of a connection diagram (final connection diagram A3), an example of a conversion definition D2, and an added linked conversion table A4. In the connection diagram (final connection diagram A3) of FIG. 4A, two circuits of 1RAHR and 1RBHR are described as examples of the signal control circuit. The conversion definition D2 in FIG. 4B includes “signal control circuit” as an extraction circuit name, “orbit condition” as an identification condition, “R” as an identification name, “upper contact” as a contact form, and an output destination. “Signal control column” is described as the column name. In the linked conversion table A4 of FIG. 4C, two rows of “1RA” and “1RB” are added by the first stage processing shown in FIG. 3, and conditions are added by the following processing. .

  As the condition extraction and conversion function, the name extraction unit 64 searches the connection diagram for the circuit name “signal control circuit” described in the conversion definition D2, and identifies the circuit having the coil name “1RAHR”. The name extraction unit 64 searches for a contact name included in this circuit, and extracts a contact that matches the identification name “R” and the contact form “top contact” described in the conversion definition D2. In FIG. 4A, “21TR” and “1RATR” are extracted.

  The name extraction unit 64 extracts the names “21T” and “1RAT” obtained by removing the identification name “R” described in the conversion definition D2 from “21TR” and “1RATR” as the orbital conditions.

  Since the route name indicated by the circuit of the coil name “1RAHR” has been extracted as “1RA” by the first stage processing shown in FIG. 3, the name extraction unit 64 uses the name column “1RA” in the interlock conversion table A4. The orbital conditions “21T” and “1RAT” are entered in the “output destination” signal control field described in the conversion definition D2 in the line indicated by “.

  The signal control circuit also includes a circuit with the coil name “1RBHR”. By repeating the same processing, the orbital condition “21T” is added to the “signal control column” of the name column “1RB” of the interlock conversion table A4. Enter "2RBT". By repeating the above processing, an interlocking conversion table A4 as shown in FIG. 4C is generated. Furthermore, by preparing various conversion definitions D2, conditions are generated in the same manner for columns other than the “signal control column” of the linked conversion table A4.

Visual comparison (C): Verification of connection diagram by comparison of interlocking conversion table and interlocking diagram table As the third stage processing, the interlocking conversion table A4 generated by the first and second stage processing and the connection diagram (final) A comparison of the original interlocking chart used when creating the connection diagram A3) is performed. When the operator performs comparison, the output unit 52 prints out the generated interlocking conversion table A4 or displays it on a predetermined monitor.

  If the connection diagram is correctly created, the table portion of the interlocking diagram used in the connection diagram creation matches the generated interlocking conversion table A4. On the other hand, if the predetermined condition is insufficient or excessive in the connection diagram, the table part of the interlocking chart does not match the generated interlocking conversion table. Therefore, it can be verified that the connection diagram is correctly created by comparing the interlock conversion table A4 with the interlock diagram.

  FIG. 5 shows an interlocking diagram A6, an example of a connection diagram A21, an example of an incorrect connection diagram A22 at the time of correction, and an interlocking conversion table A41 generated based on the incorrect connection diagram A22. Here, as a comparative example, the signal control column is compared.

  In the interlocking chart A6 of FIG. 5A, “21T” and “1RAT” are described in the signal control column of the route “1RA”. Similarly, “21T” and “1RBT” are described in the signal control column of the route “1RB”.

  FIG. 5B is an example of the connection diagram A21 created based on the interlocking chart A6. In the connection diagram “1RAHR” for the route “1RA”, there is no train in the track condition described in the signal control column. “21TR” and “1RATR” are inserted as conditions for causing the traffic signal to be displayed on the display. Similarly, “21TR” and “1RBTR” are inserted into the connection diagram “1RBHR”.

  FIG. 5C shows a case where the condition “1RBTR” of the “1RBHR” circuit in FIG. 5B is erroneously “2RBTR” as an example of the erroneous connection diagram A22.

  FIG. 5D is an interlocking conversion table A41 generated by the first and second stage processing based on the erroneous connection diagram A22. The signal control column for the route “1RA” includes “21T” and “ In the signal control column for “1RAT” and the route “1RB”, “21T” and “2RBT” are described.

  When the interlocking chart A6 in FIG. 5A is compared with the interlocking conversion table A41 in FIG. 5D, it can be verified that the signal control fields for the route “1RA” match and the connection diagram A22 is correct. Further, since the signal control column for the route “1RB” does not match, it can be verified that there is an error in the connection diagram A22.

  In this way, by comparing the interlocking chart A6 with the interlocking conversion tables A4 and A41, it is possible to verify whether there is an error in the connection diagram (final connection diagram A3).

  By the first to third stage processes, the final connection diagram A3 processed by an operator such as a designer can be effectively verified. The connection diagram is often different from the standard connection diagram depending on the railway company, but it can be dealt with by rewriting the definitions (name extraction definition D1 and conversion definition D2).

Verification (D): Mechanical comparison between interlocking conversion table and interlocking chart When the interlocking chart A6 is prepared as data, the comparison verification unit 66 mechanically compares the interlocking chart A6 and the interlocking conversion table A41. . In that case, the comparison verification unit 66 generates a mismatch list A5 indicating the mismatch portion and the content thereof as shown in FIG.

(2) Verification 2_S20 (Verification on rationality of linked data)
Next, the process of the second verification unit 62 will be described. The second verification unit 62 includes a condition matching unit 67 and an excess condition verification unit 68, and performs processing described below.

  When the conditions included in the connection diagram are correct, when the name is incorrect, or when the condition is excessive or insufficient, verification by the first verification unit 61, that is, verification using the interlocking conversion table A4 is possible. However, in addition to the self-check condition being inserted in the connection diagram, it is assumed that an irrelevant condition (excess condition) is inserted, both of which need to be verified by some means. Therefore, the condition matching unit 67 performs verification regarding the self-check condition as the fourth stage process, and the excess condition verification unit 68 performs verification regarding the excess condition as the fifth stage process. With these verification processes, a more reliable connection diagram can be verified.

Verification (E): Verification of the connection diagram regarding the self-check condition The condition check unit 67 performs check by checking the self-check condition for each circuit as a fourth stage process. Here, as an example, verification of self-check conditions included in the signal control circuit will be described.

  In the signal control circuit for each route, a lever reaction condition for confirming that the route is configured, an approach locking condition for confirming that the route is locked, and the like are inserted. In these conditions, the name obtained by removing the identification condition from the relay name matches the route name of the circuit. Since the course names used as keywords are the same name, these are called self-check conditions.

  For example, the “approach lock condition” inserted in the signal control circuit for the route “1RA” is the name “1RAASR” obtained by adding “ASR” to the “route” name. It is a contact point configured when it falls. Therefore, the approach lock condition can be extracted from the contact name and contact form included in the signal control circuit.

  FIG. 6 shows an example of a connection diagram and an example of a collation definition D3. In the connection diagram A3 in FIG. 6A, two circuits of 1RAHR and 1RBHR are described as examples of the signal control circuit. However, the close lock condition of 2RAHR is an example in which “2RBASR” is mistaken instead of the originally inserted condition “1RBASR”.

  In the collation definition D3 in FIG. 6B, “signal control circuit” is described as a circuit name to be extracted, “closed lock condition” as an identification condition, “ASR” as an identification name, and “falling contact” as a contact form. Has been.

  When the circuit name “signal control circuit” described in the collation definition D3 is searched in the connection diagram, a circuit having the coil name “1RAHR” is found. A contact name included in this circuit is searched, and a contact that matches the identification name “ASR” and the contact form “falling contact” described in the collation definition D3 is extracted. In FIG. 6A, “1RAASR” is extracted. The name “1RA” obtained by removing the identification name “ASR” described in the collation definition D3 from “1RAASR” is extracted as the name for the approaching lock condition.

  The route name indicated by the circuit of the coil name “1RAHR” has been processed as “1RA” in the process of the first stage, and matches the name “1RA” for the approach lock condition extracted above. Can be verified as correct.

  Similarly, “2RB” is extracted from the circuit having the coil name “1RBHR” as the name for the approach lock condition. Although the route name indicated by the circuit of the coil name “1RBHR” is “1RB”, it does not coincide with the name “2RB” for the approach lock condition extracted above, so it can be verified that the connection diagram is incorrect. The verification result is displayed on the screen using the output unit 52 or output to a file.

Verification (F): Verification of connection diagram regarding excess condition As a fifth stage process, the excess condition verification unit 68 performs verification regarding an excess condition. In the second stage processing described above, all conditions based on the interlocking chart inserted in each circuit are collated. In the fourth stage, all self-check conditions inserted in each circuit are verified. By the above collation, the collation of all conditions should be completed originally. However, when an excessive condition unrelated to the connection diagram is inserted, the unverified form remains. For this reason, the collation result up to the fourth stage of processing is checked to verify that there are no excessive conditions.

  FIG. 7 shows an example of the signal control circuit. In the signal control circuit related to the coil “1RBHR”, “2RBTR” is mistaken as “2RBVR” or the contact form of “1RBASR” is mistakenly used as the upper contact as compared with FIG.

  In the signal control circuit related to the coil “1RAHR”, the orbital conditions “21TR” and “1RATR” are verified in the second stage processing, and the approach locking condition “1RAASR” is verified in the fourth stage processing. Absent. Thereby, it can be verified that there is no excess condition.

  On the other hand, for the coil “1RBHR”, the orbital condition “21TR” is verified in the second stage process, but “2RBVR” is not verified as the orbital condition because the identification name is different, and “1RBASR” is the contact point. Since the forms are different, they are not collated with the approach locking conditions, and both are not collated. For this reason, “2RBVR” and “1RBASR” can be determined as excessive conditions. With the above method, it is possible to verify the connection diagram regarding the excess condition. The verification result is displayed on the screen or output to a file using the output unit 52.

Next, a modified example will be described.
In the above example, a connection diagram is used as the interlocking data, but a logical expression equivalent to the connection diagram used in electronic interlocking can also be used. A logical expression is text data in which a connection diagram is represented by a character string instead of a figure, such as a relay name, a contact symbol, and a connection symbol.

  FIG. 8 shows an example of a connection diagram (final connection diagram A3) and a logical expression. FIG. 8B is a diagram obtained by expanding the connection diagram of FIG. 8A into a logical expression.

  Explain the basic format of logical expressions. About the name of a relay contact, let a character string as it is as a name. For example, “21TR” is written. As for the contact form, "/" is added to the above character string only for the drop contact. For example, “1RAASR /” is written.

  As information indicating the connection between the relay contacts, when connecting the contacts in series, “*” is inserted between the names. When connecting contacts in parallel, insert "+" between each name. For connection diagrams in which series and parallel are combined, “(” and “)” are inserted as appropriate, assuming that “*” is given priority as in the mathematical formula. For a coil, insert "=" before the coil name. Since the logical expression expressed in this way can be expressed equivalent to a connection diagram, it can be verified using this verification apparatus.

  As described above, according to the present embodiment, it is possible to verify the interlocking data by generating the interlocking conversion table equivalent to the interlocking chart based on the interlocking data (connection diagram or logical expression) and comparing it with the interlocking chart. Furthermore, it is possible to verify the interlocking data in more detail by collating self-check conditions and searching for excess conditions. As a result, it is possible to verify defects (man-made errors or deficiencies in the interlocking data generation device) that have occurred in the process of creating the connection diagram.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it is understood by those skilled in the art that various modifications are possible for the combination of each of those components, and such modifications are also within the scope of the present invention.

10 Linked Data Design Verification System 30 Linked Data Generation Device 50 Linked Data Verification Device 51 Final Connection Diagram Acquisition Unit 52 Output Unit 61 First Verification Unit 62 Second Verification Unit 63 Conversion Table Creation Unit 64 Name Extraction Unit 66 Comparison Verification Unit 67 Conditions Verification unit 68 Excess condition verification unit

Claims (6)

A linked data verification device that verifies linked data created based on a linked diagram that describes the operating conditions of the linked device in a railway signal system,
A name extraction unit for extracting description content from the linkage data;
A conversion table creation unit for converting the extracted description contents into a tabular linked conversion table;
An output unit for outputting the interlocking chart and the interlocking conversion table, which are the basis of the interlocking data, so that they can be compared;
An interlocking data verification device comprising:   The linked data verification apparatus according to claim 1, further comprising a comparison verification unit that compares the linked diagram and the linked conversion table to determine differences.   The linked data verification apparatus according to claim 1, further comprising a condition matching unit that performs verification by checking the self-check condition for the linked data.   The interlocking data verification device according to claim 3, further comprising an excess condition verification unit that determines whether or not an excessive condition unrelated to the condition described in the interlocking chart is inserted in the interlocking data.   5. The linked data verification apparatus according to claim 1, wherein the linked data is described by a connection diagram or a logical expression. The interlocking data verification device according to any one of claims 1 to 5,
A linked data generating device for creating the linked data based on the linked chart;
An interlocking data design verification system characterized by comprising:

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