JP2018049927A - Silicon carbide semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a SiC semiconductor device capable of ensuring adhesion between a silicide layer and a wiring electrode.SOLUTION: A silicon carbide semiconductor device comprises between a silicide layer 11b and a wiring electrode 11d, a junction metal layer 11c composed of a third metal which is alloyed with the silicide layer 11b and the junction metal layer 11c is alloyed with the silicide layer 11b. This makes it possible to enhance adhesion between the silicide layer 11b and the wiring electrode 11d via the junction metal layer 11c. Since adhesion between the silicide layer 11b and the wiring electrode 11d can be enhanced, separation of the wiring electrode 11d from the silicide layer 11b can be inhibited.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a SiC semiconductor device capable of realizing ohmic contact of electrodes formed on a semiconductor element made of silicon carbide (hereinafter referred to as SiC) and a method for manufacturing the same.

  As a semiconductor device conventionally used as a power device, one using Si (silicon) as a semiconductor material is mainstream. On the other hand, SiC, which is a semiconductor with a wider band gap than Si (hereinafter referred to as a wide gap semiconductor), has a thermal conductivity three times that of Si, a maximum electric field strength of 10 times, and an electron drift speed of twice. It has a physical property value. For this reason, in recent years, studies have been made on application of SiC as a power device having a high dielectric breakdown voltage and low loss and capable of operating at high temperatures.

  As the structure of the power device, a vertical semiconductor device having a wiring electrode provided with a low-resistance ohmic electrode on the back side is the mainstream. Various materials and structures are used for the wiring electrodes of this vertical semiconductor device. As wiring electrodes in SiC devices, Ni (nickel) is formed on the surface of the silicide layer via a Ti (titanium) layer. A structure in which a laminated body such as a layer and an Au (gold) layer or an Ag (silver) layer is formed has been proposed (for example, see Patent Document 1).

JP 2010-86999 A

  When a silicide layer made of Ni silicide or the like is formed on SiC, high-temperature heat treatment is required to secure a sufficiently low ohmic. On the other hand, if high temperature heat treatment necessary for obtaining ohmic in SiC is performed on the entire SiC substrate, there is a concern about the influence on the device formed on the SiC substrate. For this reason, it is necessary to form a silicide layer by local high-temperature heat treatment using laser annealing to suppress the influence on the device.

  Here, the wiring electrode is formed after the high-temperature heat treatment. However, although the wiring electrode made of Ti or the like and the silicide layer made of Ni silicide or the like are in contact, the reactivity is poor. For this reason, the adhesion between the silicide layer and the wiring electrode cannot be ensured, which causes the wiring electrode to peel off from the silicide layer.

  In view of the above points, an object of the present invention is to provide a SiC semiconductor device and a method for manufacturing the same that can ensure adhesion between a silicide layer and a wiring electrode.

  In order to achieve the above object, in the SiC semiconductor device according to claim 1, the ohmic electrode (11) includes a silicide layer (11b) composed of a metal silicide formed on one surface side of the semiconductor substrate (1). A junction metal layer (11c) formed of a metal alloyed with the silicide layer and formed on the silicide layer, and a wiring electrode (11d) formed on the silicide layer via the junction metal layer, It is comprised.

  As described above, a bonding metal layer made of a metal alloying with the silicide layer is provided between the silicide layer and the wiring electrode, and the bonding metal layer and the silicide layer are alloyed. As a result, the adhesion between the silicide layer and the wiring electrode can be enhanced via the bonding metal layer. Since the adhesion between the silicide layer and the wiring electrode can be improved, it is possible to prevent the wiring electrode from being peeled off from the silicide layer.

  In the manufacturing method of the SiC semiconductor device according to claim 7, forming the first metal thin film (50a) which forms carbide by reacting with C in SiC on one surface of the semiconductor substrate (1); On the film, a second metal thin film (50b) that forms silicide by reacting with Si in SiC is formed, and the first metal film and the second metal film are irradiated with laser light (60). By performing laser annealing, a carbide layer (11a) composed of metal carbide is formed, and a silicide layer (11b) composed of metal silicide in contact with the carbide layer is formed. A bonding metal layer (11c) composed of a metal alloyed with the silicide layer is formed thereon, and a wiring electrode (11d) is formed on the silicide layer via the bonding metal layer. It includes the method comprising, a.

  As described above, when the carbide layer and the silicide layer are formed by laser annealing, a bonding metal layer made of a metal alloyed with the silicide layer is provided between the silicide layer and the wiring electrode. As a result, the adhesion between the silicide layer and the wiring electrode can be enhanced via the bonding metal layer. Since the adhesion between the silicide layer and the wiring electrode can be improved, it is possible to prevent the wiring electrode from being peeled off from the silicide layer.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows an example of a corresponding relationship with the specific means as described in embodiment mentioned later.

It is sectional drawing of the SiC semiconductor device concerning 1st Embodiment. It is sectional drawing which showed the manufacturing process of the drain electrode.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment will be described. First, the SiC semiconductor device according to the present embodiment will be described with reference to FIG. In the present embodiment, an SiC semiconductor device including a planar vertical power MOSFET as a vertical semiconductor element will be described. This SiC semiconductor device is suitable when applied to, for example, an inverter.

The vertical power MOSFET is formed using an n ⁺ type SiC substrate 1. The n ⁺ -type SiC substrate 1 has a main surface 1a as an upper surface and a back surface 1b as a lower surface opposite to the main surface 1a, and is made of single crystal SiC. For example, as the n ⁺ -type SiC substrate 1, a substrate having a thickness of 350 μm and an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ is used.

On the main surface 1a of the n ⁺ -type SiC substrate 1, n ⁺ -type SiC substrate n is constituted by SiC having a lower dopant concentration than the 1 ^- -type epitaxial layer (hereinafter, n ^- referred -type epitaxial layer) 2 Are stacked.

In a predetermined region in the surface layer portion of the n ⁻ type epi layer 2, p ⁻ type base regions 3 a and 3 b having a predetermined depth are formed apart from each other. The p ⁻ -type base regions 3a and 3b are provided with deep base layers 30a and 30b that are partially thickened. The deep base layers 30a and 30b are formed in portions that do not overlap n ⁺ type source regions 4a and 4b described later. In the p ⁻ -type base regions 3a and 3b, the thick portion where the deep base layers 30a and 30b are formed has a higher impurity concentration than the thin portion where the deep base layers 30a and 30b are not formed. It is dark. By forming such deep base layers 30a and 30b, the electric field strength between the n ⁺ type SiC substrate 1 and the deep base layers 30a and 30b can be increased, and an avalanche breakdown can be easily performed at this position. be able to.

p ^- is a predetermined region in the surface layer of type base region 3a, the p ^- shallow n ⁺ -type source region 4a is formed than type base region 3a. Further, p ^- type in a predetermined region in the surface layer of the base region 3b, the p ^- shallow n ⁺ -type source region 4b than type base region 3b is formed.

Further, n ⁻ -type layer 5a and n ⁺ -type layer 5b are formed on the surface of n ⁻ -type epi layer 2 and p ⁻ -type base regions 3a and 3b between n ⁺ -type source region 4a and n ⁺ -type source region 4b. An n-type SiC layer 5 made of is extended. That is, the n-type SiC layer 5 is arranged so as to connect the source regions 4a and 4b and the n ⁻ -type epi layer 2 at the surface portions of the p ⁻ -type base regions 3a and 3b. The n-type SiC layer 5 functions as a channel formation layer on the device surface during device operation. Hereinafter, the n-type SiC layer 5 is referred to as a surface channel layer.

The surface channel layer 5 is formed, for example, by ion-implanting n-type impurities into the surface portions of the n ⁻ -type epi layer 2 and the p ⁻ -type base regions 3a and 3b. Type base region 3a, n located on the top of 3b ^{- -} p of the surface channel layer 5 dopant concentration type layer 5a is, n ^- -type epitaxial layer 2 and the p ^- type base region 3a, the dopant concentration of 3b below, For example, the concentration is as low as about 1 × 10 ¹⁵ to 1 × 10 ¹⁷ cm ⁻³ . Further, n ^- dopant concentration of the n ⁺ -type layer 5b formed on the surface portion of the type epi layer 2, n ^- is the higher concentration than the type epi layer 2. Thereby, low on-resistance is achieved.

Further, p ^- type base region 3a, 3b, n ⁺ -type source region 4a, the recess 6a in the surface portion of the 4b, 6b are formed, recesses 6a, the bottom of 6b p ^- type base region 3a, 3b is It is exposed.

A gate insulating film 7 made of a silicon oxide film or the like is formed on the upper surface of the surface channel layer 5 and the upper surfaces of the n ⁺ -type source regions 4a and 4b. Further, a gate electrode 8 is formed on the gate insulating film 7, and the gate electrode 8 is covered with an insulating film 9 made of a silicon oxide film or the like. A source electrode 10 corresponding to the surface electrode is formed on the insulating film 9. The source electrode 10 is in contact with the n ⁺ type source regions 4a and 4b and the p ⁻ type base regions 3a and 3b through the contact holes formed in the insulating film 9 and the recesses 6a and 6b described above.

A drain electrode 11 is formed on the back surface 1 b of the n ⁺ type substrate 1. In the case of this embodiment, the drain electrode 11 is an ohmic electrode. As shown in FIG. 2D described later, the drain electrode 11 has a laminated structure of a carbide layer 11a, a silicide layer 11b, a bonding metal layer 11c, and a wiring electrode 11d. It is configured.

  The carbide layer 11a is composed of metal carbide formed by bonding with C in SiC. For example, the carbide layer 11a is made of carbide such as Mo (molybdenum), Ti, Nb (niobium), W (tungsten), Ta (tantalum), which is the first metal to be carbide. Although the thickness of the carbide layer 11a is arbitrary, it is 10 nm or more, for example, 70 nm. The carbide layer 11a is for trapping C that inevitably remains when the silicide layer 11b described later is formed, and does not need to be all carbided, and remains in the state of the first metal. There may be some parts.

  The silicide layer 11b is composed of a metal silicide formed by bonding with Si in SiC, and is a layer for obtaining SiC and ohmic. For example, the silicide layer 11b is made of Ni, Co (cobalt), or the like, which is a second metal to be silicided. Although the thickness of the silicide layer 11b is also arbitrary, it is 10 nm or more, for example, 100 nm. The silicide layer 11b only needs to be silicided at least at the interface with SiC, and may remain the second metal on the surface opposite to SiC.

  Although the carbide layer 11a and the silicide layer 11b are illustrated as a stacked structure here, the stacked structure is not necessarily required. That is, the structure may be such that the carbide layer 11a penetrates into the silicide layer 11b, or the structure is scattered at the interface between the silicide layer 11b and SiC or in the silicide layer 11b. Since the carbide layer 11a causes an increase in contact resistance, it is preferable that the carbide layer 11a is thin even if it exists at the interface between the silicide layer 11b and SiC, and is divided and scattered. And more preferred. Furthermore, if the carbide layer 11a is divided and scattered, but is separated from the SiC, the contact area between the silicide layer 11b and SiC increases, so that even better ohmic characteristics can be obtained. .

  Further, it is possible to obtain ohmic by forming the silicide layer 11b without forming the carbide layer 11a. However, if the carbide layer 11a is not constituted by C in SiC, a carbon layer is formed, and the silicide layer 11b and SiC may be separated from the connected carbon layer. For this reason, it is preferable that the carbide layer 11a is made thin or has a scattered structure while constituting the carbide layer 11a.

  The bonding metal layer 11c is made of a third metal that forms an alloy layer with the silicide layer 11b, and is made of, for example, Ni, Al (aluminum), Al—Si, or the like. The bonding metal layer 11c is alloyed at the interface with the silicide layer 11b. Specifically, the bonding metal layer 11c is a silicide alloy layer obtained by incorporating Si from the silicide layer 11b. The Si content ratio in the bonding metal layer 11c is smaller than the Si content ratio in the silicide layer 11b. For example, when the second metal used for the silicide layer 11b and the third metal used for the bonding metal layer 11c are both Ni, the former is about Ni: Si = 1: 1 to 1: 2, and the latter is Ni: Si is about 2: 1.

  Note that the bonding metal layer 11c does not have to be a silicide alloy layer in which all of Si is incorporated. Regarding the Si content ratio in the bonding metal layer 11c, the Si content ratio may be uniform in the entire area of the bonding metal layer 11c, but it is not necessary to be uniform in the entire area. In particular, it is preferable that the Si content ratio in the bonding metal layer 11c is high on the silicide layer 11b side and decreases toward the wiring electrode 11d side. Although there is a concern that the adhesion between the bonding metal layer 11c and the wiring electrode 11d is lowered when the Si content ratio is increased on the wiring electrode 11d side, the Si content ratio is decreased on the wiring electrode 11d side. It becomes possible to raise the adhesiveness between these by becoming low.

  The wiring electrode 11d is made of a metal for forming a pad portion to be externally connected, and has a laminated structure such as Ti / Ni / Au. As for Ti which is arranged closest to the bonding metal layer 11c, since the Si content in the bonding metal layer 11c is low as described above, it has high adhesion with the third metal constituting the bonding metal layer 11c. Have joined. In the conventional structure in which the wiring electrode is formed so as to be in contact with the silicide layer, the adhesion between the silicide layer having a large Si content and the wiring electrode is poor, and separation may occur between them. was there. However, since the bonding metal layer 11c is provided as in the present embodiment and the Si content ratio of the bonding metal layer 11c is low, the adhesion between the bonding metal layer 11c and the wiring electrode 11d can be improved. It becomes possible, and it becomes possible to suppress peeling between these.

  With the above configuration, the SiC semiconductor device having the vertical power MOSFET according to the present embodiment is configured. Next, a method for manufacturing the vertical power MOSFET shown in FIG. 1 will be described. However, since the basic manufacturing method of the vertical power MOSFET according to the present embodiment is the same as the conventional method, only the method for forming the drain electrode 11 different from the conventional method will be described.

  FIG. 2 is a diagram showing a manufacturing process of the drain electrode 11 in the vertical power MOSFET shown in FIG. 1, but the device structure of the vertical power MOSFET is not shown for the sake of simplicity.

First, a sample in which each element constituting the device shown in FIG. 1 is formed on the surface side of the n ⁺ -type substrate 1, that is, a source electrode 10 excluding the drain electrode 11 is prepared.

Then, the process shown in FIG. Specifically, the n ⁺ type substrate 1 is thinned by grinding or the like from the back surface, and the thickness of the n ⁺ type substrate 1 is set to 350 μm. Then, a protective film 40 that covers the source electrode 10 (not shown) is formed on the main surface 1 a side of the n ⁺ type substrate 1. The protective film 40 protects the surface electrode formed on the n ⁺ type substrate 1, that is, the source electrode 10, and is made of a resin material such as polyimide.

After protecting the front surface side of the n ⁺ type substrate 1 with this protective film 40, as a metal thin film forming step, a first metal that generates carbide on the back surface 1 b of the n ⁺ type substrate 1 has a thickness of, for example, 10 nm or more. By forming, the first metal thin film 50a is formed. For example, the first metal thin film 50a is formed by depositing Mo with a thickness of 70 nm by vapor deposition using a vacuum deposition apparatus. Further, the second metal thin film 50b is formed on the first metal thin film 50a by forming the second metal with a film thickness of, for example, 10 nm or more. For example, the second metal thin film 50b is formed by depositing Ni with a thickness of 100 nm using a vacuum deposition apparatus.

Next, in the process shown in FIG. 2B, as the annealing process, laser annealing is performed by irradiating the first metal thin film 50a and the second metal thin film 50b with the laser beam 60 in the atmosphere. Specifically, an LD-pumped solid-state laser with a fundamental wavelength of 1064 nm is used, a third harmonic wave with a wavelength of 355 nm is generated by a wavelength conversion adapter, and the laser beam 60 with a wavelength of 355 nm is scanned on the back surface 1 b of the n ⁺ type substrate 1. . Thereby, the laser beam 60 is irradiated to the first metal thin film 50a and the second metal thin film 50b. At this time, it is preferable that the laser beam 60 is irradiated only on the portion where the first metal thin film 50a and the second metal thin film 50b are formed by scanning or masking.

As a result, as shown in FIG. 2C, as the annealing step, the second metal constituting the second metal thin film 50b, for example, Ni reacts with Si in SiC which is the constituent material of the n ⁺ type substrate 1. Thus, the silicide layer 11b can be generated. Further, C in SiC reacts with a first metal that constitutes the second metal thin film 50b, for example, Mo, and a carbide layer 11a is generated. The carbide layer 11a formed at this time does not need to have a stacked structure with the silicide layer 11b, and may have a structure that enters the silicide layer 11b or a scattered structure. And since such an annealing process is performed by laser irradiation, local heating is possible, and it is possible to eliminate the need for high-temperature treatment for regions other than the region where laser irradiation is performed. Therefore, the influence on the device formed on the n ⁺ type substrate 1 can be suppressed.

  In FIG. 2C, all the first metal thin film 50a reacts with C to become the carbide layer 11a. However, a part of the first metal thin film 50a is not carbide and is, for example, at a location away from the SiC interface. A region that remains as the first metal thin film 50a may remain.

When such laser annealing is performed, although not shown, an unnecessary film made of silicon particles or silicon oxide (SiO ₂ ) is formed on the surface of the silicide layer 11b. Since this unnecessary film can cause peeling, it is necessary to remove it before the subsequent step shown in FIG. For this reason, the unnecessary film is removed by performing, for example, wet etching using HF (hydrofluoric acid) or plasma dry etching using ion plasma as the removing step.

  In the case of the Si semiconductor device, even when the same structure as that of the SiC semiconductor device described in the present embodiment is realized, the wiring electrode can be continuously formed after the formation of the silicide layer. High adhesion can be obtained between the electrodes. This is unnecessary because it is possible to perform annealing by high-temperature heat treatment without performing local annealing by laser annealing as in SiC semiconductor devices, and it is not necessary to take out a sample in the atmosphere as in the case of laser annealing. This is because no film is formed. In the SiC semiconductor device, an unnecessary film is generated due to the necessity of laser annealing, and a removal process for removing this is required.

  In the subsequent step shown in FIG. 2 (d), the silicide layer 11b is composed of a junction metal layer 11c composed of the silicide layer 11b and a third metal constituting an alloy layer, Ti / Ni / Au, and the like. Film formation is performed so that the wiring electrodes 90 are sequentially stacked. The bonding metal layer 11c and the wiring electrode 90 can be formed by, for example, vacuum vapor deposition using a vacuum vapor deposition apparatus, and can be continuously formed without being taken out from the same apparatus. If the bonding metal layer 11c and the wiring electrode 90 are formed by vacuum deposition, the wiring electrode 90 can be maintained while maintaining the state if the bonding metal layer 11c is formed in a vacuum state. Since it can be formed, the manufacturing process can be simplified and shortened.

  Then, in the heating apparatus, the third metal constituting the bonding metal layer 11c is annealed at a temperature at which the third metal is alloyed with the silicide layer 11b and at a temperature that does not affect the device, for example, 100 to 450 ° C. The metal and the silicide layer 11b are alloyed. As a result, the adhesion between the silicide layer 11b and the bonding metal layer 11c can be increased. At this time, Si is taken into the bonding metal layer 11c from the silicide layer 11b, and for example, the silicide layer 11b side becomes a silicide alloy layer. However, since the Si content ratio in the bonding metal layer 11c is such that Si is taken in from the silicide layer 11b, it is smaller than the Si content ratio in the silicide layer 11b. Further, the Si content ratio in the bonding metal layer 11c can be adjusted by annealing conditions and the like, and the same ratio can be obtained in all of the bonding metal layer 11c, and is higher on the silicide layer 11b side and toward the wiring electrode 11d side. It can be reduced as much as possible.

  Note that the interface side of the silicide layer 11b with the bonding metal layer 11c may remain as the second metal without being silicided. In that case, high adhesion can be obtained similarly by forming an alloy of the second metal and the third metal. Furthermore, if the second metal and the third metal are made of the same metal material, for example, Ni, high adhesion can be obtained similarly by forming a metal bond between the same metal materials.

  In addition, the bonding metal layer 11c and the wiring electrode 11d can be continuously formed in the same apparatus. Therefore, when the sample is taken out from the apparatus after the bonding metal layer 11c is formed. Such impurities are not generated on the surface of the bonding metal layer 11c. For this reason, high adhesion can be obtained also between the bonding metal layer 11c and the wiring electrode 11d.

  Furthermore, when the unnecessary film is removed using HF as described above, impurities such as fluorine may remain on the surface of the silicide layer 11b. In this case, if the wiring electrode 11d is formed directly on the silicide layer 11b, the adhesion between them is lowered. However, since the junction metal layer 11c is arranged between the silicide layer 11b and the wiring electrode 11d as in the present embodiment, the junction metal layer 11c and between the silicide layer 11b and the junction metal layer 11c High adhesion can be obtained between the wiring electrode 11d. Therefore, high adhesion can be obtained between the silicide layer 11b and the wiring electrode 11d via the bonding metal layer 11c.

  Through such a process, the drain electrode 11 is formed. Then, by forming the drain electrode 11, the vertical power MOSFET shown in FIG. 1 is completed.

  As described above, in the present embodiment, the bonding metal layer 11c composed of the third metal alloyed with the silicide layer 11b is provided between the silicide layer 11b and the wiring electrode 11d. The silicide layer 11b is alloyed. As a result, the adhesion between the silicide layer 11b and the wiring electrode 11d can be enhanced via the bonding metal layer 11c. Since the adhesion between the silicide layer 11b and the wiring electrode 11d can be enhanced, it is possible to prevent the wiring electrode 11d from being peeled off from the silicide layer 11b.

(Second Embodiment)
A second embodiment will be described. In the present embodiment, the process of alloying the third metal constituting the bonding metal layer 11c into the silicide layer 11b is changed with respect to the first embodiment, and the rest is the same as the first embodiment. Only the parts different from the first embodiment will be described.

  In the present embodiment, the third metal constituting the bonding metal layer 11c is alloyed with the silicide layer 11b by laser annealing. For example, the same annealing process as that for forming the carbide layer 11a and the silicide layer 11b is performed using the LD-excited solid-state laser used in the process shown in FIG. 2B described in the first embodiment.

  In the first embodiment, heating in the heating device is performed to alloy the third metal constituting the bonding metal layer 11c with the silicide layer 11b. That is, the entire sample on which the device has been formed is heated. For this reason, as a temperature which does not affect a device, heating temperature is 100-450 degreeC, for example. In such a case, it is necessary to set the temperature so as not to affect the device, and the third metal and the silicide layer 11b may not be sufficiently alloyed. However, by using laser annealing as in this embodiment, local heating is possible, and annealing can be performed at a higher temperature, for example, about 1000 ° C. without affecting the device. .

  Thereby, the third metal and the silicide layer 11b can be sufficiently alloyed, and the adhesion between the bonding metal layer 11c and the silicide layer 11b can be further increased.

(Other embodiments)
The present invention is not limited to the embodiment described above, and can be appropriately changed within the scope described in the claims.

  For example, in each of the above embodiments, the case where the electrode on the back surface side of the device in which each component is formed on the front surface side of the SiC substrate is an ohmic electrode has been described as an example. However, the structure described in the first embodiment is not only applicable to the back side where each component is formed on the front side of the SiC substrate, but if it is a structure that forms an ohmic electrode on SiC, It can be applied to any part. For example, the present invention can also be applied to the case where an ohmic electrode is formed on the surface side of a SiC substrate. Even in that case, when the ohmic electrode is formed after forming each component of the device, by using laser annealing, local heating becomes possible, It becomes possible to suppress the influence.

  Moreover, although the case where the joining metal layer 11c was comprised by the film | membrane of a single layer was demonstrated in the said embodiment, you may comprise by the laminated body of the multilayer of the metal material from which a material differs. For example, the bonding metal layer 11c can be configured by a multilayer structure in which Ni and Al are sequentially stacked.

In each of the above embodiments, an LD-excited solid-state laser is used as the laser light used for laser annealing. However, other laser light such as a KrF excimer laser having a fundamental wavelength of 248 nm can also be used. When a KrF excimer laser is used as the laser beam, the annealing process can be performed by setting the intensity of the laser beam to about 1300 mJ / cm ² .

  In the first embodiment, the SiC semiconductor device including the vertical power MOSFET as the semiconductor element has been described as an example. However, this is merely an example, and other semiconductor elements such as a diode and an IGBT are included. Anyway. That is, any SiC semiconductor device may be used as long as an ohmic electrode is provided for a semiconductor element formed on a semiconductor substrate made of SiC.

1 n ⁺ type SiC substrate 8 Gate electrode 10 Source electrode 11 Drain electrode 11a Carbide layer 11b Silicide layer 11c Junction metal layer 11d Wiring electrodes 50a, 50b First and second metal thin films 60 Laser light

Claims (9)

A semiconductor substrate (1) made of silicon carbide and having a semiconductor element formed thereon;
A silicon carbide semiconductor device having an ohmic electrode (11) formed on one surface of the semiconductor substrate,
The ohmic electrode is
A silicide layer (11b) composed of metal silicide formed on one surface side of the semiconductor substrate;
A junction metal layer (11c) formed on the silicide layer and composed of a metal alloyed with the silicide layer;
A silicon carbide semiconductor device comprising a wiring electrode (11d) formed on the silicide layer via the bonding metal layer.   2. The silicon carbide semiconductor device according to claim 1, wherein the bonding metal is a laminated body made of a plurality of different materials alloyed with the silicide layer.   The silicon carbide semiconductor device according to claim 1, wherein the bonding metal layer contains Si, and a Si content ratio in the bonding metal layer is smaller than a Si content ratio in the silicide layer.   The silicon carbide semiconductor device according to claim 3, wherein the Si content ratio is uniform over the entire area of the bonding metal layer.   4. The silicon carbide semiconductor device according to claim 3, wherein the Si content ratio in the bonding metal layer is lowered toward the wiring metal from the silicide layer. 5. The ohmic electrode is
Including a carbide layer (11a) composed of metal carbide formed on one side of the semiconductor substrate;
The silicon carbide semiconductor device according to claim 1, wherein the silicide layer is formed in contact with the carbide layer. Providing a semiconductor substrate (1) made of silicon carbide and having a semiconductor element formed thereon;
Forming an ohmic electrode (11) on one surface of the semiconductor substrate, and a method of manufacturing a silicon carbide semiconductor device,
Forming a first metal thin film (50a) that reacts with carbon in silicon carbide to form carbide on one surface of the semiconductor substrate;
Forming on the first metal film a second metal thin film (50b) that forms silicide by reacting with silicon in silicon carbide;
The first metal film and the second metal film are irradiated with laser light (60) to perform laser annealing, thereby forming a carbide layer (11a) made of metal carbide and the carbide layer; Forming a silicide layer (11b) composed of a metal silicide in contact therewith,
Forming a bonding metal layer (11c) made of a metal alloying with the silicide layer on the silicide layer;
Forming a wiring electrode (11d) on the silicide layer with the bonding metal layer interposed therebetween, and a method for manufacturing a silicon carbide semiconductor device.   The method for manufacturing a silicon carbide semiconductor device according to claim 7, wherein forming the bonding metal layer and forming the wiring electrode are performed continuously in the same apparatus.   The said joining metal layer is alloyed with the said silicide layer after forming the said joining metal layer, and it anneals at the temperature of 100-1000 degreeC as this alloying. A method for manufacturing a silicon carbide semiconductor device.

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