JP2018049172A - Image forming apparatus and bias power supply device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image forming apparatus that reduces manifestation of light and shade stripes generated in an image to be formed compared with a case where an oscillator is not used for a source oscillator of a modulation signal.SOLUTION: A bias power supply device 100 of an image forming apparatus comprises: a transformer 1208 that outputs an AC output signal S38 from a secondary coil; a switch circuit 1206 that causes a switch element to switch on the basis of a modulating output signal S34 and supplies a current to a primary coil of the transformer 1208; and a modulation circuit 1204 that receives a frequency setting signal S33 for setting the frequency of the AC output signal S38 and a modulating signal S11 and creates the modulating output signal S34. The AC output signal S38 has an oscillator 82 as a source oscillator, and the modulating signal S11 is created from an oscillator 81 as a source oscillator.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an image forming apparatus and a bias power supply apparatus.

  A high-frequency modulation type, so-called class D amplifier type AC high-voltage power supply device has come to be used for a power supply device included in an image forming apparatus. A high-frequency modulation AC high-voltage power supply device can operate in the saturation region of the transistor and has low loss compared to the class B amplifier method, and is therefore effective for energy saving and miniaturization.

  Patent Document 1 describes a high-voltage power supply device that suppresses output fluctuations by setting the frequency of a resonant frequency signal to an integer multiple of the frequency of an output signal frequency signal.

Japanese Patent No. 5552978

By the way, when a high-frequency modulation AC high-voltage power supply device is used as a bias power supply for an image forming apparatus, the waveform of the output AC high-voltage signal fluctuates in a clock signal that generates a modulation signal used for switching of a switch element. If this occurs, the modulation signal and the AC high voltage signal interfere with each other, and there is a risk that gray stripes will appear in the formed image.
SUMMARY OF THE INVENTION An object of the present invention is to provide an image forming apparatus that suppresses the appearance of light and shade stripes generated in an image to be formed as compared with a case where an oscillator is not used for source oscillation of a modulation signal.

According to the first aspect of the present invention, an image holding member, a charging unit that charges the image holding member, and the image holding member charged by the charging unit are exposed, and an electrostatic latent image is formed on the image holding member. An exposure unit to be formed; a developing unit that develops an electrostatic latent image that is exposed by the exposure unit and formed on the image holding body; and a transfer unit that transfers the developed image to a transfer target. At least one of the charging unit and the developing unit uses an electric field in which alternating current and direct current are superimposed, and the electric field has a primary winding and a secondary winding, and current is supplied to the primary winding. Thus, a transformer that outputs an AC output signal from the secondary winding and a switch element are provided, and the switch element is switched based on the received modulation output signal to supply a current to the primary winding of the transformer. A switching circuit that performs the frequency of the AC output signal And a modulation circuit that receives the modulation signal and generates the modulation output signal that has been subjected to pulse width modulation, and the frequency setting signal and the modulation signal are generated by a bias power source. An image forming apparatus is generated using an oscillator as a source oscillation.
The invention according to claim 2 is characterized in that the oscillator is a first oscillator that is a source oscillation of the frequency setting signal and a second oscillator that is a source oscillation of the modulation signal. The image forming apparatus according to claim 1.
The invention according to claim 3 is the image forming apparatus according to claim 2, wherein the first oscillator is a source oscillation of an alternating current setting signal for setting a current of an alternating current output signal. .
The invention according to claim 4 is the image forming apparatus according to claim 1, wherein the oscillator is a common source oscillation of the frequency setting signal and the modulation signal.
The invention according to claim 5 is the image forming apparatus according to claim 4, wherein the oscillator is a source oscillation of an alternating current setting signal for setting a current of an alternating current output signal.
The invention according to claim 6 has a primary winding and a secondary winding, and when a current is supplied to the primary winding, a transformer that outputs an AC output signal from the secondary winding; A switch circuit that has a switch element, switches the switch element based on the received modulated output signal, and supplies a current to the primary winding of the transformer; and a frequency setting signal that sets a frequency of the AC output signal; A modulation circuit that receives the modulation signal and generates the modulation output signal that is pulse-width modulated, wherein the frequency setting signal and the modulation signal are generated using an oscillator as a source oscillation. This is a bias power supply device.

According to the first aspect of the invention, compared to the case where the oscillator is not used for the source oscillation of the modulation signal, the appearance of gray stripes generated in the formed image is suppressed.
According to the second aspect of the present invention, the frequency division ratio can be easily set as compared with the case where a plurality of oscillators are not provided.
According to the invention of claim 3, it is not necessary to provide another reference signal as compared with the case where the resonator is not shared.
According to the invention of claim 4, the component mounting area and the component cost are reduced as compared with the case where the resonator is not shared.
According to the fifth aspect of the present invention, it is not necessary to provide another reference signal as compared with the case where the resonator is not shared.
According to the invention of claim 6, interference between signals can be suppressed as compared with a case where an oscillator is not used for source oscillation of a modulation signal.

1 is a diagram illustrating an example of an overall configuration of an image forming apparatus to which a first exemplary embodiment is applied. It is a figure explaining an example of the block configuration of the bias power supply device provided with the power supply board in which the charging bias power supply unit was comprised, and the signal generation board. It is a figure which shows an example of the circuit structure of a charging bias power supply unit. It is a circuit diagram showing an example of an oscillator, a frequency divider, and an integration circuit in the first embodiment, and a diagram showing waveforms of a clock signal and a modulation signal. (A) is a circuit diagram of an oscillator, a frequency divider, and an integration circuit, and (b) is a waveform of a clock signal and a modulation signal. It is a time chart explaining operation | movement of the charging bias power supply unit in 1st Embodiment. It is a figure explaining an example of the block configuration of the bias power supply device to which the first embodiment is not applied. It is the figure which showed typically the waveform of a clock signal, and the waveform of an alternating current output signal. (A) is a case of a bias power supply apparatus to which the first embodiment is applied, and (b) is a case of a bias power supply apparatus to which the first embodiment is not applied. It is a figure explaining an example of the block configuration of the bias power supply device with which 2nd Embodiment is applied. It is a figure explaining an example of the block configuration of the bias power supply device with which 3rd Embodiment is applied.

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
{First embodiment}
<Image forming apparatus 1>
FIG. 1 is a diagram illustrating an example of the overall configuration of an image forming apparatus 1 to which the first exemplary embodiment is applied. An image forming apparatus 1 shown in FIG. 1 is an image forming apparatus generally called a tandem type. The image forming apparatus 1 includes an image forming process unit 10 that forms an image corresponding to image data of each color, an image output control unit 30 that controls the image forming process unit 10, such as a personal computer (PC) 2 or an image reading device. 3 and an image processing unit 40 that performs predetermined image processing on image data received from these.

The image forming process unit 10 includes a plurality of image forming units 11Y, 11M, 11C, and 11K that are arranged in parallel at predetermined intervals. When the image forming units 11Y, 11M, 11C, and 11K are not distinguished from each other, they are referred to as image forming units 11.
The image forming unit 11K forms an electrostatic latent image and holds a toner image, and a charging roll 13K that charges the surface of the photosensitive drum 12K to a predetermined voltage (charging bias (charging electric field)). A print head 14K for exposing the photosensitive drum 12K charged by the charging roll 13K, and a developing unit 15K for developing the electrostatic latent image obtained by the print head 14K.
Further, a charging bias power supply unit 13aK for supplying a charging bias for charging the photosensitive drum 12K to the charging roll 13K, and a voltage (developing bias (developing electric field)) predetermined for the developing unit 15K to the developing unit 15K. A developing bias power supply unit 15aK is connected to each other.

The other image forming units 11Y, 11M, and 11C are similarly configured. That is, in the other image forming units 11Y, 11M, and 11C, the photosensitive drum 12K, the charging roll 13K, the print head 14K, the developing device 15K, the charging bias power supply unit 13aK, and the developing bias power supply unit 15aK in the image forming unit 11K. What is necessary is just to replace K with Y, M, and C. When these are not distinguished from each other, they are expressed as the photosensitive drum 12, the charging roll 13, the print head 14, the developing device 15, the charging bias power supply unit 13a, and the developing bias power supply unit 15a.
However, the developers 15K, 15Y, 15M, and 15C differ in the stored toner. As a result, the image forming units 11Y, 11M, 11C, and 11K form toner images of yellow (Y), magenta (M), cyan (C), and black (K), respectively.
Here, the charging roll 13 is an example of a charging unit, the photosensitive drum 12 is an example of an image carrier, the print head 14 is an example of an exposure unit, and the developing device 15 is an example of a developing unit.

Here, the charging roll 13 is formed, for example, by forming an epichlorohydrin rubber layer on the surface of a metal shaft and further coating the surface of the epichlorohydrin rubber layer with polyamide containing tin oxide conductive powder to a thickness of about 3 μm.
Further, the photosensitive drum 12 is formed by forming an organic photosensitive layer on the surface of a thin cylindrical drum made of metal, for example, and is configured such that the organic photosensitive layer is negatively charged. The development by the developing device 15 is performed by a reversal development method. Accordingly, the toner used in the developing device 15 is of the negative charge type.

In order to supply a charging bias to the charging roll 13, the voltage output from the charging bias power supply unit 13a is, for example, an alternating current (AC) voltage having a frequency of 2 kHz and a peak-to-peak value (pp value) of 2 kV ( A direct current (DC) voltage of -600 V (a direct current output voltage Vdc described later) is superimposed on an alternating current output voltage Vac described later.
Further, in order to supply a developing bias to the developing device 15, the voltage output from the developing bias power supply unit 15a is, for example, a DC voltage of −500 V superimposed on an AC voltage having a frequency of 8 kHz and a pp value of 1 kV. Is.

The charging bias power supply unit 13a and the developing bias power supply unit 15a in the first embodiment are a high-frequency modulation method (class D) that switches (turns on and off) the switching element to obtain AC or DC high-voltage output power as will be described later. (Amplifier type) switching power supply.
High frequency modulation switching power supplies are effective for energy saving.

  Further, the image forming apparatus 1 conveys the recording paper in order to multiplex-transfer the toner images of the respective colors formed by the image forming units 11Y, 11M, 11C, and 11K onto a recording paper as an example of a transfer target. A sheet conveyance belt 21, a drive roll 22 that is a roll for driving the sheet conveyance belt 21, a transfer roll 23 as an example of a transfer unit that transfers the toner image on the photosensitive drum 12 to a recording sheet, and toner on the recording sheet. And a fixing device 24 for fixing the image.

  In the image forming apparatus 1, the image forming process unit 10 performs an image forming operation based on various control signals supplied from the image output control unit 30. The image data received from the personal computer (PC) 2 or the image reading device 3 under the control of the image output control unit 30 is subjected to image processing by the image processing unit 40, and each of the image forming units 11Y, 11M, 11C and 11K. For example, in the black (K) image forming unit 11K, the photosensitive drum 12K is charged in a predetermined charging bias by the charging roll 13K while being rotated in the arrow A direction, and is supplied from the image processing unit 40. Exposure is performed by a print head 14K that emits light based on the image data. Thereby, an electrostatic latent image related to a black (K) color image is formed on the photosensitive drum 12K. The electrostatic latent image formed on the photosensitive drum 12K is developed by the developing device 15K, and a black (K) toner image is formed on the photosensitive drum 12K.

Here, the reversal development method is used. The surface of the photosensitive drum 12K is charged with a charging bias (for example, −600 V of a DC voltage on which an AC voltage is superimposed). When an image is written by the print head 14K, the electrical conductivity of the surface of the photosensitive drum 12K increases, and the voltage of the portion irradiated with light by the print head 14K becomes, for example, -600V to -200V. On the other hand, a developing bias (for example, a DC voltage of −500 V on which an AC voltage is superimposed) is supplied to the developing device 15K that stores toner. Then, the negatively charged toner adheres to the portion where the voltage on the surface of the photosensitive drum 12K is −200V. In this way, a toner image of each color is formed.
In the image forming units 11Y, 11M, and 11C, yellow (Y), magenta (M), and cyan (C) color toner images are formed, respectively.

Each color toner image formed by each image forming unit 11 is applied to a recording sheet supplied with the movement of the sheet conveying belt 21 moving in the direction of arrow B by a transfer electric field (transfer bias) applied to the transfer roll 23. Then, the toner images are sequentially electrostatically transferred to form a composite toner image in which each color toner is superimposed on the recording paper.
Thereafter, the recording paper on which the synthetic toner image is electrostatically transferred is conveyed to the fixing device 24. The synthetic toner image on the recording paper conveyed to the fixing device 24 is fixed on the recording paper by the fixing device 24 by a fixing process using heat and pressure, and is discharged from the image forming apparatus 1.

  The image forming apparatus 1 shown in FIG. 1 includes image forming units 11Y, 11M, 11C, and 11K corresponding to yellow (Y), magenta (M), cyan (C), and black (K), respectively. did. The image forming apparatus 1 may include one image forming unit 11. Further, the image forming apparatus 1 may include an image forming unit 11 of a color other than yellow (Y), magenta (M), cyan (C), and black (K).

<Bias power supply apparatus 100>
[Block Configuration of Bias Power Supply Device 100]
Here, it is assumed that the bias power supply apparatus 100 includes, as an example, a power supply substrate 110 on which a charging bias power supply unit 13aK is configured, and a signal generation substrate 120 that supplies a clock signal S01 and an alternating current setting signal S3 described later. Further, the bias power supply apparatus 100 may be any of the other charging bias power supply units 13aY, 13aM, and 13aC instead of the charging bias power supply unit 13aK.
Further, the signal generation board 120 may be provided in common to the power supply boards 110 of the charging bias power supply units 13aY, 13aM, 13aC, and 13aK, and the power supply boards of the charging bias power supply units 13aY, 13aM, 13aC, and 13aK. 110 may be provided.

Further, as another example, the bias power supply apparatus 100 may be a developing bias power supply unit 15aK instead of the charging bias power supply unit 13aK. Further, instead of the development bias power supply unit 15aK, any one of the other development bias power supply units 15aY, 15aM, and 15aC may be provided.
The bias power supply apparatus 100 operates in the same manner even when the charging bias power supply unit 13a and the developing bias power supply unit 15a are replaced.

  Hereinafter, the bias power supply apparatus 100 will be described as including, as an example, the power supply substrate 110 and the signal generation substrate 120 on which the charging bias power supply unit 13aK is configured. In this case, the bias power supply apparatus 100 uses the charging roll 13K as a load.

FIG. 2 is a diagram for explaining an example of a block configuration of the bias power supply apparatus 100 including the power supply substrate 110 and the signal generation substrate 120 on which the charging bias power supply unit 13aK is configured.
A power supply substrate 110 (hereinafter, referred to as a charging bias power supply unit 13aK) on which the charging bias power supply unit 13aK is configured includes an AC output unit 1200 and a DC output unit 1250.
The signal generation board 120 includes an oscillator 81 and frequency dividers 71 and 72. The oscillator 81 generates a reference signal S0 and transmits it to the frequency dividers 71 and 72. The frequency divider 71 transmits an alternating current setting signal S3 obtained by dividing the reference signal S0 by a predetermined frequency dividing ratio to an analog voltage conversion circuit 1201 described later of the alternating current output unit 1200. Further, the frequency divider 72 transmits a clock signal S01 obtained by dividing the reference signal S0 by a predetermined frequency dividing ratio to a first low-pass filter 1203 described later of the AC output unit 1200.
The clock signal S01 sets the frequency of an AC output signal S38 to be described later. The AC current setting signal S3 sets the current Iac of the AC output signal S38.
The oscillator 81 is a source oscillation of the clock signal S01 and the alternating current setting signal S3, and the frequency of the clock signal S01 and the alternating current setting signal S3 is set by dividing the reference signal S0 generated by the oscillator 81. Is done.

  The image output control unit 30 transmits a DC voltage setting signal S4 to the DC output unit 1250. The image output control unit 30 sets the frequency division ratios of the frequency dividers 71 and 72 and a frequency divider 73 described later.

The reference signal S0 and the clock signal S01 are rectangular wave signals with a duty ratio of 50%. The alternating current setting signal S3 is a pulse width modulation (PWM) signal in which the pulse width is modulated.
Note that the AC output setting signal S3 may be transmitted by the image output control unit 30 in the same manner as the DC voltage setting signal S4.

  The oscillator 81 may be an element in which fluctuations in oscillation frequency are suppressed with respect to changes in environmental temperature (temperature drift), such as a crystal oscillator (quartz crystal oscillator) and a ceramic oscillator (ceramic oscillator).

Next, the block configuration of the bias power supply apparatus 100 will be described in detail.
The AC output unit 1200 and the DC output unit 1250 are both switching power supplies that generate high-voltage output power by switching (turning on and off) the switch elements. In FIG. 2, as an example, it is assumed that the AC output unit 1200 is a separately excited system and the DC output unit 1250 is a self-excited system.

The AC output unit 1200 of the charging bias power supply unit 13aK includes an analog voltage conversion circuit 1201, an amplification circuit 1202, a first low-pass filter 1203, a modulation circuit 1204, a drive circuit 1205, a switch circuit 1206, a second low-pass filter 1207, a transformer 1208, and an alternating current. A current detection circuit 1209, an AC voltage detection circuit 1210, an integration circuit 1212, an oscillator 82, and a frequency divider 73 are provided.
In FIG. 2, the block configuration is not shown for the DC output unit 1250 of the charging bias power supply unit 13aK (see FIG. 3 described later).

Below, the structure of the alternating current output part 1200 is demonstrated with the relationship and operation | movement outline | summary of signal transmission / reception.
The analog voltage conversion circuit 1201 receives the alternating current setting signal S3 from the signal generation board 120. The alternating current setting signal S3 is a PWM signal as described above, and sets the value of the alternating current (sine wave) current Iac output from the transformer 1208 according to the duty ratio. This duty ratio is, for example, 3% to 100%.
Then, the analog voltage conversion circuit 1201 generates a voltage signal corresponding to the duty ratio of the received alternating current setting signal S3 (hereinafter, referred to as an analog voltage signal S31), and transmits the signal to the amplifier circuit 1202.

The amplifier circuit 1202 receives the analog voltage signal S31 from the analog voltage conversion circuit 1201 and the detection signal S51 from the alternating current detection circuit 1209. The AC current detection circuit 1209 will be described later.
Then, the amplifier circuit 1202 amplifies the difference between the voltage of the analog voltage signal S31 and the voltage of the detection signal S51, generates an error amplification signal S32, and transmits it to the first low-pass filter 1203.

  The first low-pass filter 1203 receives the clock signal S01 and the error amplification signal S32 transmitted by the amplifier circuit 1202. The first low-pass filter 1203 extracts an AC component from the clock signal S01, generates a frequency setting signal S33 in which the high-frequency component is blocked by the low-pass filter, and transmits the frequency setting signal S33 to the modulation circuit 1204. The frequency setting signal S33 has a waveform close to a sine wave. The amplitude (pp value) is set by the error amplification signal S32.

The frequency of the frequency setting signal S33 sets the frequency of the AC output signal S38 output from the transformer 1208. The AC output signal S38 is an AC output voltage Vac and an AC output current Iac.
Since the frequency setting signal S33 is a signal obtained by extracting a sine wave component from the clock signal S01 that is a rectangular wave signal with a duty ratio of 50%, the frequency of the frequency setting signal S33 is a repetition frequency of the clock signal S01.

The modulation circuit 1204 receives the frequency setting signal S33 from the first low-pass filter 1203, and receives the modulation signal S11 from the integration circuit 1212. The modulation signal S11 is, for example, a triangular wave.
The modulation signal S11 is a signal obtained by dividing the reference signal S1 transmitted from the oscillator 82 by the frequency divider 73 at a predetermined frequency division ratio and converting the reference signal S1 into a triangular wave by the integrating circuit 1212. The frequency division ratio of the frequency divider 73 is set by the image output control unit 30. The oscillator 82, the frequency divider 73, and the integration circuit 1212 that generate the modulation signal S11 will be described later with reference to FIG.

  Then, the modulation circuit 1204 compares the voltage of the frequency setting signal S33 with the voltage of the modulation signal S11, and a period in which the voltage of the modulation signal S11 is equal to or higher than the voltage of the frequency setting signal S33 and a period of less than the voltage of the frequency setting signal S33. A modulation output signal S34 having a different voltage is generated and transmitted to the drive circuit 1205. As will be described later, the modulation output signal S34 is a PWM signal whose pulse width is set by the voltage difference between the voltage of the modulation signal S11 and the frequency setting signal S33.

The drive circuit 1205 receives the modulation output signal S34 from the modulation circuit 1204, converts it into a drive signal S35 for driving the switch circuit 1206, and transmits the drive signal S35 to the switch circuit 1206. The drive signal S35 is also a PWM signal as will be described later.
The switch circuit 1206 includes two field effect transistors FET1 and FET2 described later as switching elements (see FIG. 3 described later). The drive signal S35 is a PWM signal, and the field effect transistors FET1 and FET2 of the switch circuit 1206 are alternately turned on and off (switched). Thus, the switch output signal S36 transmitted from the switch circuit 1206 to the second low-pass filter 1207 is a PWM signal that follows the drive signal S35.

  The second low-pass filter 1207 cuts off the high frequency component of the switch output signal S36 received from the switch circuit 1206, generates a sine wave signal S37, and transmits it to the transformer 1208.

  The transformer 1208 has a primary winding and a secondary winding, and the primary winding receives the sine wave signal S37 from the second low-pass filter 1207. The secondary winding of the transformer 1208 outputs an AC output signal S38 of an AC output voltage Vac (AC output current Iac) set by a winding ratio (a winding ratio between the primary winding and the secondary winding).

  The AC output signal S38 (AC output voltage Vac (AC output current Iac)) is superimposed on the DC output voltage Vdc (DC output current Idc) output by the DC output unit 1250 and the output voltage Vo (output current Io). Thus, it is applied to the charging roll 13K that charges the photosensitive drum 12K.

The AC current detection circuit 1209 detects (monitors) the AC output current Iac flowing through the photosensitive drum 12K via the charging roll 13K, and amplifies the DC voltage detection signal S51 converted in proportion to the AC output current Iac. Transmit to circuit 1202.
The AC voltage detection circuit 1210 detects (monitors) the AC output voltage Vac applied to the charging roll 13K, and transmits a DC voltage detection signal S52 converted to be proportional to the AC output voltage Vac.

  In FIG. 2, the amplifier circuit 1202 receives the detection signal S51 from the AC current detection circuit 1209, and performs feedback control (current control) so that the difference between the value set by the AC current setting signal S3 and the AC output current Iac becomes small. Control. That is, when the AC output current Iac is larger than the value set by the AC current setting signal S3, the AC output voltage Vac is controlled to be small, and the AC output current Iac is a value set by the AC current setting signal S3. If it is smaller, the AC output voltage Vac is controlled to be increased.

In FIG. 2, none of the detection signals S52 transmitted by the AC voltage detection circuit 1210 is received. The amplifier circuit 1202 may receive the detection signal S52 instead of the detection signal S51 transmitted by the alternating current detection circuit 1209. In this case, when the AC output voltage Vac is larger than a predetermined value, the AC output voltage Vac is controlled to be small, and when the AC output voltage Vac is smaller than a predetermined value, the AC output voltage Control to increase Vac.
That is, the detection signal 52 of the AC voltage detection circuit 1210 may be used for overvoltage control.

  The oscillator 81 is an example of a first oscillator, and the oscillator 82 is an example of a second oscillator.

When the bias power supply apparatus 100 includes a developing bias power supply unit 15aK (any of the other developing bias power supply units 15aY, 15aM, and 15aC) instead of the charging bias power supply unit 13aK, an AC output current Instead of Iac, the AC output voltage Vac may be controlled by feedback.
That is, in the image forming apparatus 1, the charging bias is preferably maintained at a predetermined current value, and the developing bias is preferably maintained at a predetermined voltage value.
Hereinafter, description of the AC voltage detection circuit 1210 is omitted.

Here, the bias power supply apparatus 100 includes the power supply substrate 110 on which the charging bias power supply unit 13aK is configured, and the signal generation substrate 120. The power supply board 110 and the signal generation board 120 are each a single circuit board.
However, the power supply board 110 and the signal generation board 120 on which the charging bias power supply unit 13aK is configured may be configured on individual circuit boards, or may be configured on one (one) circuit board. Also good.
On the other hand, the power supply substrate 110 constituting the charging bias power supply unit 13aK may not be formed on one (one) circuit board but may be formed on a plurality of circuit boards.

[Circuit Configuration of Charging Bias Power Supply Unit 13aK]
FIG. 3 is a diagram illustrating an example of a circuit configuration of the charging bias power supply unit 13aK.
Note that the blocks in FIG. 3 are arranged differently from those in FIG. 2 for ease of explanation. Further, the arrangement of each block is schematic and is not limited to this arrangement.
The circuit configuration of the charging bias power supply unit 13aK shown in FIG. 3 is an example and may be other circuit configurations, such as other components (error amplifier, comparator, buffer, resistor, capacitor, etc.) and other A circuit may be further included.

  FIG. 3 also shows an example of each block of the DC output unit 1250 and an example of the circuit configuration of each block.

(AC output unit 1200)
First, the AC output unit 1200 will be described.
Since the oscillator 82, the frequency divider 73, and the integration circuit 1212 will be described later with reference to FIG. 4, the modulation signal S11 and later generated by the oscillator 82, the frequency divider 73, and the integration circuit 1212 will be described here.

The analog voltage conversion circuit 1201 includes a buffer B1, resistors R1, R2, R3, and a capacitor C1.
The input terminal of the analog voltage conversion circuit 1201 is one terminal of the resistor R1 and receives the alternating current setting signal S3 from the image output control unit 30. The other terminal of the resistor R1 is connected to the input terminal of the buffer B1. The input terminal of the buffer B1 is connected to one terminal of the resistor R2. The other terminal of the resistor R2 is grounded (ground voltage GND).
The output terminal of the buffer B1 is connected to one terminal of the resistor R3. The other terminal of the resistor R3 is an output terminal of the analog voltage conversion circuit 1201 and transmits an analog voltage signal S31. Furthermore, the other terminal of the resistor R3 is connected to one terminal of the capacitor C1. The other terminal of the capacitor C1 is grounded (ground voltage GND).
The buffer B1 is supplied with the reference voltage Vref1 and the ground voltage GND.

  When the analog voltage conversion circuit 1201 receives the alternating current setting signal S3 that is a PWM signal, the capacitor C1 is charged to a voltage between the reference voltage Vref1 and the ground voltage GND. This voltage is determined by the duty ratio of the alternating current setting signal S3. As a result, the alternating current setting signal S3, which is a PWM signal, is converted into an analog voltage signal S31 of a direct current voltage.

The amplifier circuit 1202 includes an error amplifier Amp1, resistors R4 and R5, and a capacitor C2.
A non-inverting input terminal (hereinafter, referred to as a + input terminal) of the error amplifier Amp1 is connected to the other terminal of the resistor R3, which is an output terminal of the analog voltage conversion circuit 1201, and receives the analog voltage signal S31. The inverting input terminal (hereinafter, referred to as “−input terminal”) of the error amplifier Amp1 is connected to one terminal of the resistor R5. The other terminal of the resistor R5 is connected to the alternating current detection circuit 1209 and receives the detection signal S51.
The output terminal of the error amplifier Amp1 is connected to one terminal of the resistor R4. The other terminal of the resistor R4 is an output terminal of the amplifier circuit 1202.
The capacitor C2 connects between the negative input terminal of the error amplifier Amp1 and the output terminal of the error amplifier Amp1.
The error amplifier Amp1 amplifies the difference between the voltage of the analog voltage signal S31 and the detection signal S51 to generate an error amplification signal S32. Then, the error amplification signal S32 is transmitted to the first low-pass filter 1203 from the other terminal of the resistor R4 that is the output terminal of the amplifier circuit 1202.

The first low-pass filter 1203 includes an error amplifier Amp2, npn transistors Tr1 and Tr2, resistors R6, R7, R8, R9, and R10, a diode D1, and capacitors C3, C4, and C5.
One terminal of the resistor R6 is an input terminal of the first low-pass filter 1203 and receives the clock signal S01 from the frequency divider 71 (see FIG. 2). The other terminal of the resistor R6 is connected to the base terminal of the npn transistor Tr1. The emitter terminal of the npn transistor Tr1 is grounded (ground voltage GND), and the collector terminal is connected to the base terminal of the npn transistor Tr2. The emitter terminal of the npn transistor Tr2 is grounded (ground voltage GND), and the collector terminal is connected to the cathode terminal of the diode D1. The reference voltage Vref2 is supplied to the collector terminal of the npn transistor Tr1 (base terminal of the npn transistor Tr2).
One terminal of the resistor R7 is connected to the base terminal of the npn transistor Tr1, and the other terminal is grounded (ground voltage GND).
The anode terminal of the diode D1 is connected to the other terminal of the resistor R4, which is the output terminal of the amplifier circuit 1202. The anode terminal of the diode D1 is connected to one terminal of the capacitor C3.

The other terminal of the capacitor C3 is connected to one terminal of the resistor R8 and one terminal of the resistor R9. The other terminal of the resistor R8 is connected to the negative input terminal of the error amplifier Amp2 and to one terminal of the capacitor C4. The other terminal of the capacitor C4 is connected to the output terminal of the error amplifier Amp2. The other terminal of the resistor R9 is also connected to the output terminal of the error amplifier Amp2. The output terminal of the error amplifier Amp2 is grounded (ground voltage GND) via the capacitor C5 and the resistor R10. The output terminal of the error amplifier Amp2 is the output terminal of the first low-pass filter 1203.
The reference voltage Vref3 is supplied to the + input terminal of the error amplifier Amp2.

Here, the resistors R6 and R7 suppress an excessive current from flowing through the npn transistor Tr1.
The npn transistor Tr1 functions as an input buffer, and the npn transistor Tr2 modulates the error amplification signal S32 with the clock signal S01 together with the diode D1.
The capacitor C3 is a coupling capacitor and extracts an AC component from the error amplification signal S32 modulated by the clock signal S01.
The error amplifier Amp2, resistors R8, R9, R10, and capacitors C4, C5 constitute a low-pass filter, which cuts off high frequency components and generates a frequency setting signal S33 that is a sine wave.
Then, the frequency setting signal S33 is transmitted from the output terminal of the error amplifier Amp2, which is the output terminal of the first low-pass filter 1203, to the modulation circuit 1204.
The amplitude (pp value) of the frequency setting signal S33 is set by the error amplification signal S32 as will be described later.

  Here, the voltage generation circuit 1211 not shown in FIG. 2 will be described. The voltage generation circuit 1211 supplies a power supply voltage Vs (for example, 24 V) to the modulation circuit 1204, the drive circuit 1205, the switch circuit 1206, and the second low-pass filter 1207. This power supply voltage Vs is a logic level voltage (a low level (hereinafter referred to as “L”) and a high level (hereinafter referred to as “H”) in FIG. For example, it is different from 5V). Therefore, the voltage generation circuit 1211 is provided to generate the power supply voltage Vs.

Next, the modulation circuit 1204 will be described.
The modulation circuit 1204 includes a comparator Cmp. The + input terminal of the comparator Cmp receives the modulation signal S11. The negative input terminal of the comparator Cmp is connected to the output terminal of the first low-pass filter 1203 (the output terminal of the error amplifier Amp2), and receives the frequency setting signal S33. The output terminal of the comparator Cmp is connected to the drive circuit 1205.
The comparator Cmp compares the voltage of the frequency setting signal S33 and the voltage of the modulation signal S11. During the period in which the voltage of the modulation signal S11 is greater than the voltage of the frequency setting signal S33, the comparator Cmp becomes the power supply voltage Vs. A modulated output signal S34 that becomes the ground voltage GND in a period smaller than the signal S33 is generated and transmitted. The modulation output signal S34 becomes a PWM signal whose pulse width is set by the difference between the voltage of the modulation signal S11 and the voltage of the frequency setting signal S33.

The drive circuit 1205 includes a pnp transistor Tr3, an npn transistor Tr4, and a resistor R11.
One terminal of the resistor R11 is an input terminal of the drive circuit 1205, is connected to the output terminal of the comparator Cmp of the modulation circuit 1204, and receives the modulation output signal S34. The other terminal of the resistor R11 is connected in common to the base terminal of the pnp transistor Tr3 and the base terminal of the npn transistor Tr4. The collector terminal of the pnp transistor Tr3 is grounded (ground voltage GND), and the collector terminal of the npn transistor Tr4 is set to the power supply voltage Vs. The emitter terminal of the pnp transistor Tr3 and the emitter terminal of the npn transistor Tr4 are connected and serve as the output terminal of the drive circuit 1205. The output terminal of the drive circuit 1205 transmits the drive signal S35 to the switch circuit 1206.
The resistor R11 suppresses an excessive current from flowing through the pnp transistor Tr3 and the npn transistor Tr4.

When the modulation output signal S34 is the ground voltage GND, the pnp transistor Tr3 is turned on and the npn transistor Tr4 is turned off, and the drive signal S35 becomes the ground voltage GND. When the modulation output signal S34 is the power supply voltage Vs, the pnp transistor Tr3 is turned off and the npn transistor Tr4 is turned on, and the drive signal S35 becomes the power supply voltage Vs.
That is, the drive signal S35 is a PWM signal having the same voltage magnitude relationship as that of the modulation output signal S34. The driver circuit 1205 functions as a buffer that supplies a current for driving to the switch circuit 1206.

The switch circuit 1206 includes an n-channel field effect transistor FET1, a p-channel field effect transistor FET2, and resistors R12 and R13.
One terminal of the resistor R12 and one terminal of the resistor R13 are connected in common and serve as an input terminal of the switch circuit 1206, and receive the drive signal S35 from the drive circuit 1205. The other terminal of the resistor R12 is connected to the gate terminal of the field effect transistor FET1, and the other terminal of the resistor R13 is connected to the gate terminal of the field effect transistor FET2. The source terminal of the field effect transistor FET1 is grounded (ground voltage GND), and the source terminal of the field effect transistor FET2 is set to the power supply voltage Vs. Further, the drain terminal of the field effect transistor FET1 and the drain terminal of the field effect transistor FET2 are connected to each other, which is an output terminal of the switch circuit 1206 and transmits a switch output signal S36.

  When the drive signal S35 is the ground voltage GND, the field effect transistor FET1 is turned off and the field effect transistor FET2 is turned on, and the switch output signal S36 of the switch circuit 1206 becomes the power supply voltage Vs. On the other hand, when the drive signal S35 is the power supply voltage Vs, the field effect transistor FET1 is turned on and the field effect transistor FET2 is turned off, and the switch output signal S36 becomes the ground voltage GND. That is, the switch output signal S36 of the switch circuit 1206 is a PWM signal whose magnitude relationship between the drive signal S35 and the voltage is reversed.

The second low-pass filter 1207 includes an inductance L, resistors R14 and R15, and capacitors C6, C7, and C8.
One terminal of the inductance L is connected to the output terminal of the switch circuit 1206 and receives the switch output signal S36. The other terminal of the inductance L is connected to one terminal of the primary winding of the transformer 1208. A resistor R14 and a resistor R15 are connected in series between the power supply voltage Vs and the ground voltage GND. The midpoint (a connection point between the resistor R14 and the resistor R15) is connected to the other terminal of the primary winding of the transformer 1208.
The capacitor C8 is connected between one terminal and the other terminal of the primary winding of the transformer 1208.
A low-pass filter is configured by an LC circuit including an inductance L and a capacitor C8.
The capacitor C7 has one terminal connected to a connection point between the resistor R14 and the resistor R15, and the other terminal grounded. Capacitor C7 suppresses fluctuations in the voltage at the other terminal of the primary winding of transformer 1208.
The capacitor C6 is provided between the power supply voltage Vs and the ground voltage GND, and suppresses fluctuations in the power supply voltage Vs.
The second low-pass filter 1207 extracts a sine wave from the switch output signal S 36 that is a PWM signal, generates a sine wave signal S 37, and transmits the sine wave signal S 37 to the transformer 1208.

The transformer 1208 includes a primary winding and a secondary winding. The primary winding is connected to the second low-pass filter 1207.
A capacitor C9 is connected between one terminal and the other terminal of the secondary winding. Furthermore, one terminal of the secondary winding is connected to the charging roll 13K via a resistor R26. The other terminal of the secondary winding is connected to the DC output unit 1250. As a result, an output in which the AC output voltage Vac (AC output current Iac) output from the AC output unit 1200 and the DC output voltage Vdc (DC output current Idc) output from the DC output unit 1250 are superimposed on the charging roll 13K. A voltage Vo (output current Io) is applied.

The alternating current detection circuit 1209 includes diodes D2 and D3, a resistor R15, and capacitors C10 and C11.
One terminal of the capacitor C10 is an input terminal of the alternating current detection circuit 1209 and is connected to the other terminal of the secondary winding of the transformer 1208. The other terminal of the capacitor C10 is connected to the cathode terminal of the diode D2 and the anode terminal of the diode D3. The anode terminal of the diode D2 is grounded. The cathode terminal of the diode D3 is commonly connected to one terminal of the resistor R15 and one terminal of the capacitor C11. The other terminal of the resistor R15 and the other terminal of the capacitor C11 are grounded.
The cathode terminal of the diode D3 is an output terminal of the AC current detection circuit 1209, and is connected to the negative input terminal of the error amplifier Amp1 via the resistor R5 of the amplifier circuit 1202. The detection signal S51 is transmitted to the amplifier circuit 1202. To do.

  The AC output current Iac that flows to charge the photosensitive drum 12K via the charging roll 13K is input to the diode D3 via the capacitor C10 and rectified. And it is converted into a voltage by resistance R15, and becomes detection signal S51.

(DC output unit 1250)
The DC output unit 1250 omitted in FIG. 2 includes an analog voltage conversion circuit 1251, an amplifier circuit 1252, a control circuit 1253, a switch circuit 1254, a transformer 1255, a rectifier circuit 1256, and a DC voltage detection circuit 1257, as shown in FIG. .
Each circuit will be described below.

The analog voltage conversion circuit 1251 receives the DC voltage setting signal S4 transmitted by the image output control unit 30. Similar to the AC current setting signal S3, the DC voltage setting signal S4 is a PWM signal and sets the value of the DC output voltage Vdc output from the rectifier circuit 1256 according to the duty ratio.
The analog voltage conversion circuit 1251 has the same circuit configuration as the analog voltage conversion circuit 1201 of the AC output unit 1200, and includes a buffer B2, resistors R16, R17, R18, and a capacitor C12. Note that the buffer B2 functions as an inverter.
One terminal of the resistor R16 is an input terminal of the analog voltage conversion circuit 1251 and receives the DC voltage setting signal S4. The other terminal of the resistor R16 is connected to the input terminal of the buffer B2. The input terminal of the buffer B2 is connected to one terminal of the resistor R17. The other terminal of the resistor R17 is grounded (ground voltage GND).
The output terminal of the buffer B2 is connected to one terminal of the resistor R18. The other terminal of the resistor R18 is an output terminal of the analog voltage conversion circuit 1251, and transmits the analog voltage signal S41 to the amplifier circuit 1252. The other terminal of the resistor R18 is connected to one terminal of the capacitor C12. The other terminal of the capacitor C12 is grounded.
The buffer B2 is supplied with a reference voltage Vref5 and a ground voltage GND.

  When the analog voltage conversion circuit 1251 receives the DC voltage setting signal S4 which is a PWM signal, the voltage of the capacitor C12 is changed to the reference voltage Vref5 and the reference voltage (Low) which are the power supply voltage (high (high) side voltage) of the buffer B2. (Low) side voltage). This voltage is determined by the duty ratio of the DC voltage setting signal S4. As a result, the DC voltage setting signal S4, which is a PWM signal, is converted into an analog voltage signal S41 of DC voltage.

The amplifier circuit 1252 includes an error amplifier Amp3, resistors R19, R20, R21, R22, and a capacitor C13.
One terminal of the resistor R19 is an input terminal of the amplifier circuit 1252, and receives the analog voltage signal S41 from the analog voltage conversion circuit 1251. The other terminal of the resistor R19 is connected to the negative input terminal of the error amplifier Amp3. On the other hand, the positive input terminal of the error amplifier Amp3 is connected to the DC voltage detection circuit 1257 via the resistor R21 and receives the detection signal S42.
The resistor R20 and the capacitor C13 are connected in series, and the terminal of the resistor R20 that is not connected to the capacitor C13 is connected to the negative input terminal of the error amplifier Amp3. A terminal not connected to the resistor R20 of the capacitor C13 is connected to the output terminal of the error amplifier Amp3.
The output terminal of the error amplifier Amp3 is connected to one terminal of the resistor R22. The other terminal of the resistor R22 is an output terminal of the amplifier circuit 1252, and the error amplifier Amp3 transmits an error amplification signal S43 obtained by amplifying the difference between the analog voltage signal S41 and the detection signal S42 to the control circuit 1253.

  Based on the error amplification signal S43, the control circuit 1253 transmits to the switch circuit 1254 a drive signal S44 that turns on the npn transistor Tr5 that is a switch element in the switch circuit 1254.

The switch circuit 1254 includes an npn transistor Tr5 as a switch element. The base terminal of the npn transistor Tr5 is connected to the control circuit 1253 and receives the drive signal S44. The base terminal and collector terminal of the npn transistor Tr5 are connected to the transformer 1255. The emitter terminal of the npn transistor Tr5 is grounded (ground voltage GND).
The operation of the npn transistor Tr5 will be described later together with the operation of the transformer 1255.

The transformer 1255 includes a primary winding, a primary side auxiliary winding, and a secondary winding. One terminal of the primary winding is set to the power supply voltage Vs, and the other terminal is connected to the collector terminal of the npn transistor Tr5. On the other hand, one terminal of the primary side auxiliary winding is connected in common to the base terminal of the npn transistor Tr5 of the switch circuit 1254 and the control circuit 1253. The other terminal of the primary side auxiliary winding is grounded (ground voltage GND).
Both terminals of the secondary winding of the transformer 1255 are connected to the rectifier circuit 1256.

The rectifier circuit 1256 includes a diode D4, a resistor R23, and a capacitor C14. The diode D4 has a cathode terminal connected to one terminal of the secondary winding of the transformer 1255, and an anode terminal connected to one terminal of the resistor R23 and one terminal of the capacitor C14. The other terminal of the resistor R23 is an output terminal of the rectifier circuit 1256 and is connected to the other terminal of the transformer 1208 of the AC output unit 1200. Further, the other terminal of the capacitor C14 is connected to the other terminal of the secondary winding of the transformer 1255.
The rectifier circuit 1256 converts the voltage induced in the secondary winding into a negative (−) DC output voltage Vdc (DC output current Idc).

The DC voltage detection circuit 1257 includes resistors R24 and R25 and a capacitor C15.
The resistor R25 and the capacitor C15 are connected in parallel. One terminal connected in parallel is connected to the other terminal of the resistor R23 which is the output terminal of the rectifier circuit 1256 via the resistor R24. The other terminal of the resistor R25 and the capacitor C15 connected in parallel is connected to the other terminal of the capacitor C14 of the rectifier circuit 1256 and set to the reference voltage Vref6.
The reference voltage Vref6 is set so that the voltage at the + input terminal of the error amplifier Amp3 in the amplifier circuit 1252 does not become negative.
The DC output voltage Vdc is divided by the resistor R24 and the resistor R25. Therefore, the DC voltage detection circuit 1257 detects (monitors) the voltage appearing at the resistor R25, and transmits a detection signal S42 proportional to the DC output voltage Vdc to the amplifier circuit 1252.

The operation of the switch circuit 1254 and the transformer 1255 of the DC output unit 1250 will be described.
The switch circuit 1254 receives the positive (+) drive signal S44 for turning on the npn transistor Tr5 from the control circuit 1253, whereby the npn transistor Tr5 is turned on. Then, a current flows between the collector terminal and the emitter terminal of the npn transistor Tr5 via the primary winding of the transformer 1255.

When a current flows through the primary winding of the transformer 1255, a voltage that raises the voltage of the base terminal of the npn transistor Tr5 is generated in the primary side auxiliary winding. As a result, the collector current of the npn transistor Tr5 increases with time.
A voltage is also generated in the secondary winding, but no current flows through the secondary winding because the direction of the diode D4 is opposite to the direction of the voltage.

  Since the npn transistor Tr5 has a finite amplification factor, when the collector current reaches a certain value or more, the collector current cannot be increased any more, and the change in the magnetic flux of the core of the primary winding stops. As a result, a force is applied to the primary winding to cause a current to flow in the same direction as the flowing direction, and a reverse voltage is generated. As a result, a voltage in the same direction as the direction of the diode D4 is generated in the secondary winding, and a current flows in the secondary winding.

On the other hand, due to the reverse voltage generated in the primary winding, a reverse voltage is also generated in the primary side auxiliary winding, and a reverse bias is applied between the base terminal and the emitter terminal of the npn transistor Tr5. As a result, the npn transistor Tr5 is turned off.
When the current flowing through the diode D4 becomes 0, the voltage generated in the primary winding, the primary side auxiliary winding, and the secondary winding becomes 0V. Thus, the base terminal-emitter terminal of the npn transistor Tr5 is raised again to the positive (+) side by the drive signal S44 from the control circuit 1253. As a result, the npn transistor Tr5 is turned on again.
In this way, by switching (ON / OFF) the npn transistor Tr5, the DC output voltage Vdc is generated by the current flowing through the secondary winding during the OFF period.

[Oscillator 82, Frequency Divider 73, and Integration Circuit 1212]
Next, the oscillator 82, the frequency divider 73, and the integration circuit 1212 will be described.
FIG. 4 is a circuit diagram showing an example of the oscillator 82, the frequency divider 73, and the integrating circuit 1212 in the first embodiment, and shows the waveforms of the clock signal S02 and the modulation signal S11. 4A is a circuit diagram of the oscillator 82, the frequency divider 73, and the integration circuit 1212. FIG. 4B is a waveform of the clock signal S02 and the modulation signal S11.
As shown in FIG. 4A, the oscillator 82 generates a reference signal S1 and transmits it to the frequency divider 73. The frequency divider 73 divides the reference signal S1 by a predetermined frequency division ratio to generate a clock signal S02. As shown in FIG. 4B, the clock signal S02 is a rectangular wave signal with a duty ratio of 50%. The frequency division ratio of the frequency divider 73 is set by the image output control unit 30.

As shown in FIG. 4A, the integration circuit 1212 includes an error amplifier Amp4, resistors R61, R62, and R63, and capacitors C61 and C62.
One terminal of the resistor R61 which is an input terminal of the integrating circuit 1212 is connected to the frequency divider 73 and receives the clock signal S02 from the frequency divider 73.
The other terminal of the resistor R61 is connected to the negative input terminal of the error amplifier Amp4. The capacitor C61 is provided between the output terminal and the negative input terminal of the error amplifier Amp4.
The + input terminal of the error amplifier Amp4 is connected to a connection point of resistors R62 and R63 connected in series between the power supply voltage Vcc (for example, 5 V) of the error amplifier Amp4 and the ground (ground voltage GND).
A capacitor C62 is provided between the power supply voltage Vcc of the error amplifier Amp4 and the ground (ground voltage GND).

Resistors R62 and R63 divide the voltage between the power supply voltage Vcc and the ground (ground voltage GND) to set the voltage at the + input terminal of the error amplifier Amp4.
Capacitor C62 is provided to suppress voltage fluctuation between power supply voltage Vcc and ground (ground voltage GND).

The error amplifier Amp4 forms an integration circuit in which the charge / discharge time of the capacitor C61 is determined by the resistor R61 and the capacitor C61. As a result, as shown in FIG. 4B, a modulation signal S11 which is a triangular wave signal is obtained. The frequency (repetition frequency) of the modulation signal S11 is the frequency (repetition frequency) of the clock signal S02.
That is, the oscillator 82 is a source oscillation of the modulation signal S11, and the frequency of the modulation signal S11 is set by dividing the reference signal S1 generated by the oscillator 82.

  Similarly to the oscillator 81, the oscillator 82 may be an element such as a crystal oscillator (quartz crystal resonator), a ceramic oscillator, or the like, in which fluctuations in oscillation frequency with respect to environmental temperature changes are suppressed.

[Operation of Charging Bias Power Supply Unit 13aK]
Next, the operation of the charging bias power supply unit 13aK will be described using a time chart.
FIG. 5 is a time chart for explaining the operation of the charging bias power supply unit 13aK in the first embodiment. In FIG. 5, an alternating current setting signal S3, an analog voltage signal S31, a clock signal S01, a frequency setting signal S33, a modulation signal S11, a modulation output signal S34, a switch output signal S36, and an output voltage Vo are shown in order from the top.
In FIG. 6, it is assumed that time elapses in alphabetical order as indicated by time a, time b, time c,.

The alternating current setting signal S3 is transmitted from the image output control unit 30 to the charging bias power supply unit 13aK. The AC current setting signal S3 has two values “L” and “H”, and the “L” period and the “H” period in one period are set at a predetermined ratio (duty ratio). PWM signal. For example, “L” is the ground voltage GND (0V), and “H” is 5V. The current value of the AC output current Iac is set by the duty ratio.
In FIG. 5, the alternating current setting signal S3 has a period from time a to time d as one cycle. The alternating current setting signal S3 indicates that the duty ratio is 75% in the period from time a to time e, and the duty ratio is 50% in the period from time e to time f.

The analog voltage signal S31 is generated by the analog voltage conversion circuit 1201 that has received the alternating current setting signal S3. As shown in FIG. 3, the analog voltage conversion circuit 1201 generates the analog voltage signal S31 by charging the capacitor C1 with the alternating current setting signal S3.
That is, the analog voltage signal S31 has a voltage that is 75% of the reference voltage Vref1 and a time e that has a duty ratio of 50% in a period from time a to time e where the duty ratio of the alternating current setting signal S3 is 75%. Is set to 50% of the reference voltage Vref1 during the period from to f. That is, the voltage of the analog voltage signal S31 is set by the duty ratio of the alternating current setting signal S3.

The clock signal S01 is a signal obtained by dividing the reference signal S0 generated by the oscillator 81 by the frequency divider 71. The clock signal S01 has two values of “L” and “H”, the duty ratio is 50%, and the repetition frequency is the frequency of the AC output signal S38 (AC output voltage Vac, AC output current Iac). is there.
In FIG. 5, the frequency of the clock signal S01 is illustrated as being 1/8 of the frequency of the modulation signal S11 described later for convenience of explanation.

Next, in order to describe the frequency setting signal S33, the operation of the first low-pass filter 1203 and the error amplification signal S32 will be described with reference to FIG.
As shown in FIG. 3, the clock signal S01 is input to the base terminal of the npn transistor Tr1 of the first low-pass filter 1203. The npn transistor Tr1 is turned on while the clock signal S01 is “H”, the collector terminal is at the ground voltage GND, and is turned off when the clock signal S01 is “L”, and the collector terminal is the reference. The voltage becomes Vref2. Here, the reference voltage Vref2 is a positive voltage, for example, 5V.
The collector terminal of the npn transistor Tr1 is connected to the base terminal of the npn transistor Tr2. Therefore, in a period in which the collector terminal of the npn transistor Tr1 is the reference voltage Vref2 (period in which the clock signal S01 is “L”), the npn transistor Tr2 is on and the collector terminal becomes the ground voltage GND. On the other hand, during a period in which the collector terminal of npn transistor Tr1 is at ground voltage GND (period in which clock signal S01 is “H”), npn transistor Tr2 is off and the collector terminal of npn transistor Tr2 is in a floating state.

Here, the error amplification signal S32 that is the output of the amplifier circuit 1202 is a signal obtained by amplifying the difference between the voltage of the analog voltage signal S31 and the voltage of the detection signal S51 output from the alternating current detection circuit 1209 by the error amplifier Amp1. . That is, the error amplification signal S32 is a signal corresponding to (proportional to) the analog voltage signal S31.
When the error amplification signal S32 is input to the first low-pass filter 1203, it is modulated by the diode D1. In a period in which the collector terminal of the npn transistor Tr2 is at the ground voltage GND (period in which the clock signal S01 is “L”), the diode D1 is forward biased, and the error amplification signal S32 is drawn to the ground voltage GND. On the other hand, during the period in which the collector terminal of the npn transistor Tr2 is in the floating state (period in which the clock signal S01 is “H”), the diode D1 is not forward biased and the error amplification signal S32 is maintained. That is, the error amplification signal S32 is modulated by the first low-pass filter 1203 by the clock signal S01.

  The error amplification signal S32 modulated by the clock signal S01 passes through a low-pass filter including the error amplifier Amp2 in the first low-pass filter 1203 and becomes a frequency setting signal S33 that is a sine wave.

As shown in FIG. 5, the amplitude (pp value) of the frequency setting signal S33 is set by the analog voltage signal S31 (that is, the alternating current setting signal S3 shown in FIG. 5). That is, the amplitude H1 in the period in which the duty ratio of the alternating current setting signal S3 from time a to time e is 75% is the amplitude H2 in the period in which the duty ratio of the alternating current setting signal S3 from time e to time f is 50%. Is larger than (75/50 = 1.5 times).
Here, it is assumed that the detection signal S51 output from the alternating current detection circuit 1209 is not affected.

The modulation signal S11 is a triangular wave having a period from time a to time c as one cycle. The period from time a to time b is the rising edge of the triangular wave, and the period from time b to time c is the falling edge of the triangular wave. Corresponding to
In FIG. 5, for convenience of explanation, the frequency of the alternating current setting signal S3 is shown as ½ of the frequency of the modulation signal S11.

As described above, the comparator Cmp of the modulation circuit 1204 compares the voltage of the frequency setting signal S33 with the voltage of the modulation signal S11 that is a triangular wave, and the power supply is supplied during a period in which the voltage of the modulation signal S11 is greater than the voltage of the frequency setting signal S33. The modulation output signal S34 that becomes the voltage Vs and becomes the ground voltage GND in a period in which the voltage of the modulation signal S11 is smaller than the frequency setting signal S33 is generated and transmitted.
In FIG. 5, the frequency setting signal S33 is indicated by a broken line so as to overlap the modulation signal S11. The modulation output signal S34 is a PWM signal whose pulse width is set depending on the magnitude relationship between the modulation signal S11 and the frequency setting signal S33.

  As shown in FIG. 3, the field effect transistors FET1 and FET2 of the switch circuit 1206 are alternately turned on and off by the drive signal S35 having the same magnitude relationship between the modulation output signal S34 and the voltage (indicated as S34 (S35) in FIG. 5). To do.) As described above, when the modulation output signal S34 (drive signal S35) is the ground voltage GND, the field effect transistor FET1 is turned off and the field effect transistor FET2 is turned on, and the switch output signal S36 from the switch circuit 1206 is the power supply voltage. Vs. On the other hand, when the modulation output signal S34 (drive signal S35) is the power supply voltage Vs, the field effect transistor FET1 is turned on and the field effect transistor FET2 is turned off, and the switch output signal S36 from the switch circuit 1206 becomes the ground voltage GND. . That is, as shown in FIG. 5, the modulation output signal S34 (drive signal S35) and the switch output signal S36 have opposite voltage magnitudes.

  The second low-pass filter 1207 extracts the sine wave signal S37 from the switch output signal S36 that is the output of the switch circuit 1206. Then, the sine wave signal S37 becomes an AC output signal S38 (AC output voltage Vac) via the transformer 1208.

On the other hand, the DC output unit 1250 operates in the same manner. As shown in FIG. 3, the analog voltage conversion circuit 1251 generates an analog voltage signal S41 whose voltage is set by the duty ratio of the DC voltage setting signal S4, and transmits the analog voltage signal S41 to the amplifier circuit 1252. The amplifier circuit 1252 amplifies the difference between the voltage of the analog voltage signal S41 and the voltage of the detection signal S42 from the DC voltage detection circuit 1257, and transmits an error amplification signal S43 to the control circuit 1253. The control circuit 1253 generates a voltage that turns on the npn transistor Tr5 of the switch circuit 1254. As described above, when the npn transistor Tr5 of the switch circuit 1254 is repeatedly turned on and off (switching), a voltage is induced in the secondary winding of the transformer 1255.
The rectifier circuit 1256 rectifies the induced voltage and outputs a DC output voltage Vdc.

An output voltage Vo on which the AC output voltage Vac and the DC output voltage Vdc are superimposed is output from the charging bias power supply unit 13aK and applied to the charging roll 13K. As a result, the AC output current Iac flows from the charging roll 13K to the photosensitive drum 12K together with the DC output current Idc.
As described above, when the DC output voltage Vdc is −600 V, the AC output voltage Vac is 2 kHz in frequency, and the pp value is 2 kV, the output voltage Vo is equal to the ground voltage GND (0 V) as shown in FIG. It vibrates positively and negatively.

  As shown in FIG. 3, the alternating current detection circuit 1209 detects (monitors) the alternating current output current Iac and transmits a detection signal S51 converted into a voltage. The negative input terminal of the error amplifier Amp1 of the amplifier circuit 1202 receives the detection signal S51 via the resistor R5. Then, the error amplifier Amp1 controls the amplitude of the frequency setting signal S33 by amplifying the difference between the voltage of the analog voltage signal S31 received by the + input terminal and the voltage of the detection signal S51 received by the − input terminal.

On the other hand, the DC voltage detection circuit 1257 detects (monitors) the DC output voltage Vdc and transmits a detection signal S42 proportional to the DC output voltage Vdc. The + input terminal of the error amplifier Amp3 of the amplifier circuit 1252 receives the detection signal S42 via the resistor R21. Then, the error amplifier Amp3 controls the value of the DC output voltage Vdc by amplifying the difference between the voltage of the detection signal S42 received by the + input terminal and the voltage of the analog voltage signal S41 received by the − input terminal.
In this way, the charging bias power supply unit 13aK operates.

  In the charging bias power supply unit 13aK, the switch output signal S36 is generated by switching (ON / OFF) the field effect transistors FET1 and FET2 of the switch circuit 1206 based on the modulation signal S11. The switch output signal S36 is a PWM signal. The switch output signal S36 is converted to a sine wave signal S37 by the second low-pass filter 1207. Then, the sine wave signal S37 is boosted by the transformer 1208 to become an AC output signal S38 (AC output voltage Vac, AC output current Iac).

FIG. 6 is a diagram illustrating an example of a block configuration of the bias power supply apparatus 100 to which the first embodiment is not applied. Even in the bias power supply apparatus 100 to which the first embodiment is not applied, the bias power supply apparatus 100 includes a power supply board 110 and a signal generation board 120 on which a charging bias power supply unit 13aK is configured.
However, in the bias power supply apparatus 100 to which the first embodiment is not applied, the circuit for generating the modulation signal S11 in the AC output unit 1200 of the power supply substrate 110 is applied to the first embodiment shown in FIG. Different from the bias power supply device 100.

In other words, the circuit that generates the modulation signal S11 in the bias power supply apparatus 100 to which the first embodiment is not applied replaces the oscillator 82 and the frequency divider 73 in the bias power supply apparatus 100 to which the first embodiment is applied. In addition, an RC circuit 1213 is used.
The RC circuit 1213 is an oscillation circuit in which the clock signal S02 is set by charging / discharging between the resistor (R) and the capacitor (C). The values of the resistor (R) and the capacitor (C) are likely to change due to fluctuations in the environmental temperature (temperature drift). For this reason, the frequency of the clock signal S02 generated by the RC circuit 1213 tends to fluctuate.

  FIG. 7 is a diagram schematically showing the waveform of the clock signal S02 and the waveform of the AC output signal S38. FIG. 7A shows the case of the bias power supply apparatus 100 to which the first embodiment is applied, and FIG. 7B shows the case of the bias power supply apparatus 100 to which the first embodiment is not applied. 7A and 7B, the upper side is the clock signal S02, and the lower side is the AC output signal S38. In the waveforms of the clock signal S02 and the AC output signal S38, the vertical axis represents voltage (V) and the horizontal axis represents time (t). The clock signal S02 is shown with reference to the clock signal S01 (reference signal S0).

As shown in FIG. 7A, in the bias power supply apparatus 100 to which the first embodiment is applied, the clock signal S02 hardly shows a waveform fluctuation. For this reason, compared with FIG.7 (b), the alternating current output signal S38 has little fluctuation | variation of a voltage (peak voltage). Note that waveform fluctuation means that the frequency of the clock signal S02 fluctuates due to environmental temperature fluctuations (temperature drift) or the like, and the waveform shifts (varies) on the time axis.
The fact that there is almost no waveform fluctuation in the AC output signal S38 in the bias power supply apparatus 100 to which the first embodiment is applied is that fluctuations in the oscillation frequency (frequency of the reference signal S1) are suppressed by the oscillator 82. It depends.
That is, the phase relationship between the reference signal S0 generated by the oscillator 81 and the reference signal S1 generated by the oscillator 82 is difficult to shift.

On the other hand, as shown in FIG. 7B, in the bias power supply apparatus 100 to which the first embodiment is not applied, the clock signal S02 has a waveform fluctuation.
The fluctuation of the clock signal S02 in the bias power supply apparatus 100 to which the first embodiment is not applied is that the oscillation frequency of the RC circuit 1213 (the frequency of the clock signal S02) is constantly shifted (varied) due to the environmental temperature fluctuation (temperature drift). by. For this reason, the voltage (peak voltage) of the AC output signal S38 varies greatly.
Note that the amount of deviation of the clock signal S02 on the time axis is the waveform fluctuation τ of the clock signal S02.

  When the frequency of the clock signal S02 fluctuates (varies), the voltage (peak voltage) of the AC output signal S38 depends on the frequency (interference frequency) caused by the interference between the frequency setting signal S33 and the modulation signal S11 for setting the frequency of the AC output signal S38. May fluctuate and dark and light stripes (image quality unevenness) may occur in the formed image. The light and shade stripes (image quality unevenness) are called banding. Hereinafter, it is referred to as banding (image quality unevenness).

If the pitch (interval) of banding (image quality unevenness) is p (mm), the outer peripheral speed (peripheral speed) (process speed) of the photosensitive drum 12 is v (mm / s), and the interference frequency is f (Hz), The banding pitch p is expressed by p = v / f. That is, the banding pitch p is inversely proportional to the interference frequency f.
For example, when the process speed v is 300 mm / s and the interference frequency f is 60 Hz, the banding (image quality unevenness) pitch p is 5 mm.
Experience has shown that banding does not become apparent (it is difficult to see) if the pitch p is, for example, 3 mm or less, or 10 mm or more.
However, if the pitch p is, for example, more than 3 mm and less than 10 mm, banding (image quality unevenness) becomes obvious (visible).

  Table 1 shows the relationship between the waveform fluctuation τ of the clock signal S02 and the voltage fluctuation of the AC output signal S38 and banding (image quality unevenness) in the formed image. Here, the waveform fluctuation τ is expressed in ns. Then, “α” is obtained when the voltage fluctuation of the AC output signal S38 is small (state close to FIG. 7A), and when the voltage fluctuation of the AC output signal S38 is large (state close to FIG. 7B). Let it be “β”. Then, “A” indicates that banding (image quality unevenness) does not become apparent (difficult to be visually recognized), “B” indicates that banding (image quality unevenness) is slight, and banding (image quality unevenness) becomes actual (visible). The case is “C”.

As shown in Table 1, when the waveform fluctuation τ of the clock signal S02 is 0 ns, the voltage fluctuation of the AC output signal S38 is small (“α”), and banding (unevenness in image quality) does not become obvious (not easily visible). ). When the waveform fluctuation τ of the clock signal S02 is 5 ns, the fluctuation of the voltage of the AC output signal S38 is small (“α”), but the banding (image quality unevenness) is slight (“B”). When the waveform fluctuation τ of the clock signal S02 is 15 ns, the voltage variation of the AC output signal S38 is large (“β”), and banding (uneven image quality) becomes obvious (visible).
That is, in order to suppress the banding (image quality unevenness) to a state where it is not obvious or a slight state, the waveform fluctuation τ of the clock signal S02 is preferably set to 5 ns or less.
For this purpose, as in the case of the clock signal S01 using the oscillator 81 as a source oscillation, the oscillator (oscillation in the first embodiment) in which the variation in the frequency of the clock signal S02 due to the variation in the environmental temperature (temperature drift) is suppressed. The child 82) may be used as a source.

In the first embodiment, two oscillators 81 and 82 are used.
The oscillator 81 is a source oscillation of the clock signal S01 that sets the frequency of the AC output signal S38, and an oscillation source of the AC current setting signal S3 that sets the current Iac of the AC output signal S38. The oscillator 82 is a source oscillation of the modulation signal S11.
The frequency of the AC output signal S38 is 2 kHz, for example, and the frequency of the modulation signal S11 is 100 kHz, for example. That is, the frequency of the AC output signal S38 and the modulation signal S11 is greatly different. Therefore, the reference signal S0 generated by the oscillator 81 and the reference signal S1 generated by the oscillator 82 are set to different frequencies so that the frequency divider 72 that generates the AC output signal S38 and the frequency that generates the modulation signal S11. The frequency division ratio of each of the devices 73 can be easily set.

  In addition, the clock signal S01 for setting the frequency of the AC output signal S38 and the AC current setting signal S3 for setting the current Iac of the AC output signal S38 are driven by the common oscillator 81, whereby the AC current setting signal S3. On the other hand, it is not necessary to provide another reference signal.

{Second Embodiment}
In the first embodiment, the oscillator 82 and the frequency divider 73 that generate the clock signal S02 are provided on the power supply substrate 110.
In the second embodiment, the oscillator 82 and the frequency divider 73 that generate the clock signal S02 are provided on the signal generation board 120.
Since other configurations are the same as those of the first embodiment, description of similar parts is omitted, and different parts will be described.

FIG. 8 is a diagram illustrating an example of a block configuration of the bias power supply apparatus 100 to which the second exemplary embodiment is applied. Also in the bias power supply apparatus 100 to which the second embodiment is applied, the bias power supply apparatus 100 includes a power supply board 110 and a signal generation board 120 on which a charging bias power supply unit 13aK is configured.
The oscillator 82 and the frequency divider 73 are provided on the signal generation board 120.

  Even in this case, since the clock signal S02 is sourced from an oscillator (oscillator 82 in the second embodiment) that can suppress fluctuations in the oscillation frequency, the waveform fluctuation of the clock signal S02 is suppressed, and the AC signal Banding (image quality unevenness) due to fluctuations in the voltage of the output signal S38 is suppressed.

{Third embodiment}
In the bias power supply apparatus 100 to which the second embodiment is applied, the oscillator 81 and the oscillator 82 are provided on the signal generation substrate 120. The oscillator 81 is a source oscillation of the clock signal S01 and the alternating current setting signal S3. The clock signal S01 sets the frequency of the frequency setting signal S33 that sets the frequency of the AC output signal S38. The oscillator 82 is a source oscillation of the clock signal S02. The clock signal S02 sets the frequency of the modulation signal S11.
For this reason, the increase in a component mounting area and the cost of components increase.
Therefore, in the third embodiment, in the signal generation substrate 120, the oscillator 82 is omitted, and the oscillator 81 is used as the source of the clock signal S02.
Since other configurations are the same as those of the first embodiment, description of similar parts is omitted, and different parts will be described.

FIG. 9 is a diagram illustrating an example of a block configuration of the bias power supply apparatus 100 to which the third exemplary embodiment is applied. Also in the bias power supply apparatus 100 to which the third embodiment is applied, the bias power supply apparatus 100 includes a power supply substrate 110 and a signal generation substrate 120 on which a charging bias power supply unit 13aK is configured.
The frequency divider 73 is provided on the signal generation board 120 and receives the reference signal S0 from the oscillator 81.

  Even in this case, since the clock signal S02 is sourced from an oscillator (oscillator 81 in the third embodiment) that can suppress fluctuations in the oscillation frequency, the waveform fluctuation of the clock signal S02 is suppressed, and the AC signal Banding (image quality unevenness) due to fluctuations in the voltage of the output signal S38 is suppressed.

  In the first to third embodiments, the bias power supply device 100 that supplies the charging bias has been described as an example. As described above, the bias power supply apparatus 100 that supplies the developing bias may be used.

  In the first to third embodiments, the negatively charged toner is used. However, the positively charged toner may be used. At this time, the polarities of the DC output voltage Vdc output from the charging bias power supply unit 13a and the DC output voltage Vdc output from the developing bias power supply unit 15a may be set to opposite (positive (+) voltage).

  In the first to third embodiments, the AC current setting signal S3 (see FIG. 5) and the DC voltage setting signal S4 transmitted by the image output control unit 30 are “H” and “L”. And a signal having two voltages. This is to reduce the influence of noise in the transmission of these signals from the image output control unit 30 to the charging bias power supply unit 13a. Therefore, the AC voltage setting signal S3 and the DC voltage setting signal S4 transmitted by the image output control unit 30 may be analog voltage signals, and the analog voltage conversion circuits 1201 and 1251 of the charging bias power supply unit 13a may be omitted.

  Further, in the first to third embodiments, the image forming apparatus 1 corresponds to each color such as yellow (Y), magenta (M), cyan (C), and black (K). The description has been given assuming that the tandem type includes a plurality of photosensitive drums 12. The image forming apparatus 1 includes a multiple developing device including a rotary developing device in which developing devices corresponding to respective colors such as yellow (Y), magenta (M), cyan (C), and black (K) are rotatably attached. (Rotary) type.

DESCRIPTION OF SYMBOLS 1 ... Image forming apparatus, 10 ... Image forming process part, 11, 11Y, 11M, 11C, 11K ... Image forming unit, 12, 12Y, 12M, 12C, 12K ... Photosensitive drum, 13, 13Y, 13M, 13C, 13K ... Charging roll, 13a, 13aY, 13aM, 13aC, 13aK ... Charging bias power supply unit, 14, 14Y, 14M, 14C, 14K ... Print head, 15, 15Y, 15M, 15C, 15K ... Developer, 15a, 15aY, 15aM , 15aC, 15aK ... development bias power supply unit, 30 ... image output control unit, 40 ... image processing unit, 60 ... waveform setting unit, 71, 72, 73 ... frequency divider, 81, 82 ... oscillator, 100 ... bias power supply Apparatus 110 ... Power supply board 120 ... Signal generation board 1200 ... AC output unit 1201,1251 ... Ana Voltage converter circuit, 1202, 1252 ... Amplifier circuit, 1203 ... First low-pass filter, 1204 ... Modulation circuit, 1205 ... Drive circuit, 1206,1254 ... Switch circuit, 1207 ... Second low-pass filter, 1208,1255 ... Transformer, 1209 ... AC current detection circuit, 1210 ... AC voltage detection circuit, 1211 ... Voltage generation circuit, 1212 ... Integration circuit, 1213 ... RC circuit, 1250 ... DC output unit, 1253 ... Control circuit, 1256 ... Rectification circuit, 1257 ... DC voltage detection Circuit, Amp1, Amp2, Amp3, Amp4 ... error amplifier, Cmp ... comparator, FET1, FET2 ... field effect transistor, GND ... ground voltage, Io ... output current, Iac ... AC output current, Idc ... DC output current, S0, S1 ... reference signal, S01, S02 ... clock signal, 11 ... Modulation signal, S3 ... AC current setting signal, S33 ... Frequency setting signal, S34 ... Modulation output signal, S35 ... Drive signal, S36 ... Switch output signal, S37 ... Sine wave signal, S38 ... AC output signal, S4 ... DC Voltage setting signal, Tr1, Tr2, Tr4, Tr5 ... npn transistor, Tr3 ... pnp transistor, Vo ... output voltage, Vac ... AC output voltage, Vcc, Vs ... power supply voltage, Vdc ... DC output voltage, Vref1, Vref2, Vref3, Vref4, Vref5, Vref6 ... reference voltage

Claims (6)

An image carrier,
A charging unit for charging the image carrier;
Exposing the image carrier charged by the charging unit to form an electrostatic latent image on the image carrier; and
A developing unit that develops the electrostatic latent image exposed by the exposure unit and formed on the image carrier;
A transfer unit that transfers the developed image to a transfer target,
At least one of the charging unit and the developing unit uses an electric field in which alternating current and direct current are superimposed.
A transformer having a primary winding and a secondary winding and supplying an AC output signal from the secondary winding by supplying a current to the primary winding;
A switch circuit having a switch element and switching the switch element based on the received modulated output signal to supply a current to the primary winding of the transformer;
A frequency setting signal that sets a frequency of the AC output signal; a modulation circuit that receives the modulation signal and generates the modulation output signal that is pulse-width modulated;
The image forming apparatus, wherein the frequency setting signal and the modulation signal are generated using an oscillator as a source oscillation.   The image forming apparatus according to claim 1, wherein the oscillator includes a first oscillator that is a source oscillation of the frequency setting signal and a second oscillator that is a source oscillation of the modulation signal. apparatus.   The image forming apparatus according to claim 2, wherein the first oscillator is a source oscillation of an alternating current setting signal that sets a current of an alternating current output signal.   The image forming apparatus according to claim 1, wherein the oscillator is a common source oscillation of the frequency setting signal and the modulation signal.   The image forming apparatus according to claim 4, wherein the oscillator is a source oscillation of an AC current setting signal that sets a current of an AC output signal. A transformer having a primary winding and a secondary winding and supplying an AC output signal from the secondary winding by supplying a current to the primary winding;
A switch circuit having a switch element and switching the switch element based on the received modulated output signal to supply a current to the primary winding of the transformer;
A frequency setting signal that sets a frequency of the AC output signal; and a modulation circuit that receives the modulation signal and generates the modulation output signal that is pulse-width modulated, and
The bias power supply apparatus, wherein the frequency setting signal and the modulation signal are generated using an oscillator as a source oscillation.

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