JP2018042159A - Reception circuit and reception method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reception circuit and a reception method for acquiring a delay guarantee when latching a data signal on the basis of a clock with a simple configuration.SOLUTION: A reception circuit 1 comprises: a clock generation circuit 11 for generating a clock on the basis of a data signal and a strobe signal; a clock delay circuit 12 for outputting a delay clock obtained by delaying the clock only by t; data delay circuits 13, 14 for outputting first and second delay data signals obtained by delaying the data signal only by tand t; and flip flops 15, 16 for latching the first and second delay signals on the basis of the delay clock, where tis longer than time calculated by totaling tand setup time tof the flip flop 15 and hold time tof the flip flop 16, and tis longer than time calculated by totaling tand t, and shorter than time calculated by subtracting tfrom t.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a receiving circuit and a receiving method, and more particularly to a receiving circuit and a receiving method for receiving data transmitted by the DSLLink method.

  The DS-Link system is used as a transmission system of SpaceWire (space wire) which is an interface standard. In the DSLLink system, a data signal and a strobe signal are transmitted, and a receiving circuit that receives them generates a clock to be used in the circuit by exclusive OR of the received data signal and the strobe signal.

  However, in this configuration, there is a concern that the delay cannot be guaranteed when the flip-flop latches the data signal based on the clock. That is, there is a concern that the setup time for the input data cannot be secured in the flip-flop.

  As a solution to this problem, for example, a data / strobe encoding circuit disclosed in Patent Document 1 latches data by a flip-flop, then latches and holds the data, Are passed to the subsequent circuit as a pair. When the data / strobe encoding circuit receives an assertion of a signal indicating that data has been received from the subsequent circuit, the data / strobe encoding circuit again operates the flip-flop that has latched and stopped the data and receives new data.

  Patent Documents 2 and 3 disclose techniques for delaying received signals. The variable delay circuit disclosed in Patent Document 2 sets a unit delay amount in a calibration period for a delay line that delays an input signal.

  The receiving apparatus disclosed in Patent Document 3 delays the I component of the received signal by the period of the repetitive signal, obtains the difference between the delayed signal and the undelayed signal, and obtains the absolute value of the difference in the absolute value portion. . Similarly, the receiving device also obtains the absolute value of the difference between two consecutive repetitive signals by using the absolute value part for the Q component of the received signal. The receiving device adds the outputs of both absolute value parts, integrates the correlation interval, and further integrates the preamble interval. The receiving device detects the timing at which the integral value is minimum and outputs it as a synchronization signal.

JP 2007-300151 A JP 2012-015828 A JP 2002-057657 A

  However, the circuit configuration disclosed in Patent Document 1 requires a clock enable generation circuit, and accordingly, the circuit scale increases and the cost of the receiving circuit tends to increase. The circuit configuration disclosed in Patent Document 2 is a configuration in which a unit delay amount is set during a calibration period for a delay line that delays an input signal. Patent Document 2 discloses a simple configuration in which a data signal is clocked. No circuit configuration that can guarantee delay when latching based on the above is disclosed. The circuit configuration disclosed in Patent Document 3 is a configuration that delays the I component and the Q component of the received signal and outputs a synchronization signal thereof. A circuit configuration capable of ensuring a delay when latching based on a clock is not disclosed.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a receiving circuit and a receiving method capable of ensuring a delay when a data signal is latched based on a clock with a simple configuration.

  The reception circuit of the present invention includes a clock generation circuit that generates a clock based on a data signal and a strobe signal, a first data delay circuit that outputs a first delayed data signal obtained by delaying the data signal by a first time, A second data delay circuit for outputting a second delayed data signal obtained by delaying the data signal by a second time; a clock delay circuit for outputting a delayed clock obtained by delaying the clock by a clock delay time; A first flip-flop that latches a delayed data signal based on the delayed clock and outputs even data that is even-numbered data of the data signal, and latches the second delayed data signal based on the delayed clock. And a second flip-flop that outputs odd data that is odd-numbered data of the data signal. Is longer than the sum of the first time, the setup time of the first flip-flop, and the hold time of the second flip-flop, and the clock delay time is the first time and the first flip-flop. It is equal to or greater than the total time with the setup time, and is equal to or less than the time obtained by subtracting the hold time from the second time.

  The receiving method of the present invention generates a clock based on a data signal and a strobe signal, outputs a first delayed data signal obtained by delaying the data signal for a first time, and outputs the data signal for a second time. A delayed second delayed data signal is output, a delayed clock obtained by delaying the clock by a clock delay time is output, and the first flip-flop latches the first delayed data signal based on the delayed clock, The second delay data signal is latched by the flip-flop based on the delay clock, and the second time includes the first time, the setup time of the first flip-flop, and the The clock delay time is longer than the sum of the hold times of the second flip-flops, and the clock delay time is the first time and the set time. Longer than the total time of the setup time, shorter than the time obtained by subtracting the hold time from the second time.

  According to the present invention, it is possible to provide a receiving circuit and a receiving method capable of ensuring a delay when a data signal is latched based on a clock with a simple configuration.

It is a block diagram which shows the structure of the 1st Embodiment of this invention. It is a timing chart which shows the operation | movement of FIG. It is a block diagram which shows the structure of the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the 4th Embodiment of this invention. It is a block diagram which shows the structure of the 5th Embodiment of this invention. 7 is a timing chart showing the operation of FIG. 6.

  Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram illustrating a configuration of a receiving circuit according to the first embodiment. FIG. 2 is a timing chart showing the operation of the receiving circuit according to the first embodiment. As illustrated in FIG. 1, the reception circuit 1 includes a clock generation circuit 11, a clock delay circuit 12, data delay circuits 13 and 14, and flip-flops 15 and 16.

The clock generation circuit 11 generates a clock from the data signal and the strobe signal. The clock generation circuit 11 generates a potential clock by exclusive OR of the data signal and the strobe signal. As shown in FIG. 2, the potential clock is generated almost synchronously with the data signal. The data signal is a plurality of data continuously input to the receiving circuit, and the odd-numbered data O ₁ , O ₂ ,... O ₆ is called odd data. The even-numbered data E ₁ , E ₂ ... E ₆ are referred to as even data.

A potential clock is input to the clock delay circuit 12. The clock delay circuit 12 outputs a delay clock obtained by delaying the potential clock by t _c described later to the flip-flops 15 and 16.

As shown in FIG. 1, the data delay circuit 13 receives a data signal, delays the data signal, and outputs it to the flip-flop 15. Further, as shown in FIG. 2, the data delay circuit 13 delays the data signal by the first time t ₁ . A signal output from the data delay circuit 13 and delayed from the data signal by the first time t ₁ is referred to as a first delayed data signal.

As shown in FIG. 1, the data delay circuit 14 receives a data signal, delays the data signal, and outputs the delayed data signal to the flip-flop 16. Data delay circuit 14, as shown in FIG. 2, the first time period t ₁ and the flip-flop 16 set-up time of t _s and flip-flop 15 hold time t longer than the total amount of time the _h second time t ₂ The data signal is delayed and output. That is _{t 2> t 1 + t s} + t h is established. A signal output from the data delay circuit 14 and delayed from the data signal by the second time t ₂ is referred to as a second delayed data signal.

As shown in FIG. 1, the first delayed data signal output from the data delay circuit 13 and the delayed clock output from the clock delay circuit 12 are input to the flip-flop 15. The flip-flop 15 latches even data E ₁ , E ₂ ... E ₆ which are even-numbered data of the data signal as shown in FIG. 2 by latching the first delayed data signal based on the delayed clock. Output.

As shown in FIG. 1, the flip-flop 16 receives the second delayed data signal output from the data delay circuit 14 and the delayed clock output from the clock delay circuit 12. The flip-flop 16 latches the second delayed data signal based on the delayed clock, so that odd data O ₁ , O ₂ ,... O ₆ which are odd-numbered data of the data signal as shown in FIG. Is output.

The clock delay circuit 12 is longer than the time which is the sum of the first time t ₁ and setup time t _s, as shown in FIG. 2, shorter than the time obtained by subtracting the second time from t ₂ hold time t _h only t _c, to generate a delayed clock by delaying the potential clock. This result may be longer than the first delayed data signal the time from the start of the period of the even data until the rise of the delayed clock input to flip-flop 15 set-up time of t _s input to the flip-flop 15. Moreover, it can be made longer than the second hold time the time until the end of the period of the odd data of the delayed data signal t _h inputted from the rise of the delayed clock input to flip-flop 16 to the flip-flop 16.

  As described above, according to the present embodiment, the data setup time and hold time in the receiving circuit are guaranteed with a simple configuration, and the data signal can be reliably latched by the flip-flop based on the clock.

  Next, a second embodiment of the present invention will be described. FIG. 3 is a block diagram showing the configuration of the second exemplary embodiment of the present invention. As shown in FIG. 3, the receiving circuit 2 of the present embodiment is different from the first embodiment in that the clock delay circuit 17 includes two delay circuits 171 and 172 that can set different delay times. Different. The delay circuit 171 outputs a delay clock obtained by delaying the potential clock based on the set delay time to the flip-flop 15. The delay circuit 172 outputs a delay clock obtained by delaying the potential clock based on a delay time set separately from the delay circuit 171 to the flip-flop 16.

  With such a configuration, the timings of the delay clocks input to the flip-flop 15 and the flip-flop 16 can be adjusted. Therefore, according to the present embodiment, the same effects as those of the first embodiment can be obtained, and even when the delay amount from the clock generation circuit 11 to the flip-flop 15 and the delay amount to the flip-flop 16 are different. The delay of the clock input to the flip-flops 15 and 16 can be adjusted.

  Next, a third embodiment of the present invention will be described. FIG. 4 is a block diagram showing the configuration of the third exemplary embodiment of the present invention. In the receiving circuit 3 of this embodiment, as shown in FIG. 4, the clock generation circuit 18 generates a first potential clock and a second potential clock whose phases are opposite to each other, and outputs the first potential clock and the second potential clock to the clock delay circuit 19. The clock delay circuit 19 is different from the second embodiment in that it includes a selection circuit 191 that selects either the first potential clock or the second potential clock.

  The clock delay circuit of this embodiment includes delay circuits 171 and 172 similar to those of the second embodiment, and the selection clock output from the selection circuit 191 is input to the delay circuits 171 and 172. The delay circuit 171 outputs a delay clock obtained by delaying the selected clock based on the set delay time to the flip-flop 15. The delay circuit 172 outputs a delay clock obtained by delaying the selected clock to the flip-flop 16 based on a delay time set separately from the delay circuit 171.

  With this configuration, the clock input to the delay circuits 171 and 172 can be selected from two potential clocks having opposite phases. Therefore, the same effect as the first and second embodiments can be obtained, and the delay can be adjusted within the same range as the second embodiment even if the delay time that can be set by the delay circuit is halved. Become.

  Next, a fourth embodiment of the present invention will be described. FIG. 5 is a block diagram showing the configuration of the fourth exemplary embodiment of the present invention. In the receiving circuit 4 of the present embodiment, the clock delay circuit 20 includes two selection circuits 201 that are selected from the first potential clock and the second potential clock that are generated from the clock generation circuit 18 and have the opposite phases. 202. Further, the third embodiment is different from the third embodiment in that the selection clock selected by the selection circuit 201 is output to the delay circuit 171 and the selection clock selected by the selection circuit 202 is output to the delay circuit 172.

  With such a configuration, clocks input to the delay circuit 171 and the delay circuit 172 can be selected separately. Therefore, the same effects as those of the first, second, and third embodiments can be obtained, and the degree of freedom in adjustment is improved.

  Next, a fifth embodiment of the present invention will be described. FIG. 6 is a block diagram showing the configuration of the fifth exemplary embodiment of the present invention. FIG. 7 is a timing chart showing the operation of the receiving circuit according to the first embodiment. The receiving circuit 5 of this embodiment is different from that of the third embodiment in that the clock delay circuit 21 is configured to output the output of the selection circuit 211 directly to the flip-flops 15 and 16.

In the present embodiment, as shown in FIG. 7, when the selected clock is input to the flip-flops 15 and 16, the embodiment is assumed to be delayed by a time t _c ′ longer than the setup time t _s of the flip-flop 15. It is.

In the present embodiment, by adjusting the delay time t ₁ in the data delay circuit 14, the time from the start of the even data period of the delayed data signal in the flip-flop 15 to the rise of the selected clock as shown in FIG. It is adjusted to more set-up time t _s of the flip-flop 15.

Further, by adjusting the delay time t ₂ in the data delay circuit 14, the time from the rising edge of the selected clock to the end of the odd data period of the delayed data signal in the flip-flop 16 is adjusted as shown in FIG. The hold time is adjusted to _hh or more.

  With such a configuration, the same delay adjustment as that of the other embodiments can be realized with a simple configuration without providing a delay circuit in the clock delay circuit.

  While the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

1, 2, 3, 4, 5 Reception circuit 11, 18 Clock generation circuit 12, 17, 19, 20, 21 Clock delay circuit 13, 14 Data delay circuit 15, 16 Flip-flop 171, 172 Delay circuit 191, 201, 202 , 211 Selection circuit

Claims (6)

A clock generation circuit for generating a clock based on the data signal and the strobe signal;
A first data delay circuit for outputting a first delayed data signal obtained by delaying the data signal by a first time;
A second data delay circuit for outputting a second delayed data signal obtained by delaying the data signal by a second time;
A clock delay circuit for outputting a delayed clock obtained by delaying the clock by a clock delay time;
A first flip-flop that latches the first delayed data signal based on the delayed clock and outputs even data that is even-numbered data of the data signal;
A second flip-flop that latches the second delayed data signal based on the delayed clock and outputs odd data that is odd-numbered data of the data signal;
Have
The second time is longer than the sum of the first time, the setup time of the first flip-flop, and the hold time of the second flip-flop,
The receiving circuit, wherein the clock delay time is equal to or longer than a total time of the first time and the setup time, and is equal to or shorter than a time obtained by subtracting the hold time from the second time. The clock delay circuit is
A first delay circuit that delays the clock output from the clock generation circuit and outputs the delayed clock to the first flip-flop circuit;
A second delay circuit that delays the clock output from the clock generation circuit and outputs the delayed clock to the second flip-flop circuit;
The receiving circuit according to claim 1. The clock generation circuit outputs a first clock and a second clock whose phase is opposite to that of the first clock,
The clock delay circuit includes a selection circuit that selects either the first clock or the second clock.
The receiving circuit according to claim 1 or 2. The clock generation circuit outputs a first clock and a second clock whose phase is opposite to that of the first clock,
The clock delay circuit is
A first selection circuit that selects one of the first clock and the second clock and outputs the first clock to the first delay circuit;
A second selection circuit that selects one of the first clock and the second clock and outputs the selected clock to the second delay circuit;
The receiving circuit according to claim 2, comprising: The clock generation circuit outputs a first clock and a second clock whose phase is opposite to that of the first clock,
The clock delay circuit includes a selection circuit that selects one of the first clock and the second clock and outputs the selected clock to the first flip-flop circuit and the second flip-flop circuit.
The receiving circuit according to claim 1. Generate clock based on data signal and strobe signal,
Outputting a first delayed data signal obtained by delaying the data signal by a first time;
Outputting a second delayed data signal obtained by delaying the data signal by a second time;
Output a delayed clock that is delayed by the clock delay time,
Latching the first delayed data signal by a first flip-flop based on the delayed clock;
Latching the second delayed data signal by a second flip-flop based on the delayed clock;
In the receiving method,
The second time is longer than the sum of the first time, the setup time of the first flip-flop, and the hold time of the second flip-flop,
The reception method, wherein the clock delay time is longer than a total time of the first time and the setup time and shorter than a time obtained by subtracting the hold time from the second time.

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