JP2018041215A - Information processing device, and information processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid causing only specific data to occupy a temporary storage part among various data types of data relating to a request source of read data.SOLUTION: A data processing processor 10 sets a cache ID corresponding to a processing part in which an interface control part 26 requests necessity information and read-out of cache control related to read-out data. A memory controller 46 of an auxiliary storage device 40 performs control so as to select a temporary storage area of a temporary storage part 44 for temporarily storing data read out from the auxiliary storage device 40 on the basis of the necessity information of the cache control and the cache ID included in a read command from the data processing processor 10.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an information processing apparatus and an information processing method suitable for handling a plurality of types of data having different lifetimes and data sizes.

  In gaming machines such as pachinko machines and pachislot machines, a high level of entertainment can be achieved by providing a variety of effects to players in the game, such as still images, video images, sound from speakers, and light emission by LEDs. It is precisely configured to give you a feeling.

  The output of these images, sounds, and light during the game is stored in advance in the gaming machine for the output of those images, and during the game, the data is read out according to the progress of the game, It is performed by outputting as an image, light, and sound by predetermined data conversion. More specifically, the image data, sound data, and light emission data are compressed and written in a read-only memory at the time of manufacture of the gaming machine, and these data are processed exclusively during the game. The processor reads from the read-only memory and decodes it as needed, and outputs it to a liquid crystal display, a speaker, an LED (Light Emitting Diode) or the like according to the data.

  By the way, when the above-mentioned dedicated data processor reads out desired data from the read-only memory, especially in the case of gaming machines, in order to respond to various and rapidly changing output requests to the liquid crystal display, etc. It must be readable. Therefore, the cache technology is often employed for reading data from the read-only memory. Specifically, in a read-only memory, in addition to a main memory (typically a flash memory) that stores image data, audio data, and light emission data, a memory that functions as a cache (read cache) (for example, DRAM ( Dynamic Random Access Memory)) and realizes the cache function.

Patent Document 1 has a configuration in which a cache memory (6) is provided in front of the HDD (8), and data to be recorded on the HDD (8) is also two types of signals, a video signal and an audio signal. The purpose of the described technique is to enable video / audio signals having a size (one file) exceeding the capacity of the HDD (8) to be recorded well over a plurality of HDDs (8). The configuration for achieving the object is to divide the video / audio signal of one file into a plurality of parts at the switching points of the video / audio signals, and to configure a file that can be divided at each part. That's it.
Further, Patent Document 2 discloses a further application of a technique that combines a hierarchization technique using two cache memories having different capacities and a technique that separates caches between instructions and data (operands). The basic configuration is to access a relatively small first cache memory when accessing an operand and branch destination instruction of a branch instruction, and accessing a large second cache memory when absent.
In addition, Patent Document 3 discloses a device for efficiently switching to a low power mode when each processor does not have a process that it is responsible for in processing performed by a plurality of processors. Each processor has a one-to-one cache memory (FIGS. 1 and 5).

JP 2003-115168 A JP-A 64-18843 JP-T-2005-53860

However, when handling various types of data such as the above-mentioned image data, audio data, and light emission data, the lifetime (the length of time the data is used) and the data size (unit of communication data amount) according to the data type However, in this case, the type of data having a large data size basically occupies the cache memory in a biased manner, and a situation may arise where necessary data cannot be processed at a desired timing.
In particular, in a gaming machine such as a pachinko machine, although audio data and light emission data do not allow processing delay compared to image data, only image data with a large data size occupies the cache memory. There was a problem that the output of sound and light was delayed beyond the allowable amount. This is because the amount of image data is larger than that of audio data and light emission data, so that the occupancy rate in the cache memory is high, and the data of audio data and light emission data is not easily cached in the cache memory, resulting in processing delay.
The present invention has been made in view of the above, and an object thereof is to avoid the fact that only specific data occupies a temporary storage unit among various data related to a request source of read data.

  In order to solve the above problems, the invention described in claim 1 is characterized in that a storage unit that stores a plurality of types of data corresponding to a plurality of data types, and data read from the storage unit are temporarily stored in a temporary storage area. A plurality of types of data from the auxiliary storage device based on a request from an auxiliary storage device having a temporary storage unit to store, the storage unit, and a control unit for controlling the temporary storage unit, and a host CPU And a data processing processor that outputs data to a predetermined processing unit, wherein the data processing processor includes a cache control necessity information related to the read data and a processing unit that requests reading. An interface control unit for setting a corresponding cache ID, and the control unit of the auxiliary storage device is included in the read command from the data processor Characterized in that said control was to select a temporary storage area of the temporary storage unit for temporarily storing data read from said auxiliary storage device based on the requirement information and the cache ID of the cache control that.

  ADVANTAGE OF THE INVENTION According to this invention, it can avoid that only specific data will occupy a temporary memory part among the various data relevant to the request origin of read data.

It is a functional block diagram for demonstrating the structure of the information processing apparatus which concerns on one Embodiment of this invention. It is a functional block diagram for demonstrating the structure of the interface control part provided in the data processor which concerns on one Embodiment of this invention. (A) is a diagram showing a configuration of a general SATA standard read command packet, (b) is a diagram showing a configuration of an improved SATA standard read command packet generated by the interface control unit according to the present invention, (c) ) Is a diagram showing the definition of CCHID in the read command packet of the improved SATA standard. It is a functional block diagram for demonstrating the structure of the area | region control part provided in the auxiliary storage device which concerns on one Embodiment of this invention. It is a flowchart for demonstrating operation | movement of the interface control part provided in the data processor which concerns on one Embodiment of this invention. It is a flowchart for demonstrating operation | movement of the area | region control part provided in the auxiliary storage device which concerns on one Embodiment of this invention.

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.
The present invention has the following configuration in order to prevent only specific data from occupying a temporary storage unit among various data related to a request source of read data.
That is, the information processing apparatus of the present invention includes a storage unit that stores a plurality of types of data corresponding to a plurality of data types, a temporary storage unit that temporarily stores data read from the storage unit in a temporary storage area, A plurality of types of data are read from the auxiliary storage device based on a request from the upper CPU and an auxiliary storage device including a storage unit and a control unit that controls the temporary storage unit, and the data is stored in a predetermined processing unit. An information processing apparatus including an interface control unit that sets cache control necessity information related to read data and a cache ID corresponding to the processing unit that requests the read. The auxiliary storage device includes a cache control necessity information included in the read command from the data processor and a cache Wherein the control was to select a temporary storage area of the temporary storage unit for temporarily storing data read from the auxiliary storage device based on D.
By providing the above configuration, it is possible to prevent only specific data from occupying the temporary storage unit among various data related to the request source of the read data.
Hereinafter, the features of the present invention will be described in detail with reference to the drawings.

<Information processing device>
With reference to FIG. 1, the structure of the information processing apparatus which concerns on one Embodiment of this invention is demonstrated. FIG. 1 is a functional block diagram for explaining the configuration of an information processing apparatus according to an embodiment of the present invention.
The information processing apparatus 1 includes a data processor 10 and an auxiliary storage device 40.
A high-order CPU 2 shown in FIG. 1 is a CPU arranged at a high level with respect to the information processing apparatus 1 constituting a gaming machine or the like.
The data processor 10 is a processor that processes data such as images, sound, and light emission, and includes a CPU 12, an image processing unit 14, a display output unit 16, a sound processing unit 18, a sound output unit 20, a light emission processing unit 22, and a light emission output. Unit 24, interface control unit 26, and bus 28.

The CPU 12 controls the entire data processor.
The image processing unit 14 processes an image to be displayed, acquires data stored in the auxiliary storage device 40, decodes it, and draws it as an image to generate image data.
The display output unit 16 outputs the image data generated by the image processing unit 14 to a display unit such as the display 30. The display 30 is a display device such as an LCD.
The sound processing unit 18 processes an audio signal to be output, and acquires and decodes data stored in the auxiliary storage device 40 to generate sound data.
The sound output unit 20 outputs an audio signal to the speaker 32 or the like based on the generated sound data.

The light emission processing unit 22 decodes the data stored in the auxiliary storage device 40 based on the effect, and generates data for driving the light emitter such as the LED 34.
The light emission output unit 24 drives a light emitter such as an LED based on the data generated by the light emission processing unit.
An LED (light emitting diode) 34 is a semiconductor element that emits light when a voltage is applied in the forward direction, and is an example of a light emitter.
The interface control unit 26 controls an interface with the auxiliary storage device 40, and a read request requested by any one of the image processing unit 14, the sound processing unit 18, the light emission processing unit 22, and the other (CPU) is made. It is determined which processing unit or CPU has been used, and a sector count value (Sector Count) and a cache ID to be included in a read command that is a read request are set according to the determination result.

The auxiliary storage device 40 includes a storage unit (flash memory) 42, a temporary storage unit (DRAM) 44, a memory controller 46, and a bus 48.
The auxiliary storage device 40 is an SSD (Solid State Drive) including a so-called NAND flash memory. However, in a normal SSD, the temporary storage unit 44 is used as a cache memory for writing. However, the SSD used in the present invention changes the firmware of the SSD and uses the temporary storage unit 44 as a cache memory for reading. The DRAM used for writing may not be changed for reading, but a DRAM may be separately prepared for reading.
The storage unit 42 is a storage unit made up of, for example, a NAND flash memory array.
The temporary storage unit 44 is a temporary storage unit composed of, for example, a DDR DRAM, and caches read data.

The memory controller 46 includes an overall control unit 50, a sequence control unit 52, an ECC (Error Check and Correct) control unit 54, a host I / F control unit 56, a memory I / F control unit 58, and an area control unit 60. The storage device 40 is controlled.
The overall control unit 50 includes a RAM, a ROM, and the like (not shown) and controls the entire memory controller 46.
The sequence control unit 52 controls the operation of the storage unit 42 based on an internal command signal given from the memory controller 46 to the storage unit 42.
The ECC control unit 54 detects an error included in the read data based on the error collection code added to the read data, and corrects the error of the data when an error is detected.
The host I / F control unit 56 controls an interface with the host (data processing processor).
The memory I / F control unit 58 controls an interface with a NAND array that is the storage unit 42, a DRAM that is the temporary storage unit 44, or the like.
The area control unit 60 stores the data read from the storage unit 42 in the specified temporary storage area of the temporary storage unit 44 based on the cache ID specified by the data processor 10.
Each configuration of the memory controller 46 is realized by the microprocessor of the memory controller 46.
The bus 28 and the bus 48 can be connected to each other using a serial high-speed communication bus, PCIe (PCI express), or the like. The buses 28 and 48 are distinguished from each other for the sake of simplicity. It is described without.

<Interface control unit>
With reference to FIG. 2, the functional block configuration of the interface control unit shown in FIG. 1 will be described. FIG. 2 is a functional block diagram for explaining the configuration of the interface control unit provided in the data processor according to the embodiment of the present invention.
The interface control unit 26 includes a requested data amount determination unit 26a, a sector count setting unit 26b, a data request source / cache necessity determination unit 26c, a cache ID setting unit 26d, a modified read command generation unit 26e, a modified read command output unit 26f, It has.
When the request data amount determination unit 26a receives a read request from any one of the image processing unit 14, the sound processing unit 18, the light emission processing unit 22, and the CPU 12 provided in the data processor 10, from the bus, It is determined how many sectors of data should be read from the storage unit 42.
The sector count setting unit 26b sets the sector count value according to the number of sectors determined by the requested data amount determination unit 26a.
For example, according to the SATA standard, the minimum data read unit is 512 bytes, the read data amount requested by the read command is 512 bytes or less, and the requested data is stored in a single sector. The amount determination unit determines that the number of sectors is 1, and sets the sector count value 1 in the sector count setting unit 26b.
In addition, even if the read data amount requested by the read command is 512 bytes or less, if the requested data is stored across a plurality of sectors, the requested data amount determination unit has two sectors. The sector count setting unit 26b sets the sector count value 2.
Similarly, when the read data amount requested by the read command is, for example, 900 bytes, the requested data amount determination unit determines that the number of sectors is 2 when the requested data is contained in two sectors. Then, the sector count setting unit 26b sets the sector count value 2, but when the data is stored across three sectors, the requested data amount determination unit determines that the number of sectors is 3, and the sector count setting unit 26b The sector count value 3 is set at.

The request source / cache necessity determination unit 26c receives from the bus a read request output from any one of the image processing unit 14, the sound processing unit 18, the light emission processing unit 22, and the CPU 12 provided in the data processor 10. At this time, it is determined from which processing unit the request is made and whether cache control is requested or not based on information included in the read request.
The cache ID setting unit 26d sets a cache ID (region setting information) in the read command based on the determination result of the request source / cache necessity determination unit 26c. For example, when cache control is required, as shown in Table 1, the request source of the read request is associated with the cache ID, and the cache ID for storing the read data according to the request source of the read request is designated. .

The corrected read command generation unit 26e includes the sector count value set by the sector count setting unit 26b and the cache ID set by the cache ID setting unit 26d in the read command, and generates a corrected read command.
The modified read command output unit 26f includes the image processing unit 14, the sound processing unit 18, the light emission processing unit 22, the read request issued from the CPU 12, the sector count value determined by the modified read command generation unit 26d, and the cache. The ID is generated as a SATA standard command packet (FIS: Frame Information Structure) and output to the auxiliary storage device 40 as a read command.
FIG. 3A is a diagram showing a configuration of a general SATA standard read command packet, and FIG. 3B is a diagram showing an improved SATA standard read command packet configuration generated by the interface control unit 26 according to the present invention. FIG. 3C is a diagram showing the definition of CCHID (Cash ID: Cache ID) in the read command packet of the improved SATA standard.
In the modified read command generation unit 26e of the interface control unit 26 according to the present invention, instead of the conventional general command packet shown in FIG. 3A, the 13 bits to 11 bits of Count as shown in FIG. 3B. Is defined as a register representing the cache ID, the cache ID or data without cache control is stored in the register, and the sector count corresponding to the requested data is stored in the register assigned to the feature (Features) of the command packet. Set. The read request issued from the image processing unit 14, the sound processing unit 18, the light emission processing unit 22, and the CPU 12 is stored in a register assigned to the LBA of the command packet.

<Area control unit>
With reference to FIG. 4, the structure of the functional blocks of the area control unit shown in FIG. 1 will be described. FIG. 4 is a functional block diagram for explaining the configuration of the area control unit provided in the auxiliary storage device according to the embodiment of the present invention.
The area control unit 60 includes a temporary storage unit area setting unit 60a, a cache control unit 60b, and a temporary storage unit write control unit 60c.
The temporary storage unit setting unit 60a sets a temporary storage region for writing read data to the temporary storage unit 44. For example, when the temporary storage unit 44 is divided into four temporary storage regions, a cache is used. The areas for ID 0 to 3 and each cache ID are set, and the set value is supplied to the temporary storage unit write control unit 60c. The area can be arbitrarily set. For example, as shown in Table 2, a DRAM area (capacity) is set corresponding to the cache ID. Table 2 shows an example in which the temporary storage unit 44 has a capacity of 2 GB and caches four temporary storage areas. As shown in FIGS. 3B and 3C, 3 bits are used as CCHID. When assigned, eight types of cache IDs can be set, and the setting area can be arbitrarily set according to the capacity of the temporary storage unit 44.

The cache control unit 60b includes a cache ID determination unit 60d and a cache necessity determination unit 60e. The cache ID determination unit 60d and the cache necessity determination unit 60e are registers of CCHID included in the read request command received from the data processor 10. The cache ID or cache necessity is determined from the value, and the cache information (cache necessity and cache ID) is output to the temporary storage unit write control unit 60c.
The temporary storage unit write control unit 60c writes the read data from the storage unit 42 in a temporary storage area corresponding to a predetermined cache ID in the temporary storage unit 44 based on the cache information supplied from the cache control unit 60b.

  Note that the area control unit 60 is realized by a microprocessor included in the memory controller 46, and cooperates with the overall control unit 50 and the sequence control unit 52, and the LBA included in the command packet received from the data processor 10. With this register value, the memory controller 46 reads the data from the specified address of the storage unit 42 and writes the read data to the temporary storage area corresponding to the specified cache ID of the temporary storage unit 44 based on the cache information. Or the read data is output to the data processor 10 without caching.

<Operation flow of interface controller>
The operation flow of the interface control unit shown in FIG. 2 will be described with reference to FIG. FIG. 5 is a flowchart for explaining the operation of the interface control unit provided in the data processor according to the embodiment of the present invention.
In step S5, the request data amount determination unit 26a and the request source / cache necessity determination unit 26c determine whether or not a command (read command) including a read request from the image processing unit 14, the sound processing unit 18, or the like has been received. To do. If a read command is accepted, the process proceeds to steps S10 and S15.

In step S10, the requested data amount determination unit 26a determines how many sectors of data should be read from the storage unit 42 based on the requested read data amount, and the sector count setting unit 26b determines the sector count value. Set.
For example, according to the SATA standard, the minimum data read unit is 512 bytes, the read data amount requested by the read command is 512 bytes or less, and the requested data is stored in a single sector. The amount determination unit 26a determines that the number of sectors is 1, and sets the sector count value 1 in the sector count setting unit 26b.
In addition, even if the read data amount requested by the read command is 512 bytes or less, if the requested data is stored across a plurality of sectors, the requested data amount determination unit 26a has 2 sectors. And the sector count setting unit 26b sets the sector count value 2.
Similarly, if the read data amount requested by the read command is, for example, 900 bytes, and if the requested data is contained in two sectors, the requested data amount determination unit 26a determines that the number of sectors is 2 The sector count setting unit 26b sets the sector count value 2, but when the data is stored across three sectors, the requested data amount determination unit 26a determines that the number of sectors is 3, and determines the sector count. The sector count value 3 is set by the setting unit 26b.

The request source / cache necessity determination unit 26 determines whether or not cache control is necessary in step S15. If the request is a read request for which cache control is not requested (NO in step S15), a “no cache control” register. A value is set (step S20).
For example, in the case of a read request for which cache control is not requested, the request source / cache necessity determination unit 26 sets 111d as a register value without cache control.
On the other hand, in the case of a read request for which cache control is requested (YES in step S15), the request source / cache necessity determination unit 26 determines the read request request source in step S30.
Here, the request source / cache necessity determination unit 26 c receives a read request output from any one of the image processing unit 14, the sound processing unit 18, the light emission processing unit 22, and the CPU 12 provided in the data processor 10. When receiving from the bus, it is determined from which processing unit the request is received.

In response to the request source of the read request, the cache ID setting unit 26d assigns a preset cache ID (steps S41 to S44), and outputs the register value to the modified read command generation unit 26e.
In the present embodiment, the flow is described based on the relationship between the request source of the read request and the cache ID shown in Table 1.
That is, when the image processing unit 14 requests a read request (step S41), the cache ID setting unit 26d outputs the register value of the cache ID = 1 to the modified read command generation unit 26e.
When the sound processing unit 18 requests a read request (step S42), the cache ID setting unit 26d outputs the register value of the cache ID = 2 to the modified read command generation unit 26e.
Further, when the light emission processing unit 22 requests a read request (step S43), the cache ID setting unit 26d outputs the register value of the cache ID = 3 to the modified read command generation unit 26e.
When the CPU 12 requests a read request (step S44), the cache ID setting unit 26d outputs the register value of the cache ID = 0 to the modified read command generation unit 26e.

  Thereafter, in the case of “no cache control”, the modified read command generation unit 26e sets data indicating “no cache control” to the register value of the CCHID of the command packet, and features a sector count value corresponding to the read data amount. The LBA including the address of the data to be read is set as the register value, and a command packet serving as a modified read command is generated (step S50).

In the case of “with cache control”, the cache ID corresponding to the request source of the read request is set in the register value of CCHID, and the sector count value corresponding to the read data amount and the address of the data to be read are included. Is set as a register value, and a command packet to be a modified read command is generated (step S50).
After generating a command packet that is a corrected read command, the corrected read command output unit 26f outputs the corrected read command (step S60).

<Operation flow of area control unit>
With reference to FIG. 6, the operation flow of the region control unit will be described. FIG. 6 is a flowchart for explaining the operation of the area control unit 60 provided in the auxiliary storage device 40 according to the embodiment of the present invention.
In step S105, the area control unit 60 determines whether a read command has been received from the interface control unit 26. If the read command has been received, the process proceeds to step S110.

In the cache control unit 60b, the register value defined as the CCHID of the command packet that is the accepted read command is confirmed (step S110).
At this time, the cache ID determination unit 60d included in the cache control unit 60b can confirm any one of 000d, 001d, 010d, 011d, and 111d as the register value of CCHID.
The cache control unit 60b determines whether cache control is necessary and the cache ID (step S115).
For example, when the register value of CCHID is any one of 000d, 001d, 010d, and 011d, “cache control is present” is indicated, and when the register value is 111d, “no cache control” is indicated.
If the cache necessity determination unit 60e of the cache control unit 60b determines that “no cache control” (NO in step S115), the requested data is read from the storage unit 42 based on the LBA included in the command packet (step S115). In step S120, the read data is output to the data processor 10 (step S125).

On the other hand, when the cache necessity determination unit 60e of the cache control unit 60b determines that “cache control is present” in step S115 (YES in step S115), the cache ID corresponding to the register value of CCHID is recognized (step S130). .
At this time, in the cache necessity determination unit 60e, when the CCHID register value is any one of 000d, 001d, 010d, and 011d, the cache IDs are 0, 1, 2, and 3, respectively.
The cache necessity determination unit 60e outputs the cache information (cache necessity and cache ID) to the temporary storage unit write control unit 60c.
Thereafter, the memory controller 46 of the auxiliary storage device checks whether or not there is data in the temporary storage area of the temporary storage unit 44 corresponding to the cache ID recognized by the cache control unit 60b (step S135).
For example, when the cache ID is 0, the cache ID determination unit 60d reads data from the temporary storage area in which the address of the temporary storage unit 44 is 00h to FFFFFFFh, and determines whether there is data.
If there is data in the temporary storage area corresponding to the specified cache ID in the temporary storage unit 44 (YES in step S135), the data is read from the temporary storage unit 44 (step S140), and the data read to the data processor 10 is read. Is output (step S125).

On the other hand, when there is no data in the area of the temporary storage unit 44 corresponding to the cache ID recognized by the cache control unit 60b (NO in step S135), the requested data is stored from the storage unit 42 based on the LBA included in the command packet. Read (step S145), write the read data to the temporary storage area of the temporary storage unit 44 corresponding to the designated cache ID (step S150), and output (transfer) the read data to the data processor 10 (step S125).
In step S125 described above, the read data is output (transferred) from the temporary storage area of the temporary storage unit 44 to the data processor 10, but the data processor 10 temporarily stores the data in the temporary storage unit 44. You may comprise so that data may be read from an area | region.
Note that when data is written to the temporary storage area of the temporary storage unit 44 (cache), if the allocated temporary storage area is free, it is stored in the free temporary storage area, and if there is no free space, the oldest data is discarded. And cache there (LRU algorithm (Least Recently Used)). It is also possible to cache using an LFU (Least Frequently Used) algorithm.

  According to the present embodiment, in the data processor 10, the interface control unit 26 determines the request source of each processing unit that requests reading, and sets the temporary storage area of the temporary storage unit 44 according to the processing unit. Is generated. On the other hand, the memory controller 46 (control unit) of the auxiliary storage device 40 recognizes the presence / absence of cache control and the cache ID based on the cache information included in the read command from the data processor 10, and performs cache control. Since control was performed so as to select a predetermined temporary storage area as a temporary storage location of read data, various data (image data, audio data, light emission data, other data) related to the request source of the read data Of these, it can be avoided that only specific data occupies the temporary storage unit 44.

<Configuration, operation and effect of exemplary embodiment of the present invention>
<First aspect>
The information processing apparatus 1 according to this aspect includes a storage unit 42 that stores a plurality of types of data corresponding to a plurality of data types, and a temporary storage unit 44 that temporarily stores data read from the storage unit 42 in a temporary storage area. A plurality of types of data are read from the auxiliary storage device 40 based on a request from the upper CPU 2 and the auxiliary storage device 40 including the memory controller 46 that controls the storage unit 42 and the temporary storage unit 44. An information processing apparatus 1 including a data processing processor 10 that outputs data to a predetermined processing unit, wherein the data processing processor 10 responds to cache control necessity information related to read data and a processing unit that requests reading. And an interface control unit 26 for setting the cache ID, and the memory controller 46 of the auxiliary storage device 40 is a data processing process. Control is performed to select a temporary storage area of the temporary storage unit 44 that temporarily stores data read from the auxiliary storage device 40 based on the cache control necessity information and the cache ID included in the read command from the server 10 It is characterized by that.
According to this aspect, the data processor 10 sets the cache ID corresponding to the cache control necessity information related to the read data and the processing unit that requests the read, by the interface control unit 26. The memory controller 46 of the auxiliary storage device 40 temporarily stores the data read from the auxiliary storage device 40 based on the cache control necessity information and the cache ID included in the read command from the data processor 10. Since 44 temporary storage areas are selected, only specific data occupies the temporary storage unit among various data (image data, audio data, light emission data, other data) related to the request source of the read data. It is to avoid that.

<Second aspect>
The interface control unit 26 according to the present aspect determines from which of the plurality of processing units requesting reading, and determines whether or not the request requires cache control. The determination unit 26c is provided.
According to this aspect, since the request source / cache necessity determination unit 26c determines from which of the plurality of processing units requested to read, the request source of the read data can be determined. Since it is determined whether or not the request requires cache control, when the request requires cache control, it is to avoid that only specific data occupies the temporary storage unit.

<Third aspect>
The processing units of this aspect are an image processing unit 14, a sound processing unit 18, a light emission processing unit 22, and a CPU 12.
According to this aspect, even if the request source of the read data is the image processing unit 14, the sound processing unit 18, the light emission processing unit 22, and the CPU 12, various data (image data, audio data, light emission, etc.) related to the request source. It is to avoid that only specific data among the data and other data) occupies the temporary storage unit.

<4th aspect>
The memory controller 46 of the auxiliary storage device 40 according to this aspect is characterized in that two or more temporary storage areas are provided in the temporary storage unit 44 by dividing into image data and other data.
According to this aspect, the image data that tends to occupy the cache memory, the other audio data, and the temporary storage area for caching the light emission data are used separately, so that the audio data and the light emission data with a small allowable processing delay are read out. In addition, it can be performed using a cache, and sound and light can be output appropriately.

<5th aspect>
The information processing method of this aspect includes a storage unit 42 that stores a plurality of types of data corresponding to a plurality of data types, and a temporary storage unit 44 that temporarily stores data read from the storage unit 42 in a temporary storage area; A plurality of types of data are read from the auxiliary storage device 40 based on a request from the upper CPU 2 and the auxiliary storage device 40 having a memory controller 46 that controls the storage unit 42 and the temporary storage unit 44, and predetermined An information processing method by an information processing apparatus 1 including a data processing processor 10 that outputs data to the processing unit, wherein the data processing processor 10 performs cache control necessity information and read request processing related to read data An interface control step for setting a cache ID according to the memory unit, and a memory controller 46 of the auxiliary storage device 40 The temporary storage area of the temporary storage unit 44 that temporarily stores the data read from the auxiliary storage device 40 is selected based on the cache control necessity information and the cache ID included in the read command from the data processor 10. The control step is executed.
According to this aspect, the data processor 10 sets the cache control necessity information regarding the read data and the cache ID corresponding to the processing unit that requests the read. The memory controller 46 of the auxiliary storage device 40 temporarily stores the data read from the auxiliary storage device 40 based on the cache control necessity information and the cache ID included in the read command from the data processor 10. Since 44 temporary storage areas are selected, only specific data occupies the temporary storage unit among various data (image data, audio data, light emission data, other data) related to the request source of the read data. It is to avoid that.

DESCRIPTION OF SYMBOLS 1 ... Information processing apparatus, 2 ... Host CPU, 10 ... Data processor, 12 ... CPU, 14 ... Image processing part, 16 ... Display output part, 18 ... Sound processing part, 26 ... Interface control part, 26a ... Requested data amount Determining unit, 26b ... sector count setting unit, 26c ... request source / cache necessity determining unit, 26d ... cache ID setting unit (CCHID setting unit), 26e ... modified read command generating unit, 26f ... modified read command output unit, 40 ... Auxiliary storage device 42 ... Storage unit 44 ... Temporary storage unit 46 ... Memory controller 60 ... Area control unit 60a ... Temporary storage unit region setting unit 60b ... Cache control unit 60c ... Temporary storage unit write control unit 60d: Cache ID setting unit determination unit, 60e: Cache necessity determination unit

Claims (5)

A storage unit for storing a plurality of types of data corresponding to a plurality of data types;
A temporary storage unit that temporarily stores data read from the storage unit in a temporary storage area;
An auxiliary storage device comprising: the storage unit; and a control unit that controls the temporary storage unit;
A data processor that reads a plurality of types of data from the auxiliary storage device based on a request from a host CPU and outputs the data to a predetermined processing unit;
The data processor includes an interface control unit that sets cache control information related to read data and a cache ID corresponding to a processing unit that requests read.
The control unit of the auxiliary storage device temporarily stores data read from the auxiliary storage device based on the cache control necessity information and the cache ID included in the read command from the data processor An information processing apparatus controlled to select a temporary storage area. The interface control unit
A request source / cache necessity determination unit is provided for determining which of the plurality of processing units requesting the reading is a request and determining whether the request requires cache control. The information processing apparatus according to claim 1.   The information processing apparatus according to claim 1, wherein the processing unit is an image processing unit, a sound processing unit, a light emission processing unit, and a CPU.   4. The control unit of the auxiliary storage device is provided with two or more temporary storage areas in the temporary storage unit divided into image data and other data. Information processing device. A storage unit for storing a plurality of types of data corresponding to a plurality of data types;
A temporary storage unit that temporarily stores data read from the storage unit in a temporary storage area;
An auxiliary storage device comprising: the storage unit; and a control unit that controls the temporary storage unit;
An information processing method by an information processing apparatus comprising: a data processor that reads a plurality of types of data from the auxiliary storage device based on a request from a host CPU and outputs the data to a predetermined processing unit;
The data processing processor executes an interface control step for setting cache ID according to the cache control necessity information related to the read data and the processing unit requesting the reading,
The control unit of the auxiliary storage device temporarily stores data read from the auxiliary storage device based on the cache control necessity information and the cache ID included in the read command from the data processor An information processing method characterized by executing a step of controlling to select a temporary storage area.

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