JP2018032062A - Test item generation method and arithmetic unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To create an appropriate test item corresponding to a multi-core.SOLUTION: A test item generation method for generating a test item in an arithmetic unit comprising multiple CPU cores that execute multiple tasks and shared resources that the multiple CPU cores access is configured as follows. Namely, a computer identifies a task that accesses the shared resources, among the multiple tasks, the computer classifies the multiple tasks for each of the CPU cores that execute the tasks, the computer identifies an execution order of the classified multiple tasks within the CPU core, and the computer generates multiple task execution order rows in which execution orders of two or more tasks that are suited to the identified execution order of the multiple tasks in the CPU core and access the shared resources to be executed by different CPU cores are exchanged mutually, such that the test item is generated.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a test item generation method and an arithmetic device.

In recent years, the calculation amount of electronic devices has been increasing year by year due to multifunctionalization, and CPU performance required for electronic devices has increased. Therefore, this is dealt with by increasing the number of CPUs installed in the electronic device or increasing the number of CPU cores built in the CPU. That is, in any case, the processing capability is improved by mounting a plurality of CPU cores in an electronic device (multi-core). When the electronic device includes a plurality of CPU cores, the operation is more complicated than when only a single CPU core is provided, and it is not easy to create a test item for verifying this operation.
Patent Document 1 discloses a method for verifying a design, and extracts resources required to execute a discrete test case or a set of related test cases for a design. Includes steps. The method further includes building a simulation model based on the extracted resources, and executing the simulation model using only the extracted resources rather than the entire design, thereby providing a discrete test model. Testing a particular function or group of interrelated functions represented by a case or a set of related test cases to verify the design.

JP 2007-164780 A

  In the invention described in Patent Document 1, an appropriate test item corresponding to the multi-core cannot be created.

A test item generation method according to a first aspect of the present invention is a test item generation method for generating a test item in an arithmetic device including a plurality of CPU cores for executing a plurality of tasks and a shared resource accessed by the plurality of CPU cores. The computer specifies a task for accessing the shared resource among the plurality of tasks, the computer classifies the plurality of tasks for each CPU core to be executed, and the computer Specifying the execution order of the plurality of classified tasks in the CPU core, and the computer is adapted to the execution order of the plurality of tasks in the specified CPU core and executed on different CPU cores. Task execution in which the execution order of two or more tasks accessing the shared resource is interchanged By creating multiple columns, and generating a said test items.
An arithmetic device according to a second aspect of the present invention includes a storage unit in which test items generated by the test item generation method according to the first aspect and check logic for confirming the test items are stored.

  According to the present invention, it is possible to create an appropriate test item corresponding to the multi-core.

The figure which shows the hardware constitutions of the test item generation device The figure which shows the functional structure of a test item generation apparatus The figure which shows the hardware constitutions of ECU The figure which shows the functional composition of ECU Diagram showing test item generation overview The figure which shows an example of operation | movement of a test item production | generation part Flow chart showing operation of test item generator The figure which shows the functional structure of the test item generation apparatus in the modification 2.

(First embodiment)
A first embodiment of a test item generation apparatus 100 that uses the test item generation method according to the present invention will be described below with reference to FIGS. The test item generation device 100 generates a test item used in a test executed in the ECU 200 described later. In the present embodiment, the components of the computer program are called “tasks”. A task is composed of one or more CPU instructions. A task is executed by one of the CPU cores, and depending on the task, access to a shared resource 203 described later is required. In addition, what indicates the order in which a plurality of tasks are executed is referred to as a “task execution sequence”. In this embodiment, it is assumed that the test item is composed of two or more task execution permutations. That is, the test executed in ECU 200 is to execute predetermined tasks in a predetermined order according to the generated test items.

(Hardware configuration of test item generator)
FIG. 1 is a diagram illustrating a hardware configuration of the test item generation apparatus 100. The test item generation device 100 includes a CPU 101, a ROM 102, a RAM 103, and an interface 104. The CPU 101 controls the operation of the test item generation device 100. The CPU 101 realizes functions to be described later by expanding a program (not shown) stored in the ROM 102 into the RAM 103 and executing the program. The RAM 103 is used for storing a working area when the above-described program is executed and a test item generated. The interface 104 is an electronic data input / output port, and exchanges information between the test item generation device 100 and other devices. The test item generation device 100 acquires input information 6 necessary for generating a test item via the interface 104. The input information 6 is a program source code, a design document, reverse engineering information of a CPU executing the program, a test document, and the like, and includes a plurality of tasks executed by the CPU core of the ECU 200.

(Functional configuration of test item generator)
FIG. 2 is a diagram illustrating a functional configuration of the test item generation device 100. Each function shown in FIG. 2 is realized by the CPU 101 executing a program stored in the ROM 102. The test item generation device 100 includes a correspondence information unit 111, a specific information unit 112, an order information unit 113, and a test item generation unit 114 as functions thereof. Also, the RAM 103 is provided with a correspondence information storage area 121, a specific information storage area 122, an order information storage area 123, and a test item storage area 124. Here, an outline of each function will be described, and details of each function will be described later.

The correspondence information storage area 121, the specific information storage area 122, the order information storage area 123, and the test item storage area 124 are storage areas provided in the RAM 103.
The correspondence information unit 111 analyzes the input information 6 read from the interface 104, specifies which CPU core of the ECU 200 executes each of the plurality of tasks included in the input information 6, and executes the CPU Classify tasks by core. Then, correspondence information indicating the task classification result is generated. The correspondence information generated by the correspondence information unit 111 is stored in the correspondence information storage area 121. The identification information unit 112 analyzes the input information 6 and identifies which of the tasks included in the input information 6 is a task that accesses a shared resource 203 described later. And the specific information which shows the specified task is produced | generated. The specific information generated by the specific information unit 112 is stored in the specific information storage area 122.

The order information unit 113 analyzes the input information 6 and specifies the execution order of tasks executed by the same CPU core. And the order information which shows the execution order of the task performed with the same CPU core which is the specified information is produced | generated. The order information generated by the order information unit 113 is stored in the order information storage area 123. The order information may indicate the execution order of tasks for each CPU core, or may indicate a mixture of tasks executed by a plurality of CPU cores.
The test item generation unit 114 generates a test item based on the information generated by the correspondence information unit 111, the specific information unit 112, and the order information unit 113, and stores the generated test item in the test item storage area 124. The test items generated by the test item generation unit 114 are output to the ECU 200 via the interface 104.

The correspondence information unit 111, the specific information unit 112, and the order information unit 113 are all easy to process when the source code is the input information 6. The correspondence information unit 111, the specific information unit 112, and the order information unit 113 perform a search equivalent to the source code by utilizing lexical analysis or the like when the design document or the test document is the input information 6. In document analysis, it is possible to eliminate lexical analysis according to the document format.
When identifying the task that accesses the shared resource 203 by analyzing the source code, the specific information unit 112 recursively searches not only the task that directly accesses the shared resource 203 but also the call of the task. Tasks that indirectly access 203 are also identified. In addition, indirect access may be limited by specifying the number of task calls.

(ECU hardware configuration)
FIG. 3 is a diagram illustrating a hardware configuration of the ECU 200. The ECU 200 includes a first core 201, a second core 202, a shared resource 203, a ROM 204, a RAM 205, and a test item input unit 206. The first core 201 and the second core 202 are CPU cores provided in the ECU 200. The ECU 200 may include a plurality of CPUs having a single core, or may include a CPU having a plurality of cores. The shared resource 203 is a resource accessed from the first core 201 and the second core 202. For example, the shared resource 203 is one of a part of the RAM 205, a CPU register included in the ECU 200, an actuator (not shown), a sensor, and a communication bus. It is. The test item input unit 206 is an input / output port for electronic data, and the test item generated by the test item generation apparatus 100 is input thereto.

(Functional configuration of ECU)
FIG. 4 is a diagram illustrating a functional configuration of the ECU 200. Each function shown in FIG. 4 is realized by the first core 201 or the second core 202 executing a program stored in the ROM 204. The ECU 200 includes a normal mode unit 211, an operation verification mode unit 212, a mode switching unit 213, and a test execution data storage area 215 as its functions. The ECU 200 receives the test item input from the interface 104 of the test item generation apparatus 100 at the test item input unit 206. ECU 200 stores the received test item in test execution data storage area 215. ECU 200 also stores check logic for checking the execution result of the test item in test execution data storage area 215. The check logic may be created by an operator or the test item generation apparatus 100.

ECU 200 has two operation modes, a normal mode and an operation verification mode. The ECU 200 becomes effective in either the normal mode or the operation verification mode according to the operation command of the mode switching unit 213 operated by the user 3. When the normal mode is valid, the normal mode unit 211 controls the operation of the ECU 200, and when the operation verification mode is valid, the operation verification mode unit 212 controls the operation of the ECU 200.
The normal mode unit 211 performs various arithmetic processes based on an input from a sensor (not shown) included in the ECU 200 or a communication interface (not shown). The operation verification mode unit 212 sequentially executes each of the plurality of task execution permutations constituting the test item stored in the test execution data storage area 215 and collates the execution result with the check logic. The operation verification mode unit 212 may store the verification result in a storage unit (not shown) so that the verification result can be accessed from the outside. In addition, the operation verification mode unit 212 may notify the collation result using the ECU 200 or a notification unit provided in the device to which the ECU 200 is connected, for example, a speaker or a light.

(Overview of test item generation)
FIG. 5 is a diagram showing an outline of test item generation by the test item generation device 100.
Source code 4001 is a source code of a program executed in ECU 200. As indicated by reference numerals 4002 to 4007, the source code 4001 includes detailed information on the tasks f1 to f6 constituting the program, for example, whether each task accesses the shared resource 203 or not. Further, the source code 4001 includes information on the CPU core in which each task is executed and information on the order in which each task is executed in each CPU core. Note that the execution order of tasks executed by different CPU cores may change every time it is executed, and only the execution order of tasks executed by the same CPU core is revealed from the description of the source code 4001. .

When the source code 4001 is input as the input information 6 to the test item generation device 100, the correspondence information unit 111 analyzes the source code 4001 and identifies a CPU core on which each task is executed as indicated by reference numeral 4009. That is, among the tasks f1 to f6 included in the test items, the tasks f1, f3, and f5 are executed by the first core 201, and the tasks f2, f4, and f6 are specified to be executed by the second core 202.
The specific information unit 112 analyzes the source code 4001 and, as indicated by reference numeral 4008, among the tasks f1 to f6 included in the test item, the tasks that access the shared resource 203 of the ECU 200 are f3 and f4. Identify.

The order information unit 113 analyzes the source code 4001 and identifies order information indicating the execution order of tasks executed by the same CPU core, as indicated by reference numeral 4010. However, although the execution order of tasks is shown for each CPU core in FIG. 5, the execution order may be shown in a state where tasks executed by a plurality of CPU cores are mixed. For example, the execution order of tasks “f1, f2, f3, f4, f5, f6” may be specified as the order information.
The test item generation unit 114 generates a task execution permutation based on the information generated by the correspondence information unit 111, the specific information unit 112, and the order information unit 113, that is, information of reference numerals 4008, 4009, and 4010. The test item generation unit 114 is adapted to the execution order of a plurality of tasks in the specified CPU core, and the execution order of the tasks f3 and f4 that access the shared resources 203 respectively executed by different CPU cores is interchanged. A plurality of task execution permutations, here two, are generated and stored as test items in the test item storage area 124 as indicated by reference numeral 4012. Thereby, in the test item generation device 100, test items including the tasks f1 to f6 are created.

(Operation example of test item generator)
In the example shown in FIG. 5, since there are only two tasks accessing the shared resource 203, the operation of the test item generation unit 114 will be described using a slightly more complicated example. Here, when the first core 201 executes the tasks f2, f3, f5, and f7, the second core 202 executes the tasks f4 and f6, and the f2-f6 accesses the shared resource 203, the test item generation unit The test items generated by 114 will be described. Here, it is assumed that the task is executed from a task having a small number in the same CPU core. In the following, the order in which tasks and execution sequences to be described later are executed is expressed by using a right arrow “→”. For example, execution of the task f3 after the task f2 is expressed as “f2 → f3”.

  First, the test item generation unit 114 specifies the order in which tasks that access the shared resource 203 are executed for each CPU core, and generates an execution sequence. An execution sequence is a task executed in the same CPU core, in which a plurality of tasks that access the shared resource 203 are arranged in the execution order of tasks indicated by the order information stored in the order information storage area 123. It is. Here, the generated execution sequences are called α and β. As many execution sequences as the number of CPU cores are generated. The fact that the execution sequence α is composed of f2, f3, and f5 is hereinafter denoted as α0 (f2, f3, f5). Similarly, the execution sequence β is β0 (f4, f6).

Hereinafter, the procedure for the test item generation unit 114 to generate the task execution sequence will be continued with reference to FIG.
Next, the test item generation unit 114 creates a permutation using all the generated execution sequences, that is, all sequences that can be rearranged using all the generated execution sequences. In this example, as shown in the unexpanded column of FIG. 6, two of α → β and β → α are created. Hereinafter, each of the created permutations is referred to as a “permutation element”.

  Then, the test item generation unit 114 expands α and β for each of the generated permutation elements to increase the permutation elements that are variations of the execution order. For example, the expansion of α means that the first task among the tasks constituting α is separated and the number of separated tasks is added to the name of α. That is, α0 (f2, f3, f5) is expanded from f2 to α1 (f3, f5). Since this expansion has increased the number of elements constituting the permutation element, further rearrangement becomes possible. In addition, although what expanded the permutation element here is also called the "permutation element", you may call it a "development sequence." Further, although an example in which the top task constituting the execution sequence is separated is shown here, the last task constituting the execution sequence may be separated.

  Therefore, α → β, which is one of the permutation elements, is expressed as f2 → α1 (f3, f5) → β as shown in the column of “α expansion first time” in FIG. 6 by expanding α once. Expanded in the order of f2 → β → α1 (f3, f5). When α is further expanded, permutation elements α → β are expanded into a total of three as shown in the column “α expansion second time” in FIG. At this time, α2 (f5) in which α0 (f2, f3, f5) is expanded twice is f5 itself and cannot be expanded any more. Therefore, β is expanded next.

Further, permutation elements α → β are expanded into a total of five by expanding β as shown in the column “β expansion first time” in FIG. At this time, β1 (f6) in which β0 (f4, f6) is expanded once is f6 itself and cannot be expanded any more. Therefore, the expansion process of the permutation element of α → β is completed.
The test item generation unit 114 expands the permutation element β → α in the same manner as the expansion of the permutation element α → β described above. Since this process is the same as the development of the permutation element α → β, the description and the illustration in FIG. 6 are omitted.

  The execution order of the task f7 that does not access the shared resource 203 is added to the permutation element generated in this way, and this is used as the task execution permutation. The execution order of tasks that do not access the shared resource 203 is any one place that follows the execution order in the same CPU core. For example, when the execution order excluding f7 is f2-> f3-> f5-> f4-> f6, the execution order of f7 is later than f5 executed by the same CPU core, so it is inserted immediately after each of f5, f4, f6. be able to. That is, in this case, although three execution orders can be generated depending on the insertion location of f7, only one of the three is adopted as a task execution permutation, that is, one of the test items. This is because even if the execution order of tasks that do not access the shared resource 203 changes, the test is not affected.

(Flowchart of test item generator)
FIG. 7 is a flowchart showing the operation of the test item generation unit 114. The execution subject of each step in the flowchart described below is the CPU 101 of the test item generation apparatus 100.
In step S301, the task that accesses the shared resource 203 is specified for each CPU core with reference to the outputs of the correspondence information unit 111 and the specific information unit 112. In subsequent step S302, the output of the order information unit 113 is referred to, and the execution order of tasks that access the shared resource 203 is specified for each CPU core.

  In subsequent step S303, an execution sequence is generated. As described above, the execution sequence is a task executed in the same CPU core, and a plurality of tasks that access the shared resource 203 are assigned to the task execution order indicated by the order information stored in the order information storage area 123. They are arranged. That is, in step S303, the same number of execution sequences as the CPU cores are generated. In subsequent step S304, a permutation of execution sequences, that is, a plurality of permutation elements are created. The number of permutation elements created here is the factorial of the number of execution sequences generated in step S303. This is because there is no restriction on the order of execution of tasks executed by different CPU cores. In the example of FIG. 6, this corresponds to creation of α → β and β → α.

  In the subsequent step S305, the first execution series, for example, α is set as a development target. In the subsequent step S306, the first task is expanded from the execution sequence to be expanded. In the example of FIG. 6, it is equivalent to developing α0 (f2, f3, f5) from f2 → α1 (f3, f5). In the subsequent step S307, a permutation element including the order change accompanying the expansion in step S306 is generated. In a succeeding step S308, it is determined whether or not the execution sequence to be expanded can be further expanded. If it is determined that further expansion is possible, the process returns to step S306. If it is determined that further expansion is impossible, the process proceeds to step S309. In the example of FIG. 6, the process proceeds to step S309 after the second α expansion and the first β expansion.

  In step S309, it is determined whether there is an undeployed execution sequence. If it is determined that there is an unexpanded execution sequence, the process proceeds to step S310. If it is determined that there is no undeployed execution sequence, the process proceeds to step S311. In step S310, one of unexecuted execution sequences is set as a deployment target, and the process returns to step S306. In step S311, a task that has not accessed the shared resource 203 is added to the permutation element to obtain a task execution permutation. As a result, a task execution sequence can be generated for all combinations of the execution orders of the tasks f2, f4, and f6 and the tasks f3 and f5 that are executed by different CPU cores and that access the shared resource 203. In the subsequent step S312, the generated task execution sequence is stored in the test item storage area 124, and the flowchart of FIG.

According to the first embodiment described above, the following operational effects are obtained.
(1) A test item generation method for generating a test item in an arithmetic device including a plurality of CPU cores that execute a plurality of tasks and a shared resource 203 accessed by the plurality of CPU cores, that is, the ECU 200, is as follows. It is executed by the generation apparatus 100. This test item generation method includes the following four. The first is to specify a task that accesses the shared resource 203 among a plurality of tasks, which is executed by the specifying information unit 112. The second is to classify a plurality of tasks executed by the correspondence information unit 111 for each CPU core to be executed. The third is to specify the execution order in the CPU core of a plurality of classified tasks executed by the order information unit 113. Fourth, two or more tasks that are executed by the test item generation unit 114 and that match the execution order of the plurality of tasks in the specified CPU core and access the shared resources 203 respectively executed by different CPU cores The test items are generated by generating a plurality of task execution permutations in which the execution orders are replaced with each other.
Therefore, test items are created by changing the execution order of tasks that access the shared resource 203, so that appropriate test items corresponding to the multi-core can be created.

(2) In the test item generation of the test item generation device 100, a task execution permutation is generated for all combinations of task execution orders that are executed by different CPU cores and access the shared resource 203.
Therefore, even if the number of tasks is large and the number of combinations is enormous, it is possible to create test items without omissions.

(3) Test item generation by the test item generation unit 114 includes the following five items. The first is to generate an execution sequence in which tasks executed in the same CPU core are arranged in the execution order in the specified CPU core (step S303 in FIG. 7). The second is to generate a permutation of a plurality of execution sequences (step S304 in FIG. 7). Third, for each permutation, the execution sequence is expanded by separating the first or last task constituting the execution sequence from the execution sequence, and the execution sequence of the expanded execution sequence and the separated task is maintained. One or a plurality of development sequences generated by exchanging all orders with other execution series and other tasks is generated (steps S306 and S307 in FIG. 7). Fourthly, for each of the development columns, generation of the expansion sequence is repeated until the execution sequence cannot be expanded (repeating until step S308 in FIG. 7 is negatively determined). Fifthly, each of a plurality of development sequences that are generated by repetition and cannot be developed into execution sequences is set as a task execution sequence (step S312 in FIG. 7).
Therefore, even if the number of tasks is large and the number of combinations is enormous, it is possible to create test items without omission by repeating generation of execution sequence permutations and generation of expanded sequences.

(4) The arithmetic unit, that is, the ECU 200 includes a storage unit, that is, a test execution data storage area 215 in which test items generated by the above-described test item generation method and check logic for confirming the test items are stored.
Therefore, the ECU 200 can execute the test item in the ECU 200 that is an actual machine, and further check the test result using the check logic. This test item is generated by the test item generation device 100, and is a test item that does not confirm the access order of the shared resources 203 of each task in the same order.

(5) The arithmetic unit, that is, the ECU 200 includes an operation verification mode unit 212 that sequentially executes each of a plurality of task execution permutations constituting the test item, and a mode switching unit 213 that operates the operation verification mode unit 212. Therefore, ECU 200 can execute the test by switching the operation mode.

(Modification 1)
The correspondence information unit 111, the specific information unit 112, and the order information unit 113 store the input information 6 that has been input before, and the newly input information 6 matches the previous input information 6. The analysis results stored in the respective storage areas may be output to the test item generation unit 114. According to the first modification, the analysis can be omitted when there is no change in the input information 6. The effect of this modification is that the information input to the correspondence information unit 111, the specific information unit 112, and the order information unit 113 is different, and only a part of them is changed. This is noticeable when only the order is changed.

(Modification 2)
FIG. 8 is a diagram illustrating a functional configuration of the test item generation device 100 according to the second modification. The test item generation device 100 may further include a correspondence information change point analysis unit 131, a specific information change point analysis unit 132, an order information change point analysis unit 133, and a change point test item generation unit 134.
The correspondence information change point analysis unit 131 analyzes the change point of the input information 6, refers to the correspondence information stored in the correspondence information storage area 121, and sets the correspondence information related to the changed part of the input information 6 as the change point test item. The data is output to the generation unit 134. The specific information change point analysis unit 132 analyzes the change point of the input information 6, refers to the specific information stored in the specific information storage area 122, changes the specific information related to the change part of the input information 6 to the change point test item The data is output to the generation unit 134. The order information change point analysis unit 133 analyzes the change point of the input information 6, refers to the order information stored in the order information storage area 123, and changes the order information related to the changed part of the input information 6 to the change point test item. The data is output to the generation unit 134.

The change point test item generation unit 134 outputs the correspondence information change point analysis unit 131, the specific information change point analysis unit 132, the output of the order information change point analysis unit 133, and the test items stored in the test item storage area 124. Used to generate only test items that need to be modified. Then, the changed point test item generation unit 134 updates the test items stored in the test item storage area 124.
According to the second modification, the processing of the test item generation device 100 can be reduced when the input information 6 is slightly changed.

Although the program executed by the test item generation device 100 is stored in the ROM (not shown), the program may be stored in the RAM 103 or a flash memory (not shown). In addition, the test item generation apparatus 100 may use the interface 104 to read a program from another apparatus via a medium that can use the interface 104 when necessary. Here, the medium refers to, for example, a storage medium that can be attached to and detached from the input / output interface, or a communication medium, that is, a wired, wireless, or optical network, or a carrier wave or digital signal that propagates through the network. Also, part or all of the functions realized by the program may be realized by a hardware circuit or FPGA.
The above-described embodiments and modifications may be combined.
Although various embodiments and modifications have been described above, the present invention is not limited to these contents. Other embodiments conceivable within the scope of the technical idea of the present invention are also included in the scope of the present invention.

DESCRIPTION OF SYMBOLS 100 ... Test item production | generation apparatus 111 ... Corresponding information part 112 ... Specific information part 113 ... Order information part 114 ... Test item production | generation part 124 ... Test item storage area 201 ... 1st core 202 ... 2nd core 203 ... Shared resource 212 ... Operation | movement Verification mode part 213 ... Mode switching part 215 ... Test execution data storage area

Claims (5)

A test item generation method for generating a test item in an arithmetic device including a plurality of CPU cores for executing a plurality of tasks and a shared resource accessed by the plurality of CPU cores,
Identifying a task for accessing the shared resource among the plurality of tasks;
A computer classifying the plurality of tasks for each CPU core to be executed;
A computer specifying an execution order in the CPU core of the plurality of classified tasks;
Tasks in which the computer is adapted to the execution order of the plurality of tasks in the specified CPU core and the execution order of two or more tasks accessing the shared resources respectively executed by different CPU cores is interchanged A test item generation method comprising: generating the test item by generating a plurality of execution permutations. The test item generation method according to claim 1,
In the test item generation, the test item generation method generates the task execution permutation for all combinations of execution orders of tasks that are respectively executed by different CPU cores and access the shared resource. The test item generation method according to claim 1,
The test item is generated by
Generating a plurality of execution sequences in which the tasks executed in the same CPU core are arranged in the execution order based on all of the plurality of tasks; generating a permutation of the plurality of execution sequences;
For each of the permutations, the execution sequence is expanded by separating the first or last task constituting the execution sequence from the execution sequence, and the execution order of the expanded execution sequence and the separated task is Generating one or a plurality of expansion sequences that are generated by rearranging all the orders with other execution sequences and other tasks while keeping them;
For each of the expansion columns, repeating the generation of the expansion column until the execution sequence cannot be expanded;
A test item generation method comprising: each of the plurality of expansion sequences generated by the repetition and incapable of expanding the execution series is set as the task execution sequence.   An arithmetic unit comprising a storage unit storing test items generated by the test item generation method according to claim 1 and check logic for confirming the test items. The arithmetic unit according to claim 4,
An operation verification mode section for sequentially executing each of a plurality of task execution permutations constituting the test item;
An arithmetic device further comprising a mode switching unit that operates the operation verification mode unit.

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