JP2018032061A - Storage controller, and storage system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a storage controller, and a storage system capable of suppressing an increase of a response time to a write request.SOLUTION: A CM#i has an FPGA#i (or, designated LSI) directly connected to a CA#i, that, responding to a write request received from a host unit 120, identifies a logical address of CM in charge corresponding to LUN, which is identified based on the write request referring to a corresponding information list. The CM#i sets the logical address of the CM in charge identified by the FPGA#i (or, designated LSI) as the address, and transfers the write request and a piece of write data relevant to the write request.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a storage control device and a storage system.

  2. Description of the Related Art Conventionally, there is a storage system that mounts a plurality of housings storing a plurality of storage devices such as HDD (Hard Disk Drive) and SSD (Solid State Drive) and provides a storage area of the storage device to a host device. Also, in such a storage system, a plurality of storage control devices that perform access control between the host device and the storage device may be provided.

  As a prior art, for example, when data writing is instructed, data is written to the local cache and mirror cache, and data of the local cache is written to the primary disk and data of the mirror cache is written to the secondary disk. There is. Also, there are multiple RAID (Redundant Array of Inexpensive Disks) controllers for providing cache coherency in a RAID system that provides multiple host computers with read / write access to a shared storage device.

International Publication No. 2004/114115 JP-T-2004-538532

  However, in the related art, in a storage system including a plurality of storage control devices, the response time for a write request from the host device may increase. For example, it may take time to transfer data from the host device to the storage control device, and the response time to the write request may increase.

  In one aspect, an object of the present invention is to suppress an increase in response time to a write request.

  According to an aspect of the present invention, the integrated circuit includes an interface that receives a request from a host device, and an integrated circuit that is directly connected to the interface and that can reconfigure an internal circuit or a dedicated integrated circuit. However, in response to receiving the request from the interface, the correspondence between the storage device and the logical address of the storage control device that processes the request to the storage device among the plurality of storage control devices that can communicate with each other The logical address of the storage control device corresponding to the storage device identified from the received request is identified, the identified logical address is set as the destination, and the received request is transferred. A storage control device is proposed.

  According to an aspect of the present invention, there is provided a storage system including a plurality of storage control devices, wherein any one of the plurality of storage control devices receives a request from a host device, and the interface Corresponding information indicating the correspondence between the storage device and the logical address of the storage control device that processes the request to the storage device among the plurality of storage control devices that can communicate with each other in response to receiving the request from The logical address of the storage control device corresponding to the storage device specified from the received request is specified, the specified logical address is set as the destination, and the received request is transferred. Reconfigurable integrated circuit or dedicated integrated circuit and A storage system having is proposed.

  According to one aspect of the present invention, an increase in response time to a write request can be suppressed.

FIG. 1 is an explanatory diagram of an example of the storage control method according to the embodiment. FIG. 2 is a block diagram illustrating a hardware configuration example of CM # i. FIG. 3 is an explanatory diagram showing a specific example of the correspondence information list 300. FIG. 4 is a block diagram illustrating a functional configuration example of FPGA # i of CM # i. FIG. 5 is an explanatory diagram showing an operation example of the storage system 100 at the time of a write request. FIG. 6 is an explanatory diagram showing an example of address conversion at the time of a write request. FIG. 7A is a sequence diagram (part 1) illustrating an example of a write request processing procedure of the storage system 100. FIG. 7B is a sequence diagram (part 2) illustrating an example of the write request processing procedure of the storage system 100. FIG. 8 is a sequence diagram illustrating an example of a read request processing procedure of the storage system 100. FIG. 9 is a flowchart illustrating an example of a specific processing procedure of request processing of FPGA #i.

  Embodiments of a storage control device and a storage system according to the present invention will be described below in detail with reference to the drawings.

(Embodiment)
FIG. 1 is an explanatory diagram of an example of the storage control method according to the embodiment. In FIG. 1, the storage system 100 includes CE (Controller Enclosure) $ 0, $ 1 and DE (Device Enclosure) $ 0, $ 1. The storage system 100 is, for example, a system having a RAID configuration that stores data such as RAIDs 5 and 6 in a redundant manner.

  CE $ 0 includes CMs (Controller Modules) # 0 and # 1. CE $ 1 has CMs # 2 and # 3. Each CM # 0 to # 3 is an example of a storage control device that controls access to the storage under its control. The CMs # 0 to # 3 are communicably connected to each other via an FRT (Front End Router) 110.

  An example of the hardware configuration of CMs # 0 to # 3 will be described later with reference to FIG.

  The FRT 110 is an example of a connection unit that includes an FRT-SW (switch) 111 and connects CMs so as to communicate with each other. The FRT 110 may include, for example, a plurality of adapters conforming to PCIe (Peripheral Component Interconnect Express), and may be connected to the CMs # 0 to # 3 by cables or the like corresponding to PCIe.

  In FIG. 1, only the FRT 110 is shown as the FRT connecting the CMs, but the FRT may be made redundant by two or more FRTs.

  In addition, the host device 120 is connected to the CMs # 0 to # 3. The CMs # 0 to # 3 and the host device 120 are connected via a SAN (Storage Area Network) using, for example, FC (Fibre Channel), iSCSI (Internet Small Computer System Interface), or the like. Further, the CMs # 0 to # 3 and the host device 120 may be connected via a LAN (Local Area Network), the Internet, or the like.

  In FIG. 1, the case where one host device 120 is connected to CMs # 0 to # 3 has been described as an example, but the present invention is not limited to this. For example, each of a plurality of host devices may be connected to one or more CMs among CMs # 0 to # 3.

  DE $ 0 and $ 1 have a plurality of storage devices D. The storage device D may be, for example, an HDD or an SSD, or may be a logical unit (LU: Logical Unit) that is a logical storage device. In FIG. 1, DE $ 0 and $ 1 have the storage device D, but CE $ 0 and $ 1 may have the storage device D, for example.

  DE $ 0 is connected to CMs # 0 and # 1. The CMs # 0 and # 1 control access to the storage device D installed in the DE $ 0 in response to a request from the host device 120 or another CM. In the example of FIG. 1, DE $ 0 includes RAID groups RG0 to RG3 that CM # 0 is responsible for and RAID groups RG4 to RG7 that CM # 1 is responsible for. In the RAID group, a plurality of storage devices D are combined into one storage device. In this case, for example, CM # 0 controls access to the RAID groups RG0 to RG3 in response to a request from the host device 120 or another CM.

  In addition, DE $ 1 is connected to CMs # 2 and # 3. The CMs # 2 and # 3 control access to the storage device D installed in the DE $ 1 in response to a request from the host device 120 or another CM. In the example of FIG. 1, DE $ 1 includes RAID groups RG0 to RG3 that CM # 2 is responsible for and RAID groups RG4 to RG7 that CM # 3 is responsible for. In this case, for example, CM # 2 controls access to the RAID groups RG0 to RG3 in response to a request from the host device 120 or another CM.

  Note that CE $ 0 and DE $ 0 are realized as storage devices mounted in one housing, for example. Similarly, CE $ 1 and DE $ 1 are realized as storage devices mounted in one housing. Further, the number of CEs included in the storage system 100 is not limited to two, and the number of CMs included in each CE is not limited to two.

  Here, in the conventional storage system, at the time of a write request, the data that is subjected to RAID calculation from the host device is transferred to the first CM in charge of the RAID calculation (hereinafter referred to as “charged CM”), and then the transferred data is transferred to Data redundancy is performed by copying (mirroring) the data to the memory of the second CM (hereinafter referred to as “mirror CM”).

  However, since a response is returned to the host device upon completion of redundancy, the response time for the write request increases accordingly. Note that the RAID calculation includes, for example, data division and parity calculation performed in response to a request (write request, read request) from the host device 120.

  On the other hand, when transferring data for RAID calculation from the host device to the responsible CM, the physical connection relationship may cause the other CM to pass through. At this time, the CM that has received data from the host device (hereinafter referred to as “receive CM”) determines the assigned CM from the data and transfers it to the assigned CM. Response time for write requests increases.

  Specifically, for example, when the receive CM receives data from the host device, the receive CM temporarily stores the data in the memory. Then, the CPU (Central Processing Unit) of the receive CM analyzes the data stored in the memory, determines which CM performs the RAID operation, and transfers the data to the responsible CM.

  When the responsible CM receives data from the receive CM, the responsible CM stores the data in the memory. Then, the CPU of the responsible CM analyzes the data stored in the memory, determines which CM is to be copied (mirrored), and transfers the data (copy data) to the mirror CM. In addition, when the responsible CM receives the completion of the mirroring process from the mirror CM, it returns a response to the host device via the receive CM.

  Thus, in the conventional storage system, the data received from the host device is temporarily stored in the memory and then processed by the CPU. Therefore, even if the receive CM is not the responsible CM, the data received from the host device is temporarily stored in the memory, and processing load and processing time for memory access are required.

  When accessing a CA (Channel Adapter) outside the PCIe tree without going through the receive CM, the host apparatus can broadcast the write request as an interrupt from the CA to all CMs at the time of a write request from the host apparatus. It is conceivable that the responsible CM can directly receive the write request from.

  In the write request packet, data LUN (Logical Unit Number), LBA (Logical Block Addressing), and size information are stored. For this reason, each CM confirms the content of the received write request and instructs DMA (Direct Memory Access). When broadcasting write data from the host device, mirroring is also possible by preparing a cache area for storing data transmitted from all CAs in all CMs.

  However, when there are a large number of CMs, for example, in a 24CM configuration, the interrupt frequency is increased 24 times, and the interrupt (exception) processing of each CM increases. Since the interrupt processing is performed while stopping normal operations such as RAID calculation, if the number of interrupts increases, the performance of the system will be reduced. Further, as CA increases, the area (number) for storing write data from the host device also increases, resulting in increased waste of system resources.

  Therefore, in the present embodiment, in the receive CM, a request from the host device 120 without using a CPU or memory using an integrated circuit such as an FPGA (Field Programmable Gate Array) or a dedicated LSI (Large-Scale Integration). Are identified, the transfer destination is specified, and data transfer to the responsible CM or mirror CM is performed, thereby suppressing an increase in response time to a request from the host device 120.

(CM # 0 to # 3 hardware configuration example)
Next, a hardware configuration example of CMs # 0 to # 3 will be described. In the following description, an arbitrary CM among CMs # 0 to # 3 may be expressed as “CM # i” (i = 0, 1, 2, 3).

  FIG. 2 is a block diagram illustrating a hardware configuration example of CM # i. In FIG. 2, CM # i includes CPU # i, MEM (Memory) #i, IOC (Input / Output Controller) #i, CA # i, FPGA # i, and SW # i. . Each component is connected by a bus.

  The CPU #i controls the entire CM #i. The CPU #i has a DMA function. For example, DMA is a technique for reading and writing to MEM # i directly from the PCIe bus (without the operation of CPU # i). Note that the CPU #i has a DMA function here, but may have a DMA controller that controls communication in the DMA transfer separately from the CPU #i.

  MEM # i stores data and programs. The MEM # i includes, for example, a ROM (Read Only Memory), a RAM (Random Access Memory), and a flash ROM. Specifically, for example, a flash ROM or ROM stores various programs, and a RAM is used as a work area of the CPU #i. The program stored in MEM # i is loaded into CPU # i, thereby causing CPU # i to execute the coded process. MEM # i may also be used as a cache memory that temporarily stores data and programs.

  The IOC #i is an I / O control unit that controls access (I / O) to the storage device D. CA # i is an interface for communicating with the host device 120. The CA # i has an adapter that conforms to, for example, LAN, SAN, FC, and the like. The FPGA #i is an integrated circuit that can reconfigure an internal circuit. SW # i is an interface for communicating with other CMs. SW # i is, for example, a PCIe switch having a port for connecting to another CM.

  In CM # i, CPU # i / SW # i, IOC # i / SW # i, and FPGA # i / SW # i are connected by, for example, a PCIe bus. The CPU # i / MEM # i are connected by a memory bus. Further, the IOC # i / DE (DE $ 0, $ 1) are connected by, for example, SAS (Serial Attached SCSI).

  In FIG. 2, CM # i has FPGA # i, but the present invention is not limited to this. For example, the processing performed by FPGA #i in CM # i may be realized by a dedicated LSI.

(Specific example of correspondence information list 300)
Next, a specific example of the correspondence information list 300 included in the CM # i FPGA # i illustrated in FIG. 2 will be described.

  FIG. 3 is an explanatory diagram showing a specific example of the correspondence information list 300. In FIG. 3, the correspondence information list 300 includes correspondence information 300-1 to 300-10 that represent LUN information, responsible CM information, and mirror CM information in association with each other. The LUN information indicates a LUN that identifies a logical unit (LU) as an access destination. The assigned CM information indicates the logical address of the assigned CM. The mirror CM information indicates a logical address of the mirror CM.

  For example, the correspondence information 300-1 indicates the logical address “0000_2000_0000_0000” of the assigned CM # 0 when a request to the LUN0 occurs. Further, the correspondence information 300-1 indicates the logical address “0000 — 2200 — 0000 — 0000” of the mirror CM # 2 when a request to the LUN 0 occurs.

(Functional configuration example of CM # i FPGA # i)
FIG. 4 is a block diagram illustrating a functional configuration example of FPGA # i of CM # i. In FIG. 4, FPGA # i includes a reception unit 401, a specification unit 402, and a transfer unit 403. Specifically, for example, each function (receiving unit 401 to transfer unit 403) is defined using HDL (Hardware Description Language), and the HDL description is logically synthesized and given to FPGA #i. Is realized.

  The accepting unit 401 accepts a request from the host device 120 via CA # i. Here, the request is, for example, a write request (write request) or a read request (read request) with respect to any RAID group in DE $ 0 and $ 1. The request includes, for example, the LUN information of the access destination and the data size of write data (write data) or read data (read data).

  Specifically, for example, in response to the reception of a request from the host apparatus 120, the CA #i first instructs the FPGA #i of the DMA write of the request. As a result, the request from the host device 120 is sent directly to the FPGA #i without being stored in the MEM # i.

  In response to receiving a request from the host device 120, the specifying unit 402 specifies the destination of the request. Specifically, for example, the specifying unit 402 determines the command type of the request. Here, when determining that the request is a write request, the specifying unit 402 specifies the LUN included in the write request. This LUN is information for identifying a logical unit as an access destination. Then, the identifying unit 402 refers to the correspondence information list 300 to identify responsible CM information and mirror CM information corresponding to the identified LUN.

  As a result, the logical address of the assigned CM #j and the mirror CM #k can be specified as the write request destination. The assigned CM # j is a CM in charge of RAID calculation of write data related to the write request. The mirror CM # k is a CM in charge of mirroring the write data related to the write request. At the time of a write request, CM # i may be either a responsible CM # j or a mirror CM # k.

  When determining that the request is a read request, the specifying unit 402 specifies the LUN included in the read request. This LUN is information for identifying a logical unit as an access destination. Then, the identifying unit 402 refers to the correspondence information list 300 and identifies responsible CM information corresponding to the identified LUN.

  As a result, the logical address of the assigned CM #j can be specified as the destination of the read request. The assigned CM # j is a CM in charge of RAID calculation of the read data related to the read request. At the time of a read request, CM # i may be the responsible CM # j.

  The transfer unit 403 transfers the request from the host device 120 to the destination of the request specified by the specifying unit 402. Specifically, for example, in the case of a write request, the transfer unit 403 sets the logical address of the specified responsible CM # j and the logical address of the mirror CM # k as the destination, and sends the write request to the SW #. forward to i.

  As a result, address conversion is performed in SW # i, and the write request from the host device 120 is transferred to the responsible CM # j and mirror CM # k via the FRT 110, respectively. In the case of a write request, after a write request is sent from the host device 120, write data related to the write request is transferred. The transfer unit 403 stores the immediately preceding destination (write request destination), and transfers the write data from the host device 120 to the destination. A write request transfer example will be described later with reference to FIGS.

  Further, in the case of a read request, the transfer unit 403 sets the logical address of the specified responsible CM #j as the destination of the read request and transfers it to SW # i. As a result, address conversion is performed in SW # i, and a read request from the host apparatus 120 is transferred to the responsible CM # j via the FRT 110.

  Note that the PCIe bus basically performs peer-to-peer (P2P) communication, but in this case, the FPGA # i indicates whether the data is sent from the responsible CM # j or the mirror CM # k. It becomes impossible to judge. For this reason, for example, the virtual bus (bus) / Dev (device) / func (function) is assigned to the mirror CM # k so that the FPGA #i can communicate with the responsible CM # j and the mirror CM # k. assign.

  Thereby, a receiving port for communicating with each of the assigned CM #j and the mirror CM #k can be provided. As a technology for allocating virtual Bus / Dev / Func, for example, existing SR-IOV (Single Root I / O Virtualization) can be used. SR-IOV is a function that supports virtualization on the PCI device side.

  Further, each function of the above-described FPGA #i may be realized by a dedicated integrated circuit (for example, a dedicated LSI). Specifically, for example, each function (specification unit 402 to transfer unit 403) of FPGA # i is defined using HDL (or a circuit diagram), and circuit information obtained by logically synthesizing the HDL description. Based on this, it is possible to manufacture a dedicated LSI that realizes the function.

(Write request transfer example)
Next, a transfer example of a write request will be described with reference to FIGS.

  FIG. 5 is an explanatory diagram showing an operation example of the storage system 100 at the time of a write request. FIG. 6 is an explanatory diagram showing an example of address conversion at the time of a write request. Here, it is assumed that CA # 0 of CM # 0 receives a write request from the host apparatus 120 to “0000_0000_0000_0000” of LUN3. That is, CM # 0 is a receive CM.

  In this case, when FPGA # 0 receives a write request from CA # 0, it specifies LUN 3 included in the write request. Then, as illustrated in FIG. 6, FPGA # 0 refers to the correspondence information list 300 and specifies the logical address “0000_2300_0000_0000” of the responsible CM # 3 corresponding to LUN3 and the logical address “0000_2100_0000_0000” of the mirror CM # 1 To do.

  Next, FPGA # 0 sets the logical address “0000 — 2300 — 0000 — 0000” of the responsible CM # 3 and the logical address “0000 — 2100 — 0000 — 0000” of the mirror CM # 1 as the destination of the write request, and transfers them to SW # 0.

  When SW # 0 receives a write request from FPGA # 0, SW # 0 refers to memory map 600, performs address conversion of the write request, and outputs the result to FRT110. Specifically, when SW # 0 receives a write request addressed to the logical address of CM # 3 in charge, SW # 0 outputs the write request to a path corresponding to the range of logical addresses “0000 — 2300 — 0000 — 0000 to 0000 — 2380 — 0000 — 0000”. When SW # 0 receives a write request addressed to the logical address of CM # 1 in charge, SW # 0 outputs the write request to a path corresponding to the range of logical addresses “0000_2100_0000_0000 to 0000_2180_0000_0000”.

  As a result, NTV (Non Transparent Virtual) address conversion is performed, and address conversion to the physical address space is performed in the FRT 110 (NTL (Non Transparent Link) address conversion). Specifically, the FRT-SW 111 converts the assigned CM # 3 SW # 3 and mirror CM # 1 SW # 1 corresponding to each path into logical addresses, and the write request is sent to each SW # 1, SW # 1. Transferred to # 3. In each of the switches SW # 1 and # 3, conversion to a physical address on each of the MEMs # 1 and # 3 is performed, and a write request is written to the MEMs # 1 and # 3.

(Write request processing procedure of storage system 100)
Next, a write request processing procedure of the storage system 100 will be described. Here, a case where the receive CM is different from the assigned CM and the mirror CM will be described as an example.

  7A and 7B are sequence diagrams illustrating an example of a write request processing procedure of the storage system 100. FIG. In the sequence diagram of FIG. 7A, first, when the CA # i of the receive CM # i receives a write request (FCP Command) from the host device 120, it outputs the write request from the host device 120 to the FPGA #i (step S701). ).

  Next, when receiving a write request from CA # i, FPGA # i of receive CM # i executes a request process for transferring the write request to the responsible CM # j and mirror CM # k (step S702). At this time, the FPGA #i assigns a virtual Bus / Dev / Func to the mirror CM # k.

  As a result, IOCB (I / O command (control) block) is stored in the response queue of the MEM # j of the responsible CM # j and the MEM # k of the mirror CM # k. The IOCB is data used for protocol flow control and the like, and includes information indicating the content of the write request, for example.

  A specific processing procedure of the request processing of FPGA # i will be described later with reference to FIG.

  Next, the CA # i notifies the CPU # j (driver) of the responsible CM # j and the CPU # k (driver) of the mirror CM # k of the interrupt via the FPGA # i (step S703). In FPGA # i, the logical addresses of the immediately preceding destination, that is, the responsible CM # j and mirror CM # k, which are the transfer destination of the write request, are stored. For this reason, the interrupt from CA # i is notified to the logical addresses of the responsible CM # j and mirror CM # k, respectively.

  When the CPU #j of the assigned CM #j and the CPU #k of the mirror CM #k receive an interrupt, they read the interrupt factor (step S704). At this time, the CPU #j of the assigned CM #j directly accesses the CA #i and reads the interrupt factor. On the other hand, the CPU #k of the mirror CM # k accesses the virtual Bus / Dev / Func of the FPGA #i and reads the copied interrupt factor.

  If the interrupt factor is IOCB, the CPU #j, #k refers to the DMA information (write data size, etc.) in the MEM # j, #k, and writes the cache area for the write data. Preparations such as securing are performed.

  Then, the FPGA #i waits for the completion of the preparation in each of the CPUs #j and #k, and notifies the CA #i of the fact when the preparations of the respective CPUs #j and #k are completed (step S705). . When the preparations of the CPUs #j and #k are completed, the CA #i requests the host device 120 to transfer data (step S706).

  In the sequence diagram of FIG. 7B, first, when receiving a data transfer request from CA # i, the host apparatus 120 starts transfer of write data (step S707). The CA #i transfers the write data to the MEM #j of the responsible CM #j and the MEM #k of the mirror CM #k via the FPGA #i (Step S708). For example, a data correction code (BCC: Block Check Code) is added to the write data.

  When the data transfer is completed, the CA #i stores the IOCB that has completed the data transfer in the response queue of each MEM #j and #k via the FPGA #i (step S709). Next, the CA # i notifies the CPU # j (driver) of the responsible CM # j and the CPU # k (driver) of the mirror CM # k of the interrupt via the FPGA # i (step S710).

  When each of the CPUs #j and #k receives an interrupt, the CPU #j and #k read the interrupt factor and mow it (step S711). When each CPU #j, #k confirms that the data transfer has been completed normally, it stores the IOCB indicating the completion of the data transfer in the response queue of each MEM #j, #k and registers (IOCB DMA activation) ) Is written (step S712). At this time, the CPU #j directly accesses the CA #i, while the CPU #k accesses the virtual Bus / Dev / Func of the FPGA #i.

  Next, the FPGA #i waits for the completion of the data transfer in each of the CPUs #j and #k, and when the data transfer of each of the CPUs #j and #k is normally completed, notifies the CA #i to that effect (step # 1). S713). When the data transfer of each of the CPUs #j and #k is normally completed, the CA #i transmits a status transfer normal completion notification to the host device 120 (step S714).

  When the status transfer normal completion notification is transmitted to the host device 120, the CPU #j, #k is notified that the processing has been normally completed. As a result, in each CPU #j, #k, Post-processing such as releasing the cache area is performed.

  Accordingly, the FPGA #i of the receive CM #i can analyze the destination of the write request from the host device 120 and transfer the write request and the write data to the responsible CM #j and the mirror CM #k.

(Read request processing procedure of the storage system 100)
Next, a read request processing procedure of the storage system 100 will be described. Here, a case where the receive CM is different from the assigned CM will be described as an example.

  FIG. 8 is a sequence diagram illustrating an example of a read request processing procedure of the storage system 100. In the sequence diagram of FIG. 8, first, when receiving a read request (FCP Command) from the host apparatus 120, the CA # i of the receive CM # i outputs the read request from the host apparatus 120 to the FPGA #i (step S801). ).

  Next, when receiving a read request from CA # i, FPGA # i of receive CM # i executes request processing for transferring the read request to responsible CM # j (step S802). As a result, the IOCB is stored in the response queue of MEM # j of the assigned CM # j.

  A specific processing procedure of the FPGA # i request processing will be described later with reference to FIG.

  Next, the CA #i of the receive CM #i notifies the CPU #j (driver) of the responsible CM #j of an interrupt via the FPGA #i (step S803). In FPGA # i, the logical address of the CM # j in charge as the immediately preceding destination, that is, the transfer destination of the read request is stored. Therefore, an interrupt from CA # i is notified to the logical address of the responsible CM # j.

  When the CPU # j of the assigned CM # j receives an interrupt, it directly accesses the CA # i and reads the interrupt factor (step S804). Here, if the interrupt factor is IOCB, the CPU #j refers to the DMA information in the MEM # j and prepares to write the read data in the area in the MEM # j read by the CA # i. Is called.

  When the preparation of CPU #j is completed and the transfer data (read data) is ready for transfer, CA #i reads the read data from MEM #j and transfers the read data (BCC removal) to host device 120. (Step S805). Then, when the transfer of the read data is completed, CA #i transmits a Read data transmission normal completion notification to the host device 120 (step S806).

  When the read data transmission normal completion notification is transmitted to the host device 120, the CPU #j is notified that the processing has been normally completed. As a result, the CPU #j reads the read data in the MEM #j. Post-processing such as deleting is performed.

  As a result, the FPGA #i of the receive CM #i can analyze the destination of the write request from the host device 120 and transfer the read request to the responsible CM #j.

(Specific processing procedure of request processing)
Next, a specific processing procedure of FPGA # i request processing will be described.

  FIG. 9 is a flowchart illustrating an example of a specific processing procedure of request processing of FPGA #i. In the flowchart of FIG. 9, first, the FPGA #i receives a request from the host apparatus 120 from the CA #i (step S901). Next, the FPGA #i determines whether or not the accepted request is a write request (step S902).

  Here, in the case of a write request (step S902: Yes), the FPGA #i specifies an access destination LUN included in the write request (FCP Command) (step S903). Next, the FPGA #i refers to the correspondence information list 300 and identifies the logical address of the assigned CM #j and mirror CM #k corresponding to the identified LUN of the access destination (step S904).

  Then, the FPGA #i sets the logical addresses of the specified responsible CM # j and mirror CM # k as the destination of the write request, and forwards the write request to the SW # i (step S905). A series of processing ends. Thus, the write request from the host device 120 can be transferred to the responsible CM # j and the mirror CM # k by the FPGA # i.

  In step S902, in the case of a read request (step S902: No), the FPGA #i specifies the LUN of the access destination included in the write request (FCP Command) (step S906). Next, the FPGA #i refers to the correspondence information list 300 and identifies the logical address of the assigned CM #j corresponding to the identified access destination LUN (step S907).

  Then, the FPGA #i sets the logical address of the identified responsible CM # j as the destination of the read request, transfers the read request to the SW # i (step S908), and ends the series of processing according to this flowchart. . Thereby, the read request from the host device 120 can be transferred to the responsible CM # j by the FPGA # i.

  As described above, according to CM # i according to the embodiment, in response to reception of a write request from host apparatus 120 by FPGA # i (or a dedicated LSI) directly connected to CA # i. Thus, referring to the correspondence information list 300, the logical address of the assigned CM #j corresponding to the LUN identified from the write request can be identified. According to CM # i, the logical address of the specified responsible CM # j is set as the destination by FPGA # i (or a dedicated LSI), and the write request and the write data related to the write request are transferred. Can do.

  As a result, the transfer destination of the write request from the host device 120 is analyzed without using the CPU #i or MEM # i by using the FPGA #i (or dedicated LSI) directly connected to the CA # i. , The write request and write data can be transferred to the responsible CM # j. As a result, there is no need to temporarily store data from the host device 120 in the MEM # i at the time of the write request, and an increase in response time to the write request can be suppressed as compared with the case where the CPU # i processes. In addition, since an interrupt to the CPU #i does not occur at the time of a write request, it is possible to prevent the processing being executed by the CPU #i from being interrupted and improve the performance of the storage system 100.

  Further, according to CM # i, by referring to the correspondence information list 300 using FPGA # i (or a dedicated LSI), the logical address of the mirror CM # k corresponding to the LUN specified from the write request is specified. can do. According to CM # i, the logical address of the specified mirror CM # k is set as the destination by FPGA # i (or a dedicated LSI), and the write request and the write data related to the write request are transferred. Can do.

  As a result, the FPGA #i (or dedicated LSI) directly connected to CA # i is used to transfer the write request and write data to the mirror CM # k without going through the CPU # i or MEM # i. Write data can be made redundant. In addition, since data can be transferred simultaneously to the assigned CM # j and mirror CM # k, the response time for the write request is shortened compared to the case where data is transferred from the assigned CM # k to the mirror CM # k. be able to.

  Further, according to CM # i, in response to reception of a read request from the host device 120 by FPGA # i (or a dedicated LSI), the correspondence information list 300 is referred to and specified from the read request. The logical address of the assigned CM # j corresponding to the LUN can be specified. According to CM # i, the read request can be transferred by setting the logical address of the specified responsible CM # j as the destination by FPGA # i (or a dedicated LSI).

  As a result, the transfer destination of the read request from the host apparatus 120 is analyzed without using the CPU #i and the MEM # i by using the FPGA #i (or dedicated LSI) directly connected to the CA # i. , The read request can be transferred to the responsible CM # j. In addition, since an interrupt to the CPU #i does not occur at the time of a read request, it is possible to prevent the processing being executed by the CPU #i from being interrupted and improve the performance of the storage system 100.

  The following additional notes are disclosed with respect to the embodiment described above.

(Appendix 1) An interface connected to the host device;
An integrated circuit that is directly connected to the interface and that can reconfigure internal circuits or a dedicated integrated circuit, and
The integrated circuit comprises:
In response to receiving a write request from the host device via the interface, the storage control device logic that processes a request to the storage device among a plurality of storage control devices that can communicate with the storage device. Referring to the correspondence information indicating the correspondence relationship with the address, specify the logical address of the storage control device corresponding to the storage device specified from the write request,
A storage control apparatus, wherein the specified logical address is set as a destination, and the write request and write data relating to the write request are transferred.

(Supplementary Note 2) The correspondence information further indicates a correspondence relationship between the storage device and a second storage device that mirrors write data related to a request to the storage device.
The integrated circuit comprises:
Referencing the correspondence information, further specifying a logical address of a second storage control device corresponding to the storage device specified from the write request,
The storage control device according to appendix 1, wherein the specified logical address of the second storage control device is set as a destination, and the write request and the write data relating to the write request are transferred.

(Appendix 3) The integrated circuit is:
In response to receiving a read request from the host device via the interface, referring to the correspondence information, identify a logical address of the storage control device corresponding to the storage device identified from the read request,
The storage control device according to appendix 1 or 2, wherein the read request is transferred by setting the specified logical address as a destination.

(Supplementary note 4) The storage control device according to any one of Supplementary notes 1 to 3, wherein the integrated circuit capable of reconfiguring the internal circuit is a field programmable gate array (FPGA).

(Supplementary Note 5) A storage system including a plurality of storage control devices,
One of the plurality of storage control devices is a storage control device,
An interface connected to the host device;
In response to receiving a write request from the host device via the interface, the storage control device logic that processes a request to the storage device among a plurality of storage control devices that can communicate with the storage device. Referring to the correspondence information indicating the correspondence relationship with the address, the logical address of the storage control device corresponding to the storage device identified from the write request is identified, the identified logical address is set as the destination, and the write An integrated circuit capable of reconfiguring an internal circuit for transferring a request and write data related to the write request, or a dedicated integrated circuit;
A storage system comprising:

100 storage system 110 FRT
111 FRT-SW
120 Host device 300 Corresponding information list 401 Accepting unit 402 Specifying unit 403 Transfer unit # 0 to # 3, #i, #j, #k CM
#I CPU
#I MEM
#I IOC
#I CA
#I FPGA
#I SW

Claims (4)

An interface connected to the host device;
An integrated circuit that is directly connected to the interface and that can reconfigure internal circuits or a dedicated integrated circuit, and
The integrated circuit comprises:
In response to receiving a write request from the host device via the interface, the storage control device logic that processes a request to the storage device among a plurality of storage control devices that can communicate with the storage device. Referring to the correspondence information indicating the correspondence relationship with the address, specify the logical address of the storage control device corresponding to the storage device specified from the write request,
A storage control apparatus, wherein the specified logical address is set as a destination, and the write request and write data relating to the write request are transferred. The correspondence information further indicates a correspondence relationship between the storage device and a second storage device that mirrors write data related to a request to the storage device.
The integrated circuit comprises:
Referencing the correspondence information, further specifying a logical address of a second storage control device corresponding to the storage device specified from the write request,
The storage control device according to claim 1, wherein the logical address of the identified second storage control device is set as a destination, and the write request and the write data relating to the write request are transferred. The integrated circuit comprises:
In response to receiving a read request from the host device via the interface, referring to the correspondence information, identify a logical address of the storage control device corresponding to the storage device identified from the read request,
3. The storage control apparatus according to claim 1, wherein the read request is transferred by setting the specified logical address as a destination. A storage system including a plurality of storage control devices,
One of the plurality of storage control devices is a storage control device,
An interface connected to the host device;
In response to receiving a write request from the host device via the interface, the storage control device logic that processes a request to the storage device among a plurality of storage control devices that can communicate with the storage device. Referring to the correspondence information indicating the correspondence relationship with the address, the logical address of the storage control device corresponding to the storage device identified from the write request is identified, the identified logical address is set as the destination, and the write An integrated circuit capable of reconfiguring an internal circuit for transferring a request and write data related to the write request, or a dedicated integrated circuit;
A storage system comprising:

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