JP2018026385A - Manufacturing method of light-emitting diode chip - Google Patents
Manufacturing method of light-emitting diode chip Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 72
- 238000005520 cutting process Methods 0.000 claims abstract description 33
- 230000010354 integration Effects 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 239000013078 crystal Substances 0.000 claims abstract description 6
- 238000002360 preparation method Methods 0.000 claims abstract description 4
- 229910052594 sapphire Inorganic materials 0.000 claims description 11
- 239000010980 sapphire Substances 0.000 claims description 11
- 239000005304 optical glass Substances 0.000 claims description 4
- 239000011347 resin Substances 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- 239000004576 sand Substances 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 55
- 238000000034 method Methods 0.000 description 11
- 230000003287 optical effect Effects 0.000 description 7
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 5
- 229910002601 GaN Inorganic materials 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000005488 sandblasting Methods 0.000 description 2
- 230000011218 segmentation Effects 0.000 description 2
- 239000006061 abrasive grain Substances 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 239000002173 cutting fluid Substances 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005323 electroforming Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
Description
本発明は、発光ダイオードチップの製造方法に関する。 The present invention relates to a method for manufacturing a light-emitting diode chip.
サファイア基板、GaN基板、SiC基板等の結晶成長用基板の表面にn型半導体層、発光層、p型半導体層が複数積層された積層体層が形成され、この積層体層に交差する複数の分割予定ラインによって区画された領域に複数のLED(Light Emitting Diode)等の発光デバイスが形成されたウエーハは、分割予定ラインに沿って切断されて個々の発光デバイスチップに分割され、分割された発光デバイスチップは携帯電話、パソコン、照明機器等の各種電気機器に広く利用されている。 A stacked body layer in which a plurality of n-type semiconductor layers, light-emitting layers, and p-type semiconductor layers are stacked is formed on the surface of a crystal growth substrate such as a sapphire substrate, a GaN substrate, or a SiC substrate. A wafer in which a plurality of light emitting devices such as LEDs (Light Emitting Diodes) are formed in a region partitioned by the planned division line is cut along the planned division line and divided into individual light emitting device chips, and the divided light emission Device chips are widely used in various electric devices such as mobile phones, personal computers, and lighting devices.
発光デバイスチップの発光層から出射される光は等方性を有しているため、結晶成長用基板の内部にも照射されて基板の裏面及び側面からも光が出射する。然し、基板の内部に照射された光のうち空気層との界面での入射角が臨界角以上の光は界面で全反射されて基板内部に閉じ込められ、基板から外部に出射されることがないから発光デバイスチップの輝度の低下を招くという問題がある。 Since the light emitted from the light emitting layer of the light emitting device chip is isotropic, the light is emitted also to the inside of the crystal growth substrate, and the light is also emitted from the back and side surfaces of the substrate. However, of the light irradiated to the inside of the substrate, light whose incident angle at the interface with the air layer is greater than the critical angle is totally reflected at the interface and confined inside the substrate, and is not emitted outside from the substrate. Therefore, there is a problem that the luminance of the light emitting device chip is lowered.
この問題を解決するために、発光層から出射された光が基板の内部に閉じ込められるのを抑制するために、基板の裏面に透明部材を貼着して輝度の向上を図るようにした発光ダイオード(LED)が特開2014−175354号公報に記載されている。 In order to solve this problem, a light emitting diode in which a transparent member is attached to the back surface of the substrate to improve the luminance in order to prevent light emitted from the light emitting layer from being confined inside the substrate. (LED) is described in Japanese Patent Application Laid-Open No. 2014-175354.
然し、特許文献1に開示された発光ダイオードでは、基板の裏面に透明部材を貼着することにより輝度が僅かに向上したものの十分な輝度が得られないという問題がある。 However, the light emitting diode disclosed in Patent Document 1 has a problem that sufficient luminance cannot be obtained although the luminance is slightly improved by sticking a transparent member to the back surface of the substrate.
本発明はこのような点に鑑みてなされたものであり、その目的とするところは、十分な輝度が得られる発光ダイオードチップの製造方法及び発光ダイオードチップを提供することである。 The present invention has been made in view of these points, and an object of the present invention is to provide a method of manufacturing a light-emitting diode chip and a light-emitting diode chip that can obtain sufficient luminance.
本発明によると、発光ダイオードチップの製造方法であって、結晶成長用の透明基板上に発光層を含む複数の半導体層が形成された積層体層を有し、該積層体層の表面に互いに交差する複数の分割予定ラインによって区画された各領域にそれぞれLED回路が形成されたウエーハを準備するウエーハ準備工程と、該ウエーハの裏面に全面に渡り複数の貫通孔の形成された透明基板の表面を貼着して一体化ウエーハを形成する一体化工程と、該一体化工程を実施した後、該一体化ウエーハの該透明基板の裏面に該ウエーハの各LED回路に対応して複数の溝を形成する透明基板加工工程と、該透明基板加工工程を実施した後、該ウエーハを該分割予定ラインに沿って該透明基板と共に切断して該一体化ウエーハを個々の発光ダイオードチップに分割する分割工程と、を備えたことを特徴とする発光ダイオードチップの製造方法が提供される。 According to the present invention, there is provided a method for manufacturing a light-emitting diode chip, comprising: a stacked body layer in which a plurality of semiconductor layers including a light-emitting layer are formed on a transparent substrate for crystal growth; A wafer preparation step of preparing a wafer in which LED circuits are formed in each region partitioned by a plurality of intersecting division lines, and the surface of the transparent substrate having a plurality of through holes formed on the entire back surface of the wafer And an integrated process for forming an integrated wafer, and after the integrated process, a plurality of grooves corresponding to each LED circuit of the wafer are formed on the back surface of the transparent substrate of the integrated wafer. After the transparent substrate processing step to be formed and the transparent substrate processing step are performed, the wafer is cut along with the transparent substrate along the division line to form the integrated wafer into individual light emitting diode chips. Manufacturing method of the light emitting diode chip is provided which is characterized by comprising a division step of dividing, the.
好ましくは、透明基板加工工程において形成される溝の断面形状は、三角形状、四角形状、又は半円形状の何れかである。好ましくは、透明基板加工工程において形成される溝は、切削ブレード、エッチング、サンドブラスト、レーザーの何れかで形成される。 Preferably, the cross-sectional shape of the groove formed in the transparent substrate processing step is any one of a triangular shape, a quadrangular shape, and a semicircular shape. Preferably, the groove formed in the transparent substrate processing step is formed by any one of a cutting blade, etching, sand blasting, and laser.
好ましくは、該透明基板は、透明セラミックス、光学ガラス、サファイア、透明樹脂の何れかで形成され、該一体化工程において該透明基板は透明接着剤でウエーハに接着される。 Preferably, the transparent substrate is formed of any one of transparent ceramics, optical glass, sapphire, and transparent resin, and in the integration step, the transparent substrate is bonded to the wafer with a transparent adhesive.
本発明の発光ダイオードチップは、LEDの裏面に貼着された透明部材に複数の貫通孔が形成され更にその裏面に溝が形成されているので、透明部材の表面積が増大することに加え、LEDの発光層から照射され透明部材に進入した光の一部が外部に出射する際、溝部分で複雑に屈折して出射する。従って、透明部材から出射する際に透明部材と空気層との界面での入射角が臨界角以上の光の割合が減少し、透明部材から出射される光の量が増大して発光ダイオードチップの輝度が向上する。 In the light-emitting diode chip of the present invention, since a plurality of through holes are formed in the transparent member attached to the back surface of the LED and grooves are formed on the back surface, the surface area of the transparent member is increased. When a part of the light irradiated from the light emitting layer and entering the transparent member is emitted to the outside, it is refracted and emitted in a complicated manner at the groove portion. Accordingly, when the light is emitted from the transparent member, the ratio of light whose incident angle at the interface between the transparent member and the air layer is greater than the critical angle is decreased, and the amount of light emitted from the transparent member is increased, so that the light emitting diode chip Brightness is improved.
以下、本発明の実施形態を図面を参照して詳細に説明する。図1を参照すると、光デバイスウエーハ(以下、単にウエーハと略称することがある)11の表面側斜視図が示されている。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, there is shown a front side perspective view of an optical device wafer 11 (hereinafter sometimes simply referred to as a wafer) 11.
光デバイスウエーハ11は、サファイア基板13上に窒化ガリウム(GaN)等のエピタキシャル層(積層体層)15が積層されて構成されている。光デバイスウエーハ11は、エピタキシャル層15が積層された表面11aと、サファイア基板13が露出した裏面11bとを有している。 The optical device wafer 11 is configured by laminating an epitaxial layer (laminated body layer) 15 such as gallium nitride (GaN) on a sapphire substrate 13. The optical device wafer 11 has a front surface 11a on which an epitaxial layer 15 is stacked and a back surface 11b on which the sapphire substrate 13 is exposed.
ここで、本実施形態の光デバイスウエーハ11では、結晶成長用基板としてサファイア基板13を採用しているが、サファイア基板13に替えGaN基板又はSiC基板等を採用するようにしてもよい。 Here, in the optical device wafer 11 of the present embodiment, the sapphire substrate 13 is employed as the crystal growth substrate. However, a GaN substrate or a SiC substrate may be employed instead of the sapphire substrate 13.
積層体層(エピタキシャル層)15は、電子が多数キャリアとなるn型半導体層(例えば、n型GaN層)、発光層となる半導体層(例えば、InGaN層)、正孔が多数キャリアとなるp型半導体層(例えば、p型GaN層)を順にエピタキシャル成長させることにより形成される。 The stacked body layer (epitaxial layer) 15 includes an n-type semiconductor layer (for example, an n-type GaN layer) in which electrons are majority carriers, a semiconductor layer (for example, an InGaN layer) that is a light emitting layer, and a p in which holes are majority carriers. It is formed by epitaxially growing a type semiconductor layer (for example, a p-type GaN layer) in this order.
サファイア基板13は例えば100μmの厚みを有しており、積層体層15は例えば5μmの厚みを有している。積層体層15に複数のLED回路19が格子状に形成された複数の分割予定ライン17によって区画されて形成されている。ウエーハ11は、LED回路19が形成された表面11aと、サファイア基板13が露出した裏面11bとを有している。 The sapphire substrate 13 has a thickness of 100 μm, for example, and the laminate layer 15 has a thickness of 5 μm, for example. A plurality of LED circuits 19 are defined on the laminate layer 15 by a plurality of division lines 17 formed in a lattice pattern. The wafer 11 has a front surface 11a on which the LED circuit 19 is formed and a back surface 11b on which the sapphire substrate 13 is exposed.
本発明実施形態の発光ダイオードチップの製造方法によると、まず図1に示すような光デバイスウエーハ11を準備するウエーハ準備工程を実施する。次いで、図2に示すように、ウエーハ11の裏面11bに全面に渡り複数の貫通孔の形成された透明基板21の表面21を貼着して、ウエーハ11と透明基板25とを一体化して一体化ウエーハ25を形成する一体化工程を実施する。 According to the light emitting diode chip manufacturing method of the embodiment of the present invention, first, a wafer preparation step for preparing an optical device wafer 11 as shown in FIG. 1 is performed. Next, as shown in FIG. 2, the front surface 21 of the transparent substrate 21 having a plurality of through holes is adhered to the back surface 11 b of the wafer 11, and the wafer 11 and the transparent substrate 25 are integrated and integrated. An integration step for forming the chemical wafer 25 is performed.
一体化工程を実施した後、一体化ウエーハ25の透明基板21の裏面21bにLED回路19に対応して複数の溝を形成する透明基板加工工程を実施する。この透明基板加工工程は、例えば、よく知られた切削装置を用いて実施する。 After performing the integration step, a transparent substrate processing step is performed in which a plurality of grooves are formed on the back surface 21b of the transparent substrate 21 of the integrated wafer 25 corresponding to the LED circuit 19. This transparent substrate processing step is performed using, for example, a well-known cutting device.
図3(A)に示すように、切削装置の切削ユニット10は、スピンドルハウジング12と、スピンドルハウジング12中に回転可能に挿入された図示しないスピンドルと、スピンドルの先端に装着された切削ブレード14とを含んでいる。 As shown in FIG. 3A, the cutting unit 10 of the cutting apparatus includes a spindle housing 12, a spindle (not shown) rotatably inserted into the spindle housing 12, and a cutting blade 14 attached to the tip of the spindle. Is included.
切削ブレード14の切り刃は、例えば、ダイヤモンド砥粒をニッケルメッキで固定した電鋳砥石で形成されており、その先端形状は三角形状、四角形状、又は半円形状をしている。 The cutting blade of the cutting blade 14 is formed of, for example, an electroforming grindstone in which diamond abrasive grains are fixed by nickel plating, and the tip shape thereof is triangular, quadrangular, or semicircular.
切削ブレード14の概略上半分はブレードカバー(ホイールカバー)16で覆われており、ブレードカバー16には切削ブレード14の奥側及び手前側に水平に伸長する一対の(1本のみ図示)クーラーノズル18が配設されている。 The upper half of the cutting blade 14 is covered with a blade cover (wheel cover) 16, and the blade cover 16 is a pair of cooler nozzles (only one is shown) extending horizontally toward the back side and the near side of the cutting blade 14. 18 is arranged.
一対化ウエーハ25の透明基板21の裏面21bに複数の溝23を形成する透明基板加工工程では、透明基板21の裏面21bを上方に露出させて一体化ウエーハ25を図示しない切削装置のチャックテーブルで吸引保持する。 In the transparent substrate processing step in which the plurality of grooves 23 are formed on the back surface 21b of the transparent substrate 21 of the paired wafer 25, the back surface 21b of the transparent substrate 21 is exposed upward to form the integrated wafer 25 with a chuck table of a cutting device (not shown). Hold by suction.
そして、切削ブレード14を矢印R方向に高速回転させながら透明基板21の裏面21bに所定深さ切り込み、図示しないチャックテーブルに保持された一体化ウエーハを矢印X1方向に加工送りすることにより、透明基板21の裏面21bに第1の方向に伸長する溝23を切削により形成する。 Then, the cutting blade 14 is rotated at a high speed in the direction of the arrow R while cutting a predetermined depth into the back surface 21b of the transparent substrate 21, and the integrated wafer held on the chuck table (not shown) is processed and fed in the direction of the arrow X1. A groove 23 extending in the first direction is formed on the back surface 21b of the 21 by cutting.
一対化ウエーハ25を矢印X1方向に直交する方向にウエーハ11の分割予定ライン17のピッチずつ割り出し送りしながら、透明基板21の裏面21bを切削して、図4に示すように、第1の方向に伸長する複数の溝23を次々と形成する。 The back surface 21b of the transparent substrate 21 is cut while indexing and feeding the paired wafers 25 at a pitch of the division line 17 of the wafer 11 in a direction orthogonal to the arrow X1 direction, and as shown in FIG. A plurality of grooves 23 extending in succession are formed one after another.
図4(A)に示すように、透明基板21の裏面21bに形成する複数の溝23は一方向にのみ伸長する形態であってもよいし、或いは、図4(B)に示すように、第1の方向及び該第1の方向に直交する第2の方向に伸長する複数の溝23を透明基板21の裏面21bに形成するようにしてもよい。 As shown in FIG. 4 (A), the plurality of grooves 23 formed on the back surface 21b of the transparent substrate 21 may extend in only one direction, or as shown in FIG. 4 (B), A plurality of grooves 23 extending in the first direction and the second direction orthogonal to the first direction may be formed on the back surface 21 b of the transparent substrate 21.
透明基板21の裏面21bに形成する溝は、図3(B)に示すような断面三角形状の溝23、又は図3(C)に示すような断面四角形状の溝23A、又は図3(D)に示すような断面半円形状の溝23Bの何れであってもよい。 The groove formed in the back surface 21b of the transparent substrate 21 is a groove 23 having a triangular cross section as shown in FIG. 3B, or a groove 23A having a square cross section as shown in FIG. 3C, or FIG. Any of the grooves 23B having a semicircular cross section as shown in FIG.
透明基板21は、透明樹脂、光学ガラス、サファイア、透明セラミックスの何れかから形成される。本実施形態では、光学ガラスに比べて耐久性のあるポリカーボネイト、アクリル等の透明樹脂から透明基板21を形成した。尚、溝を形成する方法として、サンドブラスト、エッチング、レーザーを用いてもよい。 The transparent substrate 21 is formed from any one of transparent resin, optical glass, sapphire, and transparent ceramics. In the present embodiment, the transparent substrate 21 is formed from a transparent resin such as polycarbonate or acrylic that is more durable than optical glass. As a method for forming the groove, sand blasting, etching, or laser may be used.
透明基板21の裏面21bに複数の溝23,23A,23Bを形成する透明基板加工工程を実施した後、図5に示すように、一体化ウエーハ25の透明基板21を外周部が環状フレームFに貼着されたダイシングテープTに貼着してフレームユニットを形成し、一体化ウエーハ25をダイシングテープTを介して環状フレームFで支持する支持工程を実施する。 After performing the transparent substrate processing step of forming the plurality of grooves 23, 23A, 23B on the back surface 21b of the transparent substrate 21, the outer peripheral portion of the transparent substrate 21 of the integrated wafer 25 is formed into an annular frame F as shown in FIG. A frame unit is formed by adhering to the adhering dicing tape T, and a supporting process for supporting the integrated wafer 25 with the annular frame F through the dicing tape T is performed.
支持工程を実施した後、フレームユニットを切削装置に投入し、切削装置で一体化ウエーハ25を切削して個々の発光ダイオードチップに分割する分割ステップを実施する。この分割ステップについて、図6を参照して説明する。 After carrying out the supporting process, the frame unit is put into a cutting device, and the dividing step of cutting the integrated wafer 25 with the cutting device and dividing it into individual light emitting diode chips is carried out. This division step will be described with reference to FIG.
分割ステップでは、一体化ウエーハ25をフレームユニットのダイシングテープTを介して切削装置のチャックテーブル20で吸引保持し、環状フレームFは図示しないクランプでクランプして固定する。 In the dividing step, the integrated wafer 25 is sucked and held by the chuck table 20 of the cutting device via the dicing tape T of the frame unit, and the annular frame F is clamped and fixed by a clamp (not shown).
そして、切削ブレード14を矢印R方向に高速回転させながら切削ブレード14の先端がダイシングテープTに届くまでウエーハ11の分割予定ライン17に切り込み、クーラーノズル18から切削ブレード14及びウエーハ11の加工点に向かって切削液を供給しつつ、一体化ウエーハ25を矢印X1方向に加工送りすることにより、ウエーハ11の分割予定ライン17に沿ってウエーハ11及び透明基板21を切断する切断溝27を形成する。 Then, while rotating the cutting blade 14 in the direction of arrow R at high speed, the cutting blade 14 is cut into the division line 17 of the wafer 11 until the tip of the cutting blade 14 reaches the dicing tape T. From the cooler nozzle 18 to the processing point of the cutting blade 14 and the wafer 11. The cutting groove 27 for cutting the wafer 11 and the transparent substrate 21 is formed along the division line 17 of the wafer 11 by processing and feeding the integrated wafer 25 in the direction of the arrow X1 while supplying the cutting fluid.
切削ユニット10をY軸方向に割り出し送りしながら、第1の方向に伸長する分割予定ライン17に沿って同様な切断溝27を次々と形成する。次いで、チャックテーブル20を90°回転してから、第1の方向に直交する第2の方向に伸長する全ての分割予定ライン17に沿って同様な切断溝27を形成して、図7に示す状態にすることで、一体化ウエーハ25を図8に示すような発光ダイオードチップ31に分割する。 While indexing and feeding the cutting unit 10 in the Y-axis direction, similar cutting grooves 27 are formed one after another along the planned dividing line 17 extending in the first direction. Next, after the chuck table 20 is rotated by 90 °, similar cutting grooves 27 are formed along all the planned dividing lines 17 extending in the second direction orthogonal to the first direction, as shown in FIG. In this state, the integrated wafer 25 is divided into light emitting diode chips 31 as shown in FIG.
上述した実施形態では、一体化ウエーハ25を個々の発光ダイオードチップ31に分割するのに切削装置を使用しているが、ウエーハ11及び透明基板21に対して透過性を有する波長のレーザービームを分割予定ライン13に沿ってウエーハ11に照射して、ウエーハ11及び透明基板21の内部に厚み方向に複数層の改質層を形成し、次いで、一体化ウエーハ25に外力を付与して、改質層を分割起点に一体化ウエーハ25を個々の発光ダイオードチップ31に分割するようにしてもよい。 In the embodiment described above, the cutting device is used to divide the integrated wafer 25 into the individual light emitting diode chips 31. However, the laser beam having a wavelength that is transmissive to the wafer 11 and the transparent substrate 21 is divided. Irradiate the wafer 11 along the planned line 13 to form a plurality of modified layers in the thickness direction inside the wafer 11 and the transparent substrate 21, and then apply an external force to the integrated wafer 25 to modify the wafer. The integrated wafer 25 may be divided into individual light emitting diode chips 31 using the layers as division starting points.
図8に示された発光ダイオードチップ31は表面にLED回路19を有するLED13Aの裏面に複数の貫通孔を有する透明部材21Aが貼着されている。更に、透明部材21Aの裏面に溝23が形成されている。従って、透明部材21Aの表面積が増大する。 The light emitting diode chip 31 shown in FIG. 8 has a transparent member 21A having a plurality of through holes attached to the back surface of the LED 13A having the LED circuit 19 on the front surface. Furthermore, a groove 23 is formed on the back surface of the transparent member 21A. Therefore, the surface area of the transparent member 21A increases.
よって、透明部材21Aから外部に屈折して出射する際、透明部材21Aと空気層との界面での入射角は臨界角以上となる光の割合が減少し、透明部材21Aから出射される光の量が増大し、発光ダイオードチップ31の輝度が向上する。 Therefore, when the light is refracted and emitted from the transparent member 21A, the ratio of the light whose incident angle at the interface between the transparent member 21A and the air layer exceeds the critical angle is reduced, and the light emitted from the transparent member 21A is reduced. The amount increases, and the luminance of the light emitting diode chip 31 is improved.
10 切削ユニット
11 光デバイスウエーハ(ウエーハ)
13 サファイア基板
14 切削ブレード
15 積層体層
17 分割予定ライン
19 LED回路
21 透明基板
21A 透明部材
23,23A,23B 溝
25 一体化ウエーハ
27 切断溝
29 貫通孔
31 発光ダイオードチップ
10 Cutting unit 11 Optical device wafer (wafer)
13 Sapphire substrate 14 Cutting blade 15 Laminate layer 17 Line to be divided 19 LED circuit 21 Transparent substrate 21A Transparent member 23, 23A, 23B Groove 25 Integrated wafer 27 Cutting groove 29 Through hole 31 Light emitting diode chip
Claims (4)
結晶成長用の透明基板上に発光層を含む複数の半導体層が形成された積層体層を有し、該積層体層の表面に互いに交差する複数の分割予定ラインによって区画された各領域にそれぞれLED回路が形成されたウエーハを準備するウエーハ準備工程と、
該ウエーハの裏面に全面に渡り複数の貫通孔の形成された透明基板の表面を貼着して一体化ウエーハを形成する一体化工程と、
該一体化工程を実施した後、該一体化ウエーハの該透明基板の裏面に該ウエーハの各LED回路に対応して複数の溝を形成する透明基板加工工程と、
該透明基板加工工程を実施した後、該ウエーハを該分割予定ラインに沿って該透明基板と共に切断して該一体化ウエーハを個々の発光ダイオードチップに分割する分割工程と、
を備えたことを特徴とする発光ダイオードチップの製造方法。 A method of manufacturing a light emitting diode chip,
Each of the regions has a laminate layer in which a plurality of semiconductor layers including a light emitting layer are formed on a transparent substrate for crystal growth, and is divided into a plurality of division lines intersecting each other on the surface of the laminate layer. A wafer preparation step of preparing a wafer on which an LED circuit is formed;
An integration step of forming an integrated wafer by adhering the surface of a transparent substrate having a plurality of through-holes formed on the entire back surface of the wafer;
After carrying out the integration step, a transparent substrate processing step of forming a plurality of grooves corresponding to each LED circuit of the wafer on the back surface of the transparent substrate of the integrated wafer;
After performing the transparent substrate processing step, the dividing step of cutting the wafer together with the transparent substrate along the division line to divide the integrated wafer into individual light emitting diode chips;
A method for producing a light-emitting diode chip, comprising:
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006278751A (en) * | 2005-03-29 | 2006-10-12 | Mitsubishi Cable Ind Ltd | Garium nitride-based semiconductor light emitting element |
JP2012038889A (en) * | 2010-08-06 | 2012-02-23 | Koito Mfg Co Ltd | Fluorescent member and light-emitting module |
JP2012195404A (en) * | 2011-03-16 | 2012-10-11 | Toshiba Lighting & Technology Corp | Light-emitting device and luminaire |
WO2013114480A1 (en) * | 2012-02-01 | 2013-08-08 | パナソニック株式会社 | Semiconductor light-emitting element, method for manufacturing same, and light source device |
-
2016
- 2016-08-08 JP JP2016155415A patent/JP2018026385A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006278751A (en) * | 2005-03-29 | 2006-10-12 | Mitsubishi Cable Ind Ltd | Garium nitride-based semiconductor light emitting element |
JP2012038889A (en) * | 2010-08-06 | 2012-02-23 | Koito Mfg Co Ltd | Fluorescent member and light-emitting module |
JP2012195404A (en) * | 2011-03-16 | 2012-10-11 | Toshiba Lighting & Technology Corp | Light-emitting device and luminaire |
WO2013114480A1 (en) * | 2012-02-01 | 2013-08-08 | パナソニック株式会社 | Semiconductor light-emitting element, method for manufacturing same, and light source device |
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