JP2018022277A - Programmable logic device, information processing device, soft error recording method, and soft error recording program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To record, by a highly reliable method and at low cost, a soft error having occurred in a volatile memory included in a device that has a function of detecting a soft error but does not have a function of recording the detected soft error.SOLUTION: A programmable logic device includes control means that when receiving a signal indicating the occurrence of a soft error from a device that has a function of detecting a soft error in a built-in volatile memory but does not have a function of recording the detected soft error, writes soft error information indicating the occurrence of the soft error only to a storage area in which soft error information is not written out of a plurality of storage areas included in a nonvolatile memory. The programmable logic device is separated from a device.SELECTED DRAWING: Figure 8

Description

  The present invention relates to a technique for recording a soft error in a volatile memory built in a device that has a function of detecting a soft error but does not have a function of recording the detected soft error.

  In a programmable device (PLD: Programmable Logic Device) such as an FPGA (Field Programmable Gate Array), the influence of a soft error has become remarkable as the mounting density is increased. For example, a soft error in an FPGA is an unexpected change in the bit state of a CRAM (Configuration Random Access Memory) caused by environmental radiation. PLD has a problem that normality of circuit operation and normality of data to be held cannot be guaranteed due to a soft error.

  An example of a technique for repairing a soft error is disclosed in Patent Document 1. The FPGA monitoring and control circuit of Patent Document 1 includes a CRC (Cyclic Redundancy Check) checker built in the FPGA, an EEPROM (Electrically Erasable Programmable Read-Only Memory) externally attached to the FPGA, and a control circuit built in the FPGA. including. The CRC checker detects an error in the data stored in the CRAM. The EEPROM records error detection information and detection date / time information when an error is detected by the CRC checker. When the error detection information is recorded in the EEPROM, the control circuit displays an error occurrence on the outside. Further, the control circuit determines whether or not the FPGA reconstruction process is necessary based on the error detection information. When the reconstruction process is necessary, the control circuit causes a CPLD (Complex Programmable Logic Device) externally attached to the FPGA to execute the reconstruction process based on the configuration data stored in the CRAM.

  However, many FPGAs do not have a function of correcting soft errors. In an electronic device equipped with an FPGA that does not have a soft error correction function, it is difficult to specify that the cause of a failure is a soft error when a failure occurs in the electronic device due to a soft error. In addition, in an electronic device equipped with an FPGA that does not have a soft error correction function, if the FPGA is reconfigured due to a power cycle or the like, the soft error that caused the failure will disappear. For this reason, when the electronic device is returned to the manufacturer to investigate the failure, the failure may not be reproduced after the return and the cause of the failure may not be identified.

  Therefore, it is required to add a soft error detection and recording function at low cost to an FPGA that does not have a function of correcting a soft error. When adding a soft error detection and recording function to an FPGA that does not have a function of correcting a soft error, it is desirable that the added parts have a small number of parts, a small size, and a low price. For detecting soft errors, it is often possible to use an IP core (Intellectual Property Core) released by each FPGA manufacturer.

  However, when the failure information is recorded / held using the FPGA in which the soft error has occurred, the FPGA in which the failure is inherent is used, so that there is a problem that the reliability regarding the recording / holding of the failure information is low. is there.

  An example of a technique for repairing a soft error using a device different from the FPGA in which the soft error has occurred is disclosed in Patent Document 2. The fault repair apparatus of Patent Document 2 repairs an FPGA soft error. The FPGA includes circuit elements and an updatable memory (CRAM) that stores configuration data. The logical operation of the FPGA is defined by configuration data. The fault repair apparatus of Patent Literature 2 includes a detection unit, a storage unit, a specifying unit, a correction unit, and a count unit. The detection means detects a failure of the FPGA and outputs failure information. The storage unit stores a failure area specifying table in which the description of the configuration data related to the failure information is associated with the identification information of the memory area regarding which of the plurality of memory areas included in the memory is present. The specifying unit specifies a faulty memory area that is a memory area in which a fault has occurred based on the fault information and the fault area specifying table. The correction means detects and corrects error data that does not match the expected value based on the error detection correction code data of the configuration data for the configuration data stored in the failure occurrence memory area. The counting means counts the number of failure occurrences for each failure occurrence memory area. As a result of the above configuration, the fault repair apparatus of Patent Document 2 detects and repairs the fault of the FPGA by narrowing down to the fault occurrence location of the memory storing the configuration data.

JP 2014-052781 A JP 2014-167708 A

  However, the fault repair apparatus of Patent Document 2 detects and repairs a fault. For this reason, the fault repair apparatus disclosed in Patent Document 2 requires more complicated processing than when only detecting and recording soft errors. That is, the circuit scale required for the fault repair apparatus is larger than when only soft error detection and recording is performed. Therefore, the fault repair apparatus of Patent Document 2 has a problem that the fault repair apparatus is expensive.

  The present invention has been made in view of the above-described problems, and has a function of detecting a soft error, but the reliability of a soft error in a volatile memory built in a device that does not have a function of recording the detected soft error is reliably determined. The main purpose is to record at a low cost and at a low cost.

  In one embodiment of the present invention, a programmable logic device has a function of detecting a soft error in a built-in volatile memory, but a signal indicating the occurrence of a soft error from a device that does not have a function of recording the detected soft error. A programmable logic device provided with a control means for writing soft error information indicating the occurrence of a soft error to only a storage area in which the soft error information is not written among a plurality of storage areas included in the nonvolatile memory when received. The programmable logic device is separate from the device.

  In one embodiment of the present invention, an information processing device has a function of detecting a soft error in a built-in volatile memory, but does not have a function of recording the detected soft error, a non-volatile memory, and a software from the device. Control to write soft error information indicating the occurrence of a soft error only to a storage area in which the soft error information is not written among a plurality of storage areas included in the nonvolatile memory when a signal indicating the occurrence of an error is received An information processing apparatus including a programmable logic device including means, wherein the programmable logic device is separate from the device.

  In one embodiment of the present invention, a soft error recording method is connected to a device that has a function of detecting a soft error in a built-in volatile memory but does not have a function of recording the detected soft error, and a nonvolatile memory. In addition, when a programmable logic device that is separate from the device receives a signal indicating the occurrence of a soft error from the device, the soft error information indicating the occurrence of the soft error is stored in a plurality of storage areas included in the nonvolatile memory. Of these, only the storage area in which no soft error information is written is written.

  In one embodiment of the present invention, a soft error recording program or a recording medium storing the soft error recording program has a function of detecting a soft error in a built-in volatile memory, but a function of recording the detected soft error Soft error information that indicates the occurrence of a soft error when a signal indicating the occurrence of a soft error is received from a device that does not have a memory and a programmable logic device that is connected to a nonvolatile memory and that is separate from the device. Of the plurality of storage areas included in the non-volatile memory is executed only in the storage area in which the soft error information is not written.

  According to the present invention, a soft error in a volatile memory built in a device that has a function of detecting a soft error but does not have a function of recording the detected soft error can be recorded with a highly reliable method at low cost. There is an effect that can be done.

It is a block diagram which shows an example of a structure of the information processing apparatus in the 1st Embodiment of this invention. 4 is a timing chart illustrating an example of a read operation from the flash memory according to the first embodiment of the present invention. 3 is a timing chart illustrating an example of a write operation to the flash memory according to the first embodiment of the present invention. 3 is a timing chart illustrating an example of an erasing operation for the flash memory according to the first embodiment of the present invention. It is a block diagram which shows an example of a structure of the information processing apparatus in the 2nd Embodiment of this invention. 6 is a timing chart illustrating an example of a read operation from a flash memory according to the second embodiment of the present invention. 6 is a timing chart illustrating an example of a write operation to a flash memory according to a second embodiment of the present invention. It is a block diagram which shows an example of a structure of the information processing apparatus in the 3rd Embodiment of this invention. It is a block diagram which shows an example of the hardware constitutions which can implement | achieve the information processing apparatus in each embodiment of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings, equivalent components are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
(First embodiment)
In this embodiment, the error recording CPLD records a soft error in the CRAM included in the FPGA.

  A configuration in the present embodiment will be described.

  FIG. 1 is a block diagram illustrating an example of a configuration of an information processing apparatus according to an embodiment of the present invention. An information processing apparatus 500 according to the present embodiment includes an FPGA 200 and a CPLD 100 for error recording. The CPLD 100 is connected to the FPGA 200.

  The FPGA 200 includes a CRAM 210 that is a monitoring target for occurrence of a soft error. The CRAM 210 includes a plurality of storage areas. The FPGA 200 outputs a signal indicating whether or not a soft error has occurred in the CRAM 210 (hereinafter referred to as “soft error signal”). The soft error signal may include information indicating a storage area in the CRAM 210 where a soft error has occurred. Hereinafter, an example will be described in which the soft error signal takes a binary value of “1” indicating that a soft error has occurred and “0” indicating that a soft error has not occurred. The FPGA 200 includes, for example, a CRC checker and has a function of detecting a soft error in the CRAM 210, but does not have a function of recording the detected soft error.

  The CPLD 100 is an integrated circuit that can define and change an internal logic circuit after manufacturing. The CPLD 100 includes a soft error detection unit 110, a flash memory interface unit 120, a flash memory 130, and a read data confirmation unit 140.

  The soft error detection unit 110, the flash memory interface unit 120, and the read data confirmation unit 140 include internal logic circuits defined after the CPLD 100 is manufactured. The CPLD 100 is generally cheaper as the writable circuit scale is smaller. In addition, the simpler the process to be implemented, the smaller the circuit scale required to implement the process. Therefore, the soft error detection unit 110, the flash memory interface unit 120, and the read data confirmation unit 140 can be mounted using the cheaper CPLD 100 as the processing is simpler.

  The soft error detection unit 110 receives a soft error signal from the FPGA 200 and determines the presence or absence of a soft error based on the received soft error signal. Then, when a soft error occurs, the soft error detection unit 110 outputs a signal (hereinafter referred to as a “soft error recording instruction”) that instructs the flash memory interface unit 120 to record a soft error.

  The flash memory 130 includes a plurality of storage areas. The flash memory 130 can hold information indicating that a soft error has occurred in the FPGA 200 (hereinafter referred to as “soft error information”). The flash memory 130 is generally cheaper as the storage capacity is smaller. Therefore, the flash memory 130 can be mounted at a lower cost as the storage capacity necessary for holding the soft error information is smaller. Note that the flash memory 130 may hold information other than soft error information. The flash memory 130 may be externally attached to the CPLD 100.

  When the flash memory interface unit 120 receives a soft error recording instruction from the soft error detection unit 110, the flash memory interface unit 120, to only the storage area in which the soft error information is not written among the plurality of storage areas included in the flash memory 130, Write soft error information. The soft error information may include information indicating the date and time when the soft error occurred, information indicating the storage area where the soft error occurred in the CRAM 210, and the like.

  Further, the flash memory interface unit 120 reads the soft error information from the flash memory 130 after the CPLD 100 is activated and after the soft error information is written to the flash memory 130.

  The read data confirmation unit 140 is a signal indicating the number of occurrences of soft errors based on the number of pieces of soft error information read from the flash memory 130 by the flash memory interface unit 120 (hereinafter referred to as “number of occurrences of soft errors”). Is output to the outside of the CPLD 100.

  The operation in this embodiment will be described.

  In the following, in the soft error information storage area in the flash memory 130 (hereinafter referred to as “soft error information storage area”), the initial state of the storage area or immediately after erasing in all sectors in the storage area An example in which all the bits in all sectors in the storable area are “1” will be described. In the following, an example in which the soft error information is represented by a 2-byte bit string in which all bits are “0” will be described.

  When the CPLD 100 is activated in response to power-on or reset, the flash memory interface unit 120 reads soft error information from the flash memory 130. At this time, the flash memory interface unit 120 reads the byte strings recorded in one soft error information storage area in ascending order from the top address in the soft error information storage area in the flash memory 130. The read byte strings are transferred to the read data confirmation unit 140 one by one.

  The read data confirming unit 140 stores the byte sequence of all the bits “1” (no soft error information) among the read byte sequences described above, and the first address in the soft error information storage area. Is stored as an address for writing soft error information (hereinafter referred to as “next write address”). That is, the soft error information is not written to addresses after the next write address. The next write address represents the headmost address where no soft error information is written in the soft error information storage area.

  Further, the read data confirmation unit 140 outputs a signal indicating the number of times that a byte sequence (with soft error information) whose byte sequence is all “0” is read (number of occurrences of soft error) to the outside of the CPLD 100.

  The soft error detection unit 110 receives a soft error signal from the FPGA 200 and waits for a change in the soft error signal while the received soft error signal is “0”. Then, when the soft error signal changes from “0” to “1”, the soft error detection unit 110 determines that a soft error has been detected and instructs the flash memory interface unit 120 to write soft error information. A signal (hereinafter referred to as “write instruction”) is output.

  When the flash memory interface unit 120 receives a write instruction, the flash memory interface unit 120 writes soft error information to the storage area in the flash memory 130 indicated by the held next write address.

  After the soft error information is written to the flash memory 130, the flash memory interface unit 120 reads the soft error information from the flash memory 130. At this time, the flash memory interface unit 120 reads the byte strings recorded in one soft error information storage area in ascending order from the top address in the soft error information storage area in the flash memory 130. The read byte strings are transferred to the read data confirmation unit 140 one by one.

  The read data confirmation unit 140 next sets the address at the very beginning in the soft error information storage area in which the byte sequence of all bits “1” (no soft error information) is stored among the read byte sequences. Hold as write address.

  Further, the read data confirmation unit 140 outputs the number of soft error occurrences to the outside of the CPLD 100.

  Since the flash memory 130 is a non-volatile memory, the soft error information recorded in the flash memory 130 is not erased even when the power of the CPLD 100 is turned off or the CPLD 100 is reset. Therefore, even when the power source of the CPLD 100 is turned off or when the CPLD 100 is reset, the read data check unit 140 can output the number of soft errors that occur when the CPLD 100 is activated.

  The CPLD 100 in the present embodiment may be able to erase soft error information recorded in the flash memory 130. In that case, the information processing apparatus 500 includes the switch 300, and the CPLD 100 is connected to the switch 300. The switch 300 switches the “flash memory initialization signal” in accordance with the operation of the switch 300. Hereinafter, in the flash memory initialization signal, for example, the value “1” indicates “initialization not executed” and the value “0” indicates “initialization execution”.

  When erasing the soft error information recorded in the flash memory 130, the switch 300 outputs a value “0” to the CPLD 100 as a flash memory initialization signal. When the flash memory interface unit 120 receives the value “0” as the flash memory initialization signal, it erases the soft error information recorded in the flash memory 130. By erasing, the soft error information storage area of the flash memory 130 is initialized, and all bits of all addresses in the soft error information storage area are set to ‘1’. When the flash memory initialization signal is switched by the switch 300, it is possible to prevent the soft error information from being erased due to a malfunction of the CPLD 100. For example, the soft error information is erased by operating the switch 300 to the “0” output side only during maintenance of the CPLD 100.

  An example of specific operations of reading, writing, and erasing the soft error information to the flash memory 130 will be described. In the following, the operation of the CPLD 100 with the built-in flash memory 130 will be described with reference to FIGS.

In this operation example, the interface between the CPLD 100 and the flash memory 130 is a serial interface in which an address signal and a data signal are separated. This serial interface has an address shift signal and an address clock signal for serial address input control, and has a data shift signal and a data clock signal for serial data input control and serial data output control. For both the serial address and the serial data, the endian is MSB (Most Significant Bit) first. The address length is 9 bits and the data length is 16 bits. The serial interface has a program signal for write control and an erase signal for erase control. In this serial interface, a busy signal “1” is output from the flash memory 130 during writing or erasing. Note that each signal is described as being positive logic unless otherwise specified, but the signal in the present embodiment is not limited to positive logic, and may be negative logic.
<Read operation>
2 to 4, “CPLD clock” is a clock signal of the CPLD 100, and “control counter” is a counter indicating the timing in the CPLD clock. In the following description, the operation timing is specified using the value of the control counter. 2 to 4, some values of the control counter are omitted.

  FIG. 2 is a timing chart showing an example of a read operation from the flash memory according to the first embodiment of the present invention. In FIG. 2, “reset” indicates a reset signal for the CPLD 100.

A “flash memory input signal” is output from the CPLD 100 to the flash memory 130. A “flash memory output signal” is output from the flash memory 130 to the CPLD 100. The flash memory input signals are “address shift signal”, “address clock signal”, “address signal”, “data shift signal”, “data clock signal”, and “write data signal” (FIGS. 3 and 4). ), “Program signal” (FIG. 3), and “erase signal” (FIG. 4). The flash memory output signal includes a “read data signal” and a “busy signal”.
● The address shift signal is a signal that validates the address signal.
The address clock signal is a signal that defines the timing of the address signal.
● The address signal is a signal for serially inputting the address.
The data shift signal is a signal that controls reading of data from the flash memory.
The data clock signal is a signal that defines the timing of the write data signal and the timing of the read data signal.
● The write data signal is a signal for serial input of data to be written to the flash memory.
The program signal is a signal that controls writing of data to the flash memory.
The erase signal is a signal that controls erasure of the flash memory.
● The read data signal is a signal for serially outputting the data read from the flash memory.
A busy signal is a signal indicating that data is being written or erased in the flash memory.

  The CPLD 100 reads the soft error information from the flash memory 130 after the CPLD 100 is activated or after the soft error information is written to the flash memory 130.

When the control counter is 0:
The soft error detection unit 110 detects the change of the reset signal from “0” to “1”.

When the control counter is 1-9:
When the flash memory interface unit 120 detects the change of the reset signal from “0” to “1”, it changes the address shift signal from “0” to “1”.
The flash memory interface unit 120 outputs the address signal ('0') to the flash memory bit by bit every time the address clock signal rises while the address shift signal is '1'.
In the control counter 9, a 9-bit address “0 — 0000 — 0000” is set in the flash memory.

When the control counter is 10:
The flash memory interface unit 120 changes the address shift signal from “1” to “0”.
When the data shift signal is “0” and the data clock signal rises, the address data set in the control counter 9 is set in a data register (not shown) in the flash memory 130.
The flash memory 130 increments the address set by the control counter 9 by 1.

When the control counter is 11 to 26:
The flash memory interface unit 120 changes the data shift signal from “0” to “1”.
The data set in the data register in the flash memory 130 is output as a read data signal bit by bit at the rising edge of the data clock signal while the data shift signal is “1”.
In the control counter 26, 16-bit data is output. The read data confirmation unit 140 determines that there is no soft error information when all the bits of the output 16-bit data are “1”. When all the bits of the output 16-bit data are “0”, the read data check unit 140 determines that there is soft error information and increments the “soft error counter” by one. The soft error counter is a counter indicating the number of pieces of soft error information stored in the flash memory, that is, the number of occurrences of soft errors.

When the control counter is 27:
The flash memory interface unit 120 changes the data shift signal from “1” to “0”.
The data at the address set by the flash memory 130 in the control counter 10 is set in the data register in the flash memory when the data shift signal is “0” and the data clock signal rises.

When the control counter is 28 to 281:
The data set in the data register in the flash memory 130 is output as a read data signal bit by bit at the rising edge of the data clock signal while the data shift signal is “1”.
Thereafter, the operation when the control counter is 11 to 27 is repeated, and data is sequentially read from the flash memory 130 up to the address 15.
When the read data check unit 140 reads 16-bit data from the flash memory 130, the read data confirmation unit 140 reads the address at the head of the soft error information storage area from which data having all bits “1” is read. Hold as the next write address.
<Write operation>
FIG. 3 is a timing chart showing an example of a write operation to the flash memory according to the first embodiment of the present invention. In FIG. 3, “soft error” indicates a soft error signal for the CPLD 100.

  When the soft error detection unit 110 detects a change of the soft error signal from ‘0’ to ‘1’, the soft error detection unit 110 writes the soft error information to the flash memory 130.

When the control counter is 0:
The soft error detection unit 110 detects the change of the soft error signal from “0” to “1”.

When the control counter is 1-9:
When the flash memory interface unit 120 detects the change of the soft error signal from “0” to “1”, it changes the address shift signal from “0” to “1”.
● While the address shift signal is “1”, the flash memory interface unit 120 outputs an address signal (a3, a2, a1, a0 in FIG. 3) bit by bit to the flash memory every time the address clock signal rises. .
In the control counter 9, a 9-bit address is set in the flash memory 130. This address is the next write address. In this operation example, it is assumed that the effective address length is 4 bits. That is, the upper limit value of the number of soft error information that can be recorded is 16. Therefore, bits a3 to a0 are set in the flash memory 130. When the number of soft error information is written up to the upper limit value, no further soft error information is written. In general, since the frequency of soft errors is low, it is practically not a problem that the number of recordable soft error information is limited to the upper limit or less and writing of soft error information exceeding the upper limit is stopped. .

When the control counter is 10:
The flash memory interface unit 120 changes the address shift signal from “1” to “0”.
The flash memory interface unit 120 changes the data shift signal from “0” to “1”.

When the control counter is 10-25:
While the data shift signal is “1”, the write data is output to the flash memory 130 one bit at each rising edge of the data clock signal.
In the control counter 25, 16-bit data “0000 — 0000 — 0000 — 0000” is set in the flash memory 130.

When the control counter is 26:
The flash memory interface unit 120 changes the data shift signal from “1” to “0”.
The flash memory interface unit 120 changes the program signal from “0” to “1”.
The flash memory 130 starts writing the data set in the control counter 25 to the address set in the flash memory 130 in the control counter 9. At the same time, the flash memory 130 changes the busy signal from “0” to “1”.

When the control counter is 27:
When the writing of data to the flash memory 130 is completed, the flash memory 130 changes the busy signal from “1” to “0”.
The flash memory interface unit 120 changes the program signal from “1” to “0” in response to the busy signal changing from “1” to “0”.
<Erase operation>
FIG. 4 is a timing chart showing an example of the erase operation for the flash memory according to the first embodiment of the present invention. In FIG. 4, “flash memory initialization” indicates a flash memory initialization signal for the CPLD 100.

  When the CPLD 100 detects the change of the flash memory signal initialization signal from “0” to “1”, the data in the flash memory 130 is erased.

When the control counter is 0:
CPLD 100 detects a change from “0” to “1” in the flash memory signal initialization signal.

When the control counter is 1-9:
When the CPLD 100 detects a change from “0” to “1” in the flash signal initialization signal, the CPLD 100 changes the address shift signal from “0” to “1”.
The CPLD 100 outputs the address signal “0” to the flash memory bit by bit every time the address clock signal rises while the address shift signal is “1”.
In the control counter 9, a 9-bit address “0 — 0000 — 0000” is set in the flash memory 130. In this operation example, the flash memory 130 cannot be erased in units of bytes, but can be erased in units of sectors, and the sector 0 is selected when the most significant bit of the address is 0. In this operation example, since only sector 0 is used, address “0_0000_0000” is set.

When the control counter is 10:
CPLD 100 changes the erase signal from “0” to “1”. Thereby, erasing in the flash memory 130 is started.
When the flash memory 130 starts erasing, the flash memory 130 changes the busy signal from “0” to “1”.
When the erasure is completed, the flash memory 130 changes the busy signal from “1” to “0”.
When the busy signal changes from “1” to “0”, the CPLD 100 changes the erase signal from “1” to “0”.

  As described above, in the information processing apparatus 500 of the present embodiment, the CPLD 100 is separate from the FPGA 200. In other words, the occurrence of a soft error due to environmental radiation or the like is local, but the CPLD 100 and the FPGA 200 are located at a distance. Therefore, even when a soft error occurs in the CRAM 210 built in the FPGA 200, the CPLD 100 is likely to operate normally. That is, the CPLD 100 of the present embodiment can record soft errors with a highly reliable method.

  Further, in the information processing apparatus 500 of this embodiment, the flash memory interface unit 120 and the read data check unit 140 write and read soft error information to and from the flash memory 130 by a simple method. For example, the flash memory interface unit 120 does not need to overwrite the soft error information. Alternatively, for example, the flash memory interface unit 120 may record soft error information whose all bits are “0”, and does not need to record data other than the soft error information. Alternatively, for example, the flash memory interface unit 120 only needs to write soft error information to the next write address, and when writing the soft error information, it is necessary to search to which address the soft error information should be written in the flash memory 130. Absent. Therefore, the circuit scale of the CPLD 100 including the flash memory interface unit 120 can be suppressed. That is, the CPLD 100 of this embodiment can record soft errors at a low cost.

  Therefore, the information processing apparatus 500 according to the present embodiment has a function of detecting a soft error, but a soft error in a volatile memory built in a device that does not have a function of recording the detected soft error is highly reliable. There is an effect that recording can be performed by the method and at low cost.

  In the information processing apparatus 500 of this embodiment, the flash memory 130 includes the CPLD 100. That is, the information processing apparatus 500 of the present embodiment can realize a soft error recording function with a single device. Therefore, the information processing apparatus 500 according to the present embodiment has an effect that the information processing apparatus 500 can be downsized.

  In the information processing apparatus 500 of this embodiment, the flash memory 130 may be replaced with an EEPROM. However, the flash memory can be made smaller than the EEPROM.

In the information processing apparatus 500 of this embodiment, the flash memory 130 may be externally attached to the CPLD 100. In this case, the information processing apparatus 500 according to the present embodiment has an effect that the existing flash memory 130 can be used.
(Second Embodiment)
Next, a second embodiment of the present invention based on the first embodiment of the present invention will be described. In this embodiment, the flash memory is externally attached to the CPLD. The soft error information in the FPGA and the configuration data of the FPGA are stored in the flash memory.

  A configuration in the present embodiment will be described.

  FIG. 5 is a block diagram showing an example of the configuration of the information processing apparatus according to the second embodiment of the present invention. The information processing apparatus 505 according to the present embodiment includes an FPGA 205, an error recording CPLD 105, and a flash memory 135. The CPLD 105 is connected to the FPGA 205 and the flash memory 135.

  The FPGA 205 includes a CRAM 215 that is a monitoring target for occurrence of a soft error. The FPGA 205 acquires configuration data of the FPGA 205 from the flash memory 135 via the CPLD 105.

  The CPLD 105 includes a soft error detection unit 115, a flash memory interface unit 125, and a read data confirmation unit 145.

  The flash memory 135 includes a configuration data storage area 137 and a soft error information storage area 138.

  The FPGA 205 reads the configuration data stored in the configuration data storage area 137 of the flash memory 135 and loads it into the FPGA 205. At this time, the flash memory interface unit 125 and the read data confirmation unit 145 of the CPLD 105 pass signals between the FPGA 205 and the flash memory 135 as they are.

  When the configuration of the FPGA 205 is completed, the CPLD 105 reads the soft error information from the soft error information storage area 138 of the flash memory 135. At this time, the soft error information is read out in ascending order from the top address in the soft error information storage area 138 of the flash memory 135. The soft error information read from the flash memory 135 is passed to the read data confirmation unit 145.

  The soft error information recorded in the soft error information storage area 138 is erased simultaneously with the rewriting of the configuration data in the flash memory 135. The rewriting of the configuration data in the flash memory 135 is performed after, for example, data erasure (chip erase) in the entire flash memory.

  The other configuration of the information processing device 505 is the same as the configuration of the information processing device 500 in the first embodiment of the present invention.

  The operation in this embodiment will be described. Specifically, a case where a flash memory 135 having an SPI (Serial Peripheral Interface) is used as an example of operations for reading and writing soft error information to the flash memory will be described.

  The SPI has a clock signal, a chip select signal, a serial input signal, and a serial output signal. The chip select signal is negative logic. In the SPI, the address length is 24 bits, the data length is 8 bits, and the endian of both address and data is MSB first.

FIG. 6 is a timing chart showing an example of a read operation from the flash memory according to the second embodiment of the present invention. In FIG. 6, “reset” indicates a reset signal for the CPLD 105. In FIG. 6, some values of the control counter are omitted.
The chip select signal is a signal that validates the serial input signal and serial output signal.
A clock signal is a signal that defines the timing of a serial input signal and a serial output signal.
A serial input signal is a signal for serially inputting an instruction, address, or data to be written to the flash memory.
A serial output signal is a signal for serially outputting data read from the flash memory.

  The CPLD 105 reads the soft error information from the flash memory 135 after the activation of the CPLD 105 or after writing the soft error information to the flash memory 135.

When the control counter is 0:
The soft error detection unit 115 detects a change from “0” to “1” of the reset signal.

When the control counter is 1-8:
When the flash memory interface unit 125 detects the change of the reset signal from “0” to “1”, the control counter 1 changes the chip select signal from “1” to “0”.
The flash memory interface unit 125 outputs an instruction (OP code) “0000 — 0011” indicating read (“read”) to the serial input signal.

When the control counter is 9 to 32:
The flash memory interface unit 125 outputs the first 24 bits of the soft error information storage area 138 as a serial input signal.

When the control counter is 33 to 160:
Data read from the flash memory 135 is output from the control counter 33 as a serial output signal.
When the control counter is 33 to 40, the data at the head address is read out.
When the control counter is 41 to 48, the data of (first address + 1) is read.

When the control counter is 161:
Similarly, when 15 addresses are read out, the flash memory interface unit 125 changes the chip select from “0” to “1”.
If all bits of the output 15-address data are all “1”, the read data confirmation unit 145 determines that there is no soft error information.
If all bits in the output data at a certain address are “0”, the read data confirmation unit 145 determines that there is soft error information and increments the soft error counter by 1. Further, the read data confirmation unit 145 holds, as the next write address, the most significant address in the soft error information storage area from which all the bits “1” have been read.

  FIG. 7 is a timing chart showing an example of a write operation to the flash memory according to the second embodiment of the present invention. In FIG. 7, “soft error” indicates a soft error signal for the CPLD 105. In FIG. 7, some values of the control counter are omitted.

  When the soft error detection unit 115 detects a change of the soft error signal from ‘0’ to ‘1’, it writes the soft error information to the flash memory 135.

When the control counter is 0:
The soft error detection unit 115 detects the change of the soft error signal from “0” to “1”.

When the control counter is 1-8:
When the flash memory interface unit 125 detects the change of the soft error signal from “0” to “1”, the flash memory interface unit 125 changes the chip select signal from “1” to “0”.
The flash memory interface unit 125 outputs an OP code “0000 — 0110” indicating preparation for writing (“write enable”) to the serial input signal.

When the control counter is 9:
The flash memory interface unit 125 returns the chip select signal from “0” to “1”. As a result, the program signal can be output to the flash memory 135.

When the control counter is 10-17:
The flash memory interface unit 125 changes the chip select signal from “1” to “0”.
The flash memory interface unit 125 outputs an OP code “0000 — 0010” indicating the start of writing (“program”) to the serial input signal.

When the control counter is 18 to 41:
The flash memory interface unit 125 outputs a 24-bit address to the serial input signal. The write destination address is the next write destination address.

When the control counter is 42 to 49:
The flash memory interface unit 125 outputs 8-bit data, which is all “0” bits, to a serial input signal.

When the control counter is 50:
The flash memory interface unit 125 changes the chip select signal from “0” to “1”.

  As described above, the information processing apparatus 505 of the present embodiment is the same as the information processing apparatus 505 except that the CPLD 105 and the flash memory 135 are separate from each other and the two exchange data via a general-purpose interface. This is the same as the information processing apparatus 500 of the first embodiment of the invention. Therefore, the information processing apparatus 500 according to the present embodiment has a function of detecting a soft error, but a soft error in a volatile memory built in a device that does not have a function of recording the detected soft error is highly reliable. There is an effect that recording can be performed by the method and at low cost.

In the information processing apparatus 505 of this embodiment, the flash memory 135 is externally attached to the CPLD 105, and the flash memory 135 and the CPLD 105 exchange data via a general-purpose interface. Therefore, the information processing apparatus 505 of this embodiment has an effect that a general-purpose flash memory 135 can be used.
(Third embodiment)
Next, the third embodiment of the present invention, which is the basis of the first and second embodiments of the present invention, will be described.

  FIG. 8 is a block diagram showing an example of the configuration of the information processing apparatus according to the third embodiment of the present invention. The information processing apparatus 506 of this embodiment includes a device 206, a nonvolatile memory 136, and a programmable logic device (PLD: Programmable Logic Device) 106.

  Device 206 contains volatile memory 216. The device 206 has a function of detecting a soft error in the volatile memory 216, but does not have a function of recording the detected soft error.

  The nonvolatile memory 136 includes a plurality of storage areas.

  The PLD 106 is an integrated circuit that can define and change an internal logic circuit after manufacturing. The PLD 106 is, for example, an FPGA or a CPLD. The PLD 106 is separate from the device 206.

  The PLD 106 includes a control unit 156. Control unit 156 includes an internal logic circuit defined after manufacturing PLD 106. The PLD 106 is generally cheaper as the writable circuit scale is smaller. In addition, the simpler the process to be implemented, the smaller the circuit scale required to implement the process. Therefore, the control unit 156 can be mounted using the cheaper PLD 106 as the processing is simpler.

  When the control unit 156 receives a signal indicating the occurrence of a soft error from the device 206, the control unit 156 displays the soft error information indicating the occurrence of the soft error, among the plurality of storage areas included in the nonvolatile memory 136. Write only to the storage area where is not written.

  As described above, in the information processing apparatus 506 of this embodiment, the PLD 106 is separate from the device 206. That is, the occurrence of a soft error due to environmental radiation or the like is local, but the PLD 106 and the device 206 are located at a distance. Therefore, even when a soft error occurs in the volatile memory 216 built in the device 206, the PLD 106 is likely to operate normally. That is, the PLD 106 of the present embodiment can record a soft error with a highly reliable method.

  Furthermore, in the information processing apparatus 506 of this embodiment, the control unit 156 writes and reads soft error information to and from the nonvolatile memory 136 by a simple method. For example, the control unit 156 does not need to overwrite the soft error information. Therefore, the circuit scale of the PLD 106 including the control unit 156 can be suppressed. That is, the PLD 106 of the present embodiment can record soft errors at a low cost.

  Therefore, the information processing apparatus 506 of the present embodiment has a function of detecting a soft error, but the soft error in a volatile memory built in a device that does not have a function of recording the detected soft error is highly reliable. There is an effect that recording can be performed by the method and at low cost.

  Note that the control unit 156 in the information processing apparatus 506 of the present embodiment may be divided into a plurality of components. For example, the control unit 156 may be divided into the soft error detection unit 115, the flash memory interface unit 125, and the read data confirmation unit 145 in the second embodiment. Alternatively, for example, the control unit 156 may be divided into the soft error detection unit 110, the flash memory interface unit 120, and the read data confirmation unit 140 in the first embodiment.

  Further, in the information processing apparatus 506 of the present embodiment, the byte length of the soft error information may be a multiple of the sector length in the nonvolatile memory 136 as in the first or second embodiment. Then, the control unit 156 in the information processing apparatus 506 according to the present embodiment may write the soft error information in the nonvolatile memory 136 by using the sector length as a unit. In this case, when writing soft error information, a bit string (for example, a bit string of all bits “1”) indicating that there is no soft error information is added to the soft error information (for example, a bit string of all bits “0”). There is an effect that it is not necessary to write a byte string.

  In addition, the control unit 156 in the information processing apparatus 506 according to the present embodiment writes the start time and the soft error information after writing into the storage area included in the nonvolatile memory 136, as in the first or second embodiment. It is also possible to further read out the soft error information read from the nonvolatile memory 136 and output the number of soft error information read from the nonvolatile memory 136. In this case, the occurrence of an error can be detected based on the number of read soft error information.

  In addition, the control unit 156 in the information processing apparatus 506 of this embodiment limits the number of soft error information that can be written in the nonvolatile memory 136 to a predetermined upper limit value or less, as in the first or second embodiment. May be. Then, the controller 156 may stop writing the soft error information in the nonvolatile memory 136 after the number of soft error information reaches the upper limit. In this case, there is an effect that the storage capacity of the nonvolatile memory 136 can be limited.

  In addition, as in the first or second embodiment, the control unit 156 in the information processing device 506 according to the present embodiment outputs the number of soft error information in a storage area in which no soft error information is written. Of these, the headmost address may be held. Then, when the soft error information is written in the nonvolatile memory 136 next time, the control unit 156 writes the soft error information in the storage area indicated by the held address in the nonvolatile memory 136. Good. In this case, when the soft error information is written in the nonvolatile memory 136, there is an effect that it is not necessary to search to which address the soft error information should be written in the nonvolatile memory 136.

  Further, in the information processing apparatus 506 of the present embodiment, as in the first or second embodiment, the initial state of the storable area or the storable area in the storable area of the soft error information in the nonvolatile memory 136 Immediately after erasing in all sectors, all the bits in all sectors in the storable area may be 1. Then, the control unit 156 in the information processing apparatus 506 of the present embodiment may write byte unit data in which all bits are 0 as the soft error information. In this case, there is an effect that the process of writing the soft error information to the nonvolatile memory 136 is further simplified.

  Also, the control unit 156 in the information processing apparatus 506 of the present embodiment receives a signal instructing erasure in all sectors that can store soft error information in the nonvolatile memory 136, as in the first or second embodiment. In this case, all sectors that can store soft error information in the nonvolatile memory 136 may be erased. In this case, the recording of the soft error information can be resumed even after the remaining capacity of the non-volatile memory 136 is once lost.

  Further, in the information processing apparatus 506 of the present embodiment, the nonvolatile memory 136 may be built in the PLD 106 as in the first embodiment.

  FIG. 9 is a block diagram illustrating an example of a hardware configuration capable of realizing the communication device according to each embodiment of the present invention.

  The information processing device 907 includes a storage device 902, a CPU (Central Processing Unit) 903, a keyboard 904, a monitor 905, and an I / O (Input / Output) 908, which are connected via an internal bus 906. Yes. The storage device 902 stores an operation program for the CPU 903 such as the control unit 156. The CPU 903 controls the entire information processing device 907, executes an operation program stored in the storage device 902, and executes programs such as the control unit 156 and transmits / receives data via the I / O 908. The internal configuration of the information processing apparatus 907 is an example. The information processing device 907 may have a device configuration that connects a keyboard 904 and a monitor 905 as necessary.

  The communication device in each embodiment of the present invention described above may be realized by a dedicated device, but can also be realized by a computer (information processing device). In this case, the computer reads out the software program stored in the storage device 902 to the CPU 903 and executes the read software program in the CPU 903. In the case of each of the embodiments described above, the software program includes the functions of the respective parts of the CPLD 100 shown in FIG. 1, the functions of the respective parts of the CPLD 105 shown in FIG. 5, or the functions of the PLD 106 shown in FIG. It only needs to be described so that the function of each part can be realized. However, it is assumed that these units include hardware as appropriate. In such a case, the software program (computer program) can be regarded as constituting the present invention. Furthermore, a computer-readable storage medium storing such a software program can also be understood as constituting the present invention.

  The present invention has been exemplarily described with the above-described embodiments and modifications thereof. However, the technical scope of the present invention is not limited to the scope described in the above-described embodiments and modifications thereof. It will be apparent to those skilled in the art that various modifications and improvements can be made to such embodiments. In such a case, new embodiments to which such changes or improvements are added can also be included in the technical scope of the present invention. This is apparent from the matters described in the claims.

A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.
(Appendix 1)
When a signal indicating the occurrence of the soft error is received from a device that has a function of detecting a soft error in the built-in volatile memory but does not have a function of recording the detected soft error, the occurrence of the soft error Is a programmable logic device comprising a control means for writing soft error information representing only the storage area in which the soft error information is not written among a plurality of storage areas included in a nonvolatile memory,
The programmable logic device is a programmable logic device that is separate from the device.
(Appendix 2)
The byte length of the soft error information is a multiple of the sector length in the nonvolatile memory,
The programmable logic device according to appendix 1, wherein the control means writes the soft error information in the nonvolatile memory in units of the sector length.
(Appendix 3)
The control means includes
After starting and after writing the soft error information to the storage area, reading the written soft error information from the nonvolatile memory;
The programmable logic device according to appendix 1 or appendix 2, further comprising: outputting the number of the soft error information read from the nonvolatile memory.
(Appendix 4)
The control means limits the number of the soft error information writable in the nonvolatile memory to a predetermined upper limit value or less, and after the number of the soft error information reaches the upper limit value, The programmable logic device according to any one of appendices 1 to 3, wherein the writing of the soft error information is stopped.
(Appendix 5)
The control means includes
When outputting the number of the soft error information, in the storage area where the soft error information is not written, the address at the very beginning is held,
Of the plurality of storage areas included in the non-volatile memory, the soft error information in the non-volatile memory when the soft error information is next written to the storage area in which the soft error information is not written. The programmable logic device according to any one of appendices 1 to 4, which writes to the storage area indicated by the held address.
(Appendix 6)
In the storable area of the soft error information in the nonvolatile memory, all bits in all sectors in the storable area immediately after erasure in the initial state of the storable area or all sectors in the storable area Is 1,
The programmable logic device according to any one of appendices 1 to 5, wherein the control means writes byte-unit data in which all bits are 0 as the soft error information.
(Appendix 7)
When the control means receives a signal instructing erasure in all sectors in the nonvolatile memory capable of storing the soft error information, the control means performs erasure in all sectors in the nonvolatile memory capable of storing the soft error information. The programmable logic device according to any one of appendices 1 to 6 to be performed.
(Appendix 8)
The programmable logic device according to any one of appendices 1 to 7, wherein the nonvolatile memory is externally attached to the programmable logic device.
(Appendix 9)
When a signal indicating the occurrence of the soft error is received from a device that has a function of detecting a soft error in the built-in volatile memory but does not have a function of recording the detected soft error, the occurrence of the soft error A soft error detection unit for transmitting a soft error recording instruction for instructing recording of
Based on the soft error recording instruction, soft error information indicating the occurrence of the soft error is written only to the storage area in which the soft error information is not written among a plurality of storage areas included in a nonvolatile memory. When,
A flash memory interface unit that reads the soft error information that has been written from the nonvolatile memory after starting and after writing the soft error information to the storage area;
A programmable logic device comprising read data confirmation means for outputting the number of soft error information read from the nonvolatile memory,
The programmable logic device is a programmable logic device that is separate from the device.
(Appendix 10)
A device having a function of detecting a soft error in a built-in volatile memory, but not having a function of recording the detected soft error;
Non-volatile memory;
When a signal indicating the occurrence of the soft error is received from the device, the soft error information indicating the occurrence of the soft error is written in the plurality of storage areas included in the nonvolatile memory. An information processing apparatus comprising a programmable logic device including control means for writing only to the storage area that is not,
The programmable logic device is an information processing apparatus separate from the device.
(Appendix 11)
A programmable logic device having a function of detecting a soft error in a built-in volatile memory but not having a function of recording the detected soft error and a non-volatile memory connected to the device. Is
When a signal indicating the occurrence of the soft error is received from the device, the soft error information indicating the occurrence of the soft error is written in the plurality of storage areas included in the nonvolatile memory. A soft error recording method for writing only to the storage area.
(Appendix 12)
A programmable logic device having a function of detecting a soft error in a built-in volatile memory but not having a function of recording the detected soft error and a non-volatile memory connected to the device. In addition,
When a signal indicating the occurrence of the soft error is received from the device, the soft error information indicating the occurrence of the soft error is written in the plurality of storage areas included in the nonvolatile memory. A soft error recording program for executing a process of writing only to the storage area that is not.

  INDUSTRIAL APPLICABILITY The present invention can be used in applications that record soft errors, such as devices (network devices, communication devices, etc.) that have a soft error detection function but do not have a soft error recording function and that use programmable devices such as FPGAs. .

100 CPLD
110 Soft Error Detection Unit 120 Flash Memory Interface Unit 130 Flash Memory 140 Read Data Confirmation Unit 200 FPGA
210 CRAM
300 switch 500 information processing device 105 CPLD
115 Soft Error Detection Unit 125 Flash Memory Interface Unit 135 Flash Memory 137 Configuration Data Storage Area 138 Soft Error Information Storage Area 145 Read Data Confirmation Unit 205 FPGA
215 CRAM
505 Information processing device 106 PLD
136 Non-volatile memory 156 Control unit 506 Information processing device 902 Storage device 903 CPU
904 Keyboard 905 Monitor 906 Internal bus 907 Information processing device 908 I / O

Claims (10)

When a signal indicating the occurrence of the soft error is received from a device that has a function of detecting a soft error in the built-in volatile memory but does not have a function of recording the detected soft error, the occurrence of the soft error Is a programmable logic device comprising a control means for writing soft error information representing only the storage area in which the soft error information is not written among a plurality of storage areas included in a nonvolatile memory,
The programmable logic device is a programmable logic device that is separate from the device. The byte length of the soft error information is a multiple of the sector length in the nonvolatile memory,
The programmable logic device according to claim 1, wherein the control unit writes the soft error information in the nonvolatile memory in units of the sector length. The control means includes
After starting and after writing the soft error information to the storage area, reading the written soft error information from the nonvolatile memory;
The programmable logic device according to claim 1 or 2, further comprising: outputting the number of the soft error information read from the nonvolatile memory. The control means limits the number of the soft error information writable in the nonvolatile memory to a predetermined upper limit value or less, and after the number of the soft error information reaches the upper limit value, The programmable logic device according to claim 1, wherein writing of the soft error information is stopped. The control means includes
When outputting the number of the soft error information, in the storage area where the soft error information is not written, the address at the very beginning is held,
Of the plurality of storage areas included in the non-volatile memory, the soft error information in the non-volatile memory when the soft error information is next written to the storage area in which the soft error information is not written. The programmable logic device according to any one of claims 1 to 4, wherein data is written to the storage area indicated by the held address. In the storable area of the soft error information in the nonvolatile memory, all bits in all sectors in the storable area immediately after erasure in the initial state of the storable area or all sectors in the storable area Is 1,
The programmable logic device according to any one of claims 1 to 5, wherein the control unit writes data in units of bytes in which all bits are 0 as the soft error information. When the control means receives a signal instructing erasure in all sectors in the nonvolatile memory capable of storing the soft error information, the control means performs erasure in all sectors in the nonvolatile memory capable of storing the soft error information. The programmable logic device according to any one of claims 1 to 6. A device having a function of detecting a soft error in a built-in volatile memory, but not having a function of recording the detected soft error;
Non-volatile memory;
When a signal indicating the occurrence of the soft error is received from the device, the soft error information indicating the occurrence of the soft error is written in the plurality of storage areas included in the nonvolatile memory. An information processing apparatus comprising a programmable logic device including control means for writing only to the storage area that is not,
The programmable logic device is an information processing apparatus separate from the device. A programmable logic device having a function of detecting a soft error in a built-in volatile memory but not having a function of recording the detected soft error and a non-volatile memory connected to the device. Is
When a signal indicating the occurrence of the soft error is received from the device, the soft error information indicating the occurrence of the soft error is written in the plurality of storage areas included in the nonvolatile memory. A soft error recording method for writing only to the storage area. A programmable logic device having a function of detecting a soft error in a built-in volatile memory but not having a function of recording the detected soft error and a non-volatile memory connected to the device. In addition,
When a signal indicating the occurrence of the soft error is received from the device, the soft error information indicating the occurrence of the soft error is written in the plurality of storage areas included in the nonvolatile memory. A soft error recording program for executing a process of writing only to the storage area that is not.

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