JP2018010920A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which prevents probable solder spilling on a terminal side face at the time of forming the electrode terminals and ensures an intended solder quantity of a solder cap.SOLUTION: A semiconductor device has electrode terminals 10 on a surface of a semiconductor substrate 1. Each electrode terminal 10 is composed of a Cu layer 21, a first Ni layer 22 formed on the Cu layer 21, a porous second Ni layer 23 formed on the first Ni layer 22 and a Sn-containing layer 25 formed on the second Ni layer 23.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In recent years, as the technology node of semiconductor elements advances, the electrode terminals that connect the semiconductor elements or between the semiconductor elements and the circuit board tend to be miniaturized. For this reason, in a microbump that is a conventional electrode terminal, the terminal height decreases as the miniaturization progresses, and a gap between the semiconductor element for injecting the underfill material and the circuit board cannot be secured. Further, in the micro bump, since the solder has a drum shape, if a large amount of solder is formed in order to secure a terminal gap, a short circuit (bridge) between solders of adjacent electrode terminals is likely to occur. Therefore, Cu pillar bumps have been used as electrode terminals corresponding to miniaturization of semiconductor elements. The Cu pillar bump has a structure in which a solder cap is formed on a columnar Cu layer, and can be formed with a large ratio (aspect ratio) between the electrode diameter and the height (for example, about 1: 1).

  However, the Cu pillar bump has the following problems. Due to the further miniaturization of electrode terminals in recent years, the amount of solder that can be formed on the columnar Cu layer has decreased. Therefore, in the solder cap, the proportion of the Cu—Sn compound layer in the solder due to the reaction between the Cu layer and the solder increases. Due to the increase in the Cu—Sn compound layer, the solder material used for connection is reduced, leading to poor connection. In order to cope with this problem, a technique has been devised in which a Ni layer is formed between a Cu layer and a solder cap in a Cu pillar bump. Ni hardly reacts with the solder, and the Ni layer suppresses the reaction of the solder with Cu.

JP 2004-31755 A JP 2003-197665 A

When forming a Cu pillar bump, a columnar Cu layer and a solder layer are formed in a plating step, and then reflow is performed. This reflow is a process of melting and solidifying the solder, and is called wet back. Hereinafter, the solder before the wet back is referred to as “solder layer”, and the solder after the wet back is referred to as “solder cap”. The wet back is performed for the following purposes.
(1) In order to recognize the Cu pillar bump by the appearance inspection device, the solder is made hemispherical by wet back to give gloss and improve visibility.
(2) Suppresses the generation of voids in the connection part by removing the organic impurities taken into the solder layer during the plating process by once melting and solidifying the solder and gasifying the impurities contained in the solder. To do.

  In recent years, formic acid reflow using formic acid as a reducing agent has begun to be performed as one method of wetback. In wet back using formic acid, formic acid has the effect of removing the oxide film on the solder surface. Formic acid reacts with the oxide film at a temperature of about 150 ° C., forms formate and decomposes, so there is almost no residue, and it is a process that does not require flux cleaning after reflow like conventional rosin flux, The range of use is expanding.

  When wet back by this formic acid reflow is performed on a Cu pillar bump having a three-layer structure of a Cu layer, a Ni layer, and a solder layer, the formic acid greatly improves the wettability of the solder against Ni. Phenomenon that spills a lot to the side (solder spill) occurs. When solder spillage occurs, the solder amount of the solder cap decreases, and there is a problem that a sufficient amount of solder for connection cannot be secured.

  The present invention has been made in view of the above-described problems, and suppresses the phenomenon of Sn-containing material spilling on the side surface of the terminal, which is a concern at the time of forming an electrode terminal, and ensures the expected amount of Sn-containing layer. It is an object to provide a highly reliable semiconductor device and a method for manufacturing the same.

  One aspect of the semiconductor device is a semiconductor device having an electrode terminal on a surface of a substrate, the electrode terminal including a Cu layer, a first Ni layer formed on the Cu layer, and the first Ni A second Ni layer having a porous structure formed on the layer; and an Sn-containing layer formed on the second Ni layer.

  One aspect of a method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device having an electrode terminal on a surface of a substrate, wherein when the electrode terminal is formed, a step of forming a Cu layer on the surface of the substrate; Forming a first Ni layer on the layer; forming a second Ni layer having a porous structure on the first Ni layer; and forming an Sn-containing layer on the second Ni layer. And forming and heat-treating the Sn-containing layer.

  According to the above aspects, a spill phenomenon of Sn-containing material on the side surface of the terminal, which is a concern during formation of the electrode terminal, is suppressed, and a highly reliable semiconductor device in which an expected amount of the Sn-containing layer is ensured is realized. .

It is a schematic sectional drawing which shows the manufacturing method of the semiconductor element by 1st Embodiment in order of a process. FIG. 2 is a schematic cross-sectional view subsequent to FIG. 1, illustrating the method for manufacturing the semiconductor device according to the first embodiment in the order of steps. FIG. 3 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps, following FIG. 2. It is a schematic sectional drawing which shows the main processes of the manufacturing method of the semiconductor element by 2nd Embodiment. It is a schematic sectional drawing which shows a mode that the 2nd Ni layer of the semiconductor element by 2nd Embodiment was expanded. It is a schematic sectional drawing which shows typically the structure of the semiconductor device by 3rd Embodiment. It is a schematic sectional drawing which shows typically the structure of the semiconductor device by 4th Embodiment.

  Hereinafter, embodiments of a semiconductor device and a manufacturing method thereof will be described in detail with reference to the drawings.

(First embodiment)
In the present embodiment, the configuration of a semiconductor element (semiconductor chip) will be described along with its manufacturing method. 1 to 3 are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the present embodiment in the order of steps.

First, as shown in FIG. 1A, predetermined functional elements such as MOS transistors and multilayer wiring layers are formed on a semiconductor substrate 1.
Specifically, for example, a p-type semiconductor substrate 1 is prepared. An n-type impurity is ion-implanted into the surface of the semiconductor substrate 1 to form an n-type well 2. A gate insulating film and a gate electrode (not shown) are formed. A p-type impurity or an n-type impurity is ion-implanted into a region on both sides of the gate electrode in the semiconductor substrate 1 and a region in the vicinity thereof, to form a p-type region 3a, an n-type region 3b, a p-type source / drain region 4a, and an n-type. Source / drain regions 4b are formed. As described above, the p-type MOS transistor 10a including the gate electrode and the p-type source / drain region 4a and the n-type including the gate electrode and the n-type source / drain region 4b together with the p-type region 3a and the n-type region 3b. MOS transistor 10b is formed.

  Next, an interlayer insulating film 5 that covers the semiconductor substrate 1 is formed. Contact holes 5 a are formed in the interlayer insulating film 5. A base film such as Ti and Al are deposited on the interlayer insulating film 5 so as to fill the contact hole 5a. The base film and Al are processed by lithography and etching to form the first wiring 6. As described above, the first wiring layer 10c having the first wiring 6 connected to the p-type region 3a, the n-type region 3b, the p-type source / drain region 4a, and the n-type source / drain region 4b is formed.

  Next, an interlayer insulating film 7 covering the first wiring layer 10c is formed. Contact holes 7 a are formed in the interlayer insulating film 7. A base film such as Ti and Al are deposited on the interlayer insulating film 7 so as to fill the contact hole 7a. The base film and Al are processed by lithography and etching to form the second wiring 8. Thus, the second wiring layer 10d having the second wiring 8 connected to the first wiring 6 is formed.

  Next, an interlayer insulating film 9 that covers the semiconductor substrate 1 is formed. Contact holes 9 a are formed in the interlayer insulating film 9. A base film such as Ti and Al are deposited on the interlayer insulating film 9 so as to fill the contact hole 9a. The base film and Al are processed by lithography and etching to form the Al electrode 11. An upper insulating film 12 covering the Al electrode 11 is formed. The upper insulating film 12 is processed by lithography and etching to form an opening 12a that exposes a part of the surface of the Al electrode 11.

Subsequently, as shown in FIG. 1B, a Ti film 13 as a base film and a Cu film 14 as a plating seed film are formed. In FIG. 1B and subsequent figures, illustration of functional elements formed on the semiconductor substrate 1 and illustration of multilayer wiring layers other than the Al electrode 11 are omitted.
Specifically, a base metal, here Ti, is deposited to a thickness of about 100 nm on the upper insulating film 12 by, for example, sputtering so as to cover the inner wall surface of the opening 12a. Next, Cu to be a plating seed film is deposited to a thickness of about 200 nm by sputtering, for example. Thus, the Ti film 13 and the Cu film 14 thereon are formed.

Subsequently, as shown in FIG. 1C, a resist mask 15 for forming Cu pillar bumps is formed.
More specifically, a resist is applied on the entire surface to a thickness of about 50 μm, and openings 15a having a diameter of about 30 μm are formed in the resist at a pitch of about 50 μm by lithography. In this way, the resist mask 15 having the opening 15a exposing a part of the surface of the Cu film 14 located above the opening 12a is formed.

Subsequently, as shown in FIG. 2A, a Cu layer 21 is formed.
Specifically, Cu is deposited to a thickness of about 30 μm on the Cu film 14 in the opening 15a of the resist mask 15 by electrolytic plating. Thus, the Cu layer 21 electrically connected to the Al electrode 11 is formed.

Subsequently, as shown in FIG. 2B, a first Ni layer 22 is formed.
Specifically, Ni (Ni—P) containing phosphorus (P) is deposited on the Cu layer 21 in the opening 15a of the resist mask 15 by electroless plating. Specifically, the semiconductor substrate 1 is immersed in an electroless Ni—P plating solution in which the P concentration is adjusted to 10 wt% or more and 15 wt% or less by adjusting additives and pH. Thus, the first Ni layer 22 made of Ni—P and having a thickness of about 2 μm is formed. In the first Ni layer 22, the P concentration of Ni—P is set to a value in the range of 10 wt% or more and 15 wt% or less. When the P concentration is less than 10 wt%, the wettability with the solder described later is not sufficiently lowered. If the P concentration is higher than 15 wt%, it is difficult to form by plating, and the barrier property against solder of Ni described later becomes insufficient. By setting the P concentration to 10 wt% or more and 15 wt% or less, the first Ni layer 22 having a barrier property against solder and sufficiently low wettability with the solder is realized. In the present embodiment, the P concentration of the first Ni layer 22 is about 12 wt%.

Subsequently, as shown in FIG. 2C, a second Ni layer 23 having a porous structure is formed.
Specifically, a porous Ni (Ni-B) containing boron (B) is deposited on the first Ni layer 22 in the opening 15a of the resist mask 15 by electroless plating. Specifically, electroless Ni containing non-conductive particles (PTFE) having a diameter of about 0.5 μm and adjusting the additive, pH and the like to have a B concentration of 0.1 wt% to 0.5 wt%. -B The semiconductor substrate 1 is immersed in a plating solution. The electroless Ni—B plating is performed under predetermined conditions in which PTFE does not remain in the deposited Ni—B. In this way, the second Ni layer 23 made of Ni—B having a thickness of about 1 μm having a large number of pores 23a having a diameter of about 0.5 μm is formed instead of PTFE. In the second Ni layer 23, the B concentration of Ni-B is set to a value within a range of 0.1 wt% or more and 0.5 wt% or less. When the B concentration is less than 0.1 wt%, the effect of suppressing Ni oxidation due to oxidation of B becomes insufficient. If the B concentration is greater than 0.5 wt%, the amount of B oxide is too much and solder wettability decreases. By setting the B concentration to 0.1 wt% or more and 0.5 wt% or less, the second Ni layer 23 that suppresses the oxidation of Ni and sufficiently secures the wettability of the solder with respect to Ni—B is realized. In the present embodiment, the B concentration of the second Ni layer 23 is about 0.3 wt%.

Subsequently, as shown in FIG. 3A, a solder layer 24 is formed.
Specifically, a Su-containing layer, here, a solder layer 24 is formed on the second Ni layer 23 in the opening 15 a of the resist mask 15. Examples of the solder include Sn-Ag, Sn-Ag-Cu, Sn-Bi, and Sn-In. The solder layer 24 is formed by electrolytic solder plating to a thickness of about 11 μm using, for example, Sn-2.0 wt% Ag solder.

Subsequently, as shown in FIG. 3B, the resist mask 15 is removed, and the Ti film 13 and the Cu film 14 are etched.
Specifically, the resist mask 15 is removed by wet processing or ashing processing. Thereafter, the exposed portion between the adjacent Cu layers 21 of the Ti film 13 and the Cu film 14 is removed by etching.

Subsequently, as shown in FIG. 3C, the solder layer 24 is subjected to reflow processing.
Specifically, the solder layer 24 is reflowed (wet back) in a formic acid atmosphere. As a result, the solder layer 24 has a hemispherical shape with a height of about 15 μm and becomes a solder cap 25.
As described above, the Cu layer 21, the first Ni layer 22, the second Ni layer 23, and the solder cap 25 are sequentially stacked, and the Cu pillar bump 20 electrically connected to the Al electrode 11 is formed.

In the Cu pillar bump 20 of the present embodiment, the first Ni layer 22 and the second Ni layer 23 are inserted between the Cu layer 21 and the solder cap 25.
The second Ni layer 23 is made of Ni-B having a porous structure. By containing B, the oxidation of Ni is suppressed and the wettability of the solder is sufficiently ensured. Even if the solder layer 24 is subjected to reflow treatment in an atmosphere that greatly improves the wettability of the solder such as formic acid, the solder is impregnated into the porous 23a in the second Ni layer 23, and Ni— An alloy of B and solder is formed, and no remelted solder remains. Therefore, solder spillage on the side surface of the second Ni layer 23 due to the wet back process is suppressed.

  The first Ni layer 22 is made of Ni—P and supports the suppression of solder spillage by the second Ni layer 23. If the first Ni layer 22 is not provided, the second Ni layer 23 has a porous structure, so that there is a concern that the solder reacts with the underlying Cu through the second Ni layer 23. By providing the first Ni layer 22 between the Cu layer 21 and the second Ni layer 23, the reaction of the solder with Cu is reliably prevented. Even if some solder spillage occurs in the second Ni layer 23, the solder spillage is surely suppressed by Ni—P having low wettability with the solder, and the spilled solder reaches the Cu layer 21. Concerns are dispelled.

  As described above, in the present embodiment, the Cu pillar bump 20 ensures a sufficient barrier property against solder without causing solder spillage on the side surface of the bump. In this case, a hemispherical solder cap 25 in which the desired amount of solder is maintained can be obtained, and a fine Cu pillar bump 20 having a large aspect ratio that reliably suppresses the reaction of the solder with Cu is realized.

  As described above, according to the present embodiment, solder spillage to the side surface of the bump, which is a concern during formation of the Cu pillar bump 20, is reliably suppressed, and a desired amount of solder for the solder cap 25 is ensured with high reliability. A semiconductor element is realized.

(Second Embodiment)
In the present embodiment, as in the first embodiment, the configuration of the semiconductor element (semiconductor chip) will be described together with the manufacturing method thereof. However, the configuration of the second Ni layer is slightly different from the first embodiment. This is different from the first embodiment. FIG. 4 is a schematic cross-sectional view showing the main steps of the semiconductor device manufacturing method according to the present embodiment.

  First, similarly to the first embodiment, the processes of FIGS. 1A to 2B are performed. On the Cu layer 21 in the opening 15a of the resist mask 15, a first Ni layer 22 made of Ni—P having a P concentration of, for example, about 10 wt% is formed.

Subsequently, as shown in FIG. 4A, a second Ni layer 31 having a porous structure is formed. FIG. 5 shows an enlarged view of the second Ni layer 31.
Specifically, first, the semiconductor substrate 1 is immersed in an electroless Ni—P plating solution containing non-conductive particles (PTFE) having a diameter of about 1.0 μm and having a P concentration adjusted to, for example, about 7 wt%. The electroless Ni—P plating is performed under predetermined conditions in which PTFE does not remain in the deposited Ni—P. As described above, the first layer 31A made of Ni—P having a thickness of about 2 μm and having a large number of porous 31a having a diameter of about 1.0 μm is formed on the first Ni layer 22 instead of PTFE.

Immediately after forming the first layer 31A, the semiconductor substrate 1 is immersed in an electroless Ni—B plating solution in which the B concentration is adjusted to 0.1 wt% or more and 0.5 wt% or less, for example, about 0.5 wt%. Thereby, the second layer 31B made of Ni—B having a thickness of about 0.2 μm is formed to cover the surface of the porous 31a in the first layer 31A. When the B concentration is less than 0.1 wt%, the effect of suppressing Ni oxidation due to oxidation of B becomes insufficient. If the B concentration is greater than 0.5 wt%, the amount of B oxide is too much and solder wettability decreases. By setting the B concentration to be 0.1 wt% or more and 0.5 wt% or less, Ni oxidation can be suppressed and solder wettability to Ni-B can be sufficiently secured.
As a result, the second Ni layer 31 having the first layer 31A and the second layer 31B covering the surface of the porous 31a existing therein is formed on the first Ni layer 22.

  Thereafter, similar to the first embodiment, the steps shown in FIGS. 3A to 3C are performed. 4B, the Cu layer 21, the first Ni layer 22, the second Ni layer 31, and the solder cap 25 are sequentially stacked, and are electrically connected to the Al electrode 11. Cu pillar bumps 30 are formed.

In the Cu pillar bump 30 of the present embodiment, the first Ni layer 22 and the second Ni layer 31 are inserted between the Cu layer 21 and the solder cap 25.
The second Ni layer 31 includes a first layer 31A made of Ni—P and a second layer 31B made of Ni—B covering the surface of the porous 31a existing therein. When the second layer 31B contains B, oxidation of Ni is suppressed and solder wettability is sufficiently ensured. Even if the solder layer 24 is subjected to reflow treatment in an atmosphere that greatly improves the wettability of the solder such as formic acid, the solder is impregnated into the porous 31a in the first layer 31A and Ni-B and An alloy with the solder is formed, and no remelted solder remains. Therefore, solder spillage on the side surface of the second Ni layer 31 (Ni-P first layer 31A) is suppressed.

  The first Ni layer 22 is made of Ni—P and supports the suppression of solder spillage by the second Ni layer 23. If the first Ni layer 22 is not provided, the second Ni layer 23 has a porous structure, so that there is a concern that the solder reacts with the underlying Cu through the second Ni layer 23. By providing the first Ni layer 22 between the Cu layer 21 and the second Ni layer 23, the reaction of the solder with Cu is reliably prevented. Even if some solder spillage occurs in the second Ni layer 23, the solder spillage is surely suppressed by Ni—P having low wettability with the solder, and the spilled solder reaches the Cu layer 21. Concerns are dispelled.

  As described above, in this embodiment, the Cu pillar bump 30 ensures a sufficient barrier property against solder without causing solder spillage on the bump side surface. In this case, the hemispherical solder cap 25 in which the desired amount of solder is maintained can be obtained, and a fine Cu pillar bump 30 having a large aspect ratio that reliably suppresses the reaction of the solder with Cu is realized.

  As described above, according to the present embodiment, solder spillage onto the bump side surface, which is a concern during formation of the Cu pillar bump 30, is reliably suppressed, and a desired amount of solder for the solder cap 25 is ensured. A semiconductor element is realized.

(Third embodiment)
In the present embodiment, a semiconductor device in which a pair of semiconductor elements (semiconductor chips) are joined will be described. FIG. 6 is a schematic cross-sectional view schematically showing the configuration of the semiconductor device according to the present embodiment.

  Each semiconductor element constituting the semiconductor device of this embodiment is the semiconductor element according to the first or second embodiment. When the semiconductor device according to the first embodiment is used, the semiconductor device including the Cu pillar bumps 20 is formed through the steps of FIGS. 1A to 3C. When the semiconductor device according to the second embodiment is used, the steps shown in FIGS. 1A to 2B, 4A, and 3A to 3C are performed. A semiconductor element provided with a Cu pillar bump 30 as shown in 4 (b) is formed. In this embodiment, the case where the semiconductor element according to the first embodiment is used is illustrated, and this is referred to as a semiconductor element 40.

In this semiconductor device, a pair of semiconductor elements 40 are arranged with the Cu pillar bumps 20 facing each other, and are connected by a solder cap 25.
According to the present embodiment, a pair of semiconductor elements 40 in which the expected solder amount of the solder cap 25 is secured are bonded to each other by reliably suppressing solder spillage on the bump side surface, which is a concern when forming the Cu pillar bump 20. A highly reliable semiconductor device is realized.

(Fourth embodiment)
In the present embodiment, a semiconductor device in which a semiconductor element (semiconductor chip) is bonded to a circuit board will be described. FIG. 7 is a schematic cross-sectional view schematically showing the configuration of the semiconductor device according to the present embodiment.

  The semiconductor element that is a component of the semiconductor device of this embodiment is the semiconductor element according to the first or second embodiment. When the semiconductor device according to the first embodiment is used, the semiconductor device including the Cu pillar bumps 20 is formed through the steps of FIGS. 1A to 3C. When the semiconductor device according to the second embodiment is used, the steps shown in FIGS. 1A to 2B, 4A, and 3A to 3C are performed. A semiconductor element provided with a Cu pillar bump 30 as shown in 4 (b) is formed. In this embodiment, the case where the semiconductor element according to the first embodiment is used is illustrated, and this is referred to as a semiconductor element 40.

  This semiconductor device includes a circuit board 50 and a semiconductor element 40. The circuit board 50 includes a connection electrode 52 provided on the surface of a resin substrate 51 on which functional elements such as CMOS transistors are formed, and a solder resist 53 that covers the connection electrode 52 is formed. The connection electrode 52 includes a Cu layer 54 electrically connected to a functional element or the like, and a Ni layer 55 formed on the Cu layer 54. In the semiconductor device according to the present embodiment, the circuit board 50 and the semiconductor element 40 are arranged such that the connection electrode 52 and the Cu pillar bump 20 face each other, and are connected by the solder cap 25.

  According to the present embodiment, the semiconductor element 40 in which solder spillage to the side surface of the bump, which is a concern during the formation of the Cu pillar bump 20, is reliably suppressed and the desired amount of solder of the solder cap 25 is secured to the circuit board 50. Thus, a highly reliable semiconductor device is realized.

  Hereinafter, various aspects of the semiconductor device and the manufacturing method thereof will be collectively described as supplementary notes.

(Appendix 1) A semiconductor device having electrode terminals on the surface of a substrate,
The electrode terminal is
A Cu layer;
A first Ni layer formed on the Cu layer;
A second Ni layer having a porous structure formed on the first Ni layer;
And a Sn-containing layer formed on the second Ni layer.

  (Additional remark 2) The said 1st Ni layer contains P, The semiconductor device of Additional remark 1 characterized by the above-mentioned.

  (Supplementary note 3) The semiconductor device according to supplementary note 2, wherein the first Ni layer has a P concentration in a range of 10 wt% to 15 wt%.

  (Supplementary note 4) The semiconductor device according to any one of supplementary notes 1 to 3, wherein the second Ni layer contains B.

  (Supplementary note 5) The semiconductor device according to supplementary note 4, wherein the second Ni layer has a B concentration in a range of 0.1 wt% to 0.5 wt%.

  (Appendix 6) The semiconductor device according to any one of appendices 1 to 3, wherein the second Ni layer has a plurality of holes therein.

  (Additional remark 7) The said 2nd Ni layer has the void | hole by which the surface was coat | covered with the 2nd layer containing B in the 1st layer containing P, The additional remark 1 characterized by the above-mentioned. 4. The semiconductor device according to any one of items 3.

(Appendix 8) A method for manufacturing a semiconductor device having an electrode terminal on a surface of a substrate,
In forming the electrode terminal,
Forming a Cu layer on the surface of the substrate;
Forming a first Ni layer on the Cu layer;
Forming a second Ni layer having a porous structure on the first Ni layer;
Forming a Sn-containing layer on the second Ni layer;
And a step of heat-treating the Sn-containing layer.

  (Supplementary note 9) The method for manufacturing a semiconductor device according to supplementary note 8, wherein the first Ni layer contains P.

  (Supplementary note 10) The method for manufacturing a semiconductor device according to supplementary note 9, wherein the first Ni layer has a P concentration in a range of 10 wt% to 15 wt%.

  (Additional remark 11) The said 2nd Ni layer contains B, The manufacturing method of the semiconductor device of any one of Additional remark 8-10 characterized by the above-mentioned.

  (Supplementary note 12) The method for manufacturing a semiconductor device according to supplementary note 11, wherein the second Ni layer has a B concentration in a range of 0.1 wt% to 0.5 wt%.

  (Additional remark 13) The said 2nd Ni layer has a some void | hole inside, The manufacturing method of the semiconductor device of any one of Additional remark 8-10 characterized by the above-mentioned.

  (Additional remark 14) The said 2nd Ni layer has the void | hole by which the surface was coat | covered with the 2nd layer containing B in the 1st layer containing P, The additional remarks 8-8 characterized by the above-mentioned. 11. A method for manufacturing a semiconductor device according to any one of 10 above.

  (Supplementary note 15) The method for manufacturing a semiconductor device according to any one of supplementary notes 8 to 14, wherein the step of heat-treating the Sn-containing layer is performed in a formic acid atmosphere.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 n-type well 3a p-type area | region 3b n-type area | region 4a p-type source / drain area | region 4b n-type source / drain area | region 5, 7, 9 Interlayer insulating film 5a, 7a Contact hole 6 1st wiring 8 2nd wiring 10a p-type MOS transistor 10b c-type MOS transistor 10c first wiring layer 10d second wiring layer 11 Al electrode 12 upper insulating film 12a, 15a opening 13 Ti film 14 Cu film 15 resist mask 20, 30 Cu pillar bumps 21, 54 Cu layer 22 1st Ni layer 23, 31 2nd Ni layer 23a, 31a Porous 24 Solder layer 25 Solder cap 31A First layer 31B Second layer 40 Semiconductor element 50 Circuit board 51 Resin board 52 Connection electrode 53 Solder resist 55 Ni layer

Claims (14)

A semiconductor device having electrode terminals on the surface of a substrate,
The electrode terminal is
A Cu layer;
A first Ni layer formed on the Cu layer;
A second Ni layer having a porous structure formed on the first Ni layer;
And a Sn-containing layer formed on the second Ni layer.   The semiconductor device according to claim 1, wherein the first Ni layer contains P.   The semiconductor device according to claim 2, wherein the first Ni layer has a P concentration in a range of 10 wt% to 15 wt%.   4. The semiconductor device according to claim 1, wherein the second Ni layer contains B. 5.   5. The semiconductor device according to claim 4, wherein the second Ni layer has a B concentration in a range of 0.1 wt% or more and 0.5 wt% or less.   The semiconductor device according to claim 1, wherein the second Ni layer has a plurality of holes therein.   The said 2nd Ni layer has the void | hole by which the surface was coat | covered by the 2nd layer containing B in the 1st layer containing P, The any one of Claims 1-3 characterized by the above-mentioned. 2. The semiconductor device according to claim 1. A method of manufacturing a semiconductor device having an electrode terminal on a surface of a substrate,
In forming the electrode terminal,
Forming a Cu layer on the surface of the substrate;
Forming a first Ni layer on the Cu layer;
Forming a second Ni layer having a porous structure on the first Ni layer;
Forming a Sn-containing layer on the second Ni layer;
And a step of heat-treating the Sn-containing layer.   9. The method of manufacturing a semiconductor device according to claim 8, wherein the first Ni layer contains P.   The method for manufacturing a semiconductor device according to claim 9, wherein the first Ni layer has a P concentration in a range of 10 wt% or more and 15 wt% or less.   11. The method of manufacturing a semiconductor device according to claim 8, wherein the second Ni layer contains B. 11.   The method for manufacturing a semiconductor device according to claim 11, wherein the second Ni layer has a B concentration in a range of 0.1 wt% or more and 0.5 wt% or less.   The method for manufacturing a semiconductor device according to claim 8, wherein the second Ni layer has a plurality of holes therein.   The said 2nd Ni layer has the void | hole by which the surface was coat | covered with the 2nd layer containing B in the 1st layer containing P, The any one of Claims 8-10 characterized by the above-mentioned. A method for manufacturing a semiconductor device according to claim 1.

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