JP2017518186A - Process for permanently joining two parts by transient liquid phase interdiffusion - Google Patents

Process for permanently joining two parts by transient liquid phase interdiffusion Download PDF

Info

Publication number
JP2017518186A
JP2017518186A JP2016570808A JP2016570808A JP2017518186A JP 2017518186 A JP2017518186 A JP 2017518186A JP 2016570808 A JP2016570808 A JP 2016570808A JP 2016570808 A JP2016570808 A JP 2016570808A JP 2017518186 A JP2017518186 A JP 2017518186A
Authority
JP
Japan
Prior art keywords
metal
layer
joining
silver
tin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2016570808A
Other languages
Japanese (ja)
Other versions
JP6636465B2 (en
JP2017518186A5 (en
Inventor
ジャン−ミシェル、モレル
ローラン、ビベ
キ、リム、タン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Valeo Equipements Electriques Moteur SAS
Original Assignee
Valeo Equipements Electriques Moteur SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Valeo Equipements Electriques Moteur SAS filed Critical Valeo Equipements Electriques Moteur SAS
Publication of JP2017518186A publication Critical patent/JP2017518186A/en
Publication of JP2017518186A5 publication Critical patent/JP2017518186A5/ja
Application granted granted Critical
Publication of JP6636465B2 publication Critical patent/JP6636465B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2741—Manufacturing methods by blanket deposition of the material of the layer connector in liquid form
    • H01L2224/27418—Spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2746—Plating
    • H01L2224/27462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/275—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • H01L2224/27505—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/2908—Plural core members being stacked
    • H01L2224/29082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325—Material
    • H01L2224/32505—Material outside the bonding interface, e.g. in the bulk of the layer connector
    • H01L2224/32507—Material outside the bonding interface, e.g. in the bulk of the layer connector comprising an intermetallic compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75251—Means for applying energy, e.g. heating means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83455—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/8381—Soldering or alloying involving forming an intermetallic compound at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/8382—Diffusion bonding
    • H01L2224/83825—Solid-liquid interdiffusion

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Other Surface Treatments For Metallic Materials (AREA)
  • Die Bonding (AREA)

Abstract

本発明は、第１金属と第２金属との相互拡散を利用して、第１部材（８）と第２部材（１１）とを接合するプロセスに関する。プロセスは、一連の、第１金属から成る少なくとも１つの層を、第１部材と第２部材の接合面に蒸着するステップと、第１金属でコーティングされた接合面の間に、第２金属から成る層（１５）を挟み込むステップと、第１部材と第２部材に圧力（１８）を加え、接合面を互いに可能な限り密着させるステップと、形成された接合体を熱することで、第２金属の層を融解させ、第１・第２金属から成る金属間層を発生・成長させて作製し、第１部材と第２部材を接合するステップとを備える。本発明によれば、第１金属の層（１４）は間隙のある構造を有し、これにより、この層に対する第２金属の浸透を促進させる。The present invention relates to a process for joining a first member (8) and a second member (11) by utilizing mutual diffusion between a first metal and a second metal. The process includes depositing a series of at least one layer of a first metal on a joining surface of the first member and the second member and from the second metal between the joining surface coated with the first metal. A step of sandwiching the layer (15) formed, a step of applying pressure (18) to the first member and the second member to bring the joining surfaces into close contact with each other as much as possible, and heating the formed joined body Melting a metal layer, generating and growing an intermetallic layer composed of first and second metals, and joining the first member and the second member. According to the present invention, the first metal layer (14) has a gap structure, thereby promoting the penetration of the second metal into this layer.

Description

本発明は、過渡液相相互拡散を利用した２つの部材の永久接合一般に関する。   The present invention relates generally to permanent joining of two members utilizing transient liquid phase interdiffusion.

本発明は特に、少なくとも２つの接合部材を垂直に積み重ねた電子構造体の接合に関する。   In particular, the present invention relates to joining electronic structures in which at least two joining members are stacked vertically.

先行技術においては、過渡液相接合プロセスが知られており、これは電子部品の接合に使用される。この際、固体の銀と液体のスズの間での相互拡散が利用される。   In the prior art, transient liquid phase bonding processes are known, which are used for bonding electronic components. Here, interdiffusion between solid silver and liquid tin is utilized.

このプロセスにおいては、図１ａに示すように、２つの接合部分１、１’が、それぞれ薄い銀層（Ａｇ）２、２’によってコーティングされる。銀層２、２’の間には、薄いスズ層（Ｓｎ）４が、固体ストリップの形で配置される。このストリップは、通常５μｍ程度の厚さを有する。銀層２、２’は、平坦で緻密な層として作製され、通常１５μｍ程度の厚さを有する。   In this process, as shown in FIG. 1a, two joints 1, 1 'are coated with a thin silver layer (Ag) 2, 2', respectively. Between the silver layers 2, 2 ', a thin tin layer (Sn) 4 is arranged in the form of a solid strip. This strip usually has a thickness of the order of 5 μm. The silver layers 2 and 2 'are produced as flat and dense layers, and usually have a thickness of about 15 μm.

接合する際には、通常、７５から１２０キロパスカル（ｋＰａ）程度の圧力が上記のＡｇ／Ｓｎ／Ａｇ積層に加えられる。積層は、用途によって異なるが、数分から数時間の間、３００℃で加熱される。温度が上昇するにつれて、スズのストリップ４が溶け始め、銀層２、２’の表面を濡らす形となる。これにより、不均質な箇所で金属間化合物の発生・成長の現象が起こり、銀層２、２’の表面に微小な欠陥３を形成する。   When joining, a pressure on the order of 75 to 120 kilopascals (kPa) is usually applied to the Ag / Sn / Ag stack. Lamination is heated at 300 ° C. for minutes to hours, depending on the application. As the temperature rises, the tin strip 4 begins to melt and wets the surface of the silver layer 2, 2 '. As a result, the phenomenon of generation / growth of intermetallic compounds occurs at non-homogeneous locations, and minute defects 3 are formed on the surfaces of the silver layers 2, 2 ′.

このような発生・成長の典型的なメカニズムを図１ｂ及び１ｃに示す。液体のスズ４は銀層２、２’の表面を濡らし、その後、ＳｎＡｇの二元相図に示すように、金属間化合物５の核の等方性成長６により、金属間化合物Ａｇ３Ｓｎの固体層が形成される。金属間化合物５は、スズを多く含む液相４と同時に存在し、その組成は温度に依存して変化する。また、その融点は共晶混合物Ｓｎ９６．２％Ａｇ３．８％の融点となる。この融点は、純粋なスズの融点（２３２℃）よりもかなり低い（２２１．３℃）。接合体が共晶混合物の融点（２２１．３℃）よりも高い温度に維持されると、銀が金属間化合物層を通って液体のスズの界面まで拡散し、Ａｇ３Ｓｎの金属間化合物相が成長する。よって、金属間化合物相の粒子６が、２つの銀層２、２’から成長する。これらの粒子６は、等軸で、Ａｇ/Ｓｎ界面に垂直な成長を優先的に示し、またこの成長によって、図１ｃに示す配向された粒子の境界７が形成される。なお、銀の金属間化合物層を通る拡散経路は、粒子の成長とともに長くなる。 A typical mechanism of such generation and growth is shown in FIGS. 1b and 1c. The liquid tin 4 wets the surface of the silver layer 2, 2 ′, and then the isotropic growth 6 of the intermetallic compound 5 nuclei results in the intermetallic compound Ag 3 Sn as shown in the SnAg binary phase diagram. A solid layer is formed. The intermetallic compound 5 exists simultaneously with the liquid phase 4 containing a large amount of tin, and its composition changes depending on the temperature. Further, the melting point thereof is the eutectic mixture Sn 96.2% Ag 3.8%. This melting point is considerably lower (221.3 ° C.) than that of pure tin (232 ° C.). When the joined body is maintained at a temperature higher than the melting point (221.3 ° C.) of the eutectic mixture, silver diffuses through the intermetallic compound layer to the liquid tin interface, and the Ag 3 Sn intermetallic phase. Will grow. Thus, intermetallic phase particles 6 grow from the two silver layers 2, 2 ′. These grains 6 preferentially grow equiaxed and perpendicular to the Ag / Sn interface, and this growth forms the boundaries 7 of the oriented grains shown in FIG. 1c. The diffusion path through the silver intermetallic compound layer becomes longer as the grains grow.

スズを多く含む液相が消費されて、金属間化合物の粒子で置換されると、２つの部材１、１’が接合される。よって、接合プロセスの間中、比較的低い温度に留まることで（≦３５０℃）、融点がかなり高い金属間結合が形成される（Ｔｓｏｌｉｄｕｓ＝４８０℃、Ｔｌｉｑｕｉｄｕｓ≒６８０℃）。 When the liquid phase containing a large amount of tin is consumed and replaced with particles of an intermetallic compound, the two members 1 and 1 ′ are joined. Thus, by staying at a relatively low temperature during the bonding process (≦ 350 ° C.), an intermetallic bond with a fairly high melting point is formed (T solidus = 480 ° C., T liquidus ≈680 ° C.).

この既知の接合プロセスの欠点は、接合が完了すると、金属間結合が、結合面に対して垂直に配向された大きくて細長い粒子を含むことにある。このような結晶構造は、金属間結合の機械的特性を変化させ、弾性限界や破壊応力を低下させることが知られている。また、接合に伴う時間を短縮することも望まれている。   A disadvantage of this known bonding process is that when the bonding is completed, the intermetallic bond includes large and elongated particles oriented perpendicular to the bonding surface. Such a crystal structure is known to change the mechanical properties of the metal-to-metal bond and reduce the elastic limit and fracture stress. It is also desired to reduce the time required for joining.

第１の態様によれば、本発明は、第１金属と第２金属との相互拡散を利用して、第１部材と第２部材とを接合するプロセスである。前記第２金属は前記第１金属の融点よりも十分に低い融点を持つ。前記プロセスは、一連の、前記第１金属から成る少なくとも１つの層を、前記第１部材の第１接合面と、前記第２部材の第２接合面のそれぞれに蒸着するステップと、前記第１金属でコーティングされた前記第１接合面と前記第２接合面との間に、前記第２金属から成る層を挟み込むステップと、前記第１部材と前記第２部材に圧力を加え、前記第１接合面と前記第２接合面を互いに可能な限り密着させるステップと、前記第１部材と前記第２部材から形成された接合体を所定の時間熱することで、前記第２金属の前記層を融解させ、第１・第２金属から成る金属間層を発生・成長させて作製し、前記第１部材と前記第２部材を接合するステップとを備える。   According to the first aspect, the present invention is a process for joining the first member and the second member using mutual diffusion between the first metal and the second metal. The second metal has a melting point sufficiently lower than the melting point of the first metal. The process includes depositing a series of at least one layer of the first metal on each of the first joint surface of the first member and the second joint surface of the second member; Sandwiching a layer made of the second metal between the first joint surface coated with metal and the second joint surface, and applying pressure to the first member and the second member, The step of bringing the joining surface and the second joining surface into close contact with each other as much as possible, and heating the joined body formed from the first member and the second member for a predetermined time, thereby causing the layer of the second metal to Melting, producing and growing an intermetallic layer composed of first and second metals, and joining the first member and the second member.

既に説明した先行技術による接合プロセスと比較した場合、間隙のある構造を有する銀層を設けることによって、金属間化合物のより速い粒成長が可能になり、結果として、接合時間の短縮につながる。これは、銀と液体のスズとの間の相互拡散が起こる交換表面の面積が小さくなることと、銀が金属間化合物を通って液相のスズに至る拡散経路が短くなることによる。   Compared with the prior art bonding process already described, the provision of a silver layer with a gap structure allows faster grain growth of the intermetallic compound, resulting in reduced bonding time. This is because the area of the exchange surface where interdiffusion between silver and liquid tin occurs is reduced, and the diffusion path of silver through the intermetallic compound to the liquid phase tin is shortened.

本発明の特徴によれば、間隙のある構造を有する前記銀層は、少なくとも部分的に多孔質、及び/または粒状の層である。   According to a feature of the invention, the silver layer having a gap structure is at least partially porous and / or granular.

本発明の他の特徴によれば、前記スズ層はスズの固体ストリップである。   According to another feature of the invention, the tin layer is a solid strip of tin.

本発明の他の特徴によれば、前記第１及び第２部材に加えられる前記圧力は、概ね９ｋＰａから５５ｋＰａの間である。   According to another feature of the invention, the pressure applied to the first and second members is generally between 9 kPa and 55 kPa.

本発明の他の特徴によれば、前記第１部材と前記第２部材とから成る前記接合体は、概ね２分から１５分間、概ね２５０℃から３５０℃の間の温度で加熱される。   According to another feature of the invention, the assembly comprising the first member and the second member is heated at a temperature between approximately 250 ° C. and 350 ° C. for approximately 2 to 15 minutes.

本発明の他の特徴によれば、前記第１部材は、少なくとも１本の銅配線を有する基板であり、前記第２部材は、前記銅配線に接合される電子チップである。   According to another feature of the invention, the first member is a substrate having at least one copper wiring, and the second member is an electronic chip bonded to the copper wiring.

本発明の他の態様によれば、本発明は、第１接合部材と第２部接合材が以下に記載する接合プロセスによって接合される接合体に関する。   According to another aspect of the present invention, the present invention relates to a joined body in which a first joining member and a second part joining material are joined by a joining process described below.

本発明の他の利点や特徴は、以下の具体的な実施形態の説明と添付の図面を参照することで明らかになる。   Other advantages and features of the present invention will become apparent with reference to the following description of specific embodiments and the accompanying drawings.

図１ａ、１ｂ、１ｃは先行技術に関わり、それぞれ、既知の過渡液相接合プロセスにおける、２つの部材を接合する前のステップ、金属間化合物相の発生ステップ、金属間化合物の粒成長ステップを示す。FIGS. 1a, 1b and 1c relate to the prior art and show the steps prior to joining two members, the intermetallic phase generation step and the intermetallic grain growth step, respectively, in a known transient liquid phase joining process. . 図２ａ、２ｂ、２ｃは本発明に関わり、それぞれ、本発明の実施形態による接合プロセスにおける、２つの部材を接合する前のステップ、第１金属（Ａｇ）層へと浸透させる第２金属（Ｓｎ）の融解ステップ、２つの部材の間に金属間結合が形成された接合完了ステップを示す。Figures 2a, 2b, 2c relate to the present invention, respectively, a step prior to bonding two members in a bonding process according to an embodiment of the present invention, a second metal (Sn) that penetrates the first metal (Ag) layer. ) Melting step, and a joining completion step in which an intermetallic bond is formed between the two members. 図３ａ、３ｂ、３ｃは本発明に関わり、図２ａ、２ｂ、２ｃに示す実施形態における金属間結合が形成されるプロセスを示す。3a, 3b, 3c relate to the present invention and illustrate the process by which the intermetallic bond is formed in the embodiment shown in FIGS. 2a, 2b, 2c.

以下、図２ａから２ｃ及び図３ａから３ｃを基に、本発明の接合プロセスの実施形態を説明する。この実施形態は、基板にベア電子チップを接合する際に適用でき、また２つの金属ＳｎとＡｇの組み合わせを使用する。   Hereinafter, an embodiment of the bonding process of the present invention will be described based on FIGS. 2a to 2c and FIGS. This embodiment can be applied when bonding a bare electronic chip to a substrate, and uses a combination of two metals Sn and Ag.

図２ａに示すように、基板８は、例えば１ｍｍから２ｍｍの厚さの銅配線８’を備える。銅配線８’は、電解蒸着によって、例えば４μｍ程度の厚さのニッケル層９で覆われる。その後、本実施形態では概ね５００ｎｍの厚さの銀層１０を、例えば「フラッシュ」蒸着によってニッケル層９に蒸着する。   As shown in FIG. 2a, the substrate 8 includes a copper wiring 8 'having a thickness of 1 mm to 2 mm, for example. The copper wiring 8 ′ is covered with a nickel layer 9 having a thickness of about 4 μm, for example, by electrolytic deposition. Thereafter, in this embodiment, a silver layer 10 having a thickness of approximately 500 nm is deposited on the nickel layer 9 by, for example, “flash” deposition.

電子チップ１１はこの場合シリコンウェーハであり、例えば２００μｍの厚さを有する。その接合面は、例えば５００ｎｍ程度の厚さのニッケル層１２によって覆われる。その後、銀層１０と同様の銀層１３を、例えば「フラッシュ」蒸着によってニッケル層１２に蒸着する。   In this case, the electronic chip 11 is a silicon wafer and has a thickness of 200 μm, for example. The joint surface is covered with a nickel layer 12 having a thickness of about 500 nm, for example. Thereafter, a silver layer 13 similar to the silver layer 10 is deposited on the nickel layer 12 by, for example, “flash” deposition.

本発明による接合プロセスによれば、２０μｍ程度の厚さの多孔質銀層１４が、基板８の銀層１０に蒸着される。   According to the bonding process of the present invention, a porous silver layer 14 having a thickness of about 20 μm is deposited on the silver layer 10 of the substrate 8.

後述する実施形態にもよるが、本発明の接合プロセスにおいては、多孔質銀層１４を形成するには様々な蒸着法が使用できる。   Although depending on the embodiments described later, various vapor deposition methods can be used to form the porous silver layer 14 in the bonding process of the present invention.

本発明によるプロセスの本実施形態においては、いわゆる「コールドスプレー」法によって、多孔質銀層１４が蒸着される。その際、直径が２μｍから５μｍの銀粒子を銀層９の表面に噴射する。   In this embodiment of the process according to the invention, the porous silver layer 14 is deposited by the so-called “cold spray” method. At that time, silver particles having a diameter of 2 μm to 5 μm are sprayed onto the surface of the silver layer 9.

また、本発明によるプロセスの実施形態にもよるが、粉末状の銀を部分焼結する方法や、パウダープラズマ蒸着などによっても、多孔質銀層１４を蒸着することができる。   Further, although depending on the embodiment of the process according to the present invention, the porous silver layer 14 can be deposited by a method of partially sintering powdered silver, powder plasma deposition, or the like.

多孔質銀層１４を形成した後には、５μｍ程度の厚さの緻密なスズ層１５が、一般的な電解蒸着法によって多孔質銀層１４に蒸着される。   After the porous silver layer 14 is formed, a dense tin layer 15 having a thickness of about 5 μm is deposited on the porous silver layer 14 by a general electrolytic deposition method.

この段階で、基板８、８’、９、１０と、多孔質銀層１４と、緻密なスズ層１５とから成る接合体が、加熱プレート１６に載置されることとなる。   At this stage, the joined body composed of the substrates 8, 8 ′, 9, 10, the porous silver layer 14, and the dense tin layer 15 is placed on the heating plate 16.

その後、アクチュエータ１８に固定されたグリップツール１７を使用して吸引により電子チップ１１、１２、１３を持ち上げ、多孔質銀層１４の表面に蒸着し固定する。その後、本発明によるプロセスの本実施形態においては、アクチュエータ１８が、２５ｋＰａ程度に制御された圧力を全構造体に加え続ける。なお、この圧力は用途によって異なるが、通常９ｋＰａから５５ｋＰａの間である。加熱プレート１６の温度は、毎秒６０℃程度の加熱の割合で３００℃まで上げられる。なお、この温度は用途によって異なるが、通常概ね２５０℃から３５０℃の間である。また一般的には、第２金属（つまり、スズ（Ｓｎ））の融点は、第１金属（つまり、銀（Ａｇ））の融点よりも十分低くなくてはならない。この段階で、上記の温度によって、緻密なスズ層１５が溶ける。液体となったスズは、図２ｂに示すように、多孔質銀層１４に浸入する。   Thereafter, the gripping tool 17 fixed to the actuator 18 is used to lift the electronic chips 11, 12, 13 by suction, and the vapor deposition is fixed on the surface of the porous silver layer 14. Thereafter, in this embodiment of the process according to the present invention, the actuator 18 continues to apply a pressure controlled to about 25 kPa to the entire structure. Although this pressure varies depending on the application, it is usually between 9 kPa and 55 kPa. The temperature of the heating plate 16 is raised to 300 ° C. at a heating rate of about 60 ° C. per second. Although this temperature varies depending on the application, it is generally between 250 ° C. and 350 ° C. In general, the melting point of the second metal (that is, tin (Sn)) must be sufficiently lower than the melting point of the first metal (that is, silver (Ag)). At this stage, the dense tin layer 15 is melted by the above temperature. The liquid tin enters the porous silver layer 14 as shown in FIG. 2b.

加熱プレート１６の温度は、概ね３分間３００℃に維持され、その後冷却される。アクチュエータ１８が加える圧力は、加熱プレート１６の温度が再度２００℃を下回るまで維持される。基板８に対する電子チップ１１の接合は、図２ｂに示す最終構造を有する。   The temperature of the heating plate 16 is maintained at 300 ° C. for approximately 3 minutes and then cooled. The pressure applied by the actuator 18 is maintained until the temperature of the heating plate 16 again falls below 200 ° C. The bonding of the electronic chip 11 to the substrate 8 has the final structure shown in FIG.

図２ｃに示すように、本発明による接合プロセスによって、基板８と電子チップ１１との間で冶金的連続性のある、Ａｇ３Ｓｎから成る金属間結合１９を形成できる。その連続性は、ＮｉＡｇから成る二元合金層２０によってもたらされる。ＮｉＡｇ合金層２０は、層９、１０、及び層１２、１３から形成される。 As shown in FIG. 2 c, the bonding process according to the present invention can form an intermetallic bond 19 made of Ag 3 Sn with metallurgical continuity between the substrate 8 and the electronic chip 11. The continuity is provided by a binary alloy layer 20 made of NiAg. The NiAg alloy layer 20 is formed from the layers 9 and 10 and the layers 12 and 13.

金属間結合１９は、多数の無配向で小さい等方性粒子を含む。これにより、十分な弾性と破壊強度が得られる。これらの粒子は、通常数μｍから数十μｍの範囲の大きさである。   The intermetallic bond 19 includes a large number of non-oriented and small isotropic particles. Thereby, sufficient elasticity and breaking strength are obtained. These particles are usually in the size range of several μm to several tens of μm.

次に、図３ａ、３ｂ、３ｃを基に、ＳｎとＡｇとの相互拡散を利用する本実施形態における、本発明の接合プロセスの一般的原理を詳しく説明する。本発明の接合プロセスにおいては、多孔質の、または間隙のある、さらには粒状の金属（ここでは銀）層を、２つの接合部材の少なくとも１つの面に対して用いる。   Next, based on FIGS. 3a, 3b, and 3c, the general principle of the bonding process of the present invention in this embodiment using the mutual diffusion of Sn and Ag will be described in detail. In the joining process according to the invention, a porous, interstitial, or even granular metal (here silver) layer is used for at least one side of the two joining members.

図３ａに示すように、銀層１４に多孔性により、スズを多く含んだ液体１５が、銀層内の網状に並んだ隙間から成る通り道に浸入し、銀層の中心部まで浸透する。多孔質層は、構造上、マイクロメートル単位の構造体を高密度に含んでおり、そのような構造体が、金属間化合物相が不均質に発生する優先箇所を形成している。   As shown in FIG. 3a, due to the porosity of the silver layer 14, the liquid 15 containing a large amount of tin penetrates into the path formed by the net-like gaps in the silver layer and penetrates to the center of the silver layer. The porous layer includes a structure of a micrometer unit at a high density in terms of structure, and such a structure forms a preferential place where an intermetallic compound phase occurs heterogeneously.

図３ｂに示すように、液体のスズ１５は金属間化合物の核２１を濡らす。銀２２は金属間化合物相を通り、液体のスズの界面にまで拡散する。核の成長は等方的であり、これによって、図３ｃに示すように、多数の無配向で小さい（数μｍから数十μｍ）等方性粒子２３から成る金属間結合が形成される。この金属間結合は、高い弾性限界と高い破壊強度を有する。   As shown in FIG. 3b, the liquid tin 15 wets the core 21 of the intermetallic compound. Silver 22 passes through the intermetallic phase and diffuses to the liquid tin interface. The growth of the nuclei is isotropic, thereby forming an intermetallic bond consisting of a large number of non-oriented and small (several to tens of μm) isotropic particles 23, as shown in FIG. 3c. This intermetallic bond has a high elastic limit and high fracture strength.

Claims (7)

第１金属（Ａｇ）と第２金属（Ｓｎ）との相互拡散を利用して、第１部材（８）と第２部材（１１）とを接合するプロセスであって、前記第２金属（Ｓｎ）が前記第１金属（Ａｇ）の融点よりも十分に低い融点を持ち、前記プロセスが、一連の、
前記第１金属（Ａｇ）から成る少なくとも１つの層（１０、１３、１４）を、前記第１部材（８）の第１接合面と、前記第２部材（１１）の第２接合面のそれぞれに蒸着するステップ（ａ）と、
前記第１金属（Ａｇ）でコーティングされた前記第１接合面と前記第２接合面との間に、前記第２金属（Ｓｎ）から成る層（１５）を挟み込むステップ（ｂ）と、
前記第１部材（８）と前記第２部材（１１）に圧力（１８）を加え、前記第１接合面と前記第２接合面を互いに可能な限り密着させるステップ（ｃ）と、
前記第１部材（８）と前記第２部材（１１）から形成された接合体を所定の時間熱することで、前記第２金属（Ａｇ）の前記層を融解させ、第１・第２金属から成る金属間層（１９）を発生・成長させて作製し、前記第１部材（８）と前記第２部材（１１）を接合するステップ（ｄ）とを備え、
前記第１金属が銀（Ａｇ）であって、前記第２金属がスズ（Ｓｎ）であり、
少なくとも１つの銀層（Ａｇ、１４）が、前記銀層（Ａｇ、１４）に対する前記スズ（Ｓｎ）の浸透を促進させる間隙のある構造を有し、また、２μｍから５μｍの間の銀の粒子を有しており、
間隙のある構造を有する前記銀層（Ａｇ、１４）が、「コールドスプレー」法、粉末状の銀を部分焼結する方法、及び/またはパウダープラズマ蒸着法によって蒸着されることを特徴とするプロセス。 A process of joining the first member (8) and the second member (11) using mutual diffusion of the first metal (Ag) and the second metal (Sn), the second metal (Sn) ) Has a melting point sufficiently lower than the melting point of the first metal (Ag), and the process comprises a series of:
At least one layer (10, 13, 14) made of the first metal (Ag) is formed on each of the first joint surface of the first member (8) and the second joint surface of the second member (11). Evaporating step (a);
Sandwiching the layer (15) made of the second metal (Sn) between the first joint surface coated with the first metal (Ag) and the second joint surface (b);
Applying a pressure (18) to the first member (8) and the second member (11) to bring the first joint surface and the second joint surface into close contact with each other as much as possible (c);
The joined body formed from the first member (8) and the second member (11) is heated for a predetermined time to melt the layer of the second metal (Ag), and the first and second metals. A step (d) of generating and growing an intermetallic layer (19) comprising: joining the first member (8) and the second member (11);
The first metal is silver (Ag), and the second metal is tin (Sn);
At least one silver layer (Ag, 14) has a gap structure that promotes penetration of the tin (Sn) into the silver layer (Ag, 14), and silver particles between 2 μm and 5 μm Have
Process wherein the silver layer (Ag, 14) having a gap structure is deposited by a “cold spray” method, a method of partially sintering powdered silver, and / or a powder plasma deposition method . 請求項１に記載の接合プロセスであって、間隙のある構造を有する前記銀層（Ａｇ、１４）が、少なくとも部分的に多孔質、及び/または粒状の層である接合プロセス。   The joining process according to claim 1, wherein the silver layer (Ag, 14) having a gap structure is at least partly porous and / or granular layer. 請求項１または請求項２に記載の接合プロセスであって、前記スズ層（Ｓｎ、１５）がスズの固体ストリップである接合プロセス。   The joining process according to claim 1 or 2, wherein the tin layer (Sn, 15) is a solid strip of tin. 請求項１乃至請求項３のいずれか１つに記載の接合プロセスであって、ステップ（ｃ）において加えられる前記圧力が、概ね９ｋＰａから５５ｋＰａの間である接合プロセス。   The joining process according to any one of claims 1 to 3, wherein the pressure applied in step (c) is approximately between 9 kPa and 55 kPa. 請求項１乃至請求項４のいずれか１つに記載の接合プロセスであって、前記第１部材（８）と前記第２部材（１１）とから成る前記接合体が、概ね２分から１５分間、概ね２５０℃から３５０℃の間の温度で加熱される接合プロセス。   The joining process according to any one of claims 1 to 4, wherein the joined body composed of the first member (8) and the second member (11) is approximately 2 to 15 minutes, A bonding process heated at a temperature generally between 250 ° C and 350 ° C. 請求項１乃至請求項５のいずれか１つに記載の接合プロセスであって、前記第１部材が、少なくとも１本の銅配線（８’）を有する基板（８）であり、前記第２部材が、前記銅配線（８’）に接合される電子チップ（１１）である接合プロセス。   6. The joining process according to claim 1, wherein the first member is a substrate (8) having at least one copper wiring (8 ′), and the second member. Is an electronic chip (11) bonded to the copper wiring (8 '). 第１接合部材と第２接合部材を備える接合体であって、前記第１部材（８）と前記第２部材（１１）が、請求項１乃至請求項６のいずれか１つに記載の接合プロセスによって接合される接合体。   A joined body comprising a first joining member and a second joining member, wherein the first member (8) and the second member (11) are joined according to any one of claims 1 to 6. Bonded body joined by process
JP2016570808A 2014-06-02 2015-04-08 Process for permanent joining of two members by transient liquid phase interdiffusion Active JP6636465B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR1454951A FR3021670B1 (en) 2014-06-02 2014-06-02 METHOD FOR PERMANENTLY ASSEMBLING TWO ELEMENTS BY TRANSIENT LIQUID PHASE INTERDIFFUSION
FR1454951 2014-06-02
PCT/FR2015/050912 WO2015185812A1 (en) 2014-06-02 2015-04-08 Process for permanently assembling two elements by transient liquid phase interdiffusion

Publications (3)

Publication Number Publication Date
JP2017518186A true JP2017518186A (en) 2017-07-06
JP2017518186A5 JP2017518186A5 (en) 2019-09-05
JP6636465B2 JP6636465B2 (en) 2020-01-29

Family

ID=51417450

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016570808A Active JP6636465B2 (en) 2014-06-02 2015-04-08 Process for permanent joining of two members by transient liquid phase interdiffusion

Country Status (4)

Country Link
JP (1) JP6636465B2 (en)
DE (1) DE112015002600T5 (en)
FR (1) FR3021670B1 (en)
WO (1) WO2015185812A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017024042A (en) * 2015-07-22 2017-02-02 三菱電機株式会社 Soldering method, solder junction structure, and electronic apparatus

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130049204A1 (en) * 2011-08-22 2013-02-28 Infineon Technologies Ag Semiconductor device including diffusion soldered layer on sintered silver layer
JP2013197427A (en) * 2012-03-22 2013-09-30 Hitachi Ltd Semiconductor element, semiconductor device, semiconductor device manufacturing method and connection material
JP2014097529A (en) * 2012-10-18 2014-05-29 Fuji Electric Co Ltd Joining method by foam metal, manufacturing method of semiconductor device, and semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9583453B2 (en) * 2012-05-30 2017-02-28 Ormet Circuits, Inc. Semiconductor packaging containing sintering die-attach material
US20140120356A1 (en) * 2012-06-18 2014-05-01 Ormet Circuits, Inc. Conductive film adhesive

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130049204A1 (en) * 2011-08-22 2013-02-28 Infineon Technologies Ag Semiconductor device including diffusion soldered layer on sintered silver layer
JP2013197427A (en) * 2012-03-22 2013-09-30 Hitachi Ltd Semiconductor element, semiconductor device, semiconductor device manufacturing method and connection material
JP2014097529A (en) * 2012-10-18 2014-05-29 Fuji Electric Co Ltd Joining method by foam metal, manufacturing method of semiconductor device, and semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017024042A (en) * 2015-07-22 2017-02-02 三菱電機株式会社 Soldering method, solder junction structure, and electronic apparatus

Also Published As

Publication number Publication date
JP6636465B2 (en) 2020-01-29
DE112015002600T5 (en) 2017-03-16
WO2015185812A1 (en) 2015-12-10
FR3021670A1 (en) 2015-12-04
FR3021670B1 (en) 2019-07-12

Similar Documents

Publication Publication Date Title
JP2758373B2 (en) Low temperature ternary C4 bonding method
CN102883991B (en) Bonding process for sensitive micro- and nano-systems
TW201119079A (en) A bonding method for LED chip and bonded LED
JP6753869B2 (en) How to make composites
US10180288B2 (en) High-conductivity bonding of metal nanowire arrays
US8814030B2 (en) Improvements of long term bondline reliability of power electronics operating at high temperatures
WO2013021750A1 (en) Wiring substrate and method for manufacturing same and semiconductor device
Feng et al. Cooperative bilayer of lattice-disordered nanoparticles as room-temperature sinterable nanoarchitecture for device integrations
JP2010516478A (en) High temperature solder material
TW201246386A (en) Metallic thermal joint for high power density chips
WO2003097294A1 (en) Solder compositions for attaching a die to a substrate
JP6284164B2 (en) Junction structure and manufacturing method of junction structure
JP2008044009A (en) Method of joining members having different thermal expansion coefficients
CN111435646B (en) Semiconductor device and method for manufacturing the same
US20180200840A1 (en) Low-Temperature Bonding With Spaced Nanorods And Eutectic Alloys
JP5691901B2 (en) Power module manufacturing method
JP6795307B2 (en) Joining material, manufacturing method of joining material, manufacturing method of joining structure
JP6636465B2 (en) Process for permanent joining of two members by transient liquid phase interdiffusion
JP6144440B1 (en) Preform for semiconductor encapsulation
JP2017518186A5 (en)
US20140061921A1 (en) Gold bonding in semiconductor devices using porous gold
JP7406417B2 (en) Electrode structure and bonded structure equipped with the electrode structure
CN103043605B (en) Miniature plating stereochemical structure improves the process of wafer level metal bonding intensity
JP5387388B2 (en) Electrode structure
TWI471069B (en) Metal board used for led

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20180406

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20190117

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20190125

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20190425

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20190625

A524 Written submission of copy of amendment under article 19 pct

Free format text: JAPANESE INTERMEDIATE CODE: A524

Effective date: 20190725

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20191122

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20191218

R150 Certificate of patent or registration of utility model

Ref document number: 6636465

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250