JP2017224690A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the thickness of a semiconductor device.SOLUTION: A semiconductor device of an embodiment comprises: a first semiconductor chip including a first substrate having a first surface and a second surface opposite to the first surface and provided with a first recess, a first conductive layer arranged on the first surface, and a first contact arranged inside the first recess and reaching the first conductive layer; a second semiconductor chip including a second substrate having a third surface facing the second surface and a fourth surface opposite to the third surface and a second contact arranged on the third surface; and a first connection part arranged between the first contact and the second contact and in a region overlapping the first recess when viewed from a direction crossing the second surface and including an alloy.SELECTED DRAWING: Figure 2

Description

  The present embodiment relates to a semiconductor device and a manufacturing method thereof.

  In a semiconductor device, an electrode penetrating the substrate may be provided.

JP 2001-307057 A JP 2009-147218 A

  Reduce the thickness of the semiconductor device.

The semiconductor device of the present embodiment is a first substrate, a first substrate having a second surface provided with a first recess, which is the surface opposite to the first surface, and the first surface. A first semiconductor chip having a first conductive layer disposed thereon, a first contact disposed inside the first recess and reaching the first conductive layer, and facing the second surface A second substrate having a third surface, a second substrate having a fourth surface opposite to the third surface, and a second contact disposed on the third surface. Disposed between the semiconductor chip, the first contact and the second contact, and disposed in a region overlapping the first recess when viewed from the direction intersecting the second surface;
A first connecting portion including an alloy.

1 is a schematic cross-sectional view showing a semiconductor device according to a first embodiment. FIG. 3 is a schematic cross-sectional view showing an enlarged view of a connection portion between semiconductor chips of the semiconductor device according to the first embodiment. 1 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment. 1 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment. 1 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment. 1 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment. 1 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment. 1 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment. 1 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment. 1 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment. 1 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment. 1 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment. 1 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment. 1 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment. The typical sectional view showing the enlarged view of the connection part between the semiconductor chips of the semiconductor device concerning a second embodiment. The typical sectional view showing the enlarged view of the connection part between the semiconductor chips of the semiconductor device concerning a third embodiment.

Hereinafter, embodiments will be described with reference to the drawings. In the following description, substantially the same functions and components are denoted by the same reference numerals.

(First embodiment)
FIG. 1 is a schematic plan view illustrating a semiconductor device 10 according to this embodiment.

As illustrated in FIG. 1, the semiconductor device 10 includes a substrate 20 and semiconductor chips 30a to 30c.

The substrate 20 is, for example, an insulating resin wiring substrate or a ceramic wiring substrate provided with a wiring layer (not shown) on the surface or inside thereof. Specifically, for example, a printed wiring board using a glass-epoxy resin is used. Alternatively, a silicon interposer or a lead frame may be used.

On the substrate 20, semiconductor chips 30a to 30c are arranged in order from the substrate 20 side. In addition, when it is not particularly necessary to distinguish between the semiconductor chips 30a to 30c, they are simply referred to as the semiconductor chip 30.

The semiconductor chips 30a to 30c may be semiconductor chips having the same internal structure, or may be semiconductor chips having different internal structures. In FIG. 1, the sizes of the semiconductor chips 30 are described as being substantially equal, but the present invention is not limited to this.

A connecting portion 40a is disposed between the substrate 20 and the semiconductor chip 30a. The substrate 20 and the semiconductor chip 30a are electrically connected via the connection part 40a. Similarly, the semiconductor chip 30
A connecting portion 40b is disposed between a and the semiconductor chip 30b. The semiconductor chip 30a and the semiconductor chip 30b are electrically connected via the connection part 40b. A connecting portion 40b is disposed between the semiconductor chip 30a and the semiconductor chip 30b. The semiconductor chip 30b and the semiconductor chip 30c are electrically connected via the connection part 40c. In addition, connection part 40a-40
When the distinction of c is not particularly required, it is simply referred to as a connection portion 40.

The bonding wire 50 is provided on the surface of the semiconductor chip 30c opposite to the semiconductor chip 30b side.
Is connected. The bonding wire 50 is connected to the substrate 20. That is, the semiconductor chip 30 c and the substrate 20 are electrically connected via the bonding wire 50.

On the substrate 20, a sealing layer 60 that seals the semiconductor chips 30 a to 30 c, the connection portions 40 a to 40 c, and the bonding wires 50 together is disposed.

FIG. 2 is a cross-sectional view for explaining a connection portion 40 b as an example of the connection portion 40. That is, FIG. 2 is a schematic cross-sectional view showing an enlarged view of the connecting portion 40b and the surrounding semiconductor chips 30a and 30b.

  First, the configuration of the semiconductor chip 30a will be described.

  The semiconductor chip 30 a has a semiconductor substrate 110.

The semiconductor substrate 110 has a first surface 115a and a second surface 115b. First side 11
Reference numeral 5a denotes a surface on the substrate 20 side in FIG. The second surface 115b is a surface opposite to the first surface 115a.

The first conductive layer 120 is disposed on the first surface 115a side. On the first conductive layer 120,
The first contact 130 is disposed in electrical connection with the first conductive layer 120. A second conductive layer 140 is disposed on the first contact 130 in electrical connection with the first contact 130. A second contact 150 is disposed on the second conductive layer 140 in electrical connection with the second conductive layer 140. On the second contact 150, the third conductive layer 160 is disposed on the second contact 15.
It is arranged in electrical connection with 0. A third contact 170 is disposed on the third conductive layer 160 in electrical connection with the third conductive layer 160. A fourth conductive layer 180 is disposed on the third contact 170 in electrical connection with the third contact 170. A fourth contact 190 is disposed on the fourth conductive layer 180. The fourth contact 190 is electrically connected to the substrate 20 (not shown) via the connection portion 40a.

That is, the first conductive layer 120 is electrically connected to the substrate 20 (not shown) through the contact, the conductive layer, and the connection portion 40a.

On the first surface 115a, the first conductive layer 120, the second conductive layer 140, the third conductive layer 16
The first insulating layer 220 is disposed around the zero, fourth conductive layer 180, the first contact 130, the second contact 150, the third contact 170, and the fourth contact 190.

A second insulating layer 230 is disposed on the first insulating layer 220 and around the fourth contact 190.

The first conductive layer 120, the second conductive layer 140, the third conductive layer 160, the fourth conductive layer 180, the first contact 130, the second contact 150, and the third contact 170 are, for example, polysilicon doped with impurities, titanium, It includes one or more layers of titanium nitride, tantalum, tantalum nitride, aluminum, tungsten, copper, metal and silicon compounds, and the like.

The first insulating layer 220 includes an arbitrary insulating film such as a silicon oxide or a silicon nitride portion. The second insulating layer 230 includes polyimide.

The fourth contact 190 includes, for example, nickel or copper. Moreover, gold | metal | money, tin, etc. may be contained.

A recess 300 is formed on the second surface 115b side. The recess 300 has a side surface 305a and a bottom surface 305b. The recess 300 is a recess formed on the second surface 115b side. Alternatively, the recess 300 is a region where the thickness of the semiconductor substrate 110 is thinner than the outside of the recess 300. Furthermore, in other words, the recess 300 is a region formed with a lower surface height than the second surface 115b. Further, in order to maintain the mechanical strength of the semiconductor substrate 110, the thickness of the semiconductor substrate 110 on the bottom surface 305b is at least half of the longest thickness of the semiconductor substrate 110. Here, the thickness means a length in a direction perpendicular to the first surface or the second surface of the semiconductor substrate 110.

A first through hole 310 is formed inside the recess 300. The first through hole 310 is formed through the semiconductor substrate 110 from the recess 300. That is, the first through hole 31
0 is formed to reach the first insulating layer 220 formed on the first surface 115a.

At least the second surface 115b, the side surface 305a, the bottom surface 305b, and the first through hole 31.
A third insulating layer 320 is disposed on the 0 side surface.

On the third insulating layer 320, at least part of the first conductive layer 120, the first through hole 3
The eighth conductive layer 330 is disposed in a part of the area inside the area 10 and immediately above the bottom face 305b.
That is, the eighth conductive layer 330 is electrically connected to the first conductive layer 120.

On the eighth conductive layer 330, at least the inner side and the bottom surface 305 of the first through hole 310.
The ninth conductive layer 350 is disposed in a part of the region immediately above b. The ninth conductive layer 350 may have a hollow (void) inside. Here, immediately above is the second surface 115b.
It means that they overlap with each other, for example, when viewed from the direction perpendicular.

On the ninth conductive layer 350, the connection portion 40b is disposed. The connection part 40b is connected to the fourth contact 190 ′ of the semiconductor chip 30b. The first conductive layer 120 includes an eighth conductive layer 330,
Electrical connection is made to the semiconductor chip 30b through the ninth conductive layer 350 and the connecting portion 40b.

The third insulating layer 320 includes, for example, silicon oxide. For the eighth conductive layer 330, for example, a laminated film of titanium or copper or a laminated film of titanium or nickel is used. The ninth conductive layer 350 includes, for example, copper or nickel. The ninth conductive layer may contain tin or gold.

  The connection part 40a or 40b is, for example, an alloy containing nickel, gold, tin, copper or the like.

Here, the eighth conductive layer 330, the ninth conductive layer 350, and the connection portion 40b are connected to the semiconductor substrate 110.
The first surface 115a is disposed in a region overlapping with the recess 300 as viewed from the first surface 115a side. That is, the connection part 40b is arrange | positioned in the area | region which overlaps with the recessed part 300 seeing from the 1st surface 115a side. Also,
As shown in FIG. 2, the connection portion 40 b is disposed so as to partially overlap the third insulating layer 320 and not the semiconductor substrate 110 as viewed from the direction parallel to the second surface 115 b.

The configuration of the semiconductor chip 30b may be approximately the same as the configuration of the semiconductor chip 30a.
Therefore, detailed description is omitted. In FIG. 2, the components of the semiconductor chip 30b are shown with dashes.

(Manufacturing method of the first embodiment)
Hereinafter, the manufacturing method of the first embodiment will be described with reference to FIGS.

First, the steps up to FIG. 3 will be described. FIG. 3 is a cross-sectional view of the semiconductor wafer 35 before the semiconductor chip 30a is singulated, and is an enlarged view of a region where the connection portion 40b is formed. The semiconductor wafer 35 has a first surface 115a on which an integrated circuit such as a transistor is formed and a second surface 115c on the opposite side.

On the first surface 115a of the semiconductor substrate 110, the first conductive layer 120 and the first contact 130 are formed.
, Second conductive layer 140, second contact 150, third conductive layer 160, third contact 170
Then, the fourth conductive layer 180 is formed. These contacts and conductive layers are formed by sputtering, CVD (
Chemical Vapor Deposition), Lithography, RIE (Reactive Ion Etching), CM
It is formed by combining methods such as P (Chemical Mechanical Polishing). These contacts and conductive layers include, for example, polysilicon doped with impurities, titanium, titanium nitride,
It includes one or more layers of tantalum, tantalum nitride, aluminum, tungsten, copper, metal and silicon compounds, and the like. Also, some contacts and conductive layers may form a plurality of layers simultaneously.

A first insulating layer 220 is formed around the contact and conductive layer. The first insulating layer 220 does not need to be formed at once, and may be formed as a stack of several layers. The first insulating layer 220 is formed using silicon nitride or silicon oxide. The first insulating layer 220 is formed by PCVD (Plasma Chemical Vapor Deposition) or LPCVD (Low Pressure Chemica).
l Vapor Deposition).

  On the first insulating layer 220, for example, a second insulating layer 230 containing polyimide is formed.

Thereafter, a mask pattern (not shown) is formed on the second insulating layer 230 by lithography or the like. The fourth conductive layer 180 is formed using RIE using this mask pattern as a mask material.
To reach a contact hole. Thereafter, the mask pattern is removed by ashing or the like.

In the contact hole, for example, a barrier metal layer including titanium, titanium nitride, tantalum, tantalum nitride, or a laminated film thereof is formed. A fifth conductive layer containing nickel or copper is formed inside the barrier metal layer. The barrier metal layer and the fifth conductive layer become the fourth contact 190 as will be described later.

A sixth conductive layer 200 is formed on the fifth conductive layer. For example, nickel or copper is used for the sixth conductive layer 200. The fifth conductive layer and the sixth conductive layer may use the same type of metal, or the sixth conductive layer may be omitted.

A seventh conductive layer 210 is formed on the sixth conductive layer 200. For example, gold is used for the seventh conductive layer 210.

A mask pattern (not shown) is formed on the seventh conductive layer 210 by lithography or the like. The barrier metal layer, the fifth conductive layer, the sixth conductive layer 200, and the seventh conductive layer 210 are etched using RIE using this mask pattern as a mask material. The barrier metal layer and the fifth conductive layer become the fourth contact 190.

  Thus, the structure shown in FIG. 3 is obtained.

As shown in FIG. 4, the semiconductor substrate 110 is thinned from the second surface 115c side, and the second surface 115c becomes the second surface 115b. Moreover, the recessed part 300 is formed in the 2nd surface 115b side. In FIG. 4, the upper and lower sides of FIG. 3 and the semiconductor substrate 110 and the like are inverted.

In order to reduce the thickness of the semiconductor substrate 110, for example, a support substrate (not shown) is bonded to the first surface 115a side with an adhesive layer. Then, the semiconductor substrate 110 is thinned by polishing the second surface 115c. Note that the support substrate (not shown) may be left in the subsequent steps. That is, the support substrate may be peeled off before the semiconductor wafer 35 is separated into the semiconductor chips 30, and the support substrate may remain bonded in the previous steps.

The concave portion 300 is formed by, for example, the following method. A mask pattern (not shown) is formed on the second surface 115b using lithography or the like. The recess 300 is formed using RIE using this mask pattern as a mask material. Thereafter, the mask pattern is removed by ashing or the like. The recess 300 has a side surface 305a and a bottom surface 305b.

As shown in FIG. 5, a first through hole 310 is formed inside the recess 300. The first through hole 310 is formed so as to penetrate the semiconductor substrate 110 and reach the first insulating layer 220. The first through hole 310 does not necessarily reach the first conductive layer 120 at this point. The first through hole is formed using lithography and RIE like the recess 300.

As shown in FIG. 6, a third insulating layer 320 is formed on the second surface 115b, the side surface 305a, the bottom surface 305b, and the first through hole 310 by using, for example, PCVD. Here, the thickness of the third insulating layer on the second surface 115b is h1, and the thickness of the third insulating layer on the bottom surface of the first through hole 310 is h2. Since the third insulating layer 320 is formed by the PCVD method, the deposition rate of the third insulating layer 320 is different between the second surface 115 b and the bottom surface of the first through hole 310. This is because there is a difference in plasma density between the plasma on the second surface 115 b and the first through hole 310. That is, h1 is formed thicker than h2. More specifically, for example, h1 is 2 μm or less, and h2 is 1 μm or less. The bottom surface 30
Since 5b is close to the second surface 115b side, the third insulating layer 320 is formed to be approximately h1 thick.

As shown in FIG. 7, the entire surface is etched from the second surface 115b side. By this etching process, the third insulating layer 320 on the bottom surface of the first through hole 310 is etched. Further, the first insulating layer 220 on the bottom surface of the first through hole 310 is also etched. The bottom surface of the first through hole 310 reaches the first conductive layer 120.

As described with reference to FIG. 6, the third insulating layer 320 on the second surface 115 b is formed thicker than the bottom surface of the first through hole 310. Since the third insulating layer 320 is formed thick, the third insulating layer 320 on the second surface 115b remains without being removed by the above etching process.

As shown in FIG. 8, the eighth conductive layer 33 is formed on the third insulating layer 320 and the first conductive layer 120.
0 is formed. For example, the eighth conductive layer 330 is formed by sputtering using a stack of titanium and copper or a stack of titanium and nickel.

As shown in FIG. 9, a resist mask 340 is formed using lithography.
The resist mask 340 is formed on the second surface 115 b and at least a part of the recess 300. That is, when viewed from the second surface 115b side, the resist mask 340 has the concave portion 300.
It is formed to partially overlap.

As shown in FIG. 10, the ninth conductive layer 350 is formed using a metal plating method using the resist mask 340 as a mask material. For example, copper and nickel are used for the ninth conductive layer 350. Note that the ninth conductive layer 350 may have a void or the like formed at the center thereof.

Further, a tenth conductive layer 360 and an eleventh conductive layer 370 are formed on the ninth conductive layer 350 using a metal plating method. For example, copper is used for the tenth conductive layer 360. For example, tin is used for the eleventh conductive layer 370.

As shown in FIG. 11, the resist mask 340 is removed using, for example, an ashing method.

As shown in FIG. 12, the entire surface on the second surface 115b side is etched using the eleventh conductive layer 370 as a mask material. By this etching, the eighth conductive layer 330 becomes the second surface 11.
5b is etched in at least a part of the upper calling recess 300.

As shown in FIG. 13, the eleventh conductive layer 370 becomes a bump shape by the reflow process. In addition, a through contact 375 including the eighth conductive layer 330, the ninth conductive layer 350, the tenth conductive layer 360, and the eleventh conductive layer 370 is formed.

Thereafter, the semiconductor wafer 35 is separated into pieces, and when the support substrate is bonded in the subsequent step of FIG. 3, the support substrate is peeled off.

  Thus, the semiconductor chip 30a is formed.

The semiconductor chip 30b is also formed by the same process as the semiconductor chip 30a, for example. In addition,
As described above, the semiconductor chips 30a to 30c may have different circuit elements formed therein. Even in the case of different structures, it is preferable that the fourth contact 190, the sixth conductive layer 200, the seventh conductive layer 210, the through contact 375, and the like have the same structure and material.

As shown in FIG. 14, the semiconductor chip 30 a and the semiconductor chip 30 b are arranged on the substrate 20 (not shown) so as to overlap each other. An adhesive material such as DAF may be used.

Thereafter, by reflowing, for example, the tenth conductive layer 360 and the eleventh conductive layer 370 of the semiconductor chip 30a, and the sixth conductive layer 200 ′ and the seventh conductive layer 210 of the semiconductor chip 30b.
As shown in FIG. 2, 'forms a connecting portion 40b (alloy of the above-mentioned conductive layer).

(Effect of this embodiment)
According to this embodiment, the semiconductor substrate 110 has the recess 300 in the second surface 115b. As described above, the recess 300 is a recess formed on the second surface 115b side. Alternatively, the recess 300 is a region where the thickness of the semiconductor substrate 110 is thinner than the outside of the recess 300. Furthermore, in other words, the recess 300 is a region formed with a lower surface height than the second surface 115b.

According to the present embodiment, the connection portion 40b is disposed so as to overlap the recess 300. Thereby, the semiconductor device 10 can be thinned. Hereinafter, the reason why the semiconductor device 10 can be thinned will be described.

First, the distance between the semiconductor chip 30a and the semiconductor chip 30b is determined by the connection portions 40b, the connection portions 40b, and the conductive layers disposed between the semiconductor chips 30 (the eighth conductive layer 330 and the ninth conductive layer 350). Etc.) depending on the height. If the height of each of the conductive layers and the connecting portion 40b is reduced, there is a concern that the electrical characteristics of the semiconductor device 10 are deteriorated. In particular, when the height of the connecting portion 40b is reduced, the formation of the connecting portion 40b by alloying at the time of reflow described with reference to FIGS.

Further, simply reducing the thickness of the entire surface of the semiconductor substrate 110 reduces the mechanical strength of the semiconductor wafer 35 and the semiconductor chip 30. That is, it becomes difficult to handle the semiconductor wafer 35 and the semiconductor chip 30 during manufacturing. In particular, it is difficult to perform a series of processes as in the formation of the through contact 375 that penetrates the semiconductor wafer 35 described in FIG.

In the present embodiment, the semiconductor substrate 110 in a region where each conductive layer and the connection portion 40b are arranged is locally low. Since the semiconductor substrate 110 is locally formed low, the distance between the semiconductor chip 30a and the semiconductor chip 30b can be reduced without reducing the thickness of each conductive layer and the connection portion 40b.

That is, according to the configuration of the present embodiment, it is possible to suppress the connection failure of the connection portion 40 and to shorten the distance between the semiconductor chip 30a and the semiconductor chip 30b while facilitating the formation of the through contact 375. . That is, the semiconductor device 10 can be thinned.

In the above description, the semiconductor chips 30a and 30b and the connection portion 40b have been described as examples. However, the present embodiment can be applied to the semiconductor chips 30b and 30c or other connection portions 40 as well.

(Second embodiment)
FIG. 15 is a cross-sectional view of the connecting portion 40b according to the second embodiment. In the present embodiment, the arrangement of the connection portion 40b and the fourth contact 190 ′ is different from that in the first embodiment. Since other points are common to the first embodiment, description thereof is omitted.

The connection portion 40b is disposed so as to overlap the semiconductor substrate 110 and the third insulating layer 320 when viewed from the direction parallel to the second surface 115b.

The fourth contact 190 ′ is disposed so as to overlap with the recess 300 when viewed from the direction intersecting the second surface 115b, for example, the direction orthogonal to the second surface 115b. Furthermore, the fourth contact 190 ′ is disposed so as to overlap with a region inside the third insulating layer 320 formed on the side surface 305 a of the recess 300 when viewed from above.

According to the configuration of the present embodiment, the distance between the semiconductor chip 30a and the semiconductor chip 30b can be shortened by arranging the connection portion 40b inside the recess 300. That is, the semiconductor device 10 can be thinned.

Furthermore, since the fourth contact 190 ′ is smaller than the recess 300 or the like, the fourth contact 19
The distance between 0 ′ and the semiconductor chip 30a can be increased. That is, since the contact between the fourth contact 190 ′ and the semiconductor chip 30a is difficult, the distance between the semiconductor chip 30a and the semiconductor chip 30b can be further shortened.

(Third embodiment)
FIG. 16 is a cross-sectional view of the connecting portion 40b according to the third embodiment. In this embodiment, arrangement | positioning of the connection part 40b differs from 1st embodiment. Since other points are common to the first embodiment, description thereof is omitted.

The connection portion 40b is disposed without overlapping the semiconductor substrate 110 and the third insulating layer 320 when viewed from the direction parallel to the second surface 115b. In the present embodiment, the eighth conductive layer 330, the ninth conductive layer 3
This corresponds to the case where 50 is thick.

Even in such a case, it is possible to shorten the distance between the semiconductor chip 30a and the semiconductor chip 30b by disposing the eighth conductive layer 330 and the ninth conductive layer 350 in the recess 300. That is, the semiconductor device 10 can be thinned.

Although the embodiment of the present invention has been described, this embodiment is presented as an example and is not intended to limit the scope of the invention. The novel embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. This embodiment and its modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 20 Substrate 30 Semiconductor chip 35 Semiconductor wafer 40 Connection part 50 Bonding wire 60 Sealing layer 110 Semiconductor substrate 120 First conductive layer 130 First contact 140 Second conductive layer 150 Second contact 160 Third conductive layer 170 Third Contact 180 Fourth conductive layer 190 Fourth contact 200 Sixth conductive layer 210 Seventh conductive layer 220 First insulating layer 230 Second insulating layer 300 Recess 310 First through hole 320 Third insulating layer 330 Eighth conductive layer 340 Resist mask 350 ninth conductive layer 360 tenth conductive layer 370 eleventh conductive layer 375 through contact

Claims (11)

A first substrate, a first substrate having a second surface opposite to the first surface and provided with a first recess, and a first conductive disposed on the first surface. A first semiconductor chip having a layer and a first contact disposed inside the first recess and reaching the first conductive layer;
A second substrate having a third surface facing the second surface and a fourth surface opposite to the third surface; and a second contact disposed on the third surface And a second semiconductor chip having
A first connecting portion disposed between the first contact and the second contact, disposed in a region overlapping the first recess when viewed from a direction intersecting the second surface, and including an alloy;
A semiconductor device. The second semiconductor chip has a second conductive layer on the third surface, a second recess is provided on the fourth surface, and reaches the second conductive layer from above the second recess. The semiconductor device according to claim 1, further comprising the second contact arranged in a row. The semiconductor device according to claim 2, wherein the second contact and the second conductive layer are electrically connected. The semiconductor device according to claim 1, wherein the thickness of the first substrate of the first recess is thicker than half of the longest thickness of the first substrate. The semiconductor device according to claim 1, wherein the first connection portion is disposed so as to overlap the first recess when viewed from a direction parallel to the second surface. The semiconductor device according to claim 1, wherein the first connection portion is disposed so as to overlap the first substrate when viewed from a direction parallel to the second surface. The semiconductor device according to claim 1, wherein the first connection portion is disposed without overlapping the first substrate when viewed from a direction parallel to the second surface.   The semiconductor device according to claim 1, wherein the alloy includes tin, gold, nickel, and copper. Forming a first conductive layer on the first surface of the first substrate having a first surface and a second surface opposite the first surface;
Forming a recess having a first side surface and a first bottom surface on the second surface of the first substrate;
Forming a contact hole reaching the first surface inside the recess;
Forming a first insulating layer on the second side surface and the second bottom surface of the contact hole;
Etching at least part of the first insulating layer formed on the second bottom surface of the contact hole, and allowing the second bottom surface of the contact hole to reach the first conductive layer;
Forming a second conductive layer on the first insulating layer and the first conductive layer;
Forming a mask pattern on at least a part of the recess and a part of the region outside the recess on the second conductive layer;
Using the mask pattern as a mask, forming a third conductive layer on the second conductive layer to above the first bottom surface of the recess;
Forming a fourth conductive layer on the third conductive layer using the mask pattern as a mask;
Using the fourth conductive layer as a mask, removing the second conductive layer;
A method for manufacturing a semiconductor device comprising: The method for manufacturing a semiconductor device according to claim 9, wherein the third conductive layer and the fourth conductive layer are disposed so as to overlap the first bottom surface when viewed from a direction intersecting the second surface. The method for manufacturing a semiconductor device according to claim 9, wherein the third conductive layer and the fourth conductive layer are arranged only in a region overlapping with the concave portion when viewed from a direction intersecting the second surface.

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