JP2017220721A - Phase error correction device and wireless transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correct a phase error of the output waveform of multiple DA converters.SOLUTION: A phase error correction device for correcting the phase error between respective output signals from multiple DA converters includes a comparator circuit inputting a reference signal having a changing data value to each DA converter, comparing an analog signal from each DA converter with a predetermined threshold value and outputting a binary comparison result signal, and control means for adjusting the phase of the reference signal so that respective binary appearances of comparison result signals from the comparator circuit are substantially identical, or adjusting a phase of a clock for controlling the operation of the comparator circuit. A divider for dividing the clock by a predetermined division ratio may be included furthermore. The comparator circuit may compare the reference signal with the threshold, by using a threshold having hysteresis characteristics at the time of rising and falling of the reference signal.SELECTED DRAWING: Figure 1A

Description

  The present disclosure relates to, for example, a phase error correction apparatus that corrects phase errors of output signals from a plurality of DA converters of a quadrature modulator in a transmission signal, and a transmission apparatus that uses a plurality of DA converters having corrected phase errors. And about.

  For example, in a radio communication radar system technology, a transmission signal output from a digital-analog converter (hereinafter referred to as a DA converter) that converts a digital signal into an analog signal is applied to an object through a transmission antenna. In general, in-phase signals orthogonal to each other (referred to as in-phase components on the same phase axis as the carrier wave, hereinafter referred to as I signals) and quadrature signals (orthogonal on the phase axis orthogonal to the carrier wave). The signal is modulated by, for example, QAM modulation using an “IQ quadrature signal” including a phase component (Quadrature Phase signal, hereinafter referred to as a Q signal). Here, if the phase of the IQ quadrature signal is shifted (hereinafter referred to as a quadrature phase error), it causes a characteristic deterioration in the radio receiving apparatus. This phase shift is caused by various factors such as a wiring delay on the substrate and a delay due to variations in analog parts.

  Various methods are conceivable for correcting the phase of the final output waveform of the DA converter. For example, if digital correction is to be performed, an analog-digital converter (hereinafter referred to as an AD converter) is directly connected to the final stage to convert it into digital data, and then digital correction may be considered. However, when the AD converter is mounted, there are great demerits such as power consumption and circuit scale increase. Even if the digital data at the input stage of the DA converter is corrected, a delay due to variations or the like occurs in the DA converter itself, so that it cannot be corrected sufficiently. When such a phase error exists, a configuration described in, for example, Patent Document 1 is known that compensates for imperfect imbalance of an IQ quadrature signal in a quadrature modulator.

Japanese Patent No. 4172805 JP 2010-187334 A

  As in Patent Document 1, only by correcting the phase by the orthogonal error estimation algorithm using the previous stage value of the DA converter, variations and delays of the DA converter itself are not taken into consideration. Therefore, not all phases of the IQ orthogonal signal are necessarily optimal values. When the phases of the I signal and the Q signal are not appropriate values, the quadrature error, the amplitude error, and the like are not sufficiently corrected, so that the influence of the deterioration of the transmission signal on the reception side cannot be sufficiently suppressed.

  The present disclosure solves the above-described problems and provides a phase error correction device and a wireless transmission device that improve the correction accuracy of each output phase error of a plurality of DA converters as compared with the prior art.

A phase error correction apparatus according to an aspect of the present disclosure is provided.
A phase error correction device for correcting a phase error between output signals from a plurality of DA converters,
A comparison circuit that inputs a reference signal whose data value changes to each DA converter, compares an analog signal from each DA converter with a predetermined threshold value, and outputs a binary comparison result signal;
Control that adjusts the phase of the reference signal so that each occurrence of the binary value of the comparison result signal from the comparison circuit is substantially the same, or adjusts the phase of the clock that controls the operation of the comparison circuit Means.

  According to the phase error correction device according to the present disclosure, the output phase error can be corrected with higher accuracy than in the related art, and thus the influence of the phase error on the transmission signal can be sufficiently suppressed.

FIG. 3 is a block diagram illustrating a configuration example of a quadrature error correction apparatus 100 according to the first embodiment of the present disclosure. It is a flowchart which shows the correction process of the quadrature phase error performed by the correction apparatus 100 of the quadrature phase error of FIG. 1A. 1B is a block diagram illustrating a configuration example of a wireless transmission device 10 configured using DA converters 102 and 104 and variable delay lines 103 and 105 corrected by the quadrature phase error correction device 100 of FIG. 1A. FIG. It is a block diagram which shows the structural example of the correction | amendment apparatus 100A of the quadrature phase error concerning Embodiment 2 of this indication. FIG. 1B is a signal voltage waveform diagram showing a procedure of a quadrature phase error correction process executed by the quadrature phase error correction apparatus of FIG. 1A. It is a wave form diagram which shows the example of the reference signal pattern used in the correction apparatus 100 of the quadrature phase error of FIG. 1A. FIG. 1B is a signal voltage waveform diagram illustrating an example of a determination operation related to a threshold in the quadrature phase error correction apparatus of FIG. 1A. FIG. 1B is a signal voltage waveform diagram illustrating an example of a determination operation related to a threshold in the quadrature phase error correction apparatus of FIG. 1A. FIG. 1B is a signal voltage waveform diagram showing a case where there is a hysteresis characteristic in a determination operation relating to a threshold in the quadrature phase error correction apparatus of FIG. 1A. 1B is a waveform diagram showing a case where there is a phase error between the I signal and the Q signal from the DA converters 102 and 104 in the quadrature phase error correction apparatus 100 of FIG. 1A. 1B is a waveform diagram showing a case where there is no phase error between the I signal and the Q signal from the DA converters 102 and 104 in the quadrature phase error correction apparatus 100 of FIG. 1A.

  Embodiments according to the present disclosure will be described below with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

(Embodiment 1)
FIG. 1A is a block diagram illustrating a configuration example of the quadrature phase error correction apparatus 100 according to the first embodiment of the present disclosure. FIG. 1B is a flowchart showing a quadrature error correction process executed by the quadrature error correction apparatus 100 shown in FIG. 1A. Further, FIG. 1C is a block diagram illustrating a configuration example of the wireless transmission device 10 configured using the DA converters 102 and 104 and the variable delay lines 103 and 105 corrected by the quadrature phase error correction device 100 of FIG. 1A. is there.

  1A, a quadrature phase error correction apparatus 100 includes a reference signal generator 101, DA converters 102 and 103, variable delay lines 103 and 105, a comparison circuit 106, a frequency divider 107, and determination and control. Device 108.

  The comparison circuit 106 includes a threshold value register 106R, a switch 106S, and a comparator 106C. The comparison circuit 106 operates as a phase error correction circuit for the output signals of the DA converters 102 and 104. Although not particularly illustrated, the clock CLK in FIG. 1A is generated by a reference signal generation circuit such as a PLL circuit, for example, and is supplied to the comparison circuit 106 via the frequency divider 107 and the variable delay lines 103 and 105. Are supplied to the D / A converters 102 and 104, respectively, to drive the operation of these circuits. Note that the delay amounts of the variable delay lines 103 and 105 are adjusted by the determination and controller 108 in the fine mode. The frequency divider 107 divides the input clock CLK by a predetermined frequency division ratio (1 / N), and outputs the frequency-divided clock to the comparison circuit 106. Here, N is generally a natural number, for example, 20.

  The switch 106S selectively switches which one of the two DA converters 102 and 104 receives the signal, and is switched based on the determination and the control signal from the controller 108. The threshold value register 106R is provided to store the threshold value of the comparator 106C. For example, the threshold value register 106R stores a threshold value set value transferred from an external circuit through SPI (Serial Peripheral Interface) communication. Can be switched by a threshold switching signal from the determination and controller 108. The comparator 106C receives the signal voltage Vs input from the DA converter 102 or 104 via the switch 106S and compares it with the threshold value Vth set by the threshold value register 106R. When Vs ≧ Vth, The comparison result signal “1” is output to the determination and controller 108, while the comparison result signal “0” is output to the determination and controller 108 when Vs <Vth.

  The reference signal from the reference signal generator 101 is input to the DA converters 102 and 104, and the output signal voltage (analog signal) from the DA converter 102 is not connected to the comparator 106C via the contact a side of the switch 106S of the comparison circuit 106. The output signal voltage (analog signal) from the DA converter 104 is input to the non-inverting input terminal of the comparator 106C via the contact b side of the switch 106S of the comparison circuit 106. The binary comparison result signal of the comparator 106C is input to the determination and controller 108, and the determination and controller 108 executes the quadrature phase error correction process of FIG. 1B.

  In the quadrature phase error correction apparatus 100 configured as described above, one comparator circuit 106 is characterized by a single comparator circuit 106 for analog output signal voltages from the DA converters 102 and 104. By detecting this, it is important to eliminate variations and delays of the comparison circuit 106 itself. For example, when threshold values of output signal voltages from a plurality of DA converters 102 and 104 are determined by a plurality of comparison circuits, it is difficult to accurately detect timing because the comparison circuits have inherent variations and delays. . Therefore, the embodiment according to the present disclosure has a feature that the influence of the variation of the comparison circuit 106 itself can be removed by processing the plurality of analog input signals in a time division manner.

  Hereinafter, with reference to FIG. 1A and FIG. 1B, the correction process of the quadrature phase error will be described below.

  First, in step S1, the switch 106S is switched to the contact a side to correct the phase of the DA converter 102. Next, in step S <b> 2, a reference signal having a predetermined reference signal pattern is input from the reference signal generator 101 to the DA converter 102. Further, in step S3, the binary comparison result signal of the comparison circuit 106 changes the reference signal pattern as shown in FIG. 4, for example, and the appearance probabilities of “0” and “1” are generated for each reference signal pattern. A transition point from “0” to “1” or a transition point from “1” to “0” is detected so as to be substantially 50%. Here, the reference signal pattern of FIG. 4 has a time period in which the appearance probability of “0” and “1” is substantially 50% when the intermediate value of the data width is a threshold value. It is a signal pattern. In step S4, the reference signal pattern immediately before the detected reference signal pattern at the transition point is fixedly input. The rough mode adjustment is as described above. In the fine mode adjustment described below, “0” and “1” appear for the reference signal pattern fixed by changing the delay amount of the variable delay line 103 in step S5. The delay amount is adjusted so that the probability is substantially 50%.

  Next, in step S6, the switch 106S is switched to the contact b side to correct the phase of the DA converter 104. In step S7, a reference signal having a predetermined reference signal pattern is input from the reference signal generator 101 to the DA converter 104. In step S8, the comparison result signal of the comparison circuit 106 indicates the reference signal pattern shown in FIG. The transition point from “0” to “1” or “1” to “1” so that the appearance probability of “0” and “1” is substantially 50% for each reference signal pattern. The transition point to “0” is detected. Next, in step S9, the reference signal pattern immediately before the detected reference signal pattern at the transition point is fixed and input, and in step S10, the reference signal pattern fixed by changing the delay amount of the variable delay line 105 is fixed. The delay amount is adjusted so that the appearance probabilities of “0” and “1” for the pattern are substantially 50%, and the correction process is terminated.

  By using the DA converters 102 and 104 having the quadrature phase error corrected by the correction process and the variable delay lines 103 and 105 in the wireless transmission device 10 as shown in FIG. 1C, the IQ quadrature signal with the quadrature phase error corrected is obtained. Can be used to generate a radio transmission signal.

  1C, a wireless transmission device 10 includes a transmission signal processing circuit 1, DA converters 102 and 104, variable delay lines 103 and 105 having quadrature phase errors corrected by correction processing, a wireless transmission circuit 2, an antenna, and the like. 3. In FIG. 1C, a transmission signal processing circuit 1 performs predetermined transmission signal processing such as serial / parallel conversion on input transmission data to generate an I signal and a Q signal, and outputs DA signals 102 and 104, respectively. Via the wireless transmission circuit 2. The radio transmission circuit 2 performs, for example, QAM modulation based on the input analog I signal and Q signal, generates a predetermined radio transmission signal, and transmits it through the antenna 3.

  In the correction procedure in the quadrature phase error correction apparatus 100 of FIG. 1A configured as described above, the same reference signal is input to each DA converter 102 and 104 in order to perform phase correction of the I signal. The output signal from the DA converter 102 is compared with a comparison result signal of one comparison circuit 106 to determine whether the appearance probability of “0” or “1” is 50%. When the input reference signal is larger than the threshold value, all the comparison result signals of the comparison circuit 106 are “1”. Similarly, when the input reference signal is smaller than the threshold value, all the comparison result signals of the comparison circuit 106 are “0”. When all the comparison result signals are the same, the reference signal shifted in phase is input to each DA converter 102 and 104 again, and the reference signal pattern is changed and the determination is repeatedly performed by the comparison circuit 106. It is time to cross the values. That is, all the comparison result signals have a transition point from “0” to “1” or a transition point from “1” to “0”. Since there is always a location that coincides with the threshold value near the transition point, it is fixed to the reference signal pattern immediately before the pattern where the transition point is found, and this time, the variable delay lines 103 and 105 are used in the fine adjustment mode. The phase of the variable delay lines 103 and 105 is adjusted until the appearance probability of the “0” and “1” patterns of the comparison result signal of the comparison circuit 106 is 50%. In this way, the phases of the I signal and the Q signal are corrected and the output signals are aligned.

  FIG. 3 is a signal voltage waveform diagram showing the procedure of the quadrature phase error correction process executed by the quadrature phase error correction device 100 of FIG. 1A. 3A shows a rough mode reference signal pattern, and FIG. 3B shows a fine mode reference signal pattern.

  In FIG. 3A, when the reference signal pattern S1 is input, all the comparison result signals are “1” because the sampling points SP1 to SP3 are all above the threshold value. Next, when the reference signal pattern S2 is input, the comparison result signals are all “1” because they are similarly above the threshold value. Furthermore, when the reference signal pattern S3 is input, all the comparison result signals are “0” at the sampling points SP1 to SP3 because they are all below the threshold value. Therefore, the reference signal pattern S2 here corresponds to the previous pattern. With this reference signal pattern S2 as a starting point, this time the mode is shifted to the fine mode, and the delay amounts of the variable delay lines 103 and 105 are changed so as to sweep the reference signal pattern in FIG. 3B from S11 to S14. In FIG. 1A, the delay amount of the clock CLK is changed, but is relatively the same as that of changing the delay amount of the reference signal pattern. That is, as a modification of FIG. 1A, the variable delay lines 103 and 105 may be inserted before the input terminals of the DA converters 102 and 104. In FIG. 3B, the amount of change in the reference signal pattern is small compared to the rough mode in FIG. 3A, and the quadrature phase error can be corrected with higher accuracy.

  FIG. 4 is a waveform diagram showing an example of a reference signal pattern used in the quadrature phase error correction apparatus 100 of FIG. 1A. The reference signal pattern of FIG. 4 shows an example of a waveform pattern specialized for the rising waveform. This is because the reference signal pattern is digital data input to the DA converters 102 and 104, so that various waveforms can be generated. The reference signal pattern P1 in FIG. 4 is the waveform used in the description up to FIG. 3, and the reference signal patterns P2 and P3 are also patterns specialized for rising waveforms and can be used as input patterns in the same way.

  FIG. 5A is a signal voltage waveform diagram illustrating an example of a determination operation regarding a threshold in the quadrature phase error correction apparatus 100 of FIG. 1A. FIG. 5B is a signal voltage waveform diagram showing an example of a determination operation related to a threshold in the quadrature phase error correction apparatus 100 of FIG. 1A. 5A and 5B show supplementary explanation that the probability of appearance is about 50%. As is clear from FIG. 5A, at the sampling point SP, when the reference signal matches the threshold value, the comparison result signal always transitions from “0” to “1”. However, as shown in FIG. 5B, the waveform is distorted due to the influence of noise or the like, and depending on the sampling point SP, it cannot be determined every time whether the comparison result signal is slightly shifted and becomes “0” or “1”. Since the absolute value cannot be exactly 50%, it is expressed as “about” or substantially about 50%.

  FIG. 6 is a signal voltage waveform diagram showing a case where there is a hysteresis characteristic in the determination operation regarding the threshold in the quadrature phase error correction apparatus 100 of FIG. 1A. The comparison result signal in FIG. 6 has a wide range of uncertainty whether it is “0” or “1”, so by providing hysteresis characteristics at the rise and fall of the input signal, compared with the prior art The threshold value can be determined with high accuracy. In the case of FIG. 6, the three threshold values VthH, Vth, and VthL are set so as to have hysteresis characteristics for the comparison circuit 106, and are set to Vth ± α (α is a decimal number).

  FIG. 7A is a waveform diagram showing a case where there is a phase error between the I signal and the Q signal from the DA converters 102 and 104 in the quadrature phase error correction apparatus 100 of FIG. 1A. FIG. 7B is a waveform diagram showing a case where there is no phase error between the I and Q signals from the DA converters 102 and 104 in the quadrature phase error correction apparatus 100 of FIG. 1A. As is clear from FIG. 7A, when there is a quadrature phase error, a phase error occurs between the I signal and the Q signal. In contrast, in the case of FIG. 7B, the phase error is corrected.

(Embodiment 2)
FIG. 2 is a block diagram illustrating a configuration example of a quadrature phase error correction apparatus 100A according to the second embodiment of the present disclosure. The quadrature phase error correction apparatus 100A according to the second embodiment of FIG. 2 differs from the quadrature phase error correction apparatus 100 according to the first embodiment of FIG. 1A in the following points.
(1) The variable delay lines 103 and 105 for delaying the clock CLK are not provided.
(2) Instead of the reference signal generator 101, a reference signal generator 101A that can be swept so as to move the reference signal in the time direction by a control signal from the determination and controller 108 is provided.

  With the configuration as described above, as described in the first embodiment, the same operation as the quadrature phase error correction apparatus 100 according to the first embodiment can be performed.

(Modification)
Each functional block in the present embodiment can be typically realized by hardware. For example, each functional block can be formed on a semiconductor substrate as part of an IC (integrated circuit). Here, the IC includes an LSI (Large-Scale Integrated Circuit), an ASIC (Application-Specific Integrated Circuit), a gate array, a FPGA (Field Programmable Gate Array), and the like. Alternatively, some or all of each functional block can be implemented in software. For example, such a functional block can be realized by a program executed on a processor. In other words, each functional block described in the present specification may be realized by hardware, may be realized by software, or may be realized by any combination of hardware and software.

  Many features and advantages of the present disclosure will be apparent from the written description, and thus, it is intended by the appended claims to cover all such features and advantages of the present disclosure. Further, since many changes and modifications can be readily made by those skilled in the art, the present disclosure should not be limited to the exact configuration and operation as illustrated and described. Accordingly, all suitable modifications and equivalents are intended to be within the scope of this disclosure.

  In the configuration example of FIG. 1C, the wireless transmission device 10 has been described, but the present disclosure is not limited to this, and may be applied to a transmission device such as a wire.

  In the above embodiments, the quadrature phase error correction device has been described. However, the present disclosure is not limited to this, and the present disclosure can also be applied to a phase error correction device that corrects phase errors of output signals of a plurality of DA converters. .

(Summary of embodiment)
A phase error correction apparatus according to a first aspect is a phase error correction apparatus that corrects a phase error between output signals from a plurality of DA converters.
A comparison circuit that inputs a reference signal whose data value changes to each DA converter, compares an analog signal from each DA converter with a predetermined threshold value, and outputs a binary comparison result signal;
The phase of the reference signal is adjusted so that the binary appearances of the comparison result signal from the comparison circuit are substantially the same as each other, or the phase of the clock that controls the operation of the comparison circuit is adjusted. Control means.

  The phase error correction apparatus according to the second aspect further includes a frequency divider that divides the clock at a predetermined frequency division ratio in the phase error correction apparatus according to the first aspect.

  A phase error correction device according to a third aspect is the phase error correction device according to the first or second aspect, wherein the comparison circuit has a threshold value having a hysteresis characteristic at the rise and fall of the reference signal. Used to compare the reference signal with the threshold value.

  A phase error correction apparatus according to a fourth aspect is the phase error correction apparatus according to any one of the first to third aspects, wherein the control means changes the reference signal when the reference signal is changed. Detecting a transition point of the comparison result signal that changes from the first binary value to the second value, or a transition point of the comparison result signal that changes from the second binary value to the first value Then, the phase of the reference signal is adjusted, or the phase of the clock is adjusted.

  The phase error correction apparatus according to a fifth aspect is the phase error correction apparatus according to the fourth aspect, wherein the control means fixes the reference signal immediately before the detected transition point to fix the reference signal. The phase is adjusted or the phase of the clock is adjusted.

  A phase error correction apparatus according to a sixth aspect includes a plurality of DA converters having phase errors corrected by the phase error correction apparatus according to any one of the first to fifth aspects.

  According to the present disclosure, it is possible to improve the accuracy of correcting the phase error of the output signals of a plurality of DA converters, which is useful for a phase error correction device and the like.

DESCRIPTION OF SYMBOLS 1 Transmission signal processing circuit 2 Wireless transmission circuit 3 Antenna 10 Wireless transmission device,
100 Quadrature Phase Error Correction Device 101 Reference Signal Generator 102, 104 DA Converter (DAC)
103, 105 Variable delay line 106 Comparison circuit 106R Threshold register 106S Switch 106C Comparator 107 Divider 108 Judgment and controller

Claims (6)

A phase error correction device for correcting a phase error between output signals from a plurality of DA converters,
A comparison circuit that inputs a reference signal whose data value changes to each DA converter, compares an analog signal from each DA converter with a predetermined threshold value, and outputs a binary comparison result signal;
The phase of the reference signal is adjusted so that the binary appearances of the comparison result signal from the comparison circuit are substantially the same as each other, or the phase of the clock that controls the operation of the comparison circuit is adjusted. A phase error correction apparatus comprising a control means.   The phase error correction device according to claim 1, further comprising a frequency divider that divides the clock by a predetermined frequency division ratio.   3. The phase error correction apparatus according to claim 1, wherein the comparison circuit compares the reference signal with the threshold value using a threshold value having hysteresis characteristics at the time of rising and falling of the reference signal.   When the reference signal is changed, the control unit changes the binary value of the comparison result signal from the first value to the second value or the second value of the binary value of the comparison result signal. 4. The phase of the reference signal is adjusted by detecting a transition point that changes from the value of the first value to the first value, or the phase of the clock is adjusted. 5. Phase error correction device.   5. The phase error correction apparatus according to claim 4, wherein the control unit adjusts a phase of the reference signal by fixing a reference signal immediately before the detected transition point, or adjusts a phase of the clock.   A transmission apparatus comprising a plurality of DA converters having a phase error corrected by the phase error correction apparatus according to claim 1.

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