JP2017207903A - Processor, method and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a processor, a method and a program capable of easily analyzing a failure on a main processing system when the main processing system fails.SOLUTION: Disclosed processor 10 includes: a main processing part 11 that performs major processing; a failure detection part 13 which is disposed outside the main processing part 11, detects an occurrence of failure on the main processing part 11, and acquires a piece of information relevant to the state of the main processing part 11 which is notified irrespective of the occurrence of failure; and a monitoring control part 12 that selects a piece of state information corresponding to a point when the failure has occurred from the state information acquired by the failure detection part 13 and stores the information in an accessible state from the outside.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a processing apparatus, method, and program, and more particularly, to a processing apparatus, method, and program that include a monitoring control unit that outputs information for analyzing a failure.

  In a processing device such as a server, it is common to monitor the operation of a main processing system having a CPU (Central Processing Unit) by a monitoring control system having another CPU for the purpose of improving reliability and improving availability. is there. That is, when a failure occurs in the main processing system of the processing apparatus, the monitoring control system of the processing apparatus handles it. For example, when a failure such as a deadlock occurs in the main processing system of the processing apparatus, the deadlock is detected and dealt with by the monitoring control system of the processing apparatus. However, if a deadlock occurs in the main processing system, the supervisory control system can recognize that the deadlock has occurred, but it does not know the detailed state of the main processing system, and this may hinder the analysis of the main processing system failure. There was a problem of coming.

  Various techniques relating to failure detection of processing devices have been proposed. One of them is disclosed in Patent Document 1. Patent Document 1 discloses that when a failure occurs in an information processing apparatus having a watchdog timer therein, this watchdog timer is used to recognize that a failure has occurred. That is, it is disclosed that a failure occurring in an information processing apparatus is detected using a timeout signal of an internal watchdog timer. However, Patent Document 1 does not disclose a case where a failure occurs in the watchdog timer inside the processing apparatus.

  Further, in Patent Document 1, when a failure occurs in an information processing apparatus, the BMC (Baseboard Management Controller) firmware of the information processing apparatus detects a BIOS (Basic Input Output System) stall, and an SMI (System Management Interrupt) ) To collect CPU log information collected by the BIOS. However, Patent Document 1 does not disclose a case where a failure occurs in the SMI of the processing apparatus.

  Patent Document 2 discloses a monitoring and control device having a central processing unit and a memory for storing a processing program of the central processing unit, and the operation of the central processing unit when a predetermined checkpoint is processed in the program There is disclosed a monitoring control device including a port for outputting information to an external processing device, and storage means for storing operation information of the central processing unit outputted to the port. However, Patent Document 2 does not disclose that a detailed state of the main processing system is transmitted to the monitoring control system when a failure occurs in the processing apparatus.

Japanese Patent Laid-Open No. 2015-130023 JP 2000-293407 A

  As described above, when a deadlock occurs in the main processing system of the processing device, the supervisory control system can recognize that the deadlock has occurred, but the detailed state of the main processing system is not known, and the main processing system There was a problem that the trouble analysis was hindered.

  The present invention has been made to solve such problems, and when a failure occurs in the main processing system, a processing apparatus, a method, and a method capable of easily analyzing the failure of the main processing system, and The purpose is to provide a program.

  A processing apparatus according to the present invention is provided outside a main processing unit that performs main processing and the main processing unit, detects the occurrence of a failure in the main processing unit, and is notified regardless of the occurrence of the failure. A failure detection unit that acquires state information of the main processing unit, and monitoring control that selects state information corresponding to the occurrence of the failure from the state information acquired by the failure detection unit, and saves the state information in an externally accessible state A section.

  The method according to the present invention includes a step of detecting a failure of a main processing unit, a step of acquiring state information of the main processing unit that is notified regardless of the occurrence of the failure, and the failure from the acquired state information. Selecting state information corresponding to the occurrence of the error and storing the state information in a state accessible from the outside.

  The program according to the present invention includes a step of detecting a failure of the main processing unit, a step of acquiring the state information of the main processing unit notified regardless of the occurrence of the failure, and the failure from the acquired state information The step of selecting the state information corresponding to the occurrence of the error and the step of storing the state information in a state accessible from the outside is realized by the computer.

  According to the present invention, it is possible to provide a processing apparatus, method, and program capable of easily analyzing a failure in the main processing system when a failure occurs in the main processing system.

2 is a block diagram illustrating a processing apparatus according to Embodiment 1. FIG. 2 is a block diagram illustrating a processing apparatus according to Embodiment 1. FIG. FIG. 3 is a sequence diagram illustrating the operation of the processing apparatus according to the first embodiment. It is a figure which illustrates the event information which a platform event generation part generates. 3 is a block diagram illustrating a processing apparatus according to Comparative Example 1 of Embodiment 1. FIG. 6 is a sequence diagram illustrating the operation of a processing apparatus according to Comparative Example 1 of Embodiment 1. FIG. FIG. 6 is a block diagram illustrating a processing apparatus according to a second embodiment. FIG. 10 is a block diagram illustrating a processing apparatus according to a third embodiment. FIG. 10 is a block diagram illustrating a part of a processing apparatus according to a third embodiment.

[Embodiment 1]
Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram illustrating a processing apparatus according to the first embodiment.

  As illustrated in FIG. 1, the processing apparatus 10 according to the first embodiment includes a main processing unit 11, a monitoring control unit 12, and a failure detection unit 13. The main processing unit 11 performs main processing such as processing of information provided to the outside. The failure detection unit 13 is provided outside the main processing unit 11 and detects a failure of the main processing unit 11. Further, the failure detection unit 13 acquires the state information of the main processing unit 11 notified from the main processing unit 11 regardless of the occurrence of the failure. The monitoring control unit 12 selects state information corresponding to the occurrence of a failure from the state information acquired by the failure detection unit 13, and stores it in a state accessible from the outside.

The processing apparatus 10 according to the first embodiment will be described in detail.
FIG. 2 is a block diagram illustrating the processing apparatus according to the first embodiment.

  The processing device 10 further includes a display unit 115. The main processing unit 11 includes a CPU 111 and storage units 112 to 114.

  The processing device 10 is a device such as a web server or a file server, for example. The CPU 111 has a central processing unit (CPU), that is, a central processing unit, realizes the main functions of the processing apparatus 10, and processes information to be output to the outside and provided. The storage unit 112 is, for example, a ROM (Read-Only Memory), and stores a boot loader such as a BIOS (Basic Input Output System). The storage unit 113 is, for example, a RAM (Randum Access Memory) and is a main storage unit of the processing device 10. The storage unit 114 stores an OS (Operating System) and a file system application.

  The BIOS is one of firmware, and is a program for performing the lowest level input / output with hardware among programs installed in a processing device such as a computer. The BIOS is executed when the processing apparatus is powered on. The BIOS function includes initialization of hardware of the processing device and call of a boot loader from the storage unit.

  The boot means starting of the processing device, and corresponds to processing up to starting up the operating environment of the processing device such as an OS (Operating System) when the power is turned on. The boot loader is a program that reads a program necessary for starting up the operating environment of the processing device at the time of booting.

  The failure detection unit 13 includes a watchdog timer (WDT) control unit 131, a CPU state holding unit 134, an alarm generation unit 132, and an alarm additional information generation unit 133.

  The failure detection unit 13 is provided inside the processing apparatus 10 and outside the main processing unit 11. The CPU status holding unit 134 of the failure detection unit 13 acquires, for example, status information of the main processing unit 11 that is periodically transmitted from the main processing unit 11.

  Here, a failure that occurs in the main processing unit 11 will be described. An example of a failure that occurs in the main processing unit 11 is deadlock. As a method for detecting this deadlock, a method using a watchdog timer can be mentioned. As the watchdog timer, one included in SoC (System-on-a-chip) may be used, or an external watchdog timer may be used. An external watchdog timer may be used because of resources owned by the SoC and ease of future maintenance.

  In this example, an external watchdog timer is used. The processing device 10 includes a watchdog timer 131a in the watchdog timer control unit 131 of the failure detection unit 13, and uses this as an external watchdog timer. The watchdog timer control unit 131 detects a deadlock of the CPU 111 of the main processing unit 11 using the watchdog timer 131a. That is, the main processing unit 11 transmits a detection signal (reload request) for detecting the occurrence of a failure in the main processing unit 11 to the failure detection unit 13. For example, the watchdog timer control unit 131 of the failure detection unit 13 detects the occurrence of a failure such as a deadlock in the CPU 111 when there is no detection signal that the CPU 111 performs for the watchdog timer 131a for a predetermined period α. Judge. In this way, the failure detection unit 13 acquires failure information such as timeout information. The detection signal is called a reload request. The detection signal is transmitted within a predetermined period α. Further, the detection signal may be periodically performed.

  When the watchdog timer control unit 131 determines that a failure has occurred, the watchdog timer control unit 131 notifies the alarm additional information generation unit 133 and the alarm generation unit 132 of failure information such as timeout information.

  Note that deadlock is a failure in which a plurality of processes waits for the release of resources occupied by each other and stop processing. The watchdog timer may mean a watchdog timer function.

  The CPU state holding unit 134 holds state information of the CPU 111 notified from the CPU 111 such as a BIOS status (POST (Power On Self Test) status) when the processing apparatus 10 is activated. Further, the CPU state holding unit 134 displays the state information of the CPU 111 on the display unit 115.

  The alarm additional information generation unit 133 is a format for notifying the BMC 122 of failure information such as timeout information notified from the watchdog timer control unit 131 and the state information of the CPU 111 held in the CPU state holding unit 134. To process. The processed fault information and state information are referred to as alarm additional information. The alarm additional information generation unit 133 outputs the alarm additional information to the alarm additional information acquisition unit 122b of the BMC 122.

  The alarm generation unit 132 outputs failure information such as timeout information notified from the watchdog timer control unit 131 to the alarm acquisition unit 122c of the BMC 122. Information output from the alarm generation unit 132 is referred to as alarm information.

  The monitoring control unit 12 includes a BMC 122 and a storage unit 121. The BMC 122 includes a CPU different from the CPU included in the CPU 111. The storage unit 121 is, for example, an EEPROM (Electrically Erasable Programmable Read-Only Memory).

  The BMC 122 includes a platform event generation unit 122a, an alarm additional information acquisition unit 122b, and an alarm acquisition unit 122c. The platform event (PlatformEvent) generation unit 122a processes the alarm information and the alarm additional information into event information described later. The alarm additional information acquisition unit 122b acquires the alarm additional information output from the alarm additional information generation unit 133, and selects and stores state information corresponding to the occurrence of a failure from the acquired state information. The alarm acquisition unit 122c acquires the failure information output from the alarm generation unit 132. Status information (status information) is notified to the alarm additional information acquisition unit 122b via the routes L11 to L13 shown in FIG. 2, and alarm information is notified to the alarm acquisition unit 122c via the routes L21 to L23.

  The event information processed by the platform event generation unit 122a is stored in the storage unit 121 in a state accessible from the outside, or is output to the external device 20 as event information. Note that the output of event information from the monitoring control unit 12 to the external device 20 is output via, for example, an IPMB (Intelligent Platform Management Bus) 3.

  The display unit 115 includes, for example, a 7 segment LED (7 segment Lazer Emitting Diode), and displays the status of the BIOS when the processing apparatus 10 is activated. Further, the display unit 115 displays the state information of the CPU 111 and the failure information of the CPU 111.

  In the first embodiment, a watchdog timer 131 a for detecting the occurrence of a failure in the CPU 111 is provided in the failure detection unit 13 that is independent from the CPU 111. The failure detection unit 13 voluntarily detects a failure by the watchdog timer. Thereby, even when a failure occurs in the CPU 111 and the CPU 111 is operating abnormally, it is possible to detect the failure of the CPU 111 and notify the failure information to the BMC 122 via the failure detection unit 13.

  Further, status information of the CPU 111 is made independent from the CPU 111 and notified to the CPU status holding unit 134 of the failure detection unit 13 for status notification. Then, the state information of the CPU 111 is notified to the BMC 122 via the CPU state holding unit 134. That is, the CPU 111 notifies the failure detection unit 13 of the status and notifies the BMC 122 of the status information (status). These operations are performed spontaneously by the failure detection unit 13 and the BMC 122. As a result, even when a failure occurs in the CPU 111 and the CPU 111 is operating as described above, the state information of the CPU 111 can be output to the BMC 122 via the failure detection unit 13.

Next, the operation of the processing apparatus according to the first embodiment will be described.
FIG. 3 is a sequence diagram illustrating the operation of the processing apparatus according to the first embodiment.

  As shown in FIG. 3, the CPU 111 of the main processing unit 11 receives status information (status information of the CPU 111) that is a POST status code corresponding to the progress status of the POST status of the BIOS when the processing device 10 is started up, etc. 13 CPU status holding units 134 (step S101).

  The CPU 111 requests the watchdog timer controller 131 to reload the watchdog timer (send detection signal) together with step S101 (step S102).

  In step S <b> 101, the failure detection unit 13 acquires state information of the main processing unit 11 notified from the main processing unit 11 regardless of the occurrence of the failure. Step S101 and step S102 may be performed periodically. The notification in step S101 is abbreviated as status notification.

  The CPU state holding unit 134 causes the display unit 115 to display the contents of the status notification in step S101. Note that the watchdog timer control unit 131 starts a watchdog timer for the CPU 111 in advance before the status notification in step S101 (step S103).

  In step S102, it is assumed that the main processing unit 11 is operating normally if a watchdog timer reload request is made periodically.

  When a deadlock occurs in the main processing unit 11 (step S105), the watch dog timer reload request is delayed. If the reload request is delayed and there is no reload request for a predetermined period α, the watchdog timer control unit 131 of the failure detection unit 13 determines that a failure has occurred in the CPU 111 and times out the watchdog timer (step S106). . In step S106, the failure detection unit 13 detects a failure in the main processing unit 11, and acquires failure information such as a timeout. Then, the watchdog timer control unit 131 notifies the alarm additional information generation unit 133 and the alarm generation unit 132 of the timeout information regarding the timeout (step S107a, step S107c). The notification of timeout information is abbreviated and called timeout notification.

  The alarm additional information generating unit 133 that has received the time-out notification in step S107a inquires of the CPU status holding unit 134 about the current status information of the CPU 111 (status information of the CPU 111), and the current status information from the CPU status holding unit 134. (Step S107b). Further, the alarm additional information generation unit 133 processes the status information and the timeout information into a format for notifying the BMC 122, and generates alarm additional information (step S108a).

  Receiving the timeout information, the alarm generation unit 132 raises a watchdog timer alarm flag indicating that a watchdog timer alarm has occurred (step S108b). Raising the watchdog timer alarm flag means, for example, providing an alarm bit for the watchdog timer and turning on the alarm bit. Information on whether the alarm bit is on or off is called alarm information. The alarm generation unit 132 generates alarm information based on timeout information (failure information) of the CPU 111 of the main processing unit 11.

  The BMC 122 of the monitoring controller 12 monitors the watchdog timer alarm flag (step S104a) and monitors whether alarm additional information is generated (step S104b). In step S104a, the BMC 122 monitors whether or not the watchdog timer alarm flag is raised by, for example, polling the alarm generation unit 132. In step S104b, the BMC 122 monitors whether the alarm additional information is generated by polling the alarm additional information generation unit 133. That is, the monitoring control unit 12 issues a failure confirmation request to the alarm additional information generation unit 133 of the failure detection unit 13 and acquires the state information of the CPU 111 from the alarm additional information generation unit 133. In addition, the monitoring control unit 12 issues a failure confirmation request to the alarm generation unit 132 of the failure detection unit 13 and acquires failure information from the alarm generation unit 132. The failure confirmation request in step S104a and step S104b is periodically performed.

  When the watchdog timer alarm flag is raised and it is recognized that the watchdog timer alarm is generated (step S109a), the BMC 122 shapes the information in the platform event generation unit 122a and stores the watchdog in the storage unit 121 or the like. The timer alarm information (SEL (System Event Log)) is stored and registered (step S110a).

  If it is recognized that a watchdog timer alarm has occurred (step S109a), the BMC 122 notifies the external device 20 of an event via IPMB3 (step S111a).

  When recognizing that alarm additional information has been generated (step S109b), the BMC 122 formats the information in the platform event generation unit 122a, and stores alarm additional information (SEL (System Event Log)) in the storage unit 121 or the like. Store and register (step S110b). In step S110b, the BMC 122 selects state information corresponding to the occurrence of a failure from the state information of the CPU 111 acquired from the alarm additional information generation unit 133, and stores this in the storage unit 121 in a state where it can be accessed from the outside.

  When it is recognized that alarm additional information has been generated (step S109b), the BMC 122 notifies the external device 20 of an event via IPMB3 (step S111b). That is, the BMC 122 associates the state information and the failure information and outputs them to the outside.

Next, event information generated by the platform event generation unit 122a will be described.
FIG. 4 is a diagram illustrating event information generated by the platform event generation unit.
FIG. 4 shows information exchanged between the alarm additional information generation unit 133 of the failure detection unit 13 and the alarm additional information acquisition unit 122b of the BMC 122.

  Information D401 (alarm additional information) illustrated in FIG. 4 is information exchanged between the alarm additional information generation unit 133 and the alarm additional information acquisition unit 122b. Information D401 is alarm additional information generated by the alarm additional information generation unit 133 and output to the alarm additional information acquisition unit 122b. The information D401 includes a status issuer, a status code, and a status code (extended). The status issuer and status code (extended) are for future expansion. The status code indicates status information (state information) of the CPU 111 when a deadlock occurs (when a failure occurs) in the main processing unit 11.

  Information D402 illustrated in FIG. 4 is event information generated by the platform event (PlatformEvent) generation unit 122a of the BMC 122. The platform event generation unit 122a uses the PlatformEvent format generally defined by IPMI (Intelligent Platform Management Interface) as information D401 (alarm additional information) acquired by the alarm additional information acquisition unit 122b from the alarm additional information generation unit 133. To process. The event information generated by the platform event generation unit 122a is stored in the storage unit 121 or the external device 20.

  In this way, not only deadlock (failure information) of the CPU 111 of the main processing unit 11 but also status information (state information) of the main processing unit 11 can be transmitted to the external device 20 or the like as event information.

  A feature of the processing apparatus according to the first embodiment is that an abnormality of the CPU 111 is detected by an external watchdog timer 131a, and for example, the state information of the CPU 111 at the time of occurrence of a failure such as a watchdog timer alarm is used as event information information. 20 or the like.

The effect of the first embodiment will be described.
In the first embodiment, the CPU 111 of the main processing unit 11 notifies the failure detection unit 13 of status information as needed, detects the watchdog timer alarm spontaneously, and reports to the BMC 122 voluntarily. Yes. Then, the CPU 111 detects the failure of the CPU 111 using an external watchdog timer without using the watchdog timer of the CPU 111. As a result, even when a failure occurs in the CPU 111, the failure of the CPU 111 can be detected and the failure status of the CPU 111 can be notified to the BMC 122.

  In the first embodiment, the status information of the CPU 111 and the watchdog timer alarm information are monitored from the failure detection unit 13 existing outside the CPU 111 without using the SMI (System Management Interrupt) function of the CPU 111. This is notified to the control unit 12. Thereby, even when a failure occurs in the CPU 111, the status of the CPU 111 can be notified to the BMC 122.

  Further, when the main processing unit 11 deadlocks, the processing device 10 according to the first embodiment can transmit the status information and alarm information of the CPU 111 necessary for the cause analysis to the external device 20 or the like. Thereby, the analysis of the failure of the processing apparatus 10 can be easily performed. As a result, when a failure occurs in the main processing unit, it is possible to provide a processing device, method, and program capable of easily analyzing the failure of the main processing unit.

  In this embodiment, the BIOS status code has been described as an example. However, the present invention may be applied to an OS (Operating System) or an application process number.

  In this embodiment, the external watchdog timer has been described as an example. However, this external watchdog timer is included in the SoC (System-on-a-Chip) for monitoring and control. You may implement | achieve with a structure.

[Comparative Example 1 of Embodiment 1]
FIG. 5 is a block diagram illustrating a processing apparatus according to comparative example 1 of the first embodiment.

  As shown in FIG. 5, the processing apparatus 10a according to the comparative example 1 includes a main processing unit 11a, a monitoring control unit 12a, and a failure detection unit 13a.

  The main processing unit 11a includes a simple display unit 115 such as a 7-segment LED (Lazer Emitting Diode), for example, and displays a BIOS status (POST (Power On Self Test) status) when the processing apparatus 10a is activated. To display.

  Compared with the monitoring control unit 12 of the first embodiment, the monitoring control unit 12a is not provided with the alarm additional information acquisition unit 122b.

  The failure detection unit 13a is not provided with the CPU state holding unit 134 and the alarm additional information generation unit 133 as compared with the failure detection unit 13 of the first embodiment.

  FIG. 6 is a sequence diagram illustrating the operation of the processing apparatus according to the first comparative example of the first embodiment.

  As shown in FIG. 6, the CPU 111 of the main processing unit 11a transmits a POST status code corresponding to the progress status of the POST status of the BIOS to the display unit 115 when the processing apparatus 10a is started up (step S101) and a watchdog timer A watchdog timer reload request is periodically sent to the control unit 131 (step S102).

  When a deadlock occurs in the main processing unit 11a (step S105) and the watchdog timer reload instruction is delayed, the watchdog timer control unit 131 times out (step S106) and notifies the alarm generation unit 132 of this (step S106). S107).

  The alarm generation unit 132 raises a flag indicating that a watchdog timer alarm has occurred (step S108).

  On the other hand, the BMC 122 of the monitoring control unit 12a periodically monitors the watchdog timer alarm flag (step S104), and when the alarm is recognized (step S109), alarm information (SEL (System Event Log)) is stored in the storage unit 121 or the like. Is stored and registered (step S110), and an event is notified to the external device 20 through the IPMB3 (step S111).

  However, in the first comparative example of the first embodiment, when a deadlock occurs in the main processing unit 11a, only alarm information that a failure has occurred can be recognized. The state information of the CPU 111 cannot be recognized. Therefore, it is difficult to analyze the failure of the processing apparatus 10.

[Comparative Example 2 of Embodiment 1]
The comparative example 2 of the first embodiment is different from the first embodiment in that a failure of the CPU 111 is detected using the watch dog timer function of the CPU 111. In the second comparative example, when a failure occurs in the watchdog timer function and the CPU 111 is operating abnormally, it is difficult to detect the failure of the CPU 111.

[Comparative Example 3 of Embodiment 1]
The comparative example 3 of the first embodiment is different from the first embodiment in that a CPU failure notification is made using an SMI (System Management Interrupt) function of the CPU 111. In the third comparative example, when a failure occurs in the SMI function and the CPU 111 is operating abnormally, it is difficult to notify the failure of the CPU 111.

[Embodiment 2]
Next, a second embodiment will be described.
FIG. 7 is a block diagram illustrating a processing apparatus according to the second embodiment.

  As shown in FIG. 7, the second embodiment is different from the first embodiment in that the failure detection unit 13 includes an additional information control unit 135. The additional information control unit 135 acquires the status code a plurality of times after the deadlock has occurred, and controls how many times the acquired status code is output to the alarm additional information acquisition unit 122b at regular intervals. A desired value is set by the additional information control unit 135 for the time interval of a certain time and the number of status codes output at every certain time.

  In the second embodiment, the additional information control unit 135 sets a time interval of a fixed time and the number of status codes output every fixed time. As a result, the CPU 111 determines whether a failure such as a software runaway has occurred, or whether the software is operating properly to some extent, based on the length of the reload interval of the watchdog timer. be able to.

  For example, the monitoring control unit 12 can determine the degree of failure of the main processing unit 11 based on the time from the last detection signal before the occurrence of the failure to the first detection signal after the occurrence of the failure.

  Further, the monitoring control unit 12 may determine the degree of failure of the main processing unit 11 based on the time from the first detection signal to the second detection signal after the occurrence of the failure.

  Further, the monitoring control unit 12 may determine the degree of failure of the main processing unit 11 based on the time between the last detection signal before the occurrence of the failure and the previous detection signal.

[Embodiment 3]
Next, Embodiment 3 will be described.
FIG. 8 is a block diagram illustrating a processing apparatus according to the third embodiment.
FIG. 9 is a block diagram illustrating a part of the processing apparatus according to the third embodiment.

  As shown in FIG. 8, the failure detection unit 13 according to the third embodiment is different from the first embodiment in that it further includes an abnormality detection unit 136 and a storage unit 137. The abnormality detection unit 136 has the same function and structure as the watchdog timer control unit 131, and has a function for detecting a failure in a part other than the CPU 111. The abnormality detection unit 136 has a plurality of detection functions such as a detection function Fa, a detection function Fb, and a detection function Fc in order to detect failures at a plurality of parts.

  For example, when the failure detection unit 13 is configured by an FPGA (Field-Programmable Gate Array), a configuration file for configuring the FPGA is stored in a storage unit 137 configured by a flash ROM (Read Only Memory) or the like. Stored.

  When configuring the FPGA, the storage unit 137 storing the configuration file is accessed. At this time, the abnormality detection unit 136 detects an access abnormality to the storage unit 137 and notifies the BMC 122 of this as alarm additional information. As the alarm additional information, for example, the information is discriminated using the status issuer, status code, and status code (extended) which are information D401 shown in FIG. In this way, the abnormality detection unit 136 detects a failure.

  Further, the abnormality detection unit 136 performs an abnormality in another part in addition to an abnormality in access to the storage unit 137 using the detection function Fa, the detection function Fb, the detection function, and Fc.

  When the abnormality detection unit 136 and the watchdog timer control unit 131 detect an abnormality in a plurality of parts at the same time and notify the alarm additional information generation unit 133 that the abnormality has occurred, a conflict occurs between the information to be notified. , Information to notify may be lost. In order to avoid such information loss, for example, a FIFO (First In First Out) is provided in the failure detection unit 13 as shown in FIG.

  Next, the operation of the alarm additional information generation unit 133 according to Embodiment 3 will be described.

  As shown in FIG. 9, when there is an alarm write request from the watchdog timer control unit 131 and the abnormality detection unit 136, the alarm additional information generation unit 133 writes information in the FIFO one after another.

  When the information is written in the FIFO, the alarm additional information generation unit 133 checks the register R401 indicating the presence / absence of the alarm additional information. When the flag of the register R401 is set, this indicates a state in which information is written in the FIFO. Further, when the flag of the register R401 is not set, this indicates a state in which no information is written in the FIFO.

  The alarm additional information generation unit 133 does nothing when the flag of the register R401 is set. Further, when the flag of the register R401 is not set, the alarm additional information generation unit 133 extracts information from the FIFO, reflects the extracted information in the register R402, and sets the flag of the register R401.

  On the other hand, the BMC 122 monitors the register R401 and does nothing if the flag of the register R401 is not set. In addition, when the flag of the register R401 is set, the BMC 122 reads the contents of the register R402 and clears the flag of the register R401.

  The register R402 is a register indicating a status issue source, a status code, and a status code (extended).

  In the above embodiments, the present invention has been mainly described as a hardware configuration, but the present invention is not limited to this. The present invention can also realize processing of each component by causing a CPU (Central Processing Unit) to execute a computer program.

  In the above example, the program can be stored using various types of non-transitory computer readable media and supplied to the computer. Non-transitory computer readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (for example, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (for example, magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / W, semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM)), flash ROM, RAM (Random Access Memory) are included. The program may also be supplied to the computer by various types of transitory computer readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 10, 10a ... Processing apparatus 11, 11a ... Main processing part 12, 12a ... Monitoring control part 13, 13a ... Fault detection part 111 ... CPU 1122-114 ... Storage part 115 ... Display part 121 ... Storage part 122 ... BMC 122a ... Platform Event generation unit 122b ... alarm additional information acquisition unit 122c ... alarm acquisition unit 131 ... watchdog timer control unit 131a ... watchdog timer 132 ... alarm generation unit 133 ... alarm additional information generation unit 134 ... CPU state holding unit 135 ... additional information control Unit 136 ... Abnormality detection unit 137 ... Storage unit D401, D402 ... Information R401, R402 ... Register Fa, Fb, Fc ... Detection function L11, L12, L13, L21, L22, L23 ... Path α ... Predetermined period

Claims (10)

A main processing unit that performs main processing;
A fault detection unit that is provided outside the main processing unit, detects the occurrence of a fault in the main processing unit, and obtains status information of the main processing unit to be notified regardless of the occurrence of the fault;
From the status information acquired by the fault detection unit, select the status information corresponding to the occurrence of the fault, and save and control in a state accessible from the outside,
A processing apparatus comprising: The main processing unit transmits a detection signal for detecting the occurrence of the failure to the failure detection unit,
The failure detection unit determines that the occurrence of the failure has been detected when there is no detection signal for a predetermined period.
The processing apparatus according to claim 1. The monitoring control unit determines the degree of failure of the main processing unit based on the time from the last detection signal before the occurrence of the failure to the first detection signal after the occurrence of the failure.
The processing apparatus according to claim 2. The monitoring control unit determines a degree of failure of the main processing unit based on a time from the first detection signal to the second detection signal after the occurrence of the failure;
The processing apparatus according to claim 2 or 3. The monitoring control unit determines the degree of failure of the main processing unit based on the time between the last detection signal before the occurrence of the failure and the previous detection signal.
The processing apparatus as described in any one of Claims 2-4. The processing apparatus according to claim 2, wherein the detection signal is transmitted within the predetermined period. The monitoring control unit makes a failure confirmation request to the failure detection unit, and acquires failure information indicating whether or not the failure has occurred and the state information from the failure detection unit,
The processing apparatus as described in any one of Claims 1-6.   The processing apparatus according to claim 7, further comprising a display unit that displays the state information and the failure information. Detecting a failure of the main processing unit;
Obtaining status information of the main processing unit to be notified regardless of the occurrence of the failure;
Selecting status information corresponding to the occurrence of the failure from the acquired status information;
A step of saving in an externally accessible state;
A method comprising: Detecting a failure of the main processing unit;
Obtaining status information of the main processing unit to be notified regardless of the occurrence of the failure;
Selecting status information corresponding to the occurrence of the failure from the acquired status information;
A step of saving in an externally accessible state;
A program that makes a computer realize.

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