JP2017187714A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device with a shallower contact hole.SOLUTION: A display device includes a semiconductor layer 17 on an insulating substrate 10, an insulating film 15A formed thereon, a pedestal portion 21 formed thereon, a metal portion 22 covering the pedestal portion 21, an insulating film 12 covering the metal portion 22, a contact hole 22 formed at a position in accordance with the pedestal portion 21, and a transparent electrode 14 on the contact hole 22. The semiconductor layer 17 and the transparent electrode 14 are in electric contact with each other through the metal portion 22 and the contact hole 23. The height h1 of the pedestal portion 21 is 1/2 to 2/3 of the height h2 of the insulating film 12.SELECTED DRAWING: Figure 5

Description

  Embodiments described herein relate generally to a display device.

  Conventionally, in a display panel of a display device such as a liquid crystal display device, an organic insulating film is formed after forming a semiconductor layer, a gate insulating film, a gate line, an interlayer insulating film, and a signal line on a glass substrate of an array substrate. A pixel electrode is formed thereon. In order to connect the pixel electrode and the semiconductor layer, a contact hole is provided in the organic insulating film.

JP 2007-057847 A JP 2013-235148 A

  However, when the contact hole is deeply provided in the organic insulating film as the display panel becomes higher in definition, the ratio of the area occupied by the tapered region of the contact hole increases, the aperture ratio of the pixel decreases, and the contact hole becomes deeper. As a result, there are problems that the processing margin of the transparent electrode film is reduced, cleaning becomes difficult, and spots and unevenness occur.

  Therefore, an object of the embodiment of the present invention is to provide a display device that can make a contact hole shallow.

  An embodiment of the present invention includes an insulating substrate, a semiconductor layer on the insulating substrate, a first insulating film on the semiconductor layer, the signal line and metal part on the first insulating film, and the first insulating film. A pedestal on the film, a first contact hole formed in the first insulating film, a second insulating film covering the first insulating film, the pedestal, and the metal part, and formed in the second insulating film The second contact hole is formed on an upper surface of the pedestal portion, and the metal portion is formed by the first contact hole. The transparent electrode is in contact with the semiconductor layer and covers the upper surface of the first insulating film and the upper surface of the pedestal portion, and the transparent electrode is formed on the metal portion on the pedestal portion through the second contact hole. The height of the pedestal is in contact with the thickness of the second insulating film. 1 / 2-2 / 3, it is a display device according to claim.

  In addition, an embodiment of the present invention includes an insulating substrate, a first metal line in a peripheral region surrounding the image display region of the insulating substrate, an inorganic insulating film on the first metal line, and a second metal on the inorganic insulating film. A metal wire, a pedestal part, the inorganic insulating film, the second metal line, an organic insulating film on the pedestal part, and a conductive layer on the organic insulating film, wherein the height of the pedestal part is It is 1/2 to 2/3 of the film thickness of the organic insulating film, the second metal line has a laminated structure of at least two layers, and the second metal line covers at least the upper surface of the pedestal portion. The third contact hole is formed from the organic insulating film to the second metal line located on the upper surface of the pedestal portion, and the conductive layer is formed on the upper surface of the pedestal portion. 2 metal wires are in contact with each other through the third contact hole It is that the display device.

It is a top view of the pixel of Embodiment 1 of this invention. It is a schematic plan view of an array substrate. It is an enlarged plan view of TFT. It is the sectional view on the AA line in FIG. It is the BB sectional view taken on the line in FIG. It is CC sectional view taken on the line in FIG. It is sectional drawing of the 1st process which makes a 2nd contact hole. It is sectional drawing of the 2nd process which makes a 2nd contact hole. It is sectional drawing of the 3rd process which makes a 2nd contact hole. 4 is a longitudinal sectional view of a TFT according to Embodiment 2. 6 is a longitudinal sectional view of a TFT according to Embodiment 3. FIG. 6 is a plan view of a TFT according to Embodiment 4. FIG. 6 is a longitudinal sectional view of a TFT according to Embodiment 4. FIG. FIG. 10 is a longitudinal sectional view of a peripheral region of the fifth embodiment. FIG. 10 is a plan view of an array substrate according to a fifth embodiment. FIG. 10 is a longitudinal sectional view of a peripheral region of the fifth embodiment. FIG. 10 is a longitudinal sectional view of a first modification of the peripheral area in the fifth embodiment. FIG. 10 is a partially cutaway perspective view of a second modification of the peripheral area of the fifth embodiment.

  A liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings. It should be noted that the disclosure in the embodiment is merely an example, and those skilled in the art can easily conceive of appropriate changes while maintaining the spirit of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematically represented with respect to the width, thickness, shape, and the like of each part in comparison with actual correspondence in order to make the description clearer, but are merely examples, and the interpretation of the present invention is not limited. It is not limited. In addition, in the present specification and each drawing, the same elements and the same reference numerals as those described above with reference to the previous drawings are attached, and the detailed description may be omitted as appropriate.

  The liquid crystal display device according to the present embodiment is of a horizontal electric field method called an IPS (In-Plane Switching) method in a specific example, and in particular, an FFS (Fringe Field Switching) using a fringe electric field as an example of the IPS method. ) Method.

Embodiment 1

  The liquid crystal display device of Embodiment 1 is demonstrated with reference to FIGS.

(1) Overall configuration of display panel 1 A display panel 1 of a liquid crystal display device includes an array substrate 2, a counter substrate 3, a liquid crystal layer 4 held in a gap therebetween, and peripheral portions of both substrates 2 and 3. The sealing member 5 is bonded to seal the liquid crystal layer 4. The display panel 1 includes an image display area for displaying an image and a peripheral area surrounding the image display area.

(2) Array substrate 2
The array substrate 2 will be described with reference to FIG. 1, FIG. 2, and FIG. As shown in FIG. 2, in the image display area of the glass substrate 10 of the array substrate 2, the vertical signal lines 15 and the horizontal gate lines 16 are arranged in a lattice pattern, and a pixel 6 is formed at each intersection point. ing. The pixel 6 includes an n-type channel or p-type channel TFT (thin film transistor) 7 which is a switching element, and a pixel electrode 14. The gate line 16 is connected to the gate electrode 16 A of the TFT 7, and the signal line 15 is connected to the source electrode. The drain electrode is connected to the pixel electrode 14. As shown in FIG. 1, the pixel 6 extends long along the direction of the signal line 15, and most of the longitudinal region corresponds to the pixel opening, and the pixel electrode 14 having the slit 14A is disposed in this portion. Is done. The TFT 7 is formed at one end of the pixel 6.

  A semiconductor layer 17 made of polysilicon constituting the TFT 7 is formed on the upper surface of the glass substrate 10 of the array substrate 2, and a gate insulating film 16B is formed thereon. On top of this, gate lines 16 are formed in parallel in the horizontal direction at predetermined intervals. As shown in FIG. 2, at the end of each gate line 16 in the horizontal direction and in the peripheral region of the array substrate 2, a gate lead line 16C is formed in the vertical direction continuously to the gate line 16, and the sealing member 5 It extends to the surrounding area.

  A first interlayer insulating film 15A is formed on the gate line 16, and a signal line 15 is formed thereon in the vertical direction. An organic insulating film 12 is formed on the signal line 15 with resin. A common electrode 13 made of a transparent conductive material such as ITO or IZO is formed on the organic insulating film 12.

  A common line 20 is formed on the signal line 15 and the common electrode 13, and each common electrode 13 is electrically connected by the common line 20. A second interlayer insulating film 13 </ b> A is formed on the common electrode 13 and the common wiring 20. A pixel electrode 14 is formed on the second interlayer insulating film 13A. As shown in FIG. 4, an alignment film 18 is formed on the pixel electrode 14 and on the surface in contact with the liquid crystal layer 4. The alignment film 18 may be a horizontal alignment film that has been subjected to an alignment process by a rubbing process or an optical alignment process, or may be a vertical alignment film.

(3) TFT7
The structure of the TFT 7 will be described.

  As shown in FIG. 1, the semiconductor layer 17 formed on the glass substrate 10 extends in the vertical direction along the signal line 15 while intersecting with the gate line 16, and then bends toward the pixel electrode 14. It extends in the horizontal direction, then bends and extends in the vertical direction while crossing the gate line 16 to reach the position of the TFT 7.

  As shown in FIGS. 1 and 6, a contact hole 15B is provided in the gate insulating film 16B and the first interlayer insulating film 15A in order to connect one end of the semiconductor layer 17 and the signal line 15.

  As shown in FIGS. 6 and 7, the other end of the semiconductor layer 17 is covered with the gate insulating film 16B and the first interlayer insulating film 15A, so that a first contact hole 19 is provided.

  As shown in FIGS. 3, 6, and 7, the hemispherical pedestal portion 21 is provided on the first interlayer insulating film 15 </ b> A in the central portion of the TFT 7 and in the vicinity of the first contact hole 19. The material of the pedestal 21 is an inorganic material such as SiO or SiN, an organic material, the same material as the spacer, or a metal. The shape of the pedestal portion 21 is a hemispherical shape, that is, the side surface shape is an arc shape and the planar shape is a circular shape, but the shape is not limited to this and may be a trapezoidal shape or a square shape. Further, the pedestal 21 has a lower surface diameter of about 5 μm and an upper surface diameter of about 2 to 3 μm. The height h1 of the pedestal portion 21 is about 1/2 to 2/3 of the height h2 of the organic insulating film. When the height h2 of the organic insulating film is 3 μm, for example, the height of the pedestal portion 21 is set. h1 is, for example, about 1.5 μm to 2 μm.

  As shown in FIGS. 5 and 6, the metal part 22 covers the upper surface of the base part 21, the first contact hole, and the first interlayer insulating film 15 </ b> A between the base part 21 and the first contact hole 19. . The metal part 22 has a thickness of about 0.6 to 0.7 μm and is a metal material containing aluminum which is the same material as the signal line 15. For example, a laminated structure in which an upper layer and a lower layer of aluminum are sandwiched between titanium. Formed from. The metal part 22 is filled in the first contact hole 19 and is electrically connected to the semiconductor layer 17.

  The organic insulating film 12 covers the pedestal portion 21 covered with the metal portion 22, the signal line 15, and the first interlayer insulating film 15A.

  The second interlayer insulating film 13A is formed on the organic insulating film 12 as shown in FIGS. At a position other than the TFT 7, the common electrode 13 is formed on the organic insulating film 12, and the second interlayer insulating film 13 </ b> A is formed on the common electrode 13.

  A second contact hole 23 is formed in the organic insulating film 12 and the second interlayer insulating film 13A located above the pedestal portion 21, and the upper surface of the metal portion 22 is exposed.

  As shown in FIGS. 5 and 6, the pixel electrode 14 made of a transparent conductive material is formed on the second interlayer insulating film 13A, connected to the metal part 22 through the second contact hole 23, and electrically Is connected to the semiconductor layer 17. A ring-shaped protrusion 24 is formed at the edge of the second contact hole 23, that is, at the edge of the organic insulating film 12. Further, as shown in FIG. 3, the center of the first contact hole 19 and the center of the second contact hole 23 are provided at positions shifted in plan view. The lower surface diameter of the second contact hole 23 is about 2 to 3 μm, and is 2.5 μm in one example. The lower surface diameter of the first contact hole 19 and the lower surface diameter of the second contact hole 23 are substantially the same. Further, the lower surface diameter of the contact hole 15B for connecting the semiconductor layer 17 and the signal line 15 is about 2 to 3 μm, and the lower surface diameter of the contact hole 15B and the lower surface diameter of the second contact hole 23 are substantially the same. is there. The semiconductor layer 17 and the pedestal portion 21 partially overlap in plan view. This is to save space around the second contact hole 23. The bottom surface of the second contact hole 23 is raised by the pedestal portion 20 to form a shallow contact hole.

  The reason why the height h1 of the pedestal 21 is ½ to 2/3 of the organic insulating film 12 is that the oxide film of the pedestal 21 is formed when the height h1 is the same as the organic insulating film 12. It takes a long time to form a film and the productivity is lowered. After the film is formed, it takes a time to etch into the shape of the pedestal, and the productivity is lowered. If the pedestal 21 is too high, the metal part 22 on the side wall of the pedestal is cut. Because there is a point. Therefore, the height h1 of the pedestal portion 21 is lowered to some extent to balance with the side effects as described above, and to a height suitable for actual production.

(4) Counter substrate 3
The counter substrate 3 will be described with reference to FIG. On the glass substrate 100 of the counter substrate 3, a black matrix 102 provided in a lattice shape with a black resin material is formed. As shown in FIG. 2, the black matrix 102 is formed by a vertical portion extending along the signal line 15 so as to cover the signal line 15 and the vicinity thereof, and a horizontal portion covering each TFT 7 and the vicinity thereof. In the example shown in the figure, the horizontal portion covering the vicinity of the TFT 7 extends continuously along the gate line 16 and is formed in a lattice shape with the vertical portion covering the vicinity of the signal line 15. Each grid-like opening of the black matrix 102 corresponds to a pixel opening.

  On the black matrix 102, a color filter layer 104 made of R (red), G (green), and B (blue) is formed.

  An overcoat layer 106 made of a resin is formed on the color filter layer 104. An alignment film 110 is formed on the surface of the counter substrate 3 in contact with the liquid crystal layer 4.

(5) Manufacturing Process of Array Substrate 2 An outline of the manufacturing process of the array substrate 2 will be described with reference to FIGS.

  In the first step, a semiconductor layer 17 is formed for each pixel 6 on the glass substrate 10 of the array substrate 2, and then the entire array substrate 2 together with each semiconductor layer 17 is a gate made of a silicon oxide film, a silicon nitride film or the like. Cover with the insulating film 16B.

  In the second step, the gate line 16 and the vertical gate lead-out line D from the end of the gate line 16 are formed in the horizontal direction by a metal layer such as molybdenum alloy, and then the entire array substrate 2 is oxidized together with these lines. The first interlayer insulating film 15A made of a silicon film, a silicon nitride film or the like is covered.

  In the third step, the contact hole 15B and the first contact hole 19 are formed through the first interlayer insulating film 15A and the gate insulating film 16B to expose the semiconductor layer 17.

  In the fourth step, the base portion 21 is formed on the first interlayer insulating film 15A. The pedestal 21 is formed of an inorganic material such as SiO or SiN, an organic material, acrylic, metal, or the like, which is the same material as the spacer. The height h1 of the pedestal 21 is about 1/2 to 2/3 of the height h2 of the organic insulating film. For example, when the height h2 of the organic insulating film is about 3 μm, it is about 1.5 to 2.0 μm. And the shape of the base part 21 is formed in hemispherical type, for example.

  In the fifth step, the signal line 15 is formed of a metal such as aluminum or an alloy thereof on the first interlayer insulating film 15A. Further, the metal portion 22 is formed so as to cover the pedestal portion 21, the first contact hole 19, and the first interlayer insulating film 15 </ b> A between the pedestal portion 21 and the first contact hole 19. The signal line 15 and the metal part 22 are made of, for example, a metal material in which titanium, aluminum, and titanium are laminated, and the thickness thereof is about 0.6 to 0.7 μm.

  In the sixth step, as shown in FIG. 7, the organic insulating film 12 is formed of a transparent resin, thereby covering the signal line 15 and the metal portion 22. The height h2 of the organic insulating film is, for example, about 3 μm.

  In the seventh step, a hole is formed in the organic insulating film 12 above the pedestal portion 21 to expose the upper surface of the metal portion 22 to form the second contact hole 23. The manufacturing method at this time will be described with reference to FIGS.

  As shown in FIG. 8, the second contact hole 23 is formed in the organic insulating film 12 by exposing and developing. At this time, a protrusion 24 is formed at the edge of the second contact hole 23. This is an effect of the convex shape of the organic insulating film 12, and the depth of the second contact hole 23 becomes extremely shallow.

  As shown in FIG. 9, the protrusion 24 of the organic insulating film 12 is rounded when reflowed by heat treatment or the like, and the surface becomes smooth.

  In the eighth step, a common electrode made of a transparent conductive material such as ITO or IZO is formed on the organic insulating film 12. However, the common electrode 13 is not formed near the TFT 7. The thickness of the common electrode 13 is, for example, about 10 to 30 nm (0.01 to 0.03 μm).

  In the ninth step, the common line 20 is formed on the common electrode 13 and the signal line 15, and each common electrode 13 is electrically connected by the common line 20.

  In the tenth step, a second interlayer insulating film 13 </ b> A covering the common electrode 13, the common line 20, etc. is formed on the entire array substrate 2.

  In the eleventh step, a contact hole is opened in the second interlayer insulating film 13A corresponding to the position of the second contact hole 23, and the upper surface of the metal portion 22 is exposed. In this case, the side surface of the second contact hole 23 is covered with the second interlayer insulating film 13A.

  In the twelfth step, a transparent pixel electrode 14 made of a transparent conductive material such as ITO or IZO is formed. The thickness of the pixel electrode 14 is, for example, 10 to 30 nm (0.01 to 0.03 μm). At this time, the pixel electrode 14 and the upper surface of the metal portion 22 are electrically connected through the second contact hole 23.

  In the thirteenth step, an alignment film 18 made of resin is formed on the entire array substrate 2, and finally a photo-alignment process is performed by ultraviolet irradiation.

(6) Manufacturing process of counter substrate 3 An outline of a manufacturing process of the counter substrate 3 will be described.

  In the first step, as shown in FIG. 4, a black matrix 102 made of a resin layer in which a black pigment is dispersed or a metal layer is formed on a glass substrate 100 of the counter substrate 3.

  In the second step, three color filter layers 104R, 104B, and 104G made of resin layers in which red, blue, and green pigments are dispersed are formed in order.

  In the third step, as shown in FIG. 9, an overcoat layer 106 that uniforms uneven thickness and unevenness between the color filter layers 104R, 104B, and 104G is formed. The thickness of the overcoat layer 106 is, for example, 0.5 to 2 μm, particularly 0.8 to 1.2 μm.

  In the fourth step, an alignment film 110 made of a resin is formed on the overcoat layer 106, and then a photo-alignment process by ultraviolet irradiation is performed.

(7) Effect In the present embodiment, since the lower surface of the second contact hole 23 is raised by the pedestal portion 21 and is shallow, the taper region of the second contact hole 23 is reduced, the pixel aperture ratio is improved, and the ITO The processing margin of the pixel electrode 14 is also increased. This improves the yield.

  In addition, since the depth of the second contact hole 23 is shallow, cleaning becomes easy, spots and unevenness are reduced, and the display quality of the display panel 1 is improved.

  In addition, since the pedestal portion 21 is about 1/2 to 2/3 of the height h2 of the organic insulating film, the time for forming the pedestal portion 21 can be shortened, and the metal portion 22 covering the pedestal portion 21 is also provided. Will not break. Therefore, the difficulty of etching the metal part 22 does not increase, unevenness and the like are reduced, and the display quality of the display panel 1 is improved. Further, when the pedestal portion 21 is formed of metal, the electrical connection between the semiconductor layer 17 and the pixel electrode 14 can be ensured even if the metal portion 22 is disconnected.

  Further, since the diameter of the second contact hole 23 is reduced, a flat portion region for forming the spacer is increased, a sufficient region for forming the spacer is secured, and variations in the liquid crystal layer 4 can be further reduced.

  Further, the metal portion 22 in the region of the second contact hole 23 has a structure protruding from other regions, but the organic insulating film 12 is excellent in flatness, so that the surface becomes smooth and the pixel electrode 14 Make the connection with the good.

Embodiment 2

  Next, the display panel 1 of the liquid crystal display device of Embodiment 2 is demonstrated based on FIG. The present embodiment is not the image display area as in the first embodiment, but the structure of its peripheral area.

  As shown in FIG. 10, a gate insulating film 16B, a gate lead line 16C, and a first interlayer insulating film 15A are formed on the upper surface of the glass substrate 10 in the peripheral region of the array substrate 2. A pedestal portion 21 is formed on the first interlayer insulating film 15A. The pedestal portion 21 may have a hemispherical shape, a trapezoidal shape, a square shape, or the like having a circular planar shape and an arc-shaped side surface shape.

  A common power supply line 50 for supplying power to the common electrode 13 is formed so as to cover the pedestal portion 21. An organic insulating film 12 made of a transparent resin is formed so as to cover the common power supply wiring 50. A third contact hole 51 is opened at a position corresponding to the pedestal 21 in the organic insulating film 12, and the common electrode 13 is formed thereon. In this case, the common power supply wiring 50 corresponds to the metal part 22 of the first embodiment. The lower surface diameter of the third contact hole 51 is, for example, 2 to 3 μm. Further, the upper surface diameter of the pedestal portion 21 is substantially the same as the lower surface diameter of the third contact hole 51. Further, the organic insulating film 12 has a protrusion at the edge of the third contact hole 51 as in the first embodiment.

  Even in the present embodiment, the lower surface of the third contact hole 51 is raised, and the depth of the third contact hole 51 becomes shallow.

  In the second embodiment, the configuration is shown in which the common power supply wiring 50 and the common electrode 13 are connected. However, instead of this, the sensor wiring and the sensor wiring formed on the organic insulating film 12 are connected. There may be. Moreover, it is also possible to use the common wiring 20 which is a 3rd metal wire as sensor wiring. The material of the common wiring 20 or sensor wiring at this time is, for example, a three-layer structure of Mo / Al / Mo.

Embodiment 3

  Next, the display panel 1 of the liquid crystal display device of Embodiment 3 is demonstrated based on FIG.

  In the first embodiment, the pixel electrode 14 is formed on the common electrode 13, but the glass substrate 10, the semiconductor layer 17, the gate insulating film 16B, the first interlayer insulating film 15A, and the pedestal portion 21 are formed. A first contact hole 19 is formed at the end of the semiconductor layer 17. The pedestal portion 21 is covered with a metal portion 22, and the metal portion 22 is electrically connected to the semiconductor layer 17 through the first contact hole 19. An organic insulating film 12 is formed on the first interlayer insulating film 15 </ b> A and the metal portion 22. A second contact hole 23 is formed in the organic insulating film 12 corresponding to the pedestal portion 21. A pixel electrode that is a transparent electrode is formed on the organic insulating film 12. The height h1 of the pedestal 21 is about 1/2 to 2/3 of the height h2 of the organic insulating film. The semiconductor layer 17 and the pixel electrode 14 are electrically connected via the second contact hole 23 and the metal part 22. A second interlayer insulating film 13A is formed on the pixel electrode 14, and the common electrode 13 is formed thereon. Next, the common line 20 is formed at a position corresponding to the signal line 15 in the common electrode 13, and the alignment film 18 is formed on the common electrode 13 and the common line 20.

  Also in the present embodiment, the lower surface of the second contact hole 23 is raised and shallowed by the pedestal portion 21.

Embodiment 4

  Next, the display panel 1 of the liquid crystal display device of Embodiment 4 is demonstrated based on FIG. 12 and FIG.

  The present embodiment is that, in the structure of the first embodiment, the pedestal 21 itself is raised by a gate branch line 16D extending from the gate line 16. That is, when the gate line 16 is formed, the gate branch line 16D is formed at a position corresponding to the pedestal portion 21 of the TFT 7, and the first interlayer insulating film 15A and the pedestal portion 21 are formed thereon. Thereby, the pedestal 21 is raised further by the thickness h3 of the gate branch line 16D. In this case, since the height h1 of the pedestal portion 21 is the same as that of the first embodiment, productivity does not decrease.

Embodiment 5

  Next, the display panel 1 of the liquid crystal display device of Embodiment 4 is demonstrated based on FIGS.

  As shown in FIG. 14, in the peripheral region of the display panel 1, spacers 60, 61, 62 are formed on the counter substrate 3 side, the gap with the array substrate 3 is maintained, and the seal member 5 is provided in that portion. ing. At this time, in order to increase the adhesion area of the seal member 5, grooves 63 are formed on the four sides of the organic insulating film 12 of the array substrate 2 as shown in FIG. In this embodiment, as shown in FIGS. 15 and 16, in order to further increase the bonding area of the seal member 5, linear protrusions, that is, protrusions 64 are formed in the grooves 63. The protrusion 64 is manufactured in the same process as the pedestal 21 in the image display area. Further, the same material as that of the pedestal portion 21 is used as the material of the protruding portion 64.

  As a result, the adhesion area increases by the surface area of the protrusion 64, and the adhesion of the seal member 5 is more reliably improved.

  In the present embodiment, the protrusion 64 is formed, but instead of this, as a first modification, a hemispherical protrusion 65 may be projected on a straight line as shown in FIG.

  As a second modification, hemispherical protrusions 66 may be arranged in a staggered manner in the grooves 63 as shown in FIG.

  Further, as a third modification, the protrusions 64 are not provided in the grooves 63 on the organic insulating film 12, but the organic insulating film 12 is coated on the protrusions 64, and the organic matter corresponding to the protrusions 64 is organic. The height h2 of the insulating film may be increased.

Example of change

  In the above embodiment, the liquid crystal display device has been described as being of the IPS system or the like, but the effect of preventing color mixture can be obtained even if the liquid crystal display apparatus is of another lateral electric field system. Even in a liquid crystal display device in which a common electrode (counter electrode) is provided on the counter substrate, the color mixing limit angle is increased and the thickness of the liquid crystal layer in the vicinity of the signal line is reduced to prevent color mixing. Can be obtained.

  In addition, all embodiments that can be implemented by those skilled in the art based on the embodiments of the present invention as appropriate are included in the scope of the present invention as long as they include the gist of the present invention.

  Further, within the scope of the idea of the present invention, those skilled in the art can conceive various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. . For example, those in which the person skilled in the art appropriately added, deleted, or changed the design of the above-described embodiment, or those in which a process was added, omitted, or changed conditions also include the gist of the present invention. As long as it falls within the scope of the present invention.

  In addition, other functions and effects brought about by the correspondence described in the present embodiment are apparent from the description of the present specification, or can be conceived by those skilled in the art from time to time. .

DESCRIPTION OF SYMBOLS 1 ... Display panel, 2 ... Array substrate, 3 ... Opposite substrate, 4 ... Liquid crystal layer, 6 ... Pixel, 7 ... TFT, 10 ... Glass substrate, 12 ... Organic insulating film 13 ... Common electrode 13A ... Second interlayer insulating film 14 ... Pixel electrode 15 ... Signal line 15A ... First interlayer insulating film 15B ... Contact hole DESCRIPTION OF SYMBOLS 16 ... Gate line, 16B ... Gate insulating film, 17 ... Semiconductor layer, 18 ... Alignment film, 19 ... 1st contact hole, 20 ... Common wiring, 21 ... Base part , 22 ... Metal part, 23 ... Second contact hole, 24 ... Projection

Claims (12)

An insulating substrate;
A semiconductor layer on the insulating substrate;
A first insulating film on the semiconductor layer;
The signal line and the metal part on the first insulating film;
A pedestal on the first insulating film;
A first contact hole formed in the first insulating film;
A second insulating film covering the first insulating film, the pedestal part, and the metal part;
A second contact hole formed in the second insulating film;
A transparent electrode on the second insulating film;
With
The second contact hole is formed on an upper surface of the pedestal portion,
The metal part is formed so as to contact the semiconductor layer in the first contact hole and cover the upper surface of the first insulating film and the upper surface of the pedestal part,
The transparent electrode contacts the metal part on the pedestal part through the second contact hole,
The height of the pedestal is 1/2 to 2/3 of the thickness of the second insulating film.
A display device characterized by that. The pedestal is formed from an inorganic material,
The planar shape of the pedestal portion is circular, and the side surface shape is an arc shape.
The display device according to claim 1. The second insulating film has a protrusion on an edge of the second contact hole;
The display device according to claim 1. The center of the first contact hole and the center of the second contact hole are formed at positions shifted in plan view.
The display device according to claim 1. The lower surface diameter of the first contact hole and the lower surface diameter of the second contact hole are substantially the same.
The display device according to claim 1. An insulating substrate;
A first metal line in a peripheral region surrounding the image display region of the insulating substrate;
An inorganic insulating film on the first metal wire;
A second metal wire and a pedestal on the inorganic insulating film;
The inorganic insulating film, the second metal wire, an organic insulating film on the pedestal, and
A conductive layer on the organic insulating film;
With
The height of the pedestal is 1/2 to 2/3 of the thickness of the organic insulating film,
The second metal wire has a laminated structure of at least two layers,
The second metal wire is formed so as to cover at least the upper surface of the pedestal portion,
A third contact hole is formed from the organic insulating film to the second metal line located on the upper surface of the pedestal;
The conductive layer is in contact with the second metal line formed on the upper surface of the pedestal part through the third contact hole,
A display device characterized by that. The conductive layer is a transparent conductive film or a third metal wire having a laminated structure of at least two layers.
The display device according to claim 6. In the region where the third contact hole is formed, the pedestal portion, the second metal line, and the conductive layer are laminated.
The display device according to claim 6. The lower surface diameter of the third contact hole is 2 to 3 μm.
The display device according to claim 6. The pedestal portion has a circular planar shape, and the side surface shape of the pedestal portion is an arc shape.
The display device according to claim 6. The upper surface diameter of the pedestal portion is substantially the same as the lower surface diameter of the third contact hole.
The display device according to claim 6. The organic insulating film has a protrusion on an edge of the third contact hole.
The display device according to claim 6.

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