JP2017174885A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having improved reliability.SOLUTION: In a semiconductor device SA1, at a position adjacent to a first terminal (first lead out of a plurality of leads LD1) to which a digital signal is applied, a second terminal (second lead out of the plurality of leads LD1) which becomes floating potential is arranged. This makes it possible to maintain a digital signal applied to the first terminal even when the first terminal and the second terminal are short circuited. As a result, in the case where a function of monitoring an abnormal condition based on an abnormality detection signal which is the digital signal output from the first terminal is ensured, even when the first terminal and the second terminal are short circuited, the function of monitoring the abnormal condition can be operated without introducing errors.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a semiconductor device, for example, a technique effective when applied to a semiconductor device that handles digital signals.

  Japanese Patent Application Laid-Open No. 2001-94040 (Patent Document 1) describes a technique for making the length of a non-connect lead shorter than the lengths of other leads.

  Japanese Patent Laying-Open No. 2014-165425 (Patent Document 2) describes a technique in which a non-connect lead that is not connected to a wire is arranged next to a connect lead that is connected to a wire.

JP 2001-94040 A JP 2014-165425 A

  In the semiconductor device, for example, a semiconductor chip mounted on a chip mounting portion (tab) and a part of leads of a lead group disposed apart from the chip mounting portion are connected by wires, and the semiconductor chip There is a package structure in which a part of each lead included in the lead group and a wire are sealed with a sealing body made of resin. From the viewpoint of improving the reliability of a semiconductor device having such a package structure, for example, a device for a lead is desired.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  In the semiconductor device according to one embodiment, the potential of the second lead arranged adjacent to the first lead to which the digital signal is applied is a floating potential.

  According to one embodiment, the reliability of a semiconductor device can be improved.

1 is a plan view showing an external configuration of a semiconductor device in a first embodiment. 4 is a circuit block diagram schematically showing a circuit configuration formed in the semiconductor device in the first embodiment. FIG. 3 is a plan view schematically showing the internal structure of the semiconductor device in the first embodiment. FIG. FIG. 4 is a schematic diagram showing a configuration in which, for example, a power supply terminal and a digital signal terminal are arranged adjacent to each other in the first region of FIG. 3. FIG. 6 is a schematic diagram showing a first feature point in the first embodiment. FIG. 10 is a study diagram for explaining the process leading to the second feature point in the first embodiment. It is a figure which shows the structure of a related technique typically. 6 is a diagram schematically showing a second feature point in the first embodiment. FIG. It is a figure which shows the structure of a related technique typically. It is a figure which shows typically the 3rd feature point in a modification. In related technology, it is a schematic diagram which expands and shows the vicinity area | region of one corner | angular part of the chip | tip mounting part which carried out rectangular shape. FIG. 10 is a diagram schematically showing feature points in the second embodiment. FIG. 10 is a plan view showing a manufacturing process for a semiconductor device in a third embodiment. FIG. 14 is a plan view showing a manufacturing step of the semiconductor device following that of FIG. 13; FIG. 15 is a plan view illustrating a manufacturing step of the semiconductor device following that of FIG. 14; FIG. 16 is a plan view illustrating a manufacturing step of the semiconductor device following that of FIG. 15; It is a top view which shows typically the internal structure of the semiconductor device in a modification.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(Embodiment 1)
<Explanation of terms>
In this specification, “electronic component” means a component using electrons, and in particular, a component using electrons in a semiconductor is a “semiconductor component”. An example of the “semiconductor component” is a semiconductor chip. Therefore, the phrase including “semiconductor chip” is “semiconductor component”, and the superordinate concept of “semiconductor component” is “electronic component”.

  In this specification, the “semiconductor device” is a structure including a semiconductor component and an external connection terminal electrically connected to the semiconductor component. For example, the semiconductor component is covered with a sealing body. Means a structure. In particular, the “semiconductor device” is configured to be electrically connected to an external device through an external connection terminal.

  Furthermore, in this specification, the “power transistor” means a unit transistor by connecting a plurality of unit transistors (cell transistors) in parallel (for example, connecting thousands to hundreds of thousands of unit transistors in parallel). This means an aggregate of unit transistors that realizes the function of the unit transistor even at a current larger than the allowable current of. For example, when the unit transistor functions as a switching element, the “power transistor” is a switching element applicable to a current larger than the allowable current of the unit transistor. In particular, in this specification, the term “power transistor” is used as a phrase indicating a general concept including both “power MOSFET” and “IGBT”, for example.

<External configuration of semiconductor device>
FIG. 1 is a plan view showing an external configuration of the semiconductor device SA1 according to the first embodiment. As shown in FIG. 1, the semiconductor device SA1 in the first embodiment has a sealing body MR whose planar shape is a rectangular shape. In FIG. 1, a plurality of leads LD1 (first lead group) are arranged along the first side S1 of the sealing body MR extending in the y direction, and are located on the opposite side of the first side S1. A plurality of leads LD2 (second lead group) are arranged along the second side S2 of the sealing body MR. At this time, a part of each of the plurality of leads LD1 is exposed from the sealing body MR, and a part of each of the plurality of leads LD2 is exposed from the sealing body MR. Specifically, as shown in FIG. 1, each part of the plurality of leads LD1 protrudes from the first side S1 of the sealing body MR, and each part of the plurality of leads LD2 is part of the sealing body MR. It protrudes from the second side S2. As described above, the external appearance of the semiconductor device SA1 in the first embodiment is configured.

<Circuit configuration of semiconductor device>
Next, a circuit configuration formed inside the semiconductor device SA1 in the first embodiment will be described. FIG. 2 is a circuit block diagram schematically showing a circuit configuration formed in the semiconductor device SA1 in the first embodiment. In FIG. 2, the semiconductor device SA1 in the first embodiment includes a circuit block BLK1 and a circuit block BLK2. The circuit block BLK1 and the circuit block BLK2 are connected by a micro isolator ISO that can transmit an electric signal in a non-contact manner. At this time, for example, in the circuit block BLK1, a support IC (Integrated Circuit) for assisting a microcomputer that realizes comprehensive control is formed, and in the circuit block BLK2, for example, based on an instruction from the support IC. Thus, a pre-driver IC that controls the switching operation of the power transistor (external semiconductor device) that is a component of the inverter is formed. In particular, in the first embodiment, an IGBT (Insulated Gate Bipolar Transistor) is assumed as an example of a power transistor (switching element). For example, the semiconductor device SA1 in the first embodiment is used for drive control of an electric motor mounted on an electric vehicle, a hybrid vehicle, or the like. That is, the semiconductor device SA1 in the first embodiment has a control function of a power transistor that constitutes an inverter that controls the rotation of the electric motor, and also includes a microcomputer (ECU) that comprehensively controls the entire vehicle and the inverter. It also has a relay function between them. Specifically, in FIG. 2, the relay function with the microcomputer is realized by the support IC formed in the circuit block BLK1, and is included in the external semiconductor device by the pre-driver IC formed in the circuit block BLK2. The switching operation of the power transistor is realized. That is, the semiconductor device SA1 in the first embodiment is configured to be connectable to, for example, an external semiconductor device including a switching element that constitutes an inverter. The semiconductor device SA1 in the first embodiment is, for example, Thus, the switching operation of the power transistor that constitutes the switching element is controlled.

  First, the circuit configuration of the circuit block BLK1 will be described. In FIG. 2, the circuit block BLK1 has a control unit CU1 that functions as a central processing unit (MCU). For example, a power supply potential is supplied from the terminal VCC1 to the control unit CU1. For example, the power supply potential supplied from the terminal VCC1 to the control unit CU1 is 3.3V or 5V. On the other hand, the ground potential (reference potential) is supplied from the terminal GND1 to the internal circuit of the circuit block BLK1.

  Further, the circuit block BLK1 has a terminal INA, and a non-inverted logic (Active High) gate drive signal is input from the terminal INA to the control unit CU1 in the circuit block BLK1. For example, when the gate drive signal input from the terminal INA is “H”, the control unit CU1 outputs a signal for turning on the IGBT to the circuit block BLK2, and the gate drive signal input from the terminal INA is “L”. In this case, the control unit CU1 outputs a signal for turning off the IGBT to the circuit block BLK2. However, when the gate drive signal input from the terminal INB described later is “H” or “open”, the control unit CU1 outputs a signal for turning off the IGBT regardless of the input from the terminal INA described later. Output to block BLK2. As shown in FIG. 2, the terminal INA is pulled down to the ground (GND) through a resistance element of about 100 kΩ inside the circuit block BLK1, and when the terminal INA is “open”, the control unit CU1 , Outputs a signal for turning off the IGBT to the circuit block BLK2.

  Furthermore, the circuit block BLK1 has a terminal INB, and an inverted logic (Active Low) gate drive signal is input from the terminal INB to the control unit CU1 in the circuit block BLK1. For example, when the gate drive signal input from the terminal INB is “L”, the control unit CU1 outputs a signal for turning on the IGBT to the circuit block BLK2, and the gate drive signal input from the terminal INB is “H”. In this case, the control unit CU1 outputs a signal for turning off the IGBT to the circuit block BLK2. However, when the gate drive signal input from the terminal INA is “L” or “open”, the control unit CU1 outputs a signal for turning off the IGBT to the circuit block BLK2 regardless of the input from the terminal INB. Output to. As shown in FIG. 2, the terminal INB is pulled up to a power supply potential through a resistance element of about 100 kΩ inside the circuit block BLK1, and when the terminal INB is “open”, the control unit CU1 A signal for turning off the IGBT is output to the circuit block BLK2.

  Subsequently, the circuit block BLK1 has a terminal FO, and a fault non-inverted output signal is output from the terminal FO. Specifically, the terminal FO is an open drain output terminal indicating a fault state (abnormal state), and an abnormality of an IGBT included in an external semiconductor device (not shown) provided outside the semiconductor device SA1 is detected. In this case, an “H” digital signal (abnormality detection signal) is output from the terminal FO. On the other hand, when no abnormality of the IGBT is detected, a digital signal of “L” is output from the terminal FO.

  The circuit block BLK1 has a terminal FOB, and a fault inversion output signal is output from the terminal FOB. Specifically, the terminal FOB is an open drain output terminal indicating a fault state (abnormal state), and a digital signal obtained by inverting the logic of the digital signal output from the terminal FO is output from the terminal FOB. For example, when an abnormality of an IGBT included in an external semiconductor device provided outside the semiconductor device SA1 is detected, an “L” digital signal (abnormality detection signal) is output from the terminal FOB. On the other hand, when no abnormality of the IGBT is detected, a digital signal of “H” is output from the terminal FOB.

  Further, the circuit block BLK1 has a terminal TMP, and a PWM signal (digital signal) corresponding to the temperature of the IGBT is output from the terminal TMP. For example, a PWM signal is output that compares the triangular wave generated by charging / discharging the capacitive element with a constant current and the forward voltage (VF) of the temperature detection diode that detects the temperature of the IBGT. In this case, PWM signals having different duty ratios are output from the terminal TMP according to the temperature of the IGBT. Therefore, the duty ratio of the PWM signal includes information related to the temperature of the IGBT.

  Next, the circuit configuration of the circuit block BLK2 will be described. In FIG. 2, the circuit block BLK2 has a control unit CU2 that functions as a central processing unit (MCU). For example, a power supply potential is supplied from the terminal VCC2 to the control unit CU1. For example, the power supply potential supplied from the terminal VCC2 to the control unit CU2 is 15V. On the other hand, the ground potential (reference potential) is supplied from the terminal GND2 to the internal circuit of the circuit block BLK2.

  Further, the circuit block BLK2 has a regulator REG, and the regulator REG inputs the power supply potential supplied from the terminal VCC2, and generates a 5V power supply. The 5V power generated by the regulator REG is supplied to the control unit CU2 and is also output to the outside from the terminal VREG. The 5V power source output from the terminal VREG can be used for an external circuit that detects the temperature of the IGBT, for example. Note that, in order to stabilize the voltage inside the circuit block BLK2, the terminal VREG is connected to a capacitor (capacitor) even when the terminal VREG is not connected to an external load.

  Subsequently, in FIG. 2, the circuit block BLK2 includes a gate driver GD. The gate driver GD has a function of controlling the switching operation of an IGBT (external semiconductor device) connected to the outside. Specifically, the gate driver GD is electrically connected to the gate electrode of the IGBT, and is configured to control the on / off operation of the IGBT by controlling the gate voltage applied to the gate electrode of the IGBT. Has been. In particular, based on the gate drive signals input to the terminal INA and the terminal INB of the circuit block BLK1, the control unit CU1 of the circuit block BLK1 transmits the IGBT to the control unit CU2 of the circuit block BLK2 via the micro isolator ISO. A control signal related to the switching control is output. Thereafter, the control unit CU2 of the circuit block BLK2 controls the gate driver GD based on this control signal. As a result, the gate driver GD finally performs an on / off operation (switching operation) of the IGBT based on an instruction from the control unit CU2.

  Next, the circuit block BLK2 has a mirror clamp part MC. The mirror clamp MC has a function of preventing the IGBT from turning on and is electrically connected to the gate electrode of the IGBT. The IGBT self-turn-on is a phenomenon described below. That is, when the IGBT is turned off and a large voltage is applied to the collector of the IGBT, a current is passed from the gate electrode to the ground via the gate resistor in order to charge the parasitic capacitance between the collector and the gate electrode existing in the IGBT. Flowing. As a result, the potential of the gate electrode rises, and although the IGBT is turned off, the gate potential is increased based on the parasitic capacitance, so that the IGN is turned on. This phenomenon is a phenomenon called IGBT self-turn-on. Therefore, in the mirror clamp part MC, when the IGBT is turned off, the gate electrode of the IGBT and the ground are connected with a low impedance separately from the gate driver GD, thereby suppressing the potential increase of the gate electrode. Self-turn-on is suppressed.

  As shown in FIG. 2, the circuit block BLK2 has a soft turn-off unit STO. The soft turn-off unit STO is configured to forcibly and slowly turn off the IGBT when, for example, an abnormality of the IGBT typified by overcurrent or overheating is detected (when a fault state is detected). That is, when the IGBT is suddenly turned off when an abnormality such as an overcurrent occurs, an excessive voltage is applied between the collector and the emitter of the IGBT, which may damage the IGBT. Therefore, for example, when an abnormality of the IGBT is detected, the soft turn-off part STO is used without using the gate driver GD or the mirror clamp part MC having a high current driving capability, so that it is accumulated in the gate electrode of the IGBT. The electric charge is discharged slowly. Specifically, the soft turn-off unit STO is configured to gently discharge the charge accumulated in the gate electrode of the IGBT by interposing a high-resistance resistance element between the gate electrode and the ground. .

  Subsequently, the circuit block BLK2 includes a current detection unit CS. For example, an IGBT chip on which an IGBT is formed is formed with a main IGBT that functions as a switching element of an inverter and a detection IGBT for detecting an overcurrent. That is, the detection IGBT is provided for detecting an overcurrent flowing between the collector and the emitter of the main IGBT. That is, the detection IGBT is provided to detect an overcurrent flowing between the collector and the emitter of the main IGBT and protect the main IGBT from being destroyed by the overcurrent. In this detection IGBT, the collector of the detection IGBT is electrically connected to the collector of the main IGBT, and the gate electrode of the detection IGBT is electrically connected to the gate electrode of the main IGBT. The sense emitter of the detection IGBT is provided separately from the emitter of the main IGBT. The sense emitter of this detection IGBT is connected to the current detection unit CS provided in the circuit block BLK2 shown in FIG. The current detector CS is configured to detect the collector-emitter current of the main IGBT based on the output of the sense emitter of the detection IGBT. When the current detection unit CS detects an overcurrent, the control unit CU2 controls the gate driver GD to cut off the gate voltage applied to the gate electrode of the main IGBT, thereby protecting the main IGBT. ing.

  Specifically, the detection IGBT is used as a current detection element for preventing an overcurrent from flowing through the main IGBT due to a load short circuit or the like. For example, the current ratio between the current flowing through the main IGBT and the current flowing through the detection IGBT is designed to be main IGBT: detection IGBT = 1000: 1. That is, when a current of 200 A flows through the main IGBT, a current of 200 mA flows through the detection IGBT.

  Here, in an actual application, a sense resistance element electrically connected to the sense emitter of the detection IGBT is externally attached, and the voltage at both ends of the sense resistance element is fed back to the current detection unit CS. The control unit CU2 connected to the current detection unit cuts off the power supply when the voltage across the sense resistor becomes equal to or higher than the set voltage. That is, when the current flowing through the main IGBT becomes an overcurrent, the current flowing through the detection IGBT also increases. As a result, the current flowing through the sense resistor also increases, so that the voltage across the sense resistor increases, and when this voltage exceeds the set voltage, the current flowing through the main IGBT is in an overcurrent state. I can understand that.

  When an overcurrent of the IGBT is detected by the current detection unit CS configured as described above (when an abnormality of the IGBT is detected), the control unit CU2 of the circuit block BLK2 → the microisolator ISO → the control unit of the circuit block BLK1 An “H” digital signal (abnormality detection signal) is output from the terminal FO via the CU1.

  Next, the circuit block BLK2 includes a temperature detection unit TS. For example, a temperature detection diode is also formed in the IGBT chip on which the IGBT is formed, and this temperature detection diode is provided for detecting the temperature of the IGBT (in general terms, the temperature of the semiconductor chip). . That is, the temperature of the IGBT is detected by changing the voltage of the temperature detecting diode according to the temperature of the IGBT. This temperature detection diode has a pn junction formed by introducing impurities of different conductivity types into polysilicon, and has a cathode (cathode) and an anode (anode).

  The temperature detection unit TS is electrically connected to the above-described temperature detection diode. This temperature detection circuit is configured to indirectly detect the temperature of the IGBT based on the output between the cathode and anode of the temperature detection diode. A temperature detection diode composed of a pn junction diode has a characteristic that when a forward voltage of a certain value or more is applied, the forward current flowing through the temperature detection diode abruptly increases. The voltage value at which the forward current starts to flow suddenly changes depending on the temperature, and this voltage value decreases as the temperature rises. Therefore, in the first embodiment, this characteristic of the temperature detection diode is used. That is, the temperature can be indirectly monitored by passing a constant current through the temperature detection diode and measuring the voltage value across the temperature detection diode. In an actual application, a PWM signal that compares the voltage value (temperature signal) of the temperature detection diode thus measured with a triangular wave is output. In this case, after a PWM signal (digital signal, abnormality detection signal) having a different duty ratio is output from the temperature detection unit TS of the circuit block BLK2 according to the temperature of the IGBT, it passes through the microisolator ISO and the circuit block BLK1. , And output from the terminal TMP of the circuit block BLK1.

<Internal structure of semiconductor device>
Next, the internal structure of the semiconductor device SA1 in the first embodiment will be described. FIG. 3 is a plan view schematically showing the internal structure of the semiconductor device SA1 in the first embodiment. As shown in FIG. 3, the semiconductor device SA1 in the first embodiment is arranged with a plurality of leads LD1 (first lead group) arranged side by side in the y direction, and spaced apart from the plurality of leads LD1 in the x direction. And a plurality of leads LD2 (second lead group) arranged side by side in the y direction. At this time, the plurality of leads LD1 include leads having different lengths. In particular, among the plurality of leads LD1, the lead having the first length is most frequently included. Similarly, the plurality of leads LD2 include leads having different lengths. In particular, among the plurality of leads LD2, the lead having the first length is most frequently included. Note that the number of the plurality of leads LD1 is equal to the number of the plurality of leads LD2.

  Next, as shown in FIG. 3, the chip mounting portion TAB1 having a rectangular planar shape and the chip mounting portion TAB2 having a rectangular planar shape are sandwiched between the plurality of leads LD1 and the plurality of leads LD2. Has been placed. Specifically, the chip mounting portion TAB1 is disposed closer to the plurality of leads LD1 than the chip mounting portion TAB2. In other words, the chip mounting part TAB2 is arranged closer to the plurality of leads LD2 than the chip mounting part TAB1. In particular, in the first embodiment, the planar size of the chip mounting portion TAB1 is smaller than the planar size of the chip mounting portion TAB2.

  For example, as shown in FIG. 3, most of the leads LD1 are spaced apart from the chip mounting portion TAB1, but some of the leads LD1 of the plurality of leads LD1 are not mounted on the chip mounting portion TAB1. It is formed so that it can be connected integrally with. Similarly, most of the leads LD2 are spaced apart from the chip mounting portion TAB2, but some of the leads LD2 of the plurality of leads LD2 are integrally connected to the chip mounting portion TAB1. Is formed.

  On the chip mounting portion TAB1, for example, a rectangular semiconductor chip CHP1 is mounted via an adhesive (not shown). On the other hand, a rectangular semiconductor chip CHP2 is mounted on the chip mounting portion TAB2, for example, via an adhesive (not shown). At this time, as shown in FIG. 3, the semiconductor chip CHP1 is included in the chip mounting portion TAB1 in a plane, and the semiconductor chip CHP2 is included in the chip mounting portion TAB2 in a plane. The planar size of the semiconductor chip CHP1 is smaller than the planar size of the semiconductor chip CHP2.

  An integrated circuit is formed inside the semiconductor chip CHP1, and specifically, a circuit element (including a part of the micro isolator ISO and a terminal made of the lead LD1) constituting the circuit block BLK1 shown in FIG. Except) is formed. On the other hand, an integrated circuit is also formed inside the semiconductor chip CHP2, specifically, a circuit element (including a part of the micro isolator ISO and a lead LD2) that constitutes the circuit block BLK2 shown in FIG. Except the terminal). As shown in FIG. 3, a plurality of pads PD1 are formed on the surface of the semiconductor chip CHP1, and a plurality of pads PD2 are formed on the surface of the semiconductor chip CHP2. Here, as shown in FIG. 3, the pad PD1 formed on the semiconductor chip CHP1 is electrically connected to a part of the leads LD1 of the leads LD1 by wires W. Similarly, the pad PD2 formed on the semiconductor chip CHP2 is electrically connected to some leads LD2 of the plurality of leads LD2 by wires W. Furthermore, a part of the pads PD1 formed on the semiconductor chip CHP1 and a part of the pads PD2 formed on the semiconductor chip CHP2 are also electrically connected by wires W. As a result, the circuit elements (including the components of the microisolator ISO) of the circuit block BLK1 formed on the semiconductor chip CHP1 and the circuit elements (the components of the microisolator ISO) of the circuit block BLK2 formed on the semiconductor chip CHP2 Are also connected in a non-contact manner.

  In the semiconductor device SA1 according to the first embodiment, the maximum voltage applied to the semiconductor chip CHP1 side (circuit block BLK1 side in FIG. 2) is about several volts. On the other hand, when an IGBT is connected to the semiconductor device SA1 in the first embodiment, the maximum voltage applied to the semiconductor chip CHP2 side (the circuit block BLK2 side in FIG. 2) is about several hundred volts to several thousands volts. In the first embodiment, in consideration of this, non-contact electric signal transmission by a micro isolator ISO using inductive coupling between inductors is employed. Furthermore, in the first embodiment, it is necessary to ensure the breakdown voltage of the lead LD1 electrically connected to the semiconductor chip CHP1 and the lead LD2 electrically connected to the semiconductor chip CHP2, and therefore, as shown in FIG. As described above, a so-called SOP (Small Outline Package) structure (see FIG. 1) in which a plurality of leads LD1 and a plurality of leads LD2 are arranged to face each other is employed.

<Characteristics in Embodiment 1>
Next, feature points in the first embodiment will be described. First, as shown in FIG. 1, in the semiconductor device SA1 in the first embodiment, the number of leads LD1 protruding from the side S1 is equal to the number of leads LD2 protruding from the side S2. At this time, as shown in FIG. 2, the semiconductor device SA1 in the first embodiment is provided with a circuit block BLK1 and a circuit block BLK2. As apparent from FIG. 2, the number of components of the circuit block BLK2 is larger than the number of components of the circuit block BLK1, and therefore, the number of leads LD2 used in connection with the circuit block BLK2 is The number of leads LD1 used in connection with BLK1 is larger. In other words, the number of leads LD1 used in connection with the circuit block BLK1 is smaller than the number of leads LD2 used in connection with the circuit block BLK2.

  This means that the number of leads LD2 protruding from the side S2 in FIG. 1 is determined in accordance with the number of leads LD2 used by being connected to the circuit block BLK2. As shown in FIG. 1, in the semiconductor device SA1 in the first embodiment, considering that the number of leads LD1 protruding from the side S1 is equal to the number of leads LD2 protruding from the side S2, the side S1 This means that there are many unused leads that are not connected to the circuit block BLK1 in addition to the leads LD1 that are used by being connected to the circuit block BLK1. That is, in the first embodiment, the number of leads LD1 that are actually used among the plurality of leads LD1 protruding from the side S1 in FIG. 1 is small.

  Therefore, the basic idea in the first embodiment is that the unused lead that is not actually used among the plurality of leads LD1 protruding from the side S1 is effectively used to improve the reliability of the semiconductor device SA1. It is an idea. In other words, in the first embodiment, in order to improve the reliability of the semiconductor device SA1, the configuration related to the unused lead is devised. Below, the point with respect to the structure relevant to an unused lead is demonstrated.

  The first feature point in the first embodiment is, for example, that a second terminal (plurality of floating potentials) at a position adjacent to a first terminal (first lead of the plurality of leads LD1) to which a digital signal is applied. The second lead of the leads LD1 is disposed. Thereby, for example, even when the first terminal and the second terminal are short-circuited, the digital signal applied to the first terminal is maintained. As a result, for example, when the digital signal output from the first terminal is an abnormality detection signal and the function of monitoring an abnormal state is realized based on the abnormality detection signal, even if the first terminal and the second terminal Even if the terminal is short-circuited, the function for monitoring an abnormal state can be normally operated without malfunction. From this, according to the 1st feature point in this Embodiment 1, a reliable abnormality monitoring function is realizable.

  Specifically, the first feature point in the first embodiment will be described by paying attention to a plurality of leads LD1 (terminal VCC1, terminal NC1, terminal TMP) existing in the area AR of FIG.

  FIG. 4 is a schematic diagram showing a configuration in which, for example, the terminal VCC1 and the terminal TMP are arranged adjacent to each other in the area AR of FIG. As shown in FIG. 4, the terminal VCC1 is electrically connected to the pad PD1A of the semiconductor chip CHP1 mounted on the chip mounting portion TAB1 by the wire W1A. On the other hand, the terminal TMP is electrically connected to the pad PD1B of the semiconductor chip CHP1 mounted on the chip mounting portion TAB1 by the wire W1B.

  At this time, a power supply potential (for example, 5 V) is applied to the terminal VCC1. Further, a PWM signal (digital signal) output from the temperature detection unit TS shown in FIG. 2 is applied to the terminal TMP. Therefore, for example, in FIG. 4, when the terminal VCC1 and the terminal TMP are short-circuited (short-circuited), the PWM signal is not output from the terminal TMP. This means that a temperature abnormality based on the PWM signal cannot be detected. Therefore, for example, as shown in FIG. 4, in the configuration in which the terminal VCC1 and the terminal TMP are arranged adjacent to each other, a malfunction occurs when the adjacent terminals VCC1 and the terminal TMP are short-circuited (short-circuited). The fear increases.

  Therefore, in the first embodiment, the device shown in FIG. 4 is devised. Specifically, FIG. 5 is a schematic diagram showing the first feature point in the first embodiment. In FIG. 5, the first characteristic point in the first embodiment is that a terminal NC1 that is a floating potential is arranged between the terminal VCC1 and the terminal TMP. That is, the first feature point in the first embodiment is that the terminal NC1 that becomes a floating potential at a position adjacent to the terminal TMP to which the PWM signal (digital signal) output from the temperature detection unit TS shown in FIG. 2 is applied. The point is to place. Specifically, in FIG. 5, as an example of the terminal NC1 having a floating potential, the terminal NC1 is configured from a non-connect terminal (non-connect lead) that is not connected to the semiconductor chip. However, as another example of the terminal NC1 having a floating potential, a terminal electrically connected to a so-called “dummy pad” that is not electrically connected to the integrated circuit formed in the semiconductor chip can be cited. . In either case, since the potential of the terminal NC1 becomes a floating potential, even if the terminals NC1 and TMP adjacent to each other are short-circuited, the PWM signal output from the temperature detection unit TS shown in FIG. The (digital signal) itself can be maintained and output from the terminal TMP. This means that even if the terminals NC1 and TMP adjacent to each other are short-circuited, temperature abnormality detection based on the PWM signal can be normally performed. As a result, according to the first embodiment, a highly reliable abnormality monitoring function can be realized.

  In this specification, for example, even if a first terminal to which a digital signal is applied and a second terminal arranged at a position adjacent to the first terminal are short-circuited, the first terminal is applied to the first terminal. The potential applied to the second terminal when the digital signal is maintained is referred to as a “floating potential”. In this specification, “digital signal is maintained” means that the value of the digital signal is not inverted when the first terminal and the second terminal are short-circuited. For example, “digital signal is maintained” means that “H” included in the digital signal is not inverted to “L” even when the first terminal and the second terminal are short-circuited, and It means that “L” included in the digital signal is not inverted to “H”.

  In addition, in FIG. 5, the configuration example in which the terminal NC1 that becomes the floating potential is arranged between the terminal VCC1 to which the power supply potential (for example, +5 V) is applied and the terminal TMP to which the digital signal is applied has been described. However, the first feature point in the first embodiment is not limited to this configuration. That is, according to the first feature point in the first embodiment, for example, a ground terminal to which a ground potential (0 V) is applied, and a terminal (first terminal) to which a digital signal (for example, PWM signal) is applied. It can also be embodied as a configuration in which a terminal (second terminal) having a floating potential is arranged between the two.

  For example, when a ground terminal and a terminal to which a digital signal (PWM signal) is applied (first terminal) are arranged adjacent to each other, a terminal to which the ground terminal and a digital signal (PWM signal) are applied (first terminal) When a short circuit occurs, no PWM signal is output from the terminal (first terminal).

  On the other hand, a terminal (second terminal) having a floating potential is arranged between the ground terminal and a terminal (first terminal) to which a digital signal (PWM signal) is applied. In this case, since the potential of the terminal (second terminal) is a floating potential, even if the adjacent terminal (first terminal) and the terminal (second terminal) are short-circuited, the PWM signal The (digital signal) itself can be maintained and output from the terminal (first terminal).

  From the above, the first feature point in the first embodiment can be expressed as a technical idea summarized as follows. That is, the semiconductor device SA1 has a fixed potential terminal (fixed potential lead) to which a fixed potential is applied, and the second terminal that is a floating potential in a plan view is a first terminal to which a digital signal is applied. It is arranged at a position sandwiched between the fixed potential terminals. At this time, the fixed potential is a power supply potential or a ground potential. For example, when the fixed potential is the ground potential, the fixed potential terminal may be electrically connected to the chip mounting portion. it can.

  Subsequently, the second feature point in the first embodiment is premised on the first feature point in which a second terminal having a floating potential is arranged at a position adjacent to the first terminal to which a digital signal is applied. And the 2nd feature point in this Embodiment 1 is that the length of the 2nd terminal arranged in the position away from the semiconductor chip rather than the 1st terminal is shorter than the length of the 1st terminal, and the following And the points shown in Here, the following points indicate that the plurality of terminals (first terminal group) including the first terminal and the second terminal include the most terminals of the first length, and the second terminals The length is a point that is a second length shorter than the first length. Further, the second feature point in the first embodiment further includes the following points. That is, in the second feature point in the first embodiment, the first terminal has a wide portion, and the wide portion has a distance between the wide portion and the second terminal equal to or greater than a design allowable distance between the leads. On the other hand, when the length of the second terminal is assumed to be the first length, the distance between the wide portion and the second terminal includes a shape that is shorter than the design allowable distance between the leads. .

  According to the second feature point of the first embodiment as described above, the length of the first wire connecting the wide portion of the first terminal and the pad of the semiconductor chip can be shortened, and the first terminal Connection reliability between the wide portion and the first wire can be improved.

  This point will be specifically described below. FIG. 6 is an examination diagram for explaining the process leading to the second feature point (configuration shown in the region BR shown in FIG. 3) in the first embodiment.

  First, in FIG. 6, a terminal FO (lead LD1) to which a digital signal is applied, a terminal NC2A (lead LD1) that is a non-connect terminal, and a terminal GND1 (lead LD1) to which a ground potential is applied are in the y direction. It is arranged to line up. Specifically, the terminal NC2A is disposed on the left side of the terminal FO, and is disposed at a position where the distance between the terminal NC2A and the semiconductor chip CHP1 is larger than the distance between the terminal FO and the semiconductor chip CHP1. ing. Further, the terminal GND1 is disposed on the left side of the terminal NC2A, and is disposed at a position where the distance between the terminal GND1 and the semiconductor chip CHP1 is larger than the distance between the terminal NC2A and the semiconductor chip CHP1. . The terminal GND1 is connected to the chip mounting part TAB1, and the semiconductor chip CHP1 is mounted on the chip mounting part TAB1.

  Here, focusing on the terminal FO shown in FIG. 6, for example, the terminal FO exists at a position relatively distant from the semiconductor chip CHP1. For this reason, the length of the wire W connecting the terminal FO and the pad PD1 of the semiconductor chip CHP1 is increased. An increase in the length of the wire W means an increase in material cost. Moreover, when the length of the wire W becomes long, a wire flow is likely to occur due to the injection pressure of the resin in the sealing process (molding process), which may cause a short circuit between adjacent wires. . Therefore, it is desirable to make the wire W connecting the terminal FO and the pad PD1 of the semiconductor chip CHP1 as short as possible from the viewpoint of reducing the manufacturing cost and improving the reliability of the semiconductor device.

  Therefore, a configuration shown in the related art shown in FIG. 7 is being studied. Note that the “related technology” in the present specification is a technology that has a problem newly found by the inventor and is not a known prior art, but is a prerequisite technology for a new technical idea (unknown technology). This is a technique described with the intention of

  FIG. 7 is a diagram schematically illustrating the configuration of the related art. In the related technique shown in FIG. 7, the terminal FO is formed with a wide portion WP1 so as to shorten the distance between the semiconductor chip CHP1 and the terminal FO. In the wide portion WP1 of the terminal FO, the terminal FO and the wire are formed. W is connected. Specifically, in FIG. 7, a connection point P1 between the wide portion WP1 of the terminal FO and the wire W is shown. Accordingly, according to the related technique shown in FIG. 7, the length of the wire W connecting the terminal FO and the pad PD1 of the semiconductor chip CHP1 can be shortened as compared with the configuration shown in FIG.

  However, since the inventor newly found that there is room for improvement in the wire bonding process in which the terminal FO and the pad PD1 of the semiconductor chip CHP1 are connected by the wire W in the related technique shown in FIG. Will be described.

  In FIG. 7, in the wire bonding step, the leads LD <b> 1 and the semiconductor chip CHP <b> 1 are connected by the wires W while the lead frame is pressed by a clamper (pressing jig) CLP. At this time, in order to avoid interference between the clamper CLP and the wire bonding tool (capillary), as shown in FIG. 7, a minimum distance R from the connection point P1 between the wire W and the wide portion WP1 to the pressing position of the clamper CLP is set. It is necessary to secure. On the other hand, it is necessary to secure the design allowable distance DL1 between the wide portion WP1 of the terminal FO and the terminal NC2A, for example, in order to prevent a short circuit failure. That is, in the related technique shown in FIG. 7, it is necessary to secure the minimum distance R and also secure the design allowable distance DL1. As a result, as shown in FIG. 7, in the related technique, the area where the wide portion WP1 can be pressed by the clamper CLP at the minimum distance R from the connection point P1 becomes small. Therefore, the clamp of the wide portion WP1 by the clamper CLP is reduced. Is insufficient. This means that in the related art, rattling of the wide portion WP1 cannot be sufficiently suppressed, thereby causing a reduction in connection strength between the wide portion WP1 of the terminal FO and the wire W. Become. That is, in the related art, it is difficult to improve the connection strength between the wide portion WP1 of the terminal FO and the wire W as a result of insufficient pressing of the wide portion WP1 by the clamper CLP.

  Therefore, in the first embodiment, as shown in FIG. 8, in order to shorten the length of the wire W that connects the terminal FO and the pad PD1 of the semiconductor chip CHP1, the wide portion WP2 is provided in the terminal FO. As a premise, a device for improving the connection strength between the wide portion WP2 of the terminal FO and the wire W is provided. Below, this device point is demonstrated.

  FIG. 8 is a diagram schematically showing the second feature point in the first embodiment. In FIG. 8, the second feature point in the first embodiment is that the wide portion of the terminal FO is also formed in the space created by shortening the length of the terminal NC2A which is a non-connect terminal and shortening the length of the terminal NC2A. The WP2 is configured to spread.

  First, also in the first embodiment, as shown in FIG. 8, a wide portion WP2 is provided in the terminal FO, and a connection point P1 with the wire W is formed in the wide portion WP2. As a result, also in the first embodiment, the length of the wire W connected between the terminal FO and the pad PD1 of the semiconductor chip CHP1 is made shorter than in the case where the wide portion WP2 is not provided in the terminal FO. Can do. As a result, according to the first embodiment, it is possible to reduce the manufacturing cost by shortening the length of the wire W. Further, according to the first embodiment, by reducing the length of the wire W, the wire flow can be suppressed. As a result, the occurrence of a short circuit between adjacent wires can be suppressed, whereby the semiconductor device Reliability can be improved.

  In the first embodiment, the length of the terminal NC2A, which is a non-connect terminal, is shortened, and the wide portion WP2 of the terminal FO is widened in a space created by shortening the length of the terminal NC2A. ing. That is, in the first embodiment, the length of the terminal NC2A that is a non-connect terminal adjacent to the terminal FO is shortened. Specifically, for example, if the plurality of leads LD1 include the largest number of leads having the first length, in the first embodiment, as shown in FIG. 8, a terminal NC2A which is a non-connect terminal Is set to a second length shorter than the first length. In particular, the terminal NC2A which is a non-connect terminal can be the lead having the shortest length among the leads LD1 included in the plurality of leads LD1.

  As a result, as shown in FIG. 8, according to the first embodiment, the wide portion WP2 of the terminal FO is widened in a space created by shortening the length of the terminal NC2A which is a non-connect terminal. can do. That is, the second feature point in the first embodiment is to effectively utilize the space created by shortening the length of the terminal NC2A which is a non-connect terminal. In this regard, according to the first embodiment, as shown in FIG. 8, while ensuring a minimum distance R from the connection point P1 between the wide portion WP2 of the terminal FO and the wire W to the pressing position of the clamper CLP. The design allowable distance DL1 between the wide portion WP1 of the terminal FO and the terminal NC2A can also be ensured. Furthermore, in the first embodiment, as shown in FIG. 8, the area where the wide portion WP1 can be pressed by the clamper CLP at a minimum distance R from the connection point P1 is expanded, so that the wide portion WP2 of the terminal FO is expanded. Can be sufficiently suppressed by the clamper CLP. From this, according to the second feature point in the first embodiment, it means that rattling of the wide portion WP2 is sufficiently suppressed, and the wide portion WP2 of the terminal FO can be firmly fixed by the clamper CLP. This means that stable wire bonding can be performed, whereby the connection strength between the wide portion WP2 of the terminal FO and the wire W can be improved. That is, according to the second feature point in the first embodiment, the minimum distance R for avoiding the interference between the clamper CLP and the wire bonding tool (capillary) is secured, and the wide portion WP1 of the terminal FO and the terminal The wide portion WP2 can be sufficiently pressed by the clamper CLP while ensuring the design allowable distance DL1 with the NC 2A. As described above, the second characteristic point of the first embodiment is that the wide portion WP2 of the terminal FO is configured to be widened in a space created by shortening the length of the terminal NC2A that is a non-connect terminal. With this second feature point, it is possible to securely fix the wide portion WP2 by the clamper CLP while securing both the minimum distance R and the design allowable distance DL1.

  In other words, in the related art configuration in which the length of the terminal NC2A that is a non-connect terminal is not shortened, the design allowable distance DL1 cannot be secured if the wide portion WP2 of the terminal FO is widened so as to approach the terminal NC2A. is there. That is, in the wide portion WP2, the distance between the wide portion WP2 and the terminal NC2A is not less than the design allowable distance DL1 between the leads, while the length of the terminal NC2A is not shortened. It can be said that the distance between the wide portion WRP2 and the terminal NC2A in a case where it is assumed that the lead LD1 is included in the same length as the first length included in a large number includes a shape that is shorter than the design allowable distance DL1 between the leads. .

  From the above, according to the second feature point in the first embodiment, the length of the wire W connected between the terminal FO and the pad PD1 of the semiconductor chip CHP1 can be shortened, and the terminal FO. The connection strength between the wide portion WP1 and the wire W can be improved. Therefore, according to the second feature point in the first embodiment, the manufacturing cost of the semiconductor device SA1 can be reduced and the reliability of the semiconductor device SA1 can be improved.

<Modification>
For example, in the second feature point in the first embodiment described above, as shown in FIG. 8, the terminal NC2A, which is a non-connect terminal, is located farther from the semiconductor chip CHP1 than the terminal FO to which the digital signal is applied. The description is based on the premise of the arrangement to be arranged. However, in the semiconductor device SA1 in the first embodiment, a configuration in which the non-connect terminal adjacent to the terminal FO to which the digital signal is applied is disposed at a position closer to the semiconductor chip CHP1 than the terminal FO can be employed. In the case of this configuration, the semiconductor device SA1 in the modification of the first embodiment has the third feature point described below. Specifically, the third feature point will be described.

  FIG. 9 is a diagram schematically illustrating the configuration of the related art. In the related technique shown in FIG. 9, the terminal NC2B which is a non-connect terminal adjacent to the terminal FO is arranged at a position closer to the semiconductor chip CHP1 than the terminal FO. At this time, when the length of the terminal NC2B, which is a non-connect terminal, is equal to or greater than the first length of the terminal most frequently included in the plurality of terminals (the plurality of leads LD1), the terminal FO and the terminal Since it is necessary to ensure a design allowable distance from the NC 2B, it is difficult to extend the extending portion in the y direction from the terminal FO toward the semiconductor chip CHP1. Therefore, in the related technique shown in FIG. 9, the terminal NC2B adjacent to the terminal FO is arranged at a position closer to the semiconductor chip CHP1 than the terminal FO, and extends in the y direction from the terminal FO toward the semiconductor chip CHP1. Due to a synergistic factor with the point where it is difficult to provide the extending portion, the length of the wire W connecting the terminal FO and the pad PD1 of the semiconductor chip CHP1 cannot be shortened. An increase in the length of the wire W means an increase in material cost. Moreover, when the length of the wire W becomes long, a wire flow is likely to occur due to the injection pressure of the resin in the sealing process, which may cause a short circuit between adjacent wires. Therefore, in the related technique shown in FIG. 9, there is room for improvement from the viewpoint of reducing the manufacturing cost and improving the reliability of the semiconductor device.

  Therefore, in this modified example, as shown in FIG. 10, in order to shorten the length of the wire W that connects the terminal FO and the pad PD1 of the semiconductor chip CHP1, the non-contact position is closer to the semiconductor chip CHP1 than the terminal FO. On the premise that the terminal NC2B which is a connection terminal is provided, a contrivance is made to shorten the length of the wire W. Below, this device point is demonstrated.

  FIG. 10 is a diagram schematically illustrating the third feature point in the present modification. In FIG. 10, the third feature point in the present modification is that the length of the terminal NC2B, which is a non-connect terminal, is shortened, and the space created by shortening the length of the terminal NC2B is used to change the semiconductor chip from the terminal FO. It is in the point which provided the extending | stretching part LP extended in ay direction toward CHP1. That is, in this modification, as shown in FIG. 10, the length of the terminal NC2B which is a non-connect terminal is shortened. Specifically, for example, if the plurality of leads LD1 include the largest number of leads having the first length, in this modification, as shown in FIG. 10, the length of the terminal NC2B which is a non-connect terminal is used. The second length is shorter than the first length. In particular, the terminal NC2B which is a non-connect terminal can be the lead having the shortest length among the leads LD1 included in the plurality of leads LD1.

  As a result, according to the present modification, a space is generated by shortening the length of the terminal NC2B. Therefore, using this space, an extending portion extending in the y direction from the terminal FO toward the semiconductor chip CHP1. LP can be provided. This is because, in this modification, a space is generated by shortening the length of the terminal NC2B. Therefore, even if the extending portion LP extending in the y direction from the terminal FO toward the semiconductor chip CHP1 is provided, this extension This is because a design allowable distance between the portion LP and the terminal NC2B having a reduced length can be secured. That is, in the present modification, since the distance between the terminal FO and the terminal NC2B is increased by reducing the length of the terminal NC2B, a margin greater than the design allowable distance is generated, so that the y from the terminal FO toward the semiconductor chip CHP1 The extending portion LP extending in the direction can be provided in the terminal FO. As a result, in this modified example, as shown in FIG. 10, it becomes possible to connect the wire W to the extending portion LP of the terminal FO, thereby comparing with the case where the extending portion LP is not provided in the terminal FO, The length of the wire W connecting the terminal FO and the pad PD1 of the semiconductor chip CHP1 can be shortened. Therefore, according to this modification, the remarkable effect that the manufacturing cost can be reduced and the reliability of the semiconductor device can be improved.

(Embodiment 2)
Next, feature points in the second embodiment will be described. In the second embodiment, for example, attention is focused on the structure indicated by the region CR in FIG. For example, FIG. 11 is a schematic diagram showing an enlarged region in the vicinity of one corner CNR1 of the rectangular chip mounting portion TAB2 in the related art. In FIG. 11, a terminal GND2 (lead LD2) connected to the chip mounting portion TAB2 is formed in a region near the corner portion CNR1 of the chip mounting portion TAB2. A semiconductor chip CHP2 is mounted on the chip mounting portion TAB2, and a pad PD1 and a terminal GND2 formed on the semiconductor chip CHP2 are connected by a wire W. In particular, in FIG. 11, the terminal GND2 has a connection part (first part) FU connected to the chip mounting part TAB2, and a connection point P2 to the wire W exists in the connection part FU of the terminal GND2. .

  Here, the semiconductor chip CHP2 and the chip mounting portion TAB2 are covered with a sealing body (not shown) in a sealing process, but a heat resistance test is performed on the semiconductor device in the subsequent process. The As a result, thermal stress is applied to the semiconductor device, and the thermal stress peels off at the interface between the blank region between the end of the semiconductor chip CHP2 and the end of the chip mounting portion TAB2 and the sealing body. May occur. When such peeling occurs, the peeling tends to proceed along the path PH1 of FIG. 11 starting from the corner CNR1 of the chip mounting portion TAB2. Therefore, when the length of the path PH1 shown in FIG. 11 is short, the peeling of the sealing body from the chip mounting portion TAB2 easily reaches the connection point P2 between the connection portion FU of the terminal GND2 and the wire W. May cause the wire W to peel off.

  Thus, in the present second embodiment, even if the sealing body is peeled off from the chip mounting portion TAB2, a measure is taken to make it difficult for the wire W to peel off.

  FIG. 12 is a diagram schematically showing feature points in the second embodiment. In FIG. 12, the feature point in this embodiment is that the terminal GND2 connected to the chip mounting portion TAB2 is connected to the connection portion FU in addition to the connection portion (first portion) FU to which two chip mounting portions TAB are connected. In addition, it has a convex portion (second portion) SU protruding toward the corner portion CNR1 while being separated from the chip mounting portion TAB2. In other words, as shown in FIG. 12, the feature point of the second embodiment is that the terminal GND2 is connected to the connection part (first part) FU connected to the chip mounting part TAB2, and to the connection part FU, and And a convex portion (second portion) SU provided to face the chip mounting portion TAB2 via a space (gap). The convex portion SU is a connection portion between the terminal GND2 and the wire W, and when attention is paid to the corner portion CNR1 closest to the terminal GND2 among the plurality of corner portions present in the chip mounting portion TAB2, the convex portion SU is , Is arranged closer to the corner CNR1 than the connecting portion FU.

  At this time, a route passing through the inside of the chip mounting portion TAB2 and the inside of the terminal GND2 is considered. In this case, the path length PH2 between the corner portion CNR1 of the chip mounting portion TAB2 and the connection point P3 when the wire W having the first length is connected at the connection point P3 in the convex portion (second portion) SU is: That is, the first length of the wire W is longer than the path length PH1 between the corner CNR1 of the chip mounting portion TAB2 and the connection point P2 when the wire W is connected at the connection point P2 in the terminal GND2 other than the convex portion SU. Can do.

  Thereby, according to the second embodiment, as shown in FIG. 12, the path length PH2 between the connection point P3 between the convex portion SU of the terminal GND2 and the wire W and the corner portion CNR1 is shown in FIG. It can be longer than the path length PH1. This means that according to the second embodiment, the peeling of the sealing body from the chip mounting portion TAB2 becomes difficult to reach the connection point P3 between the convex portion SU of the terminal GND2 and the wire W. Therefore, peeling of the wire W can be suppressed. That is, according to the feature point of the second embodiment, the length of the path length PH2 from the corner portion CNR1 of the chip mounting portion TAB2 to the connection point P3 with the wire W existing on the convex portion SU of the terminal GND2 is increased. can do. As a result, even if peeling occurs between the surface of the chip mounting portion TAB and the sealing body starting from the corner portion CNR1 of the chip mounting portion TAB2, peeling does not easily reach the connection point P3. According to 2, peeling of the wire W can be effectively suppressed. Therefore, according to the second embodiment, the reliability of the semiconductor device can be improved.

(Embodiment 3)
In the third embodiment, a method for manufacturing a semiconductor device including the feature points in the first embodiment and the feature points in the second embodiment will be described with reference to the drawings.

<Method for Manufacturing Semiconductor Device>
1. Lead Frame Preparation Step First, as shown in FIG. 13, a lead frame LF having a chip mounting portion TAB1, a chip mounting portion TAB2, a plurality of leads LD1, and a plurality of leads LD1 is prepared. Here, the chip mounting part TAB1 and the chip mounting part TAB2 are arranged side by side in the x direction, and the planar size of the chip mounting part TAB2 is larger than the planar size of the chip mounting part TAB1. The plurality of leads LD1 are disposed closer to the chip mounting unit TAB1 than the chip mounting unit TAB2, and are arranged side by side in the y direction. Similarly, the plurality of leads LD2 are arranged closer to the chip mounting unit TAB2 than the chip mounting unit TAB1, and are arranged side by side in the y direction. Note that the number of the plurality of leads LD1 is equal to the number of the plurality of leads LD2.

2. Next, as shown in FIG. 14, for example, the semiconductor chip CHP1 is mounted on the chip mounting portion TAB1 through a die bonding material (not shown). Similarly, for example, the semiconductor chip CHP1 is mounted on the chip mounting portion TAB1 via a die bond material (not shown). At this time, the planar size of the semiconductor chip CHP1 is smaller than the planar size of the chip mounting portion TAB1, and the planar size of the semiconductor chip CHP2 is smaller than the planar size of the chip mounting portion TAB2. That is, as shown in FIG. 14, in plan view, the semiconductor chip CHP1 is disposed so as to be included in the chip mounting portion TAB1, and the semiconductor chip CHP2 is disposed so as to be included in the chip mounting portion TAB2. The

3. Wire Bonding Step Subsequently, as shown in FIG. 15, the pad PD1 formed on the semiconductor chip CHP1 and one lead LD1 of the plurality of leads LD1 are electrically connected by the wire W. Further, the pad PD2 formed on the semiconductor chip CHP2 and one lead LD2 of the plurality of leads LD2 are electrically connected by a wire W. Further, the pad PD1 of the semiconductor chip CHP1 and the pad PD2 of the semiconductor chip CHP2 are electrically connected by a wire W.

  Specifically, for example, focusing on the area AR in FIG. 3 and FIG. 5 which is an enlarged view, in the wire bonding process in the first embodiment, as shown in FIG. 5, the terminal VCC1 (lead LD1) and the semiconductor The pad PD1A of the chip CHP1 is connected by a wire W1A, and the terminal TMP (lead LD1) and the pad PD1B of the semiconductor chip CHP1 are connected by a wire W1B. Note that the terminal NC1 sandwiched between the terminal VCC1 and the terminal TMP and the semiconductor chip CHP1 are not connected by the wire W. As a result, the terminal NC1 functions as a non-connect terminal in which the potential of the terminal NC1 is “floating potential”.

  Further, in the wire bonding process, attention is focused on the region BR of FIG. 3 and FIG. 8 which is an enlarged view. At this time, the plurality of leads LD1 includes the largest number of leads LD1 of the first length, and the length of the terminal NC2A is a second length shorter than the first length. In addition, the terminal FO arranged at a position adjacent to the terminal NC2A has a wide portion WP2 that spreads in a space generated by setting the length of the terminal NC2A to the second length.

  Here, the wire bonding step includes a step of preparing a clamper CLP for fixing the lead frame LF, a wide portion WP2 of the terminal FO, excluding the terminal NC2A, and some of the leads LD1 of the plurality of leads LD1. Contacting the clamper CLP. The wide portion WP2 of the terminal FO overlaps the clamper CLP in a direction that passes through the connection point P1 between the terminal FO and the wire W and is orthogonal to the contact line (clamper outline) of the terminal FO and the clamper CLP. Has a site.

  Thereby, according to the manufacturing method of the semiconductor device in the present third embodiment, rattling of the wide portion WP2 can be sufficiently suppressed, and the wide portion WP2 of the terminal FO can be firmly fixed by the clamper CLP. For this reason, in the wire bonding step according to the third embodiment, stable wire bondability can be realized, whereby the connection strength between the wide portion WP2 of the terminal FO and the wire W can be improved. Therefore, according to the semiconductor device manufacturing method of the third embodiment, the reliability of the semiconductor device SA1 can be improved.

4). Molding process (sealing process)
Next, as shown in FIG. 16, for example, a chip mounting part TAB1, a chip mounting part TAB2, a semiconductor chip CHP1, a semiconductor chip CHP2, a wire W, a part of each of the plurality of leads LD1, and a plurality of Each part of the lead LD2 is sealed with a sealing body MR made of resin. At this time, for example, as can be seen by comparing FIG. 6 and FIG. 8, in the present third embodiment, the length of the wire W connecting the terminal FO and the pad PD1 of the semiconductor chip CHP1 can be shortened. The wire flow resulting from the resin sealing pressure can be suppressed. As a result, according to the semiconductor device manufacturing method of the third embodiment, the manufacturing cost can be reduced by shortening the length of the wire W. In addition, according to the method of manufacturing a semiconductor device in the third embodiment, the wire flow can be suppressed by shortening the length of the wire W. As a result, the occurrence of a short circuit between adjacent wires can be suppressed. Thereby, the reliability of the semiconductor device can be improved.

5. Thereafter, although not shown, a conductor film is formed on the surface of each part of the plurality of leads LD1 exposed from the sealing body MR and the surface of each part of the plurality of leads LD2 exposed from the sealing body MRY. A certain plating film is formed.

6). Marking Step Subsequently, although not shown, information (marks) such as a product name and a model number is formed on the surface of the sealing body MR made of resin. In addition, as a formation method of a mark, the method of printing by a printing system and the method of marking by irradiating the surface of a sealing body with a laser can be used.

7). Individualization Step Thereafter, the leads LD1 and LD2 are cut to obtain a plurality of individual semiconductor devices SA1 from the lead frame LF. Thereafter, for example, a test process such as an electrical characteristic inspection or an appearance inspection is performed. In particular, these test processes include a heat resistance test, and the heat stress is applied to the semiconductor device SA1.

  In this regard, in the third embodiment, for example, as shown in the region CR of FIG. 3 and FIG. 12 which is an enlarged view, the connection point P3 and the corner portion CNR1 between the convex portion SU of the terminal GND2 and the wire W Is made longer than the route PH1 shown in FIG. This means that according to the third embodiment, the peeling of the sealing body from the chip mounting portion TAB2 becomes difficult to reach the connection point P3 between the convex portion SU of the terminal GND2 and the wire W. Therefore, peeling of the wire W can be suppressed. That is, according to the third embodiment, even if the surface of the chip mounting portion TAB and the sealing body are peeled off from the corner CNR1 of the chip mounting portion TAB2 due to the thermal stress of the heat resistance test, Since it becomes difficult to reach the connection point P3, the peeling of the wire W can be effectively suppressed. Therefore, according to the semiconductor device manufacturing method of the third embodiment, the reliability of the semiconductor device can be improved.

  Thereafter, the semiconductor device SA1 determined to be non-defective is packed and shipped. As described above, the semiconductor device SA1 according to the third embodiment can be manufactured.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

<Modification>
In the first to third embodiments, the package structure in which a plurality of semiconductor chips (for example, two semiconductor chips) are included in the semiconductor device SA1 has been described as an example. However, the technical idea in the embodiment is not limited to this, and may be applied to a package structure in which one semiconductor chip is included in the semiconductor device SA2, for example, as shown in FIG. it can. FIG. 17 is a plan view schematically showing the internal structure of the semiconductor device SA2 in this modification. Also in FIG. 17, the first characteristic point in the first embodiment is that the terminal VCC1 to which the power supply potential is applied, the terminal D1 to which the digital signal is applied, the terminal VCC1 and the terminal D1 are sandwiched, and is not connected. It is embodied in the configuration of the terminal NC1, which is a terminal.

  In FIG. 17, the second feature point of the first embodiment also includes a terminal GND1 to which a ground potential is applied, a terminal D2 to which a digital signal is applied, a terminal GND1 and a terminal D2, and non- It is embodied in the configuration of a terminal NC2A which is a connection terminal.

  Further, in FIG. 17, a semiconductor chip CHP on which a pad PD is formed is mounted on the chip mounting portion TAB, and the feature point in the second embodiment is also a terminal GND2 connected to the chip mounting portion TAB. It is embodied in.

  The embodiment includes the following forms.

(Appendix 1)
(A) preparing a lead frame having a chip mounting portion and a first lead group including a first lead and a second lead adjacent to each other;
(B) mounting a semiconductor chip on the chip mounting portion;
(C) after the step (b), electrically connecting the semiconductor chip and the first lead with a first wire;
With
The first lead group includes the most leads of the first length,
A length of the second lead is a second length shorter than the first length;
The first lead has a wide portion that extends into a space generated by setting the length of the second lead to the second length,
The step (c)
(C1) preparing a clamper for fixing the lead frame;
(C2) excluding the second lead, and bringing the clamper into contact with the wide portion of the first lead and a part of the first lead group,
(C3) After the step (c2), electrically connecting the semiconductor chip and the first lead with a first wire;
Including
The wide portion passes through a first connection point between the first lead and the first wire and overlaps the clamper in a direction perpendicular to a first contact line between the first lead and the clamper. A method for manufacturing a semiconductor device.

CHP1 semiconductor chip CHP2 semiconductor chip CNR1 Corner (first corner)
DL1 Design tolerance FO terminal (first lead)
FU connection part (first part)
LD1 lead (first lead group)
LD2 lead (second lead group)
LP extension MR seal NC1 terminal (second lead)
NC2A terminal (second lead)
NC2B terminal (second lead)
PH1 path length (first path length)
PH2 path length (second path length)
P1 connection point P2 connection point (second connection point)
P3 connection point (first connection point)
SU Convex (second part)
S1 side (first side)
S2 side (second side)
TAB1 chip mounting part TAB2 chip mounting part TMP terminal (first lead)
VCC1 terminal (Lead for fixed potential)
GND1 terminal (Lead for fixed potential)
GND2 terminal (Lead for fixed potential)
W wire (first wire)
WP2 Wide part

Claims (19)

A sealing body having a rectangular planar shape;
A first lead group disposed along a first side of the sealing body in plan view;
A second lead group disposed along the second side of the sealing body located on the opposite side of the first side in a plan view;
A chip mounting portion disposed between the first lead group and the second lead group;
A semiconductor chip mounted on the chip mounting portion;
A first lead included in the first lead group;
A first wire that electrically connects the first lead and the semiconductor chip;
A second lead included in the first lead group and adjacent to the first lead;
With
A digital signal is applied to the first lead,
The semiconductor device, wherein the potential of the second lead is a floating potential. The semiconductor device according to claim 1,
The semiconductor device, wherein the second lead is a non-connect lead that is not electrically connected to the semiconductor chip. The semiconductor device according to claim 1,
The length of the second lead is a semiconductor device shorter than the length of the first lead. The semiconductor device according to claim 1,
The semiconductor device, wherein the second lead is disposed at a position farther from the semiconductor chip than the first lead. The semiconductor device according to claim 4,
The first lead group includes the most leads of the first length,
A length of the second lead is a second length shorter than the first length;
The first lead has a wide portion;
In the case where the wide portion assumes that the distance between the wide portion and the second lead is not less than the design allowable distance between the leads, while the length of the second lead is the first length. A semiconductor device including a shape in which a distance between the wide portion and the second lead is shorter than the design allowable distance between the leads. The semiconductor device according to claim 5,
The wide portion extends to a space generated by setting the length of the second lead to the second length. The semiconductor device according to claim 5,
The semiconductor device, wherein the second lead is a lead having the shortest length among the leads included in the first lead group. The semiconductor device according to claim 1,
The semiconductor device, wherein the second lead is disposed closer to the semiconductor chip than the first lead.
The semiconductor device according to claim 8,
The first lead group includes the most leads of the first length,
A length of the second lead is a second length shorter than the first length;
The first lead extends by extending the second lead in the direction closer to the semiconductor chip than by setting the second lead to the first length by making the second lead the second length. A semiconductor device having a portion. The semiconductor device according to claim 9.
The semiconductor device, wherein the first wire is connected to the extending portion of the first lead. The semiconductor device according to claim 9.
The semiconductor device, wherein the second lead is a lead having the shortest length among the leads included in the first lead group. The semiconductor device according to claim 1,
The semiconductor device further includes a fixed potential lead to which a fixed potential is applied,
In plan view, the second lead is disposed at a position sandwiched between the first lead and the fixed potential lead. The semiconductor device according to claim 12,
The semiconductor device, wherein the fixed potential is a power supply potential or a ground potential. The semiconductor device according to claim 12,
The fixed potential is a ground potential,
The semiconductor device, wherein the fixed potential lead is electrically connected to the chip mounting portion. The semiconductor device according to claim 1,
The semiconductor device is configured to be connectable to an external semiconductor device,
The semiconductor device, wherein the digital signal applied to the first lead is an abnormality detection signal for detecting an abnormality of the external semiconductor device. The semiconductor device according to claim 15,
The external semiconductor device includes a switching element,
The semiconductor device, wherein the abnormality detection signal is a signal for detecting an abnormality of the switching element. The semiconductor device according to claim 16, wherein
The semiconductor device, wherein the switching element is a power transistor. A chip mounting portion whose planar shape is a rectangular shape;
A semiconductor chip mounted on the chip mounting portion;
A lead electrically connected to the chip mounting portion;
A wire for electrically connecting the lead and the semiconductor chip;
A sealing body for sealing the semiconductor chip, the wire, and a portion of the lead;
With
The lead is
A first portion connected to the chip mounting portion;
A second part connected to the first part and provided to face the chip mounting part via a space;
Have
The second part is a connection part between the lead and the wire,
When attention is paid to the first corner closest to the lead among the plurality of corners existing in the chip mounting portion, the second portion is arranged closer to the first corner than the first portion. A semiconductor device. The semiconductor device according to claim 18.
When considering a path passing through the inside of the chip mounting portion and the inside of the lead,
The first path length between the first corner of the chip mounting portion and the first connection point when the first length of the wire is connected at the first connection point in the second part is A second path between the first corner of the chip mounting portion and the second connection point when the wire having the first length is connected at a second connection point in the lead other than the second portion. A semiconductor device that is longer than its length.

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