JP2017174278A - Image processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce overhead caused by reading of image data from memory.SOLUTION: Provided is an image processing device (11) configured to read image data from memory and perform image processing in accordance with a command. As pre-processing prior to image processing, a controller (12) sets first image data that has been already read as second image data when storage destination addresses of the first image data and the second image data, which are read frame by frame in the described order, are identical.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an image processing apparatus that draws and displays image data using a frame buffer that stores image data for one frame.

  In general, image data of still images and moving images is compression-coded and mounted on an amusement device. A memory storing compressed data obtained by performing compression encoding on various image data is connected to the image processing apparatus, and the compressed data is read from the memory and decoded each time an image is displayed.

  The image display performance in the amusement device largely depends on the time required to read out the compressed data from the memory. This is particularly noticeable in a frame buffer type image processing apparatus.

  Patent Documents 1 and 2 disclose a pseudo cache system in which a data buffer is arranged between a memory and a CPU (Central Processing Unit), and the data buffer is regarded as a cache memory. Patent Documents 3 and 4 disclose image processing apparatuses provided with a plurality of frame buffers.

  According to the pseudo cache systems of Patent Documents 1 and 2, and the image processing apparatuses of Patent Documents 3 and 4, a reduction in overhead caused by reading compressed data from a memory can be expected.

JP 2003-108438 A (published on April 11, 2003) JP 5-233449 A (published on September 10, 1993) JP 2007-298760 A (published November 15, 2007) JP 7-225710 A (released August 22, 1995)

  The present inventor has intensively studied to realize further reduction of overhead due to time required for reading from the memory in the frame buffer type image processing apparatus. As a result, the present inventor has completed the present invention.

  An object of the present invention is to realize an image processing apparatus that reduces the overhead caused by reading image data from the memory by preloading the image data from the memory.

  In order to solve the above problem, an image processing apparatus according to an aspect of the present invention is an image processing apparatus that reads out image data from a memory and performs image processing in accordance with a command including a storage destination address. First, second, and third command buffers that are sequentially written in units of frames, and first and second that are faster in reading speed than the memory and in which image data read from the memories are sequentially written in units of frames. As a preload buffer and preprocessing of the image processing, the first storage destination address included in the first command written in the first command buffer and immediately after the first command written in the second command buffer If the second storage destination address included in the second command matches the first command according to the first command. The first image data written in the load buffer, and a setting unit for setting the second image data to be written into the second pre-load buffer in accordance with the second command.

  Here, “the preprocessing of the image processing” means “preloading” in which image data is read from the memory in advance.

  According to the above configuration, if the second storage destination address matches the first storage destination address, the storage destination in the memory is the same. Therefore, the first image data and the second image data are the same image data. It can be said that there is.

  In this case, the first image data read out in advance is set as the second image data read out according to the second command by the setting unit, so there is no need to read the second image from the memory, and the reading is performed from the memory The second image can be read from the second preload buffer having a high speed.

  For this reason, it is possible to reduce overhead caused by reading image data from the memory.

  The image processing apparatus according to each aspect of the present invention may be realized by a computer. In this case, the image processing apparatus is realized by a computer by causing the computer to operate as each unit included in the image processing apparatus. A control program for the image processing apparatus to be executed and a computer-readable recording medium on which the control program is recorded also fall within the scope of the present invention. Furthermore, the image processing apparatus according to each aspect of the present invention may be realized as an integrated circuit (IC chip). In this case, a chip including the integrated circuit also falls within the scope of the present invention.

  According to the present invention, it is possible to reduce overhead caused by reading image data from a memory.

It is a block diagram which shows the premise structure of the image processing apparatus which concerns on this invention. 1 is a block diagram illustrating a configuration of an image processing apparatus according to an embodiment of the present invention. It is a timing chart which shows the procedure of the image processing by the said image processing apparatus.

  First, a configuration that is a premise of the image processing apparatus according to the present invention will be described, and then the image processing apparatus according to the present invention will be described in one embodiment. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and redundant description is omitted.

  FIG. 1 is a block diagram showing a premise configuration (hereinafter referred to as “premise device”) of an image processing apparatus of the present invention. In FIG. 1, an image display device 100 including a prerequisite device 101 and a CPU 201, a ROM 202, and an LCD 203 connected to the prerequisite device 101 is illustrated. The prerequisite device 101 reads out and decodes sprite compressed image data from the ROM 202 in accordance with a command given from the CPU 201 or reads out sprite uncompressed image data from the ROM 202 to generate image data to be displayed on the LCD 203. To do. The CPU 201 is a processor that controls the entire information device or the like on which the prerequisite device 101 is mounted, and supplies commands and data for displaying images such as sprites, backgrounds, and fonts on the LCD 203 to the prerequisite device 101. To do. The ROM 202 stores compressed or uncompressed format image data for a display target such as various sprites, backgrounds, and fonts, an α blend value in a compressed format or an uncompressed format used for α blending, and the like.

  The prerequisite apparatus 101 includes a controller 102, a command buffer 103, a preload buffer 104, a DMAC (direct memory access controller) 105, a decoder 106, a decode buffer 107, a drawing engine 108, a frame buffer 109, And a display control unit 110.

  In the prerequisite apparatus 101, the CPU 201 writes a command into the command buffer 103. The command buffer 103 performs double buffering, and includes a first command buffer 103a and a second command buffer 103b.

  The preload unit 102a of the controller 102 reads a command written in the first command buffer 103a or the second command buffer 103b, and specifies a command for instructing reading of image data from the ROM 202. If preloading of the image data is specified in the specified command, the preload unit 102a sets transfer of image data from the ROM 202 to the preload buffer 104 to the DMAC 105.

  The DMAC 105 transfers the set image data. Along with this transfer, the storage destination address indicating the storage location of the image data included in the command is rewritten from the address in the ROM 202 to the address in the preload buffer 104 by the preload unit 102a.

  The command execution unit 102b of the controller 102 causes the decoder 106 to decode the image data in accordance with the command written in the first command buffer 103a or the second command buffer 103b.

  The decoder 106 reads the image data from the preload buffer 104 if the storage address of the image data included in the command is an address in the preload buffer 104, and reads the image data if the address is in the ROM 202. Read from ROM 202. Conventionally, necessary image data is read from the ROM 202 each time an image is displayed. In the prerequisite apparatus 101, the image data for which preloading is designated by the user is preloaded by the preloading unit 102a as described above, and reading of the image data by the decoder 106 is not performed from the ROM 202 but actually the preload buffer 104. Read from. Since the preload buffer 104 can use a high-speed accessible memory such as a DRAM, the time required to read the image data is shortened as compared with the case of reading the image data from the ROM 202.

  Note that the ratio of image data to be preloaded among the image data stored in the ROM 202 is limited by the capacity of the preload buffer 104. If the capacity of the preload buffer 104 is sufficiently large with respect to the capacity of the image data stored in the ROM 202, all of the image data stored in the ROM 202 can be targeted for preloading.

  The decoder 106 decodes the image data read from the preload buffer 104 or the ROM 202 and writes the decoded image data to the decode buffer 107.

  The command execution unit 102b further causes the drawing engine 108 to generate image data to be displayed on the LCD 203 in accordance with the command written in the first command buffer 103a or the second command buffer 103b.

  The drawing engine 108 reads image data from the decode buffer 107 frame by frame, and generates drawing data obtained by performing scaling / deformation, color processing, etc. on the image data. The drawing engine 108 writes the generated drawing data in the frame buffer 109. The frame buffer 109 performs double buffering and includes a first frame buffer 109a and a second frame buffer 109b. In the first frame buffer 109a and the second frame buffer 109b, image data is alternately written in units of frames, one of which is written image data for drawing, and the other is read image data for display.

  The display control unit 110 performs display control of an image on the LCD 203 based on the drawing data written in the first frame buffer 109a and the second frame buffer 109b.

  The above is the configuration and operation of the base device 101. In the prerequisite apparatus 101, as described above, preloading by the preloading unit 102a is performed on image data for which preloading is designated by the user. This preload designation is defined in a command given from the CPU 201 to the prerequisite apparatus 101. For example, at the development site of an amusement machine, the timing for writing a command to the command buffer 103 in units of frames, the timing for preloading from the ROM 202 to the preload buffer 104 in units of frames, etc. are tested on a computer in advance, and then output from the CPU 201 for each frame. Command to be decided.

  The above work is performed using software such as an authoring tool. However, the work is particularly affected by the size of the preload buffer 104, and it takes a lot of work by repeating trial and error. This is because if the processing is not in time within the prerequisite device 101, a so-called frame drop occurs and the desired display cannot be obtained.

  Accordingly, the present inventor has conducted further diligent studies, and has a configuration that eliminates the need for the user to pre-select image data to be preloaded, that is, automatically displays the image while displaying it and without the user. The present inventors have found a configuration in which image data to be selected can be selected, and have completed the present invention. According to the present invention, the above-described operation is unnecessary, and the user's trouble can be saved.

  Hereinafter, an image processing apparatus according to an embodiment of the present invention will be described. FIG. 2 is a block diagram showing a configuration of the image processing apparatus according to the embodiment of the present invention.

  The image processing apparatus 11 is connected to a CPU 201, a ROM (memory) 202, and an LCD 203, as in the base apparatus 101, and constitutes the image display apparatus 1. The image processing apparatus 11 includes a controller 12, a command buffer 13, a preload buffer 14, a DMAC 15, a decoder 16, a decode buffer 17, a drawing engine 18, a frame buffer 19, and a display control unit 20. ing.

  The controller 12 is a circuit that reads out image data from the ROM 202 in accordance with a command given from the CPU 201 and performs control for generating drawing data to be displayed on the LCD 203 from the read image data. A command given from the CPU 201 is written in the command buffer 13.

  The command buffer 13 performs triple buffering, and includes a first command buffer 13a, a second command buffer 13b, and a third command buffer 13c. In the first command buffer 13a, the second command buffer 13b, and the third command buffer 13c, a command is written by the CPU 201, and the written command is read.

  Commands are written in the first command buffer 13a, the second command buffer 13b, and the third command buffer 13c in frame units. The first command buffer 13a, the second command buffer 13b, and the third command buffer 13c are read in frame units in this order.

  For example, if the buffer in which the command currently being drawn is written is the first command buffer 13a, the second command buffer 13b is read and preloaded. Then, the CPU 201 writes a command into the third command buffer 13c.

  The controller 12 includes a preload unit (setting unit) 12a, a command execution unit (execution unit) 12b, and an address comparison unit 12c. The preload unit 12a reads a command written in the first command buffer 13a, the second command buffer 13b, or the third command buffer 13c, and specifies a command for instructing reading of image data from the ROM 202.

  The address comparison unit 12c includes the storage destination address of the image data and the writing order included in the command specified by the preloading unit 12a in the command written in the command buffer in the previous order of the command. The image data storage destination address is compared to determine whether or not they match. The preload unit 12a sets transfer of image data from the ROM 202 to the preload buffer 14 to the DMAC 15 according to the command specified by the preload unit 12a based on the determination result that the address comparison unit 12c does not match.

  In contrast, if the preload unit 12a determines that the address comparison unit 12c matches, the preload unit 12a does not set transfer of image data from the ROM 202 to the preload buffer 14 for the DMAC 15, but instead sets the following settings: I do.

  As shown in FIG. 2, the preload buffer 14 includes a first preload buffer 14a and a second preload buffer 14b. The preload buffer 14 performs simple double buffering without managing each free area of the first preload buffer 14a and the second preload buffer 14b. The first preload buffer 14a and the second preload buffer 14b are alternately frame by frame, one is preloaded by the DMAC 15 and image data is written from the ROM 202 by the DMAC 15, and the other is rendered by the decoder 16 for rendering. Data is read out.

  The preload buffer 14 uses a high-speed accessible memory such as a DRAM, and the read speed of the preload buffer 14 is higher than the read speed of the ROM 202.

  Returning to the description of the preload unit 12a again. When it is determined that the address comparison unit 12c matches, the preload unit 12a transfers the image data from one of the first preload buffer 14a and the second preload buffer 14b to the other, which is first in the order of writing to the DMAC 15. Set up forwarding.

  The transfer of the image data between the first preload buffer 14a and the second preload buffer 14b is basically that if the image data to be preloaded exists in the first preload buffer 14a or the like, the image data is bothered. Instead of preloading from the ROM 202, the image data present in the first preload buffer 14a or the like is used to avoid preloading from the ROM 202.

  The storage destination address comparison by the address comparison unit 12c described above is performed in order to check whether image data to be preloaded exists in the first preload buffer 14a or the like. The fact that the storage destination address included in a certain command (following command) matches the storage destination address included in the command (destination command) whose writing order was the order immediately before the succeeding command means that the preceding command This indicates that the image data stored at the matching storage destination address is preloaded from the ROM 202 first.

  Here, the command buffer 13 is different from the command buffer 103 of the premise device 101 in that it performs triple buffering in order to perform storage destination address comparison by the address comparison unit 12c. This is because, in order to perform this storage destination address comparison, a buffer for holding a command whose writing order is one order before the command written by the CPU 201 is required.

  The DMAC 15 transfers image data from the ROM 202 to the preload buffer 14, or transfers image data between the first preload buffer 14a and the second preload buffer 14b. In the former transfer, the storage destination address indicating the storage location of the image data included in the command is rewritten from the address in the ROM 202 to the address in the preload buffer 14 by the preload unit 12a.

  On the other hand, in the latter transfer, the storage destination address indicating the storage location of the image data included in the command is rewritten to a new address in the preload buffer 14 by the preload unit 12a. That is, it is caused by the change of the storage destination address in the preload buffer 14 accompanying the transfer between the first preload buffer 14a and the second preload buffer 14b.

  The command execution unit 12b of the controller 12 causes the decoder 16 to decode the image data according to the command written in the first command buffer 13a, the second command buffer 13b, or the third command buffer 13c. The decoder 16 reads the image data from the preload buffer 14.

  Here, in the case of the premise device 101, the image data to be preloaded is only the image data for which preloading is designated in advance by the user. In the image processing apparatus 11, the preloaded image data is not specified by the user. When the image data preloaded according to the previous command is the same as the image to be preloaded according to the subsequent command between two commands in which the order of writing to the command buffer 13 is continuous, the image data is not read from the ROM 202 The image data preloaded in advance is used.

  As a result, it is not necessary for the user to select in advance the image data to be preloaded, and the image data to be preloaded can be selected while performing image display.

  The decoder 16 decodes the image data read from the preload buffer 14 and writes the decoded image data to the decode buffer 17.

  The command execution unit 12b further causes the drawing engine 18 to generate image data to be displayed on the LCD 203 in accordance with the command written in the first command buffer 13a, the second command buffer 13b, or the third command buffer 13c. The first command buffer 13a, the second command buffer 13b, and the third command buffer 13c are switched and read in units of frames in a predetermined order.

  Note that the configurations and operations of the drawing engine 18, the frame buffer 19, and the display control unit 20 are the same as those of the drawing engine 108, the frame buffer 109, and the display control unit 110 of the base device 101, and thus description thereof is omitted here. To do. The above is the configuration and operation of the image processing apparatus 11.

  Finally, the procedure of image processing by the image processing apparatus 11 will be described with reference to FIG. FIG. 3 is a timing chart showing the procedure of image processing by the image processing apparatus 11.

  In synchronization with the V_BLANK signal VB0, the CPU 201 gives a command to the image processing apparatus 11 (S01, S02). The command CMD # 3 is given in S01, and is written in the command buffer Cbuff2 in S02.

  In FIG. 3, “command CMD # n” means a command group including a plurality of commands used to configure the nth frame.

  The preload unit 12a reads a command written in the command buffer 13 and specifies a command for instructing reading of image data from the ROM 202 (S02). In S02, the command CMD # 2 written in the command buffer Cbuff1 is read, and is specified as a command for instructing reading of image data from the ROM 202.

  The address comparison unit 12c compares the storage destination address included in the command with the storage destination address included in the command written in the command buffer having the previous writing order, and whether or not they match. Is determined (S03). In S03, the storage destination address of the command CMD # 2 written in the command buffer Cbuff1 is compared with the storage destination address of the command CMD # 1 written in the command buffer Cbuff0.

  The preload unit 12a sets transfer of image data from the ROM 202 to the preload buffer 14 to the DMAC 15 according to the command specified by the preload unit 12a based on the determination result that the address comparison unit 12c does not match. On the other hand, if the preload unit 12a determines that the address comparison unit 12c matches, the preload unit 12a transfers the DMAC 15 from the first preload buffer 14a or the second preload buffer 14b, which has been written first, to the other. Image data transfer is set (S03). The DMAC 15 transfers image data from the ROM 202 to the preload buffer 14 or transfers image data between the first preload buffer 14a and the second preload buffer 14b (S04). In S03 and S04, the image data Data # 2 is transferred to the preload buffer PBuff1 based on the determination result by the address comparison unit 12c.

  The command execution unit 12b causes the decoder 16 to decode the image data according to the command written in the command buffer 13. The decoder 16 reads the image data from the preload buffer 14 (S06). The decoder 16 decodes the image data read from the preload buffer 14 and writes the decoded image data to the decode buffer 17 (S07). In S06, the image data Data # 1 is read from the preload buffer PBuff0 according to the command CMD # 1 written in the command buffer Cbuff0, and the decoded image data Data # 1 is written in the decode buffer 17 in S07. ing.

  The command execution unit 12b causes the drawing engine 18 to generate image data to be displayed on the LCD 203 according to the command written in the command buffer 13 (S05). The drawing engine 18 reads image data from the decode buffer 17 frame by frame, and generates drawing data obtained by performing enlargement / reduction / deformation, color processing, etc. on the image data (S08). In S05, the drawing engine 18 generates drawing data # 1 in S08 according to the command CMD # 1 written in the command buffer Cbuff0.

  The drawing engine 18 writes the generated drawing data in the frame buffer 19 (S09). In S09, drawing data # 1 is written in the frame buffer 19.

  The display control unit 20 performs display control of an image on the LCD 203 based on the drawing data written in the first frame buffer 19a and the second frame buffer 19b (S10). In S10, display control of the image on the LCD 203 is performed based on the drawing data # 0 written in the frame buffer 19.

  In this way, image processing is performed, and an image is displayed (# 0) on the LCD 203 (S11).

  In synchronization with the V_BLANK signals VB1, VB2, and VB3, the same processes S21 to S30, S41 to S50, and S61 to S70 as the above S01 to S11 are executed, and the image is displayed on the LCD 203 (# 1, # 2, # 3) (S31, S51, S71).

  The image processing apparatus 11 may be realized by a logic circuit (hardware) formed in an integrated circuit (IC chip) or the like, or may be realized by software using a CPU (Central Processing Unit).

  In the latter case, the image processing apparatus 11 includes a CPU that executes instructions of a program that is software that realizes each function, and a ROM (Read Only Memory) in which the program and various data are recorded so as to be readable by a computer (or CPU). Alternatively, a storage device (these are referred to as “recording media”), a RAM (Random Access Memory) that expands the program, and the like are provided. And the objective of this invention is achieved when a computer (or CPU) reads the said program from the said recording medium and runs it. As the recording medium, a “non-temporary tangible medium” such as a tape, a disk, a card, a semiconductor memory, a programmable logic circuit, or the like can be used. The program may be supplied to the computer via an arbitrary transmission medium (such as a communication network or a broadcast wave) that can transmit the program. The present invention can also be realized in the form of a data signal embedded in a carrier wave in which the program is embodied by electronic transmission.

  The present invention is not limited to the above-described embodiment, and various modifications are possible within the scope shown in the claims, and the present invention is also applied to an embodiment obtained by appropriately combining technical means disclosed in the embodiment. It is included in the technical scope of the invention.

  In the above embodiment, the command buffer 13 performs triple buffering and the preload buffer 14 performs double buffering. However, the present invention is not limited to the number of buffers. The command buffer 13 may include four or more buffers, and the preload buffer 14 may include three or more buffers.

  For example, when the transfer from the ROM 202 to the preload buffer 14 takes one cycle (interval between V_BLANK signals shown in FIG. 3) or more, the preload buffer 14 includes three or more buffers to absorb an instantaneous load increase. It becomes possible to do. Similarly, for the command buffer 13, when the storage destination address comparison by the address comparison unit 12c takes one or more cycles, the command buffer 13 includes four or more buffers to absorb an instantaneous load increase. Is possible.

  In the above-described embodiment, the number of commands written to each of the first command buffer 13a, the second command buffer 13b, and the third command buffer 13c is not limited to one, but to configure each frame Needless to say, a command group including a plurality of used commands may be written.

  11 Image processing apparatus 12, 102 Controller 12a, 102a Preload unit (setting unit) 12b 102b Command execution unit (execution unit) 12c Address comparison unit 13, 103 Command buffer 13a, 103a First command buffer, 13b, 103b Second command buffer, 13c Third command buffer, 14, 104 Preload buffer, 14a First preload buffer, 14b Second preload buffer, 15, 105 DMAC, 16, 106 Decoder, 17, 107 Decode buffer, 18, 108 Drawing engine, 19, 109 Frame buffer, 20, 110 Display control unit, 101 Prerequisite device, 109a First frame buffer, 109b Second frame buffer, 201 CPU, 202 ROM (menu Mori), 203 LCD.

Claims (6)

An image processing apparatus that reads out image data from a memory and performs image processing according to a command including a storage destination address,
First, second, and third command buffers in which the commands are sequentially written in units of frames;
A first preload buffer and a second preload buffer in which image data read out from the memory are sequentially written in units of frames;
As preprocessing of the image processing, a first storage destination address included in the first command written in the first command buffer and a second command immediately after the first command written in the second command buffer If the second storage destination address included in the first image data matches the first image data written to the first preload buffer according to the first command, the second image written to the second preload buffer according to the second command. An image processing apparatus comprising: a setting unit configured as data.   The image processing apparatus according to claim 1, wherein the setting unit rewrites the second storage destination address to a storage destination address of image data written in the second preload buffer. When the first storage destination address matches the second storage destination address, the setting unit
Transferring the first image data from the first preload buffer to the second preload buffer;
The image processing apparatus according to claim 2, wherein the second storage destination address is rewritten to an address in the second preload buffer.   2. The setting unit reads the second image data from the memory and writes the second image data in the second preload buffer when the first storage destination address and the second storage destination address do not match. The image processing apparatus according to any one of?   The image processing apparatus according to claim 1, further comprising an execution unit that executes a third command written in the third command buffer as the image processing.   The image processing apparatus according to claim 1, wherein the image processing is performed by a frame buffer method.

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