JP2017174194A - Image processing apparatus, load distribution method and load distribution program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To distribute a load of a plurality of processor cores, while shortening a processing time after movement of a thread.SOLUTION: An image processing apparatus comprises: a plurality of processor cores; a plurality of cache memories corresponding to the plurality of processor cores, respectively; a processing object thread determination unit 13 that determines an object thread assigned to an object core; a hit rate acquisition unit 33 that acquires a cache hit rate; a first prediction unit 15 that predicts a first processing speed in which the object core executes the object thread on the basis of the cache hit rate of the object core; a second prediction unit 19 that predicts a second processing speed in which a candidate core executes the object thread with the cache hit rate as zero; a determination unit 21 that compares the first processing speed with the second processing speed, and determines a change of the assignment of the object thread; and an assignment change unit 23 that changes the assignment of the object thread from the object core to the candidate core.SELECTED DRAWING: Figure 4

Description

  The present invention relates to an image processing apparatus, a load distribution method, and a load distribution program, and more particularly to an image processing apparatus including a multi-core processor having a plurality of cores, a load distribution method and a load distribution program executed by the image processing apparatus.

  In recent years, multi-core processors having a plurality of cores are known, and it is conceivable that a multi-core processor is mounted on an MFP (Multi Function Peripheral) represented by an image processing apparatus that processes images. In a multi-core processor, different processes are executed in parallel by assigning threads to a plurality of cores. However, depending on the thread allocation state, the load on a certain core may become larger than on other cores. For this reason, a technique for distributing a load among a plurality of cores is known.

  For example, Japanese Patent Laid-Open No. 2008-191949 discloses a multi-core system having a plurality of multi-core processors having a plurality of core processors and a shared resource sharing the resources of each multi-core processor, and load information of each multi-core processor. Load information collection means for acquiring load information at the time of accessing the shared resource, load information of each multi-core processor acquired by the load information collection means, and load information at the time of access A load distribution determination unit that determines whether or not to perform load distribution, and a load distribution unit that distributes a load when the load distribution determination unit determines that load distribution is to be performed. A multi-core system is described, characterized in that it is. In the multi-core system described in Japanese Patent Application Laid-Open No. 2008-191949, threads allocated to a multi-core processor with an increased load are moved to a multi-core processor with a low load, so that the load can be distributed among a plurality of multi-core processors. it can.

However, in a multi-core processor after moving a thread, it takes time to write data to the cache memory, and the cache hit rate for accessing the cache memory when executing the thread to be moved is higher than before moving. Not necessarily high. For this reason, there is a problem that the processing speed at which the multi-core processor after the movement executes the thread to be moved may be slower than before the movement.
JP 2008-191949 A

  The present invention has been made to solve the above-described problems, and one object of the present invention is to distribute the load of a plurality of processor cores while shortening the processing time after the movement of a thread to be moved. It is to provide an image processing apparatus capable of performing the above.

  Another object of the present invention is to provide a load distribution method capable of distributing loads of a plurality of processor cores while shortening a processing time after movement of a thread to be moved.

  Still another object of the present invention is to provide a load distribution program capable of distributing the load of a plurality of processor cores while shortening the processing time after movement of a thread to be moved.

  In order to achieve the above object, according to one aspect of the present invention, an image processing device includes a plurality of processor cores, a plurality of cache memories respectively corresponding to the plurality of processor cores, and a target core among the plurality of processor cores. Target thread determination means for determining one of one or more threads assigned to the target thread, hit rate acquisition means for acquiring the cache hit ratio of each of the plurality of processor cores, and acquisition of the target core by the hit ratio acquisition means A first prediction means for predicting a first processing speed at which the target core executes the target thread based on the cache hit rate, and a candidate core different from the target core among the plurality of processor cores determines the cache hit rate Second prediction means for predicting the second processing speed when the target thread is executed as zero, and the first processing speed And the second processing speed to determine whether to change the target thread assignment from the target core to the candidate core, and based on the determination result by the determination means, assign the target thread. Allocation changing means for changing from a target core to a candidate core.

  According to this aspect, the first processing speed at which the target core executes the target thread is predicted based on the cache hit rate acquired for the target core, and the candidate core executes the target thread with the cache hit rate set to zero. The second processing speed is predicted, and by comparing the first processing speed and the second processing speed, it is determined whether or not the allocation of the target thread is changed from the target core to the candidate core. Based on this, the allocation of the target thread is changed from the target core to the candidate core. For this reason, since the first processing speed before moving the target thread is compared with the second processing speed after moving the target thread, the processing speed for processing the target thread is expected to increase. The target thread is moved. As a result, it is possible to provide an image processing apparatus capable of distributing the loads of a plurality of processor cores while shortening the processing time after movement of a thread to be moved.

  Preferably, an occupancy rate acquisition unit that acquires an occupancy rate for each of one or more threads executed by each of the plurality of processor cores is further provided, and the first prediction unit includes the occupancy rate of the target thread acquired by the occupancy rate acquisition unit And the first processing speed is predicted based on the cache hit rate of the target core acquired by the hit rate acquisition unit, and the second prediction unit is executed by one or more candidate cores acquired by the occupation rate acquisition unit The second processing speed is predicted based on the remaining capacity of the candidate core calculated from the occupancy of each thread.

  According to this aspect, the first processing speed is predicted based on the occupancy ratio of the target thread and the cache hit ratio of the target core, and the candidate is calculated from the occupancy ratio of each of one or more threads executed by the candidate core. The second processing speed is predicted based on the remaining capacity of the core. For this reason, the processing speed before and after moving the target thread can be accurately predicted.

  Preferably, the information processing apparatus further comprises capability information acquisition means for acquiring processing capacities of the plurality of processor cores, wherein the first prediction means predicts the first processing speed based on the processing capacity of the target thread, and second prediction means Predicts the second processing speed further based on the processing capability of the candidate core.

  According to this aspect, the target thread can be adapted to a case where the processing capability of the processor core before moving and the processor core after moving are different.

  Preferably, the determination unit determines whether or not to change the allocation of the target thread from the target core to the candidate core at predetermined time intervals.

  According to this aspect, since it is determined whether or not the assignment of the target thread is changed at a predetermined time interval, the loads of the plurality of processor cores can be distributed at the predetermined time interval.

  Preferably, the assignment changing means, when the image data to be processed by the target thread is divided into a plurality of processing unit parts and processed, the assignment of the target thread determined to change the assignment by the judging means It changes in response to the completion of any of the processing unit parts.

  According to this aspect, since the thread assignment is not changed until the processing of any one of the plurality of processing unit parts of the image data is completed, the same process is prevented from being repeatedly executed before and after the movement. can do.

  Preferably, a variable thread determining unit that determines a thread that executes a program in which any one of the plurality of processor cores defines a process for converting image data as a variable thread is further provided, and the target thread determining unit is a variable thread determining unit One of the one or more variable threads determined by the above is determined as the target thread.

  According to this aspect, since the thread that executes the program that defines the process for converting the image data is the object of movement, the first processing speed and the second processing speed can be accurately predicted.

  Preferably, the target thread determination unit determines the target thread in descending order of priority from the plurality of variable threads determined by the variable thread determination unit.

  According to this aspect, since it is determined whether or not to move a plurality of variable threads in descending order of priority, the processing of variable threads having a high priority can be terminated early.

  According to another aspect of the present invention, the load distribution method is a load distribution method executed by an image processing device, and the image processing device includes a plurality of processor cores and a plurality of processor cores respectively corresponding to the plurality of processor cores. A target thread determining step of determining one of one or more threads assigned to the target core among the plurality of processor cores as a target thread, and obtaining a cache hit rate of each of the plurality of processor cores A hit rate acquisition step, a first prediction step of predicting a first processing speed at which the target core executes the target thread based on the cache hit rate acquired for the target core in the hit rate acquisition step, and a plurality of processor cores A candidate core that is different from the target core executes the target thread with a cache hit rate of zero. Whether to change the allocation of the target thread from the target core to the candidate core by comparing the first processing speed and the second processing speed with the second prediction step for predicting the second processing speed when A determination step of determining, and an allocation change step of changing the allocation of the target thread from the target core to the candidate core based on the determination result in the determination step.

  According to this aspect, it is possible to provide a load distribution method capable of distributing the load of a plurality of processor cores while shortening the processing time after movement of a thread to be moved.

  According to still another aspect of the present invention, the load distribution program is a load distribution program executed by a multi-core processor that controls the image processing apparatus, and the multi-core processor includes a plurality of processor cores and a plurality of processor cores. A plurality of corresponding cache memories, a target thread determining step for determining one of one or more threads assigned to the target core among the plurality of processor cores as a target thread, and a cache for each of the plurality of processor cores A hit rate acquisition step for acquiring a hit rate; a first prediction step for predicting a first processing speed at which the target core executes the target thread based on the cache hit rate acquired for the target core in the hit rate acquisition step; Of the multiple processor cores, different from the target core The second prediction step of predicting the second processing speed when the core executes the target thread with the cache hit rate being zero is compared with the first processing speed and the second processing speed, thereby assigning the target thread. A determination step for determining whether or not to change from the target core to the candidate core, and an assignment changing step for changing the allocation of the target thread from the target core to the candidate core based on the determination result in the determination step. To run.

  According to this aspect, it is possible to provide a load distribution program capable of distributing the loads of a plurality of processor cores while shortening the processing time after movement of a thread to be moved.

1 is a perspective view showing an external appearance of an MFP in the present embodiment. 2 is a block diagram showing an outline of a hardware configuration of an MFP according to the present embodiment. FIG. 2 is a diagram illustrating an example of a configuration of a multi-core processor included in an MFP according to the present embodiment. FIG. It is a figure which shows an example of the function which the multi-core processor with which MFP in this Embodiment is provided has. It is a figure which shows an example of capability definition data. It is a 1st figure for demonstrating the movement of a process target thread. It is a 2nd figure for demonstrating the movement of a process target thread. It is a flowchart which shows an example of the flow of a load distribution process.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same parts are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed description thereof will not be repeated.

  FIG. 1 is a perspective view showing the appearance of the MFP according to the present embodiment. FIG. 2 is a block diagram showing an outline of the hardware configuration of the MFP according to the present embodiment. 1 and 2, MFP 100 functioning as an image processing apparatus includes a main circuit 110, a document reading unit 130 for reading a document, and an automatic document transport device for transporting a document to document reading unit 130. 120, an image forming unit 140 for forming an image on a sheet or the like based on image data output by the document reading unit 130 reading the document, and a paper feeding unit 150 for supplying the image forming unit 140 with a sheet. And an operation panel 160 as a user interface.

  The main circuit 110 includes a multi-core processor 111, a communication interface (I / F) unit 112, a ROM 113, a RAM 114, a hard disk drive (HDD) 115 as a mass storage device, a facsimile unit 116, a CD-ROM ( And an external storage device 117 to which a Compact Disk ROM) 118 is mounted. Multi-core processor 111 is connected to automatic document feeder 120, document reading unit 130, image forming unit 140, paper feeding unit 150, and operation panel 160, and controls the entire MFP 100.

  The ROM 113 stores a program executed by the multi-core processor 111 or data necessary for executing the program. The RAM 114 is used as a work area when the multi-core processor 111 executes a program.

  Communication I / F unit 112 is an interface for connecting MFP 100 to a network. The multi-core processor 111 communicates with a computer connected to a network via the communication I / F unit 112 to transmit / receive data. The communication I / F unit 112 can communicate with a computer connected to the Internet via a network.

  The facsimile unit 116 is connected to the public switched telephone network (PSTN) and transmits facsimile data to the PSTN or receives facsimile data from the PSTN. The facsimile unit 116 stores the received facsimile data in the HDD 115 or outputs it to the image forming unit 140. The image forming unit 140 prints the facsimile data received by the facsimile unit 116 on a sheet. Further, the facsimile unit 116 converts the data stored in the HDD 115 into facsimile data, and transmits the facsimile data to a facsimile machine connected to the PSTN.

  The external storage device 117 is loaded with a CD-ROM 118. The multi-core processor 111 can access the CD-ROM 118 via the external storage device 117. The multi-core processor 111 loads the program recorded on the CD-ROM 118 mounted on the external storage device 117 to the RAM 114 and executes it. The medium for storing the program executed by the multi-core processor 111 is not limited to the CD-ROM 118, but an optical disc (MO (Magnetic Optical disc) / MD (Mini Disc) / DVD (Digital Versatile Disc)), IC card, optical A semiconductor memory such as a card, mask ROM, EPROM (Erasable Programmable ROM), or EEPROM (Electrically EPROM) may be used.

  The program executed by the multi-core processor 111 is not limited to the program recorded on the CD-ROM 118, and the program stored in the HDD 115 may be loaded into the RAM 114 and executed. In this case, another computer connected to the network may rewrite the program stored in HDD 115 of MFP 100 or may add a new program and write it. Further, MFP 100 may download a program from another computer connected to the network and store the program in HDD 115. The program here includes not only a program directly executable by the multi-core processor 111 but also a source program, a compressed program, an encrypted program, and the like.

  Operation panel 160 includes a display unit 161 and an operation unit 163. The display unit 161 is, for example, a liquid crystal display device (LCD), and displays an instruction menu for a user, information about acquired image data, and the like. The operation unit 163 includes a touch panel 165 and a hard key unit 167. The touch panel 165 is a capacitive type. Note that the touch panel 165 is not limited to the capacitance method, and other methods such as a resistance film method, a surface acoustic wave method, an infrared method, and an electromagnetic induction method can be used. Hard key portion 167 includes a plurality of hard keys. The hard key is, for example, a contact switch.

  FIG. 3 is a diagram illustrating an example of a configuration of a multi-core processor included in the MFP according to the present embodiment. Referring to FIG. 3, the multi-core processor 111 includes a first processor core 51, a first cache memory 53 dedicated to the first processor core 51, a second processor core 55, and a second cache dedicated to the second processor core 55. 2 cache memory 57. The first cache memory 53 and the second cache memory 57 are connected to the RAM 114, and the first processor core 51 and the second processor core 55 share the RAM 114.

  Since the first processor core 51 and the second processor core 55 can execute the program, the multi-core processor 111 can execute the program in parallel. An operating system (hereinafter referred to as “OS”) executed by the multi-core processor 111 assigns a thread to either the first processor core 51 or the second processor core 55. A thread is a process defined by a part of a program. The OS executed by the multi-core processor 111 generally assigns each of a plurality of threads for processing having no dependency relationship to either the first processor core 51 or the second processor core 55. When one or more threads are assigned to the first processor core 51 and one or more threads are assigned to the second processor core 55, a plurality of threads are executed in parallel.

  The load of each of the first processor core 51 and the second processor core 55 depends on processing executed by one or more threads assigned to the first processor core 51 and the second processor core 55. For this reason, the load of each of the first processor core 51 and the second processor core 55 differs depending on the difference between the thread assigned to the first processor core 51 and the thread assigned to the second processor core 55. Also, the frequency and cache hit rate at which the thread assigned to the first processor core 51 accesses the first cache memory 53, and the frequency and cache at which the thread assigned to the second processor core 55 accesses the second cache memory 57. The hit rate is often different. For this reason, the OS executed by the multi-core processor 111 changes the thread assignment in order to level the load on the first processor core 51 and the load on the second processor core 55.

  FIG. 4 is a diagram illustrating an example of functions of the multi-core processor included in the MFP according to the present embodiment. The function shown in FIG. 4 is obtained by executing a load distribution program stored in the ROM 113, the HDD 115 or the CD-ROM 118 by either the first processor core 51 or the second processor core 55 of the multi-core processor 111. 111 is a function realized by 111. Referring to FIG. 4, the multicore processor 111 includes a variable thread determination unit 11, a processing target thread determination unit 13, a first prediction unit 15, a candidate core determination unit 17, a second prediction unit 19, and a determination unit. 21, an assignment change unit 23, and an acquisition unit 25.

  The variable thread determination unit 11 determines a variable thread from among the threads assigned to the first processor core 51 and the second processor core 55. The variable thread is a thread that executes a program that defines processing for converting image data, among threads that are executed by either the first processor core 51 or the second processor core 55. The process of converting the image data includes a process of repeating a predetermined process a plurality of times. Processes other than variable threads are called fixed threads. The variable thread determination unit 11 outputs thread identification information for identifying the determined variable thread to the processing target thread determination unit 13. When determining a plurality of variable threads, the variable thread determination unit 11 outputs a plurality of thread identification information for identifying each of the plurality of variable threads to the processing target thread determination unit 13.

  The processing target thread determination unit 13 determines a variable thread to be processed from one or more variable threads respectively corresponding to one or more thread identification information input from the variable thread determination unit 11. Priorities are set in advance for the variable threads, and the processing target thread determination unit 13 determines the variable thread having the highest priority among the one or more variable threads as the processing target thread. After determining the processing target thread, the processing target thread determination unit 13 receives a determination result from the determination unit 21 described later. When the determination result indicating that the allocation is not changed is input from the determination unit 21, the processing target thread determination unit 13 receives one or more variable corresponding to one or more thread identification information input from the variable thread determination unit 11. Among the threads, a variable thread having a priority set next to the priority of the variable thread previously determined as the processing target thread is determined as the processing target thread. In response to determining the processing target thread, the processing target thread determination unit 13 outputs the thread identification information of the variable thread determined as the processing target thread to the first prediction unit 15 and the candidate core determination unit 17.

  The acquisition unit 25 acquires the states of the first processor core 51 and the second processor core 55. When the acquisition unit 25 acquires the states of the first processor core 51 and the second processor core 55, the acquisition unit 25 outputs the acquired states to the first prediction unit 15 and the second prediction unit 19. The acquisition unit 25 includes a capability information acquisition unit 31, a hit rate acquisition unit 33, and an occupancy rate acquisition unit 35.

  The capability information acquisition unit 31 acquires capability information of each of the first processor core 51 and the second processor core 55. The capability information of each of the first processor core 51 and the second processor core 55 is information indicating the calculation speed. The information indicating the calculation speed is, for example, a clock frequency.

  The hit rate acquisition unit 33 acquires the cache hit rate of each of the first processor core 51 and the second processor core 55. The cache hit rate is a rate at which data to be read is stored in the cache memory. The hit rate acquisition unit 33 acquires a first cache hit rate for the first processor core 51 and a second cache hit rate for the second processor core 55.

  The occupation rate acquisition unit 35 acquires the occupation rates in the first processor core 51 and the second processor core 55, respectively. The timing at which the occupancy rate acquisition unit 35 acquires the occupancy rate is the same as the timing at which the hit rate acquisition unit 33 acquires the cache hit rate. The occupation ratio is a ratio of the processing time of the thread to the whole. The occupation rate acquisition unit 35 acquires an occupation rate for each of one or more threads allocated to the first processor core 51 for the first processor core 51, and is allocated to the first processor core 51 for the first processor core 51. The occupation rate is acquired for each of one or more threads.

  The first prediction unit 15 receives the thread identification information of the processing target thread from the processing target thread determination unit 13, and receives the states of the first processor core 51 and the second processor core 55 from the acquisition unit 25. The first prediction unit 15 specifies one of the first processor core 51 and the second processor core 55 to which the processing target thread is assigned.

  Here, a case where the processing target thread is assigned to the first processor core 51 will be described as an example. In this case, the first prediction unit 15 specifies the first processor core 51 that executes the processing target thread. The first prediction unit 15 predicts the first processing speed at which the first processor core 51 executes the processing target thread based on the cache hit rate of the first processor core 51 and the occupation rate of the processing target thread. Specifically, the first prediction unit 15 predicts the first processing speed by referring to capability definition data that is predetermined for the capability information of the first processor core 51. The capability definition data defines an occupation rate and a processing time for processing unit data for each of a plurality of cache hit rates.

  FIG. 5 is a diagram illustrating an example of capability definition data. The capability definition data defines the relationship between the processing time for processing unit data and the occupation rate for each of a plurality of cache hit rates. In FIG. 5, the horizontal axis indicates the CPU occupation ratio, the vertical axis indicates the processing time, and the unit data is 1 GByte data. The capability definition data 201 corresponding to a cache hit rate of 0%, capability definition data 203 when the cache hit rate is 40%, and capability definition data 205 when the cache hit rate is 80% are shown. As shown in FIG. 5, the higher the cache hit rate, the shorter the processing time, and the higher the CPU occupation rate, the shorter the processing time.

  Returning to FIG. 4, the first prediction unit 15 stores in advance capability definition data corresponding to the capability information of the first processor core 51, and based on the capability definition data, the cache hit of the first processor core 51 Based on the rate and the occupation rate of the processing target thread, the first processing speed is predicted, and a set of core identification information and the first processing speed for identifying the first processor core 51 is output to the determination unit 21. Specifically, the first prediction unit 15 refers to the capability definition data corresponding to the capability information of the first processor core 51, and performs processing in the capability definition data corresponding to the cache hit rate of the first processor core 51. A value obtained by dividing the data amount of unit data by the processing time corresponding to the thread occupancy is defined as the first processing speed. For example, if the cache hit rate is 80% and the occupancy rate of the processing target thread is 20%, the processing time for processing unit data is 500 μs, so the first processing speed is determined to be 2 Mbyte / μs. If the cache hit rate is 40% and the occupancy rate of the processing target thread is 40%, the processing time for processing the unit data is 500 μs, so the first processing speed is determined to be 2 Mbyte / μs. If the cache hit rate is 0% and the occupancy rate of the processing target thread is 75%, the processing time for processing the unit data is 500 μs, so the first processing speed is determined to be 2 Mbyte / μs.

  The candidate core determination unit 17 determines a processor core different from the processor core to which the processing target thread is assigned as a candidate core in response to the thread identification information of the processing target thread being input from the processing target thread determination unit 13. To do. Here, since the processing target thread is assigned to the first processor core 51, the candidate core determination unit 17 determines the second processor core as a candidate core. The candidate core determination unit 17 outputs the core identification information for identifying the second processor core determined as the candidate core and the thread identification information of the processing target thread to the second prediction unit 19. When the multi-core processor 111 has three or more processor cores, the candidate core determination unit 17 includes two or more processor cores different from the processor core to which the processing target thread is assigned among the three or more processor cores. Are determined as candidate cores. The candidate core determination unit 17 outputs to the second prediction unit 19 two or more core identification information for identifying each of the two or more processor cores determined as candidate cores and the thread identification information of the processing target thread.

  The second prediction unit 19 receives the core identification information of the candidate core and the thread identification information of the processing target thread from the candidate core determination unit 17. The second prediction unit 19 predicts the second processing speed when the candidate core executes the processing target thread with the cache hit rate set to zero, and determines a set of the core identification information of the candidate core and the second processing speed. Output to. Here, the core identification information of the second processor core 55 is input. In this case, the second prediction unit 19 predicts the second processing speed when the second processor core 55 executes the target thread with the cache hit rate being 0%. Specifically, the second prediction unit 19 calculates the remaining power of the second processor core 55 based on the occupancy rates of all the threads assigned to the second processor core 55. A value obtained by subtracting the sum of the occupation ratios of all the threads allocated to the second processor core 55 from 100% is set as the remaining capacity of the second processor core 55. The second prediction unit 19 refers to the capability definition data predetermined for the capability information of the second processor core 55, and assumes that the processing target thread occupies all of the calculated remaining power of the second processor core 55. Then, the second processing speed is predicted. The capability definition data defines an occupation rate and a processing time for processing unit data for each of a plurality of cache hit rates. The second prediction unit 19 refers to the capability definition data corresponding to the cache hit rate of 0%, sets the remaining capacity as the occupation rate, and calculates a value obtained by dividing the data amount of the unit data by the processing time corresponding to the occupation rate. The second processing speed is determined. The second prediction unit 19 outputs a set of the core identification information of the second processor core and the second processing speed to the determination unit 21. In addition, when a plurality of core identification information is input from the candidate core determination unit 17, the second prediction unit 19 predicts the second processing speed for each of the plurality of processor cores identified by the plurality of core identification information, The processor core that maximizes the second processing speed is specified, and a set of the core identification information of the specified processor core and the second processing speed is output to the determination unit 21.

  The determination unit 21 receives a set of the core identification information of the processor core to which the processing target thread is assigned and the first processing speed from the first prediction unit 15, and receives the core identification information of the candidate core and the first core from the second prediction unit 19. A pair with two processing speeds is input. The determination unit 21 compares the first processing speed and the second processing speed, determines whether to change the allocation of the processing target thread, and outputs the determination result to the allocation change unit 23. The determination unit 21 determines whether or not to change the processing target thread assignment at predetermined time intervals. The determination unit 21 determines to change the allocation of the processing target thread if the second processing speed is higher than the first processing speed, but allocates the processing target thread if the second processing time is equal to or less than the first processing time. Judged not to change. The determination result indicates whether to change the assignment. When determining that the allocation is to be changed, the determination unit 21 outputs the core identification information of the candidate core to the allocation change unit 23 in addition to the determination result.

  Here, the determination unit 21 receives a set of the core identification information and the first processing speed of the first processor core 51 to which the processing target thread is assigned from the first prediction unit 15, and receives the candidate core from the second prediction unit 19. The set of the core identification information of the second processor core 55 and the second processing speed determined in the above is input. The determination unit 21 determines to change the allocation of the processing target thread if the second processing speed is higher than the first processing speed, and determines the determination result indicating that the allocation is to be changed and the core identification information of the second processor core 55. The data is output to the allocation changing unit 23. The determination unit 21 determines that the allocation of the processing target thread is not changed if the second processing speed is equal to or lower than the first processing speed, and outputs a determination result indicating that the allocation is not changed to the processing target thread determination unit 13.

  When the determination result indicating that the allocation is changed is input from the determination unit 21, the allocation change unit 23 inputs the processing target thread input from the processing target thread determination unit 13 together with the determination result from the determination unit 21. The second processor core specified by the core identification information is assigned. As a result, the variable thread that is the processing target thread that has been executed by the first processor core 51 is executed by the second processor core 55.

  The allocation changing unit 23 includes a processing unit determining unit 27. The processing unit determination unit 27 determines a processing unit when the processing target thread divides the image data into a plurality of processing unit parts. The assignment changing unit 23 changes the assignment in response to the completion of any one of the processing unit parts. For example, when the image data includes a plurality of pages, the processing unit determination unit 27 determines a portion of each of the plurality of pages as a processing unit portion. In this case, the assignment changing unit 23 sets the processing target thread assigned to the first processor core 51 to the second processing target thread in response to the completion of processing of any one of the plurality of pages included in the image data. Assign to the processor core.

  In addition, when the image data includes a plurality of lines, the processing unit determination unit 27 determines a part of each of the plurality of lines as a processing unit part. In this case, the assignment changing unit 23 sets the processing target thread assigned to the first processor core 51 as the second processing target thread in response to the completion of processing of any one of a plurality of rows included in the image data. Assign to the next processor core.

  Further, when the image data includes a plurality of attribute-specific data having different attributes, the processing unit determination unit 27 determines the plurality of attribute-specific data as processing unit portions. For example, when the image data includes a character area in which characters are represented, a line drawing area in which graphics are represented, and a photo area in which photographs are represented, the image data is attribute-specific data consisting only of character areas, and only graphics. And attribute-specific data consisting only of photographs. When the image data is color, the image data includes attribute-specific data consisting of only red, attribute-specific data consisting of only green, and attribute-specific data consisting of only blue. In this case, the assignment changing unit 23 performs processing in response to completion of processing of any attribute-specific data of the plurality of attribute-specific data included in the image data by the processing target thread assigned to the first processor core 51. The target thread is assigned to the second processor core.

  Further, when the target thread executes an encoding process for encoding image data, the processing unit determination unit 27 determines a unit part to be encoded as a processing unit part. In this case, when the processing target thread allocated to the first processor core 51 performs the encoding process on the image data, the allocation changing unit 23 selects any one of the plurality of unit parts to be encoded included in the image data. In response to the completion of the processing of the unit part, the processing target thread is assigned to the second processor core.

<Specific example>
Next, a specific example will be described in the case where the first processor core 51 and the second processor core 55 have the same capability.

  FIG. 6 is a first diagram for explaining the movement of the processing target thread. Referring to FIG. 6, when the cache hit rate of the first processor core 51 is 80% and the occupation rate of the processing target thread is 10%, refer to the capability definition data 205 with the cache hit rate of 80%. Then, since the processing time corresponding to the occupation rate of 10% is 1000 μs, the first processing speed is predicted to be 1 Mbute / μs. When the cache hit rate of the second processor core 55 is set to 0% and the capability definition data 201 with the cache hit rate of 0% is referred to, the occupation rate corresponding to the processing time of 1000 μs is 40%. For this reason, when the sum of the occupation ratios of all the threads allocated to the second processor core 55 is smaller than 60%, the second processing speed becomes larger than 1 Mbyte / μs. In other words, if the remaining capacity of the second processor core 55 is greater than 40%, the second processing speed is greater than 1 Mbyte / μs. For this reason, it is predicted that the processing target thread is terminated earlier when the processing target thread is executed by the second processor core 55 than when the processing target thread is continuously executed by the first processor core 51.

  FIG. 7 is a second diagram for explaining the movement of the processing target thread. Referring to FIG. 7, when the cache hit rate of the first processor core 51 is 40% and the occupation rate of the processing target thread is 20%, refer to the capability definition data 203 with the cache hit rate of 40%. Then, since the processing time corresponding to the occupation rate of 20% is 1000 μs, the first processing speed is predicted to be 1 Mbyte / μs. When the cache hit rate of the second processor core 55 is set to 0% and the capability definition data 201 with the cache hit rate of 0% is referred to, the occupation rate corresponding to the processing time of 1000 μs is 40%. For this reason, when the sum of the occupation ratios of all the threads allocated to the second processor core 55 is smaller than 60%, the second processing speed becomes larger than 1 Mbyte / μs. In other words, if the remaining capacity of the second processor core 55 is greater than 40%, the second processing speed is greater than 1 Mbyte / μs. For this reason, it is predicted that the processing target thread is terminated earlier when the processing target thread is executed by the second processor core 55 than when the processing target thread is continuously executed by the first processor core 51.

  FIG. 8 is a flowchart illustrating an example of the flow of load distribution processing. The load distribution process is performed by the multi-core processor 111 by executing one of the first processor core 51 and the second processor core 55 included in the multi-core processor 111 by executing a load distribution program stored in the ROM 113, HDD 115, or CD-ROM 118. It is a process to be executed. Referring to FIG. 8, multi-core processor 111 determines whether or not a predetermined time has elapsed (step S01). The predetermined time is an elapsed time after the execution of the process of step S01, an elapsed time after the execution of the load distribution process, and an elapsed time after the end of the load distribution process. The predetermined time can be arbitrarily determined. The process waits until a predetermined time elapses (NO in step S01). If the predetermined time elapses (YES in step S02), the process proceeds to step S02.

  In step S02, a variable thread is determined, and the process proceeds to step S03. One or more threads that are executed in each of the first processor core 51 and the second processor core 55 and that executes a process of converting image data are determined as variable threads. In step S03, the variable thread having the highest priority is set as the processing target thread among the one or more variable threads determined in step S02. When one variable thread is determined in step S02, the variable thread is set as a processing target thread. Here, a case where a variable thread assigned to the first processor core 51 is set as a processing target thread will be described as an example.

  In the next step S04, the processor core to which the processing target thread is assigned is determined as the target core, and the process proceeds to step S05. If the processing target thread is assigned to the first processor core 51, the first processor core 51 is determined as the target core, and if the processing target thread is assigned to the second processor core 55, the second processor core 55 is set as the target core. To decide. In step S05, state information of each of the first processor core 51 and the second processor core 55 is acquired. Specifically, the capability information and cache hit rate of each of the first processor core 51 and the second processor core 55, the occupation rate of each of one or more threads assigned to the first processor core 51, and the assignment to the second processor core 55 The occupation ratio of each of the one or more threads obtained is acquired.

  In step S06, the first processing time is predicted. The first processing speed at which the processing target thread is executed by the first processor core 51 to which the processing target thread is assigned is predicted. Assuming that the occupation rate acquired in step S05 for the processing target thread continues in the first processor core 51, corresponds to the cache rate acquired in step S05 of the capability definition data corresponding to the first processor core 51. Referring to the capability definition data to be processed, a value obtained by dividing the data amount of the unit data by the processing time corresponding to the occupation rate of the processing target thread is set as the first processing time.

  In the next step S07, a processor core other than the target core is selected, and the process proceeds to step S08. Here, since only the second processor core 55 exists in addition to the first processor core 51 that is the target core, the second processor core 55 is selected. If there are three or more processor cores, one is selected from two or more processor cores other than the target core.

  In the next step S08, the second processing time is predicted, and the process proceeds to step S09. The second processor core 55 selected in step S07 sets the cache hit rate to 0% and predicts the second processing speed for executing the variable thread set as the processing target thread in step S03. Specifically, the remaining capacity of the second processor core 55 is calculated based on the occupancy rates of all the threads assigned to the second processor core 55 acquired in step S05. A value obtained by subtracting the sum of the occupation ratios of all the threads allocated to the second processor core 55 from 100% is set as the remaining capacity of the second processor core 55. Then, among the capability definition data predetermined for the capability information of the second processor core 55, the capability definition data corresponding to the cache hit rate of 0% is referred to and the processing target thread is the second processor core 55. Assuming that all of the surplus power occupies the processing time of the second processor core 55, the surplus power is defined as the occupation rate, and a value obtained by dividing the data amount of the unit data by the processing time corresponding to the occupation rate is determined as the second processing speed. To do.

  In the next step S09, it is determined whether or not there is an unselected processor core in step S07. If there is an unselected processor core, the process returns to step S07; otherwise, the process proceeds to step S10. When the process proceeds to step S10, if the number of processor cores is three or more, the second processing time is determined for each of two or more processor cores other than the target core.

  In step S10, the processor core having the maximum second processing speed is set as a candidate core, and the process proceeds to step S11. In step S11, the first processing speed predicted in step S06 is compared with the second processing speed predicted for the processor core set as the candidate core in step S10. If the second processing speed is greater than the first processing speed, the process proceeds to step S12; otherwise, the process proceeds to step S15. In step S15, it is determined whether there is an unselected variable task. Of the variable threads determined in step S02, it is determined whether or not there is a variable thread that is not set as a processing target thread in step S03. If there is an unselected variable thread, the process returns to step S03; otherwise, the process returns to step S01.

  In step S12, a processing unit is determined. In step S03, a processing unit is determined based on processing executed by the variable thread set as the processing target thread or image data to be processed by the variable thread. When the image data includes a plurality of pages, a portion of each of the plurality of pages is determined as a processing unit portion. Further, when the image data includes a plurality of lines, a part of each of the plurality of lines is determined as a processing unit part. When the image data includes a plurality of attribute-specific data having different attributes, the plurality of attribute-specific data are determined as processing unit portions. When the process executed by the variable thread is an encoding process for encoding image data, a unit part to be encoded is determined as a processing unit part.

  In step S13, it is determined whether or not the processing unit determined in step S12 has been completed. In the processing target thread executed in the first processor core 51, the processing unit portion is in a standby state until the processing of the processing unit portion is completed. When the processing of the processing unit portion is completed, the processing proceeds to step S14.

  In step S14, the variable thread set as the processing target thread in step S03 is assigned to the processor core set as the candidate core in step S10, and the process returns to step S01. Here, the variable thread being executed by the first processor core 51 is assigned to the second processor core 55. As a result, the variable thread that has been executed by the first processor core 51 is executed by the second processor core 55. For this reason, the load of the first processor core 51 can be distributed to the second processor core 55.

  As described above, MFP 100 according to the present embodiment functions as an image processing apparatus, and based on the cache hit rate acquired for first processor core 51 to which a processing target thread is assigned, first processor core 51 has The first processing speed for executing the processing target thread is predicted, and the second processor core 55 determined as the candidate core predicts the second processing speed when the processing target thread is executed with the cache hit rate set to zero. The first processing speed is compared with the second processing speed, and when the second processing speed is higher than the first processing speed, the allocation of the processing target thread is changed from the first processor core 51 to the second processor core 55. For this reason, since the first processing speed before moving the target thread is compared with the second processing speed after moving the target thread, the processing speed for processing the target thread is expected to increase. The target thread is moved. As a result, it is possible to distribute the loads of the plurality of processor cores while shortening the processing time after the movement of the thread to be moved.

  One or more threads executed by the second processor core 55 by predicting the first processing speed based on the occupation rate of the processing target thread in the first processor core 51 and the cache hit rate of the first processor core 51. Since the second processing speed is predicted based on the remaining power of the second processor core 55 calculated from the respective occupancy rates, the processing speed before and after moving the processing target thread can be accurately predicted.

  Further, the first processing speed is predicted by referring to the capability definition data corresponding to the processing capability of the first processor core 51, and the second definition is referred to the capability definition data corresponding to the processing capability of the second processor core 55. Since the processing speed is predicted, even when the processing capacities of the first processor core 51 and the second processor core 55 are different, the load of a plurality of processor cores is distributed while shortening the processing time after movement of the thread to be moved. be able to.

  In addition, since it is determined at predetermined time intervals whether or not the allocation of the processing target thread is changed, it is possible to distribute the loads of the plurality of processor cores at predetermined time intervals.

  In addition, when processing image data to be processed by a processing target thread by dividing it into a plurality of processing unit parts, the processing target thread is allocated until processing of any processing unit part of the plurality of processing unit parts is completed. Since no change is made, it is possible to avoid the same process from being executed repeatedly before and after the movement.

  Also, a thread that executes a program that defines a process for converting image data is determined as a variable thread, and one of one or more variable threads is determined as a target thread. Therefore, a thread that executes a process that repeatedly executes the same process Can be determined as the target thread. In addition, the first processing speed and the second processing speed before and after the movement can be accurately predicted.

  Further, when there are a plurality of variable threads, the target threads are determined in descending order of priority, so that the variable threads with high priority can be terminated early.

  In the above-described embodiment, the MFP 100 has been described as an example of an image processing apparatus. However, a load distribution method for causing the MFP 100 to execute the load distribution process illustrated in FIG. The invention can be understood as a load distribution program to be executed by the multi-core processor 111 included in the MFP 100.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

<Appendix>
(1) The image processing apparatus according to claim 5, wherein when the image data includes a plurality of pages, the allocation changing unit determines a portion of each of the plurality of pages as a processing unit portion.
(2) The image processing apparatus according to (5) or (1), wherein, when the image data includes a plurality of rows, the allocation changing unit determines a portion of each of the plurality of rows as a processing unit portion.
(3) The allocation changing unit determines the plurality of attribute-specific data as processing unit parts when the image data includes a plurality of attribute-specific data having different attributes. ).
(4) The image according to claim 5, wherein, when the target thread executes an encoding process for encoding image data, the allocation changing unit determines a unit part to be encoded as a processing unit part. Processing equipment.

  100 MFP, 110 main circuit, 111 multi-core processor, 112 communication I / F unit, 113 ROM, 114 RAM, 115 HDD, 116 facsimile unit, 117 external storage device, 118 CD-ROM, 120 automatic document feeder, 130 document reading , 140 Image forming section, 150 Paper feed section, 160 Operation panel, 161 Display section, 163 Operation section, 165 Touch panel, 167 Hard key section, 11 Variable thread determination section, 13 Processing target thread determination section, 15 First prediction section 17 candidate core determination unit, 19 second prediction unit, 21 determination unit, 23 allocation change unit, 25 acquisition unit, 27 processing unit determination unit, 31 capability information acquisition unit, 33 hit rate acquisition unit, 35 occupancy rate acquisition unit, 51 First processor core, 53 first cache memory, 55 2 processor cores, 57 second cache memory.

Claims (9)

Multiple processor cores,
A plurality of cache memories respectively corresponding to the plurality of processor cores;
Target thread determination means for determining one of one or more threads assigned to the target core among the plurality of processor cores as a target thread;
Hit rate acquisition means for acquiring a cache hit rate for each of the plurality of processor cores;
First prediction means for predicting a first processing speed at which the target core executes the target thread based on the cache hit rate acquired for the target core by the hit rate acquisition means;
Second prediction means for predicting a second processing speed when a candidate core different from the target core among the plurality of processor cores executes the target thread with a cache hit rate of zero;
Determining means for determining whether to change the allocation of the target thread from the target core to the candidate core by comparing the first processing speed and the second processing speed;
An image processing apparatus comprising: an assignment changing unit that changes the assignment of the target thread from the target core to the candidate core based on a determination result by the determination unit. An occupancy rate acquisition means for acquiring an occupancy rate for each of one or more threads executed by each of the plurality of processor cores,
The first prediction unit is configured to determine the first processing speed based on the occupation rate of the target thread acquired by the occupation rate acquisition unit and the cache hit rate of the target core acquired by the hit rate acquisition unit. Predict
The second predicting unit predicts the second processing speed based on a surplus capacity of the candidate core calculated from an occupancy rate of each of one or more threads executed by the candidate core acquired by the occupancy rate acquiring unit. The image processing apparatus according to claim 1. A capability information acquisition means for acquiring the processing capability of the plurality of processor cores;
The first predicting means predicts the first processing speed based on the processing capability of the target thread;
The image processing apparatus according to claim 2, wherein the second prediction unit predicts the second processing speed based further on a processing capability of the candidate core.   The image processing apparatus according to claim 1, wherein the determination unit determines whether to change the allocation of the target thread from the target core to the candidate core at a predetermined time interval.   The allocation changing means, when dividing the image data to be processed by the target thread into a plurality of processing unit parts, processes the allocation of the target thread determined to change the allocation by the determining means. The image processing apparatus according to claim 1, wherein a thread changes according to completion of processing of any of the plurality of processing unit portions. Variable thread determination means for determining, as the variable thread, a thread that executes a program in which any one of the plurality of processor cores defines processing for converting image data;
The image processing apparatus according to claim 1, wherein the target thread determination unit determines one of one or more variable threads determined by the variable thread determination unit as a target thread.   The image processing apparatus according to claim 6, wherein the target thread determination unit determines a target thread in descending order of priority from the plurality of variable threads determined by the variable thread determination unit. A load balancing method executed by an image processing apparatus,
The image processing apparatus includes a plurality of processor cores,
A plurality of cache memories respectively corresponding to the plurality of processor cores,
A target thread determination step of determining one of one or more threads assigned to the target core among the plurality of processor cores as a target thread;
A hit rate acquisition step of acquiring a cache hit rate of each of the plurality of processor cores;
A first prediction step of predicting a first processing speed at which the target core executes the target thread based on the cache hit rate acquired for the target core in the hit rate acquisition step;
A second predicting step of predicting a second processing speed when a candidate core different from the target core among the plurality of processor cores executes the target thread with a cache hit rate of zero;
A determination step of determining whether or not to change the allocation of the target thread from the target core to the candidate core by comparing the first processing speed and the second processing speed;
A load distribution method comprising: an allocation changing step of changing the allocation of the target thread from the target core to the candidate core based on a determination result in the determining step. A load balancing program executed by a multi-core processor that controls the image processing apparatus,
The multi-core processor includes a plurality of processor cores,
A plurality of cache memories respectively corresponding to the plurality of processor cores,
A target thread determination step of determining one of one or more threads assigned to the target core among the plurality of processor cores as a target thread;
A hit rate acquisition step of acquiring a cache hit rate of each of the plurality of processor cores;
A first prediction step of predicting a first processing speed at which the target core executes the target thread based on the cache hit rate acquired for the target core in the hit rate acquisition step;
A second predicting step of predicting a second processing speed when a candidate core different from the target core among the plurality of processor cores executes the target thread with a cache hit rate of zero;
A determination step of determining whether or not to change the allocation of the target thread from the target core to the candidate core by comparing the first processing speed and the second processing speed;
A load distribution program that causes the multi-core processor to execute an allocation change step of changing the allocation of the target thread from the target core to the candidate core based on a determination result in the determination step.

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