JP2017167972A - Memory controller and method for controlling the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the reduction of data transfer efficiency occurring in order to obtain a preamble period.SOLUTION: In the memory controller for performing writing/reading between memories when requiring an access for performing writing from an external bus master to a memory or performing reading from the memory, a command issuing section comprises: a determination part for determining whether a second command succeeding a first command and having the same type as the first command is stored in a command queue when inputted as the first command from the command queue; and a control part for delaying the issue timing of the first command according to predetermined conditions when determining that the second command succeeding the first command in the determination part and having the same type as the first command is stored in the command queue.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a memory controller that controls a DRAM, and more particularly to a memory controller that controls a read command issue timing and a write command issue timing to a DRAM.

  In recent years, DDR4 SDRAM has been proposed that is faster than conventional DDR3 SDRAM. The DDR4 SDRAM operates in synchronization with a high-speed clock from 800 MHz to 1.6 GHz. In particular, in the DDR4 SDRAM that operates at a high speed of 1.3 GHz to 1.6 GHz, a function of setting a preamble period that starts a DQS signal, which is a synchronization signal of read data and write data, to 2 cycles before data transfer is supported. Yes. As the preamble period, one cycle or two cycles are selected by setting the mode register (see Non-Patent Document 1).

  In addition, the LPDDR4 SDRAM, which is a low power consumption DDR4 SDRAM, has a preamble period fixed to 2 cycles (see Non-Patent Document 2).

JEDEC STANDARD DDR4 SDRAM JESD79-4A JEDEC STANDARD LPDDR4 SDRAM JESD209-4

  In the DDR SDRAM, a read command or a write command is issued at a clock interval that is half or more of the burst length of the DRAM. When a read command or a write command is issued at a clock interval that is half the burst length of the DRAM, data transfer is continuous and data transfer efficiency is maximized.

  When a DDR3 SDRAM having a preamble period of 1 cycle is used with a burst length of 8, it is possible to issue a read command or a write command at an arbitrary interval of 4 cycles or more. However, when a DDR4 SDRAM having a preamble period of 2 cycles is used with a burst length of 8, it is necessary to issue a read command or a write command at intervals of 4 cycles or 6 cycles.

  DDR4 DRAM having a preamble period of 2 cycles needs to issue read commands and write commands at intervals of 5 cycles even when the memory controller can issue read commands and write commands at intervals of 5 cycles, and data transfer efficiency decreases.

In order to solve this problem, for example, a memory controller of the present invention has the following configuration. That is,
A memory controller for writing / reading to / from a memory,
When there is an access request for writing to or reading from the memory from an external bus master, command generation means for generating a command for the memory from the access request and storing it in a command queue;
Command issuing means for inputting a command from the command queue and issuing a command toward the memory;
The command issuing means includes
When the first command is input from the command queue, it is determined whether or not a second command of the same type as the first command is stored in the command queue subsequent to the first command. Discriminating means for discriminating;
If it is determined by the determining means that the second command of the same type as the first command is stored in the command queue following the first command, the issuing timing of the first command is set. And control means for delaying according to a predetermined condition.

  According to the present invention, for a DRAM having a preamble period of a plurality of cycles, the data transfer efficiency generated to secure the preamble period can be improved by delaying the timing of issuing the preceding command and continuously performing the data transfer. Reduction can be suppressed.

FIG. 3 is a diagram illustrating a configuration example of a memory controller according to the first embodiment. FIG. 3 is a diagram illustrating a configuration example of a command issuing circuit according to the first embodiment. The figure which shows the flow of a process at the time of the read command reception in embodiment. The figure which shows the flow of a process at the time of the read command issue in embodiment. The figure which shows a timing chart in case a read command continues. The figure which shows the flow of a process when a write command is received. The figure which shows the flow of a process at the time of issuing a write command. The figure which shows the timing chart in case a write command continues.

  Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

[First Embodiment]
FIG. 1 is a schematic configuration diagram of a memory controller 100 according to the first embodiment. The memory controller 100 is connected to an external bus (including a write data bus and a read data bus). The memory controller 100 is also connected to the DRAM 110, issues a command to the DRAM 110 in accordance with a request from a bus master (for example, CPU) on the external bus, and performs writing / reading with the DRAM 110. For example, when there is a write request to the DRAM 110 from the outside, the memory controller 100 issues (transmits) a write command to the DRAM 110, and subsequently transmits a write data synchronization signal and write data to the DRAM 110. When the memory controller 100 receives a read request from the external bus, the memory controller 100 issues a read command to the DRAM 110. As a result, since the read data synchronization signal and read data are output from the DRAM 110, the memory controller 100 receives the read data and outputs it on the external bus.

  This will be described in more detail. When the memory controller 100 receives a memory access request from the bus master on the external bus, the memory controller 100 stores the received memory access request in the command generation circuit 101. The command generation circuit 101 converts the received memory access request into a command, and transmits the converted command to the command queue 102. The command queue 102 stores not only commands generated by the command generation circuit 101 but also commands for executing DRAM refresh and calibration. The command issuing circuit 103 inputs the commands stored in the command queue 102 in order, and outputs (issues) the commands to the DRAM 110 according to the timing described below.

  The timer 106 observes the command issued by the command issuing circuit 103 in order to adjust the issuing interval of the command issued to the DRAM 110 to the DRAM specification, measures the elapsed time since the command issuance, and sends the measurement result to the command issuing circuit 103. Notice. The data rate measuring circuit 107 observes the data reading speed (transfer rate) of the read data bus of the external bus, and notifies the command issuing circuit 103 of the observation result as the data rate of the read data bus. The data rate measuring circuit 107 also observes the data write speed of the external bus and notifies the command issuing circuit 103 of the observation result as the data rate of the write data bus.

  The write data buffer 104 is a buffer for temporarily storing received write data and then transferring (writing) to the DRAM 110, and notifies the command issuing circuit 103 of the stored data amount. The read data buffer 105 is a buffer for temporarily storing the data output from the DRAM 110 and transmitting the data to the read data bus, and notifies the command issuing circuit 103 of the buffer free space.

  The synchronization signal generation circuit 108 generates a write data synchronization signal at the time of write transfer to the DRAM 110. The input / output switching circuit 109 transfers the write data transferred by the write data buffer 104 and the synchronization signal generated by the synchronization signal generation circuit 108 to the DRAM 110 during write transfer. At the time of read transfer, the read data and synchronization signal transferred by the DRAM 110 are transferred to the read data buffer 105. The command issuing circuit 103 receives a command from the command queue 102, controls the command transmission timing, and issues (transmits) the command to the DRAM 110.

  FIG. 2 is a block diagram of the command issuing circuit 103 in the first embodiment. The command issuing circuit 103 includes a timing prediction unit 801 and a command issuing unit 802. When the subsequent command is a read, the timing prediction unit 801 predicts the subsequent command issuance timing from the free space notified from the read data buffer 105 and the read data bus data rate notified from the data rate measurement circuit 107. To do. When the subsequent command is a write, the issue timing of the subsequent command is predicted from the write data buffer storage amount notified from the write data buffer 104 and the data rate of the write data bus notified from the data rate measuring circuit 107.

  The command issuing unit 802 determines the read command issue timing from the next command stored in the command queue 102, the measurement result of the timer 106, the free space notified from the read data buffer 105, and the prediction result notified from the timing prediction unit 801. To do. The command issuing unit 802 transmits a write command from the next command stored in the command queue 102, the measurement result of the timer 106, the data amount notified from the write data buffer 104, and the prediction result notified from the timing prediction unit 801. Determine timing.

  FIG. 3 is a flowchart illustrating a processing flow when the command issuing circuit 103 according to the first embodiment receives a read command from the command queue 102.

  When receiving the read command, the command issuing circuit 103 determines from the timer measurement result whether or not the received read command is issued to the DRAM 110 so as not to violate the DRAM timing constraint (S201). If the read command is issued and the timing constraint of the DRAM 110 is not violated, the command issue circuit 103 determines whether or not the read data buffer 105 has a space for storing the read data for one read command (S202). . If the read data buffer 105 has a space for one read command, the command issuing circuit 103 determines from the command information stored at the head of the command queue 102 whether the next command is also the same type of read command ( S203). If the next command is not a read command, or if it is determined that the next command is not stored in the command queue 102, the command issuing circuit 103 issues the received read command to the DRAM 110 (S204). . If the next command is also a read command, the command issuing circuit 103 controls the issue timing of the read command (S205). After the issue timing control process, the command issue circuit 103 issues the received read command to the DRAM 110 (S204).

  Next, the flow of the read command issue timing control process in S205 will be described with reference to the flowchart of FIG.

  The command issuing unit 802 determines whether the data rate of the read data bus is equal to or higher than the data rate of the DRAM 110 (S301). When the data rate of the read data bus is equal to or higher than the data rate of the DRAM 110, the command issuing unit 802 does not delay the command issue timing (S302).

  When the data rate of the read data bus is not equal to or higher than the data rate of the DRAM 110, the command issuing unit 802 determines whether the data rate of the read data bus is ½ or higher of the data rate of the DRAM 110 (S303). . It is assumed that the data rate of the read data bus is ½ or more of the data rate of the DRAM 110. In this case, does the command issuing unit 802 have a space for storing ½ or more of the read data for the subsequent read in the read data buffer 105 within the “preamble period−1” cycle by the DQS signal (data strobe signal)? Is predicted (S304). For example, when the preamble period is “3” and the burst length of the DRAM is “8”, the free space in the read data buffer 105 increases by 2 in two cycles. Therefore, at the determination timing, if the read data buffer has 2 or more free space in the read data buffer 105 for the subsequent read command, the free space in the read data buffer 105 after 2 cycles becomes 4 or more. Therefore, in the “preamble period−1” cycle, a space for storing 1.2 or more of the read data for the subsequent read is created in the read data buffer. If the condition is satisfied, the received command issuance is delayed until there is a free space in the read data buffer 105 for storing ½ or more of the read data for the subsequent read command (S305). As a result, the read data transfer for the delayed read command and the subsequent read command can be continuously performed without interposing the preamble period.

  On the other hand, if the condition is not satisfied, the command issue is not delayed (S302). This is because even if the read command is issued without delay, the preamble period is completed before the read data transfer is started for the subsequent read command, so that the data transfer efficiency is not lowered due to the preamble period.

  When the data rate of the read data bus is not ½ or more of the DRAM data rate, the command issuing unit 802 determines whether the data rate of the read data bus is ¼ or more of the DRAM data rate (S306). ). Assume that the data rate of the read data bus is ¼ or more of the data rate of the DRAM. In this case, the command issuing unit 802 predicts whether or not there is a free space in the read data buffer 105 for storing 3/4 or more of the read data for the subsequent read within the “preamble period-1” cycle (S307). For example, when the preamble period is 3 and the burst length of the DRAM is 8, the free space in the read data buffer 105 increases by 1 in 2 cycles. Therefore, at the determination timing, if the read data buffer 105 has 5 or more empty read data buffers for the subsequent read command, the read data buffer empty after 2 cycles becomes 6 or more. Therefore, in this case, in the “preamble period-1” cycle, a space for storing 3/4 or more of the read data for the subsequent read is created in the read data buffer. If the condition is satisfied, the command issuing unit 802 delays the received command issuance until there is a free space in the read data buffer 105 for storing 3/4 or more of the read data for the subsequent read (S308). If the condition is not satisfied, the command issue is not delayed (S302).

  If the data rate of the read data bus is not ¼ or higher than the data rate of the DRAM, command issue is not delayed (S302).

  Note that the predictions in S304 and S307 are performed on the assumption that the data rate of the read data bus at the time of prediction is constant from the prediction until the subsequent command is issued. Etc.

  Next, the operation of the conventional memory controller and the operation when the read command of the memory controller 100 of the present embodiment continues will be described with reference to FIG. For simplicity, FIG. 5 shows operation waveforms when the burst length of the DRAM 110 is 8, the preamble period is 3 cycles, and the data rate of the read data bus is constant at 1/2 the data rate of the DRAM. .

  First, the operation of the conventional memory controller will be described. The memory controller issues a read command RD0 at timing T1 (reference numeral 400). At timing T5, the free space in the read data buffer for the read command RD1 becomes 8. If the preamble period is 1, the memory controller can issue a read command RD1 at timing T5 (reference numeral 401). However, in order to ensure three cycles of the preamble period, the memory controller issues the read command RD1 at timing T8 (reference numeral 402). As a result, the read data transfer of the read command RD1 is completed at timing T18.

  Next, the operation of this embodiment will be described. When it is time to issue the read command RD0 at timing T1, the memory controller 100 confirms that the read data buffer 105 is free for the next read command RD1 (reference numeral 403). In the cycle at timing T1, there are two or more vacant spaces in the read data buffer 105, and therefore the memory controller 100 does not issue a read command at this stage. At timing T2, the free space in the read buffer 105 for the read command RD1 becomes 4, and the read command RD0 is issued (reference numeral 404). At timing T6, the memory controller 100 issues a read command RD1 (reference numeral 405). As a result, the read data transfer for the read commands RD0 and RD1 is continuous, and the transfer completion is at timing T16.

  As described above, when the read command continues, the command issuing unit 103 determines the subsequent command issue timing, the read data buffer fullness (read data buffer free space), the number of data strobe preamble cycles, The determination is made based on the burst length of one command and the data rate of the bus and memory. Then, the command issuing unit 103 delays the issue timing of the preceding command so that the read by the two commands is continuous. As a result, compared to the conventional example, the read data transfer by two commands can be completed two cycles earlier.

  Next, processing when the command issuing circuit 103 of the memory controller 100 of the first embodiment receives a write command from the command queue 102 will be described with reference to the flowchart of FIG.

  When receiving a write command from the command queue 102, the command issuing circuit 103 determines from the measurement result of the timer 106 whether or not the received write command is issued to the DRAM 110 so as not to violate the DRAM timing constraint (S501).

  If the write command is issued and the timing constraint of the DRAM 110 is not violated, the command issuing circuit 103 determines whether there is data to be written (write data) corresponding to the write command in the write data buffer 104 (S502). . When there is write data corresponding to the write command in the write data buffer 104, the command issuing circuit 103 determines whether the next command subsequent to the write command of interest stored at the head of the command queue 102 is also a write command ( S503).

  If the next command is not a write command, or if the next command is not stored in the command queue 102, the command issuing circuit 103 issues the received write command of interest (S504). On the other hand, if the next command is also a write command, the command issuing circuit 103 performs control processing for the issue timing of the write command of interest (S505). Then, the command issue circuit 103 issues the received write command of interest after the issue timing control processing (S504).

  Here, the flow of the write command issuance timing control in S505 will be described with reference to the flowchart of FIG.

  The command issuing circuit 103 determines whether the data rate of the write data bus is equal to or higher than the data rate of the DRAM 110 (S601). When the data rate of the write data bus is equal to or higher than the data rate of the DRAM 110, the command issue circuit 103 does not delay the command issue timing (S602).

  If the data rate of the write data bus is not equal to or higher than the data rate of the DRAM, the command issuing circuit 103 determines whether the data rate of the write data bus is ½ or higher of the data rate of the DRAM (S603). If it is ½ or more, the command issuing circuit 103 predicts whether or not ½ or more of the write data for the subsequent write command is stored in the write data buffer 104 within the “preamble period−1” cycle (S604). ). For example, when the preamble is 3 and the DRAM burst length is 8, two data are stored in the write data buffer 104 in two cycles. Therefore, if two or more pieces of write data for subsequent write transfers are stored at the determination timing, the number of write data stored after two cycles is four or more. Therefore, in this case, the command issuing circuit 103 determines that ½ or more of the write data for the subsequent write command is stored in the write data buffer 104 within the “preamble period−1” cycle.

  Therefore, when this condition is satisfied, the command issuing circuit 103 delays the command issuing timing until the write data for the subsequent write command is stored in the write data buffer 104 by ½ or more (S605). As a result, the write data transfer for the delayed write command and the subsequent write command is continuously performed without any preamble period.

  If the above condition is not satisfied, the command issuing circuit 103 does not delay the command issuing (S602). This is because even if the write command is issued without delay, the preamble period is completed before the write data transfer is started with respect to the subsequent write command, so that the data transfer efficiency is not lowered due to the preamble period.

  When the data rate of the write data bus is not 11/2 or higher than the data rate of the DRAM, the command issuing circuit 103 determines whether the data rate of the write data bus is 1/4 or higher than the data rate of the DRAM 110. (S606). If it is 1/4 or more, it is predicted whether 3/4 or more of the write data for the subsequent write command will be stored in the write data buffer 104 within the “preamble period-1” cycle (S607).

For example, if the preamble period is 3 and the DRAM burst length is 8, one write data is stored in the write data buffer 104 in two cycles. Therefore, if five or more pieces of write data for the subsequent write command are stored in the write data buffer 104 at the determination timing, the number of write data stored after two cycles is six or more. Therefore, in this case, the command issuing circuit 103 determines that 3/4 or more of the write data for the subsequent write command is stored in the write data buffer 104 within the “preamble period−1” cycle. When the condition is satisfied, the command issuing circuit 103 delays the command issuing timing until the data for the subsequent write command is stored in the write data buffer 104 for 3/4 transfer (S608). If this condition is not satisfied, the command issuing circuit 103 does not delay command issuing (S602).
If the data rate of the write data bus is not ¼ or more of the data rate of the DRAM, the command issuing circuit 103 does not delay the command issuing timing (S602).

  The predictions in S604 and S607 in FIG. 7 are performed on the assumption that the data rate of the write data bus at the time of prediction is constant from the prediction until the subsequent command is issued. May be.

  Next, with reference to FIG. 8, the operation of the conventional memory controller and the operation in the case where the write command of the memory controller of this embodiment continues will be described. 8 assumes that the burst length of the DRAM 110 is 8, the preamble period is 3 cycles, and the data rate of the write data bus is constant at 1/4 of the data rate of the DRAM 110.

  First, the operation of the conventional memory controller will be described. At timing T1, the memory controller issues a write command WR0 (reference numeral 700). At timing T5, the number of write data stored for the write command WR1 becomes 8. If the preamble period is 1, the memory controller can issue a write command WR1 at timing T6 (reference numeral 701). However, in order to ensure three cycles of the preamble period, the issue of the write command WR1 is at timing T8 (reference numeral 702). As a result, the write data transfer is completed at timing T18.

  Next, the operation of the memory controller 100 in this embodiment will be described. When the timing at which the write command QR0 can be issued at the timing T1, the memory controller 100 checks the number of write data stored for the next write command WR1 (reference numeral 703). In the cycle at the timing T1, there are five or more write data for the write command WR1, and therefore no write command is issued. At timing T5, the memory controller 100 issues the write command WR0 in response to the fact that the write data for the write command WR1 has become 6 (reference numeral 704). At timing T6, the memory controller 100 issues a write command WR1 (reference numeral 705). As a result, the write data transfer by the two write commands is continuous, and the transfer completion is at timing T16.

  As described above, when the write command continues, the command issuing unit 301 determines the issue timing of the subsequent command, the write data buffer fullness (write data buffer storage amount), the number of data strobe preamble cycles, and one command. Judgment is made based on the burst length and the data rate of the bus and memory. Then, the command issuing unit 103 delays the issuing timing of the preceding command so that the writing by the two commands is continuous. As a result, compared with the conventional example, the completion of the write data transfer by two commands is accelerated by “2” cycles.

  In the present embodiment, the memory controller has been described in which the subsequent command issue is prevented from being delayed in order to secure the preamble period by delaying the previous command issue when the read command or the write command continues.

  Since the preceding command issuance is delayed, the data transfer corresponding to the preceding command is slower than the conventional example. For this reason, for example, when the preceding command is a transfer command with a high priority, it is possible to prevent a transfer with a high priority from being delayed by not applying this embodiment. In addition, the transfer priority can be determined by, for example, attribute information of the transfer request.

DESCRIPTION OF SYMBOLS 100 ... Memory controller, 101 ... Command generation circuit, 102 ... Command queue, 103 ... Command issue circuit, 104 ... Write data buffer, 105 ... Read data buffer, 106 ... Timer, 107 ... Data rate measurement circuit, 108 ... Synchronization signal generation Circuit 109 ... Input / output switching circuit 110 ... DRAM

Claims (6)

A memory controller for writing / reading to / from a memory,
When there is an access request for writing to or reading from the memory from an external bus master, command generation means for generating a command for the memory from the access request and storing it in a command queue;
Command issuing means for inputting a command from the command queue and issuing a command toward the memory;
The command issuing means includes
When the first command is input from the command queue, it is determined whether or not a second command of the same type as the first command is stored in the command queue subsequent to the first command. Discriminating means for discriminating;
If it is determined by the determining means that the second command of the same type as the first command is stored in the command queue following the first command, the issuing timing of the first command is set. And a control means for delaying according to a predetermined condition.   The memory controller according to claim 1, wherein the memory is a DDR4 SDRAM. When both the first command and the second command are read commands from the memory, the control means
Issuing the second command based on the free space of the read data buffer for outputting the data output from the memory to the external bus, the number of data strobe preamble cycles, and the burst length of one command First determination means for determining timing;
Based on the result of the determination by the first determination means, data is output from the memory by the first command in the cycle immediately before the cycle in which data output from the memory is started by issuing the second command. 3. The memory controller according to claim 2, further comprising: a second determination unit configured to determine the issuance timing of the first command so that reading of the first command is completed. When both the first command and the second command are write commands to the memory, the control means
The issuance timing of the second command is determined based on the storage amount of the write data buffer for storing data to be written from the external bus to the memory, the number of data strobe preamble cycles, and the burst length of one command. First determination means;
Based on the determination result of the first determination means, in the cycle immediately before the cycle in which the output of the data stored in the write data buffer to the memory is started by issuing the second command, 3. The memory according to claim 2, further comprising: a second determination unit configured to determine an issue timing of the first command so that reading of data to the memory by the first command is completed. controller.   The second determination means determines the issuance timing of the first command by further referring to a transfer rate with the external bus and a transfer rate with the memory. Item 5. The memory controller according to Item 3 or 4. A method for controlling a memory controller for writing / reading to / from a memory,
A command generation step of generating a command for the memory from the access request and storing the command in the command queue when the command generation means has an access request for writing to or reading from the memory from an external bus master When,
A command issuing means for inputting a command from the command queue and issuing a command toward the memory;
The command issuing step includes
When the first command is input from the command queue, it is determined whether or not a second command of the same type as the first command is stored in the command queue subsequent to the first command. A discriminating step for discriminating;
If it is determined that the second command of the same type as the first command is stored in the command queue after the first command in the determination step, the issue timing of the first command is determined. And a control step of delaying according to a predetermined condition. A method for controlling a memory controller.

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