JP2017167644A - Data transfer device, data transfer method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that it is difficult to guarantee an execution sequence of DMA (Direct Memory Access) transfer with a simple configuration.SOLUTION: A data transfer device comprises transfer execution means which executes DMA transfer according to transfer information which has been set for executing DMA transfer. The transfer execution means stands by for a predetermined period of time after executing DMA transfer according to the transfer information, and then executes DMA transfer according to another transfer information.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a data transfer device, a data transfer method, and a program, and more particularly, to a data transfer device, a data transfer method, and a program that perform direct memory access.

  DMA (Direct Memory Access) is known as a technique for transferring data between memories and memories, between registers and memories, and between memories and I / O devices without going through a CPU (Central Processing Unit).

  As a technique related to the DMA, there is, for example, Patent Document 1. Patent Document 1 describes a DMA control device having a plurality of DMA request cores, an arbiter device, and a timer. According to Patent Literature 1, when a DMA request core issues a DMA request, the DMA request core transfers information indicating the DMA execution start request time together with the DMA transfer information to the arbiter device. Further, the arbiter device arbitrates the DMA execution order based on the DMA execution start request time. According to Patent Document 1, such a configuration enables efficient control.

JP 2006-215621 A

  In the case of the technique described in Patent Document 1, it is necessary to use an arbiter device in order to guarantee the DMA transfer execution order. For this reason, if the arbiter device is not provided, the DMA transfer execution order cannot be guaranteed. That is, in order to guarantee the execution order of DMA transfer, it is necessary to use an arbiter device, and it is difficult to guarantee the execution order of DMA transfer with an easy configuration.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer apparatus that solves the problem that it is difficult to guarantee the DMA transfer execution order with a simple configuration.

In order to achieve such an object, a data transfer apparatus according to one aspect of the present invention provides:
Transfer information for performing DMA (Direct Memory Access) transfer is set, and transfer execution means for performing DMA transfer based on the set transfer information is provided.
The transfer execution means adopts a configuration in which after performing a DMA transfer based on the transfer information, after waiting for a predetermined time, a DMA transfer based on another transfer information is performed.

In addition, a data transfer method according to another aspect of the present invention includes:
A data transfer method performed by a data transfer device,
Transfer information for performing DMA (Direct Memory Access) transfer is set, and DMA transfer is performed based on the set transfer information.
After performing the DMA transfer based on the transfer information, after waiting for a predetermined time, the DMA transfer based on another transfer information is performed.

Moreover, the program which is the other form of this invention is:
In the data transfer device,
Transfer information for performing DMA (Direct Memory Access) transfer is set, and transfer execution means for performing DMA transfer based on the set transfer information is realized.
The transfer execution means is a program for performing a DMA transfer based on another transfer information after performing a DMA transfer based on the transfer information and waiting for a predetermined time.

  The present invention, which is configured as described above, can provide a data transfer apparatus that solves the problem that it is difficult to guarantee the DMA transfer execution order with a simple configuration.

It is a block diagram showing an example of composition of a system concerning a 1st embodiment of the present invention. It is an example of the structure which the processor 21 shown in FIG. 1 has. It is a figure which shows an example of a structure of the DMA descriptor shown in FIG. It is a figure which shows an example of a structure of the DMA descriptor shown in FIG. It is a figure which shows an example of the operation | movement at the time of a general system performing DMA transfer. It is a figure which shows an example of the operation | movement at the time of the system which concerns on the 1st Embodiment of this invention guaranteeing an execution order and performing DMA transfer. It is a sequence diagram which shows an example of operation | movement of the system which concerns on the 1st Embodiment of this invention. It is a sequence diagram which shows an example of operation | movement of a general system. It is a sequence diagram which shows an example of other operation | movement of a general system. It is a schematic block diagram which shows an example of a structure of the data transfer apparatus which concerns on the 2nd Embodiment of this invention.

[First Embodiment]
A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram illustrating an example of the configuration of the system 1. FIG. 2 is an example of a configuration that the processor 21 has. 3 and 4 are diagrams illustrating an example of the configuration of the DMA descriptor 312. FIG. FIG. 5 is a diagram illustrating an example of an operation when a general system performs DMA transfer. FIG. 6 is a diagram illustrating an example of an operation when the system 1 according to the first embodiment of the present invention performs the DMA transfer while guaranteeing the execution order. FIG. 7 is a sequence diagram illustrating an example of the operation of the system 1. 8 and 9 are sequence diagrams illustrating an example of the operation of a general system.

  In the first embodiment of the present invention, a system 1 that performs DMA (Direct Memory Access) transfer will be described. The processor 21 of the system 1 in the present embodiment sets the DMA descriptor 312 when performing DMA transfer. As will be described later, the DMA descriptor 312 in the present embodiment can include a write request completion time indicating the time for which the DMA engine 311 that has executed a DMA transfer according to the DMA descriptor 312 waits until the next DMA transfer is performed. . When the write request completion time is included in the DMA descriptor 312, the DMA engine 311 executes the DMA transfer based on the DMA descriptor 312, waits for the write request completion time, and then executes the next DMA transfer.

  Referring to FIG. 1, a system 1 (data transfer device) according to the present embodiment includes a host PC (Personal Computer) 2 and an acceleration processor 3. In addition, the host PC 2 and the acceleration processor 3 are connected via a communication network 4 so that they can communicate with each other.

  The host PC 2 includes a processor 21 (control means) that executes arithmetic processing and a host memory 22 that stores information.

  The processor 21 in this embodiment has a DMA descriptor setting means 211 as shown in FIG. The DMA descriptor setting means 211 is realized by the processor 21 executing a program stored in a storage device (not shown).

  The DMA descriptor setting unit 211 sets a DMA descriptor 312 (transfer information), which will be described later, when executing DMA transfer (data transfer). For example, the DMA descriptor setting unit 211 sets the DMA descriptor 312 as shown in FIGS.

  Referring to FIG. 3, the DMA descriptor setting unit 211 sets a DMA descriptor 312 including information such as write data, a transfer source address, a transfer destination address, a transfer length, and a transfer request.

  Referring to FIG. 4, the DMA descriptor setting means 211 is added to the above configuration when the transfer source address (transfer source) and the transfer destination address (transfer destination) when executing the DMA transfer satisfy a predetermined condition. Then, the DMA descriptor 312 including items of write request completion time valid and write request completion time is set.

  For example, when the transfer source address and the transfer destination address exist within a predetermined range and the transfer destination address of the preceding DMA transfer is included in the subsequent transfer source address, the DMA descriptor setting unit 211 The DMA descriptor 312 for performing the DMA transfer is set as shown in FIG. In other words, the DMA descriptor setting unit 211 performs the DMA transfer for the address space in which the data transfer is guaranteed to be completed within a fixed time, and guarantees the execution order in FIG. The DMA descriptor 312 as shown is set.

  Further, the DMA descriptor setting unit 211 performs the series of DMA transfers when it is determined that the series of DMA transfers need to guarantee the execution order based on the transfer source address and the transfer destination address. Necessary settings are made for the same DMA descriptor 312 so that the same DMA engine 311 performs the same. For example, when performing DMA transfer in which the execution order is guaranteed, the DMA descriptor setting unit 211 sets the entry n + 1 for the same DMA descriptor 312 and then sets the entry n + 1. Note that n is an arbitrary value.

  As described above, the DMA descriptor setting unit 211 determines whether or not to guarantee the execution order based on the transfer source address and the transfer destination address. For example, when the transfer destination address of the preceding DMA transfer is included in the subsequent transfer source address (within a predetermined time from the preceding DMA transfer), the DMA descriptor setting unit 211 causes an address conflict between DMA transfers. Therefore, it is determined that it is necessary to guarantee the execution order.

  The item for which the write request completion time is valid indicates whether or not to wait for a predetermined time after performing a DMA transfer until the next DMA transfer is performed. When the write request completion time validity is set in the DMA descriptor 312, the DMA engine 311 performs a DMA transfer based on the DMA descriptor 312 and then waits for a predetermined time to perform the next DMA transfer. . On the other hand, when the write request completion time validity is not set in the DMA descriptor 312, the DMA engine 311 executes the DMA transfer without waiting between the DMA transfer. The write request completion time indicates a waiting time until the next DMA transfer is executed after the DMA transfer is executed. The write request completion time is determined in advance based on, for example, the time required to complete the data transfer when transferring data from the transfer source address to the transfer destination address.

  Based on the DMA descriptor 312 set by the processor 21 of the host PC 2, the acceleration processor 3 executes DMA transfer between the memory and the memory, between the register and the memory, between the registers and the register, etc. without going through the processor 21. That is, the acceleration processor 3 executes data transfer between the host memory 22 and the memory 33 or between the registers 321 and between the host memory 22 or the memory 33 and the registers 321 based on the DMA descriptor 312.

  Referring to FIG. 1, the acceleration processor 3 includes a DMA unit 31 that executes DMA transfer, a plurality of cores 32, and a memory 33. As shown in FIG. 1, the DMA unit 31 and the core 32, the core 32 and the memory 33, the core 32 and another core 32, and the memory 33 and the DMA unit 31 are connected so as to communicate with each other.

  The DMA unit 31 includes a plurality of DMA engines 311 (transfer executing means) and a plurality of DMA descriptors 312. The DMA unit 31 can process a plurality of DMA transfers in parallel by a plurality of DMA engines 311 and a plurality of DMA descriptors 312.

  The DMA engine 311 performs DMA transfer based on the DMA descriptor 312. If the DMA descriptor 312 includes a write request completion time, the DMA engine 311 performs a DMA transfer based on the DMA descriptor 312 and then waits for the write request completion time to perform the next DMA transfer.

  The DMA descriptor 312 indicates transfer information when executing DMA transfer. As described above, the DMA descriptor 312 includes write data, a transfer destination address, a transfer source address, a transfer request, and a transfer length (see FIG. 3). The DMA descriptor 312 can include a write request completion time valid (standby information) and a write request completion time (standby time information) (see FIG. 4).

  The DMA descriptor 312 is set by the DMA descriptor setting unit 211 of the processor 21 as described above. The DMA descriptor 312 is referred to by the DMA engine 311.

  The core 32 includes an address-mapped register 321 and an arithmetic unit 322. There are two types of access paths to the register 321, including an access path from the host PC 2 and an access path from the arithmetic unit 322 included in the core 32.

  The memory 33 is a storage device such as a RAM (Random Access Memory). The memory 33 is used for DMR transfer or the like.

  The system 1 has the above configuration, for example.

  In the system 1 described above, it is assumed that the register 321 included in the core 32 is mapped to a memory address space capable of DMA transfer. Further, when the transfer source address and the transfer destination address are within a predetermined range such as access from the DMA engine 311 to the register 321, the processing is completed within a fixed time.

  Assume that DMA transfers are performed in the order set in the DMA descriptor 312. On the other hand, since the plurality of DMA descriptors 312 are processed in parallel by the plurality of DMA engines 311, the execution order is not guaranteed. Further, even in the case of DMA transfer using the same DMA descriptor 312, if there is an address conflict between two DMA transfers, the execution order is not guaranteed in principle.

  The system 1 in this embodiment can guarantee the execution order in the DMA transfer using the same DMA descriptor 312 by setting the DMA descriptor 312 including the write request completion time as described above. Become.

  Next, an example of an operation when a general system and the system 1 described in the present embodiment perform DMA transfer using the same DMA descriptor 312 will be described with reference to FIGS.

  5 and 6, after the preceding DMA transfer transfers data from the address “0x1000” to the address “0x2000”, the subsequent DMA transfer transfers data from the address “0x2000” to the address “0x3000”. An example of the case is shown.

  Referring to FIG. 5, in the case of a general system, before the write process for the address “0x2000” is completed, the read process from the address “0x2000” by the subsequent DMA transfer is started. Therefore, the subsequent DMA transfer may not be able to read data reflecting the data of the previous DMA transfer. As described above, in a general system, data transfer cannot be reliably guaranteed between two DMA transfers.

  On the other hand, referring to FIG. 6, the preceding DMA descriptor 312 includes “0x1” indicating that the write request completion time is valid, and a write request completion time “0x100”. Therefore, in the case of FIG. 6, after executing the preceding DMA transfer, the DMM engine 311 waits for the write request completion time and executes the subsequent DMA transfer. Therefore, as shown in FIG. 6, after the write process for the address “0x2000” by the preceding DMA transfer is completed, the read process from the address “0x2000” by the subsequent DMA transfer is started. Thus, it can be seen that the system 1 can reliably guarantee data transfer between two DMA transfers.

  Next, an example of the operation of the system 1 will be described with reference to FIG. In FIG. 7, a case where two DMA transfers for which the execution order is to be guaranteed is performed will be described.

  Referring to FIG. 7, the DMA descriptor setting unit 211 of the processor 21 performs necessary settings for the same DMA descriptor 312. Specifically, the DMA descriptor setting unit 211 performs setting for instructing the preceding DMA transfer (step S101) and setting for instructing the subsequent DMA transfer (step S102). The DMA descriptor setting unit 211 performs setting including the write request completion time valid and the write request completion time when performing the preceding setting.

  When the DMA descriptor 312 is set, the DMA engine 311 of the acceleration processor 3 executes the DMA transfer based on the DMA descriptor 312 instructing the preceding DMA transfer (step S201). The DMA transfer is performed by issuing a DMA request and transferring data from the transfer source indicated by the DMA descriptor 312 to the transfer destination. And after the data transfer is complete. The DMA transfer is complete.

  The DMA engine 311 waits until the write request completion time elapses after executing the DMA transfer because the DMA descriptor 312 instructing the preceding DMA transfer includes the write request completion time. Then, after the write request completion time has elapsed, the DMA descriptor 312 for instructing the subsequent DMA transfer is executed (step S202).

  As described above, when the DMA descriptor 312 includes a write request completion time, the DMA engine 311 according to the present embodiment executes another DMA transfer after waiting for the write request completion time.

  In addition to the methods described in this embodiment, there are a confirmation method using polling (see FIG. 8) and a confirmation method using DMA transfer completion interrupt (see FIG. 9) as methods for guaranteeing the execution order of two DMA transfers. .

  As shown in FIG. 8, in the case of the confirmation method by polling, the processor 21 performs polling to confirm the end of the preceding DMA transfer. Therefore, the processor 21 is occupied to confirm the completion of the DMA transfer from the start of the first DMA transfer to the start of the second DMA transfer.

  As shown in FIG. 9, in the case of the confirmation method using the DMA transfer completion interrupt, when the DMA transfer is completed, the acceleration processor 3 notifies the host PC 2 of the DMA transfer completion interrupt. When the host PC 2 detects a DMA transfer completion interrupt, the processor 21 activates an interrupt handler process. At that time, the processor 21 needs to save the process and start a new process that were performed before the interrupt was detected. For this reason, there is a tendency that the latency until the DMA transfer completion notification, the host PC interrupt detection, and the subsequent DMA transfer start is deteriorated. The DMA transfer completion interrupt can only know that the DMA engine 311 has issued a DMA transfer request and has a small amount of information. Therefore, which DMA descriptor 312 is completed separately, or whether the data transfer is successful. It is necessary to confirm. As described above, even with the confirmation method based on the DMA transfer completion interrupt, there arises a problem that the latency is deteriorated.

  As described above, in the case of the confirmation method by polling or the confirmation method by DMA transfer completion interrupt, problems such as an increase in the occupied time of the processor 21 occur. On the other hand, as shown in FIG. 7, in the case of the system 1 described in the present embodiment, the DMA transfer execution order can be guaranteed without causing the processor 21 to occupy more time than necessary. That is, processor resources can be used efficiently.

  As described above, the system 1 according to this embodiment includes the DMA descriptor 312 and the DMA engine 311 including the write request completion time. With this configuration, when the DMA descriptor 312 includes a write request completion time, the DMA engine 311 performs a DMA transfer based on the DMA descriptor 312 and then waits for the write request completion time, and then waits for the next DMA. You can transfer. As a result, after the preceding DMA transfer is completed, the subsequent DMA transfer can be executed. As a result, the acceleration processor 3 can guarantee the execution order, and as a result, the processor 21 does not need to wait and can efficiently use processor resources.

  In the present embodiment, the case where the execution order of two DMA transfers is guaranteed has been described. However, the DMA transfer for which the system 1 guarantees the execution order is not limited to two. The system 1 can be configured to guarantee the execution order of three or more multiple DMA transfers.

  In this embodiment, the example in which the software determines whether or not the DMA transfer should guarantee the execution order such as address conflict between DMA transfers has been described. However, it may be configured to compare addresses between DMA transfers by hardware.

  In this embodiment, when the execution order of two DMA transfers is guaranteed, the write request completion time is included in the preceding DMA descriptor 312. However, the subsequent DMA descriptor 312 may include a configuration corresponding to the write request completion time. In this case, when the DMA engine 311 tries to perform DMA transfer based on the subsequent DMA descriptor 312, it waits for a predetermined time before performing DMA transfer.

  Further, the system 1 shown in FIG. 1 is merely an example. The system 1 may include a plurality of processors 21 or may include cores 32 other than four. A plurality of memories 33 may be provided. Further, the number of DMA engines 311 and the number of DMA descriptors 312 included in the DMA unit 31 are not particularly limited.

[Second Embodiment]
Next, a second embodiment will be described with reference to FIG. In the second embodiment, an outline of the configuration of the data transfer device 5 will be described.

  Referring to FIG. 10, the data transfer apparatus 5 according to the present embodiment includes a transfer execution unit 51.

  The transfer execution means 51 is set with transfer information for performing DMA transfer, and performs DMA transfer based on the set transfer information. The transfer execution means 51 performs the DMA transfer based on the transfer information and then performs the DMA transfer based on the other transfer information after waiting for a predetermined time.

  As described above, the data transfer device 5 according to the present embodiment includes the transfer execution unit 51. With this configuration, the transfer execution unit 51 can perform DMA transfer based on other transfer information after performing DMA transfer based on the set transfer information and then waiting for a predetermined time. As a result, after the preceding DMA transfer is completed, the subsequent DMA transfer can be executed. That is, the DMA transfer execution order can be guaranteed with an easy configuration.

  The data transfer device 5 can be realized by incorporating a predetermined program in the data transfer device 5. Specifically, in the program according to another aspect of the present invention, transfer information for performing DMA (Direct Memory Access) transfer is set in the data transfer apparatus, and transfer that performs DMA transfer based on the set transfer information is performed. Executing means is realized, and the transfer executing means is a program for performing DMA transfer based on other transfer information after performing DMA transfer based on transfer information and waiting for a predetermined time.

  Further, the data transfer method executed by the operation of the data transfer device 5 described above is a data transfer method performed by the data transfer device, in which transfer information for performing DMA (Direct Memory Access) transfer is set. In this method, the DMA transfer is performed based on the set transfer information, the DMA transfer is performed based on the transfer information, and after waiting for a predetermined time, the DMA transfer is performed based on another transfer information.

  Even the invention of the program or the data transfer method having the above-described configuration can achieve the above-described object of the present invention because it has the same operation as the above-described data transfer device 5.

<Appendix>
Part or all of the above-described embodiment can be described as in the following supplementary notes. The outline of the data transfer apparatus and the like in the present invention will be described below. However, the present invention is not limited to the following configuration.

(Appendix 1)
Transfer information for performing DMA (Direct Memory Access) transfer is set, and transfer execution means for performing DMA transfer based on the set transfer information is provided.
The transfer execution unit performs a DMA transfer based on the transfer information, performs a DMA transfer based on another transfer information after waiting for a predetermined time after performing a DMA transfer based on the transfer information.

(Appendix 2)
The data transfer device according to attachment 1, wherein
The transfer execution means waits for a predetermined time after performing DMA transfer based on the transfer information when the transfer information including standby information for waiting for execution of the next DMA transfer for a predetermined time is set. A data transfer apparatus that performs DMA transfer based on the transfer information.

(Appendix 3)
The data transfer device according to appendix 1 or 2,
When the transfer information including the waiting time information indicating the waiting time until the next DMA transfer is set, the transfer executing means performs the DMA transfer based on the transfer information, and then executes the transfer information. A data transfer apparatus that waits for the time indicated by the waiting time information included in the data and performs DMA transfer based on the other transfer information.

(Appendix 4)
The data transfer device according to attachment 3, wherein
The waiting time information indicates a time required for completing the transfer of data from the transfer source to the transfer destination, which is executed by DMA transfer.

(Appendix 5)
A data transfer device according to any one of appendices 1 to 4,
A data transfer device comprising control means for setting the transfer information.

(Appendix 6)
The data transfer device according to attachment 5, wherein
The control unit sets the transfer information including waiting time information indicating a waiting time until the next DMA transfer is executed when a transfer source and a transfer destination in executing the DMA transfer satisfy a predetermined condition. Data transfer device.

(Appendix 7)
The data transfer device according to attachment 6, wherein
The control means performs the preceding DMA transfer when the transfer source and the transfer destination are within a predetermined range and the transfer destination of the preceding DMA transfer is included in the transfer source of the subsequent DMA transfer. A data transfer apparatus for including the waiting time information in the transfer information for

(Appendix 8)
A data transfer device according to any one of appendices 5 to 7,
It has multiple transfer execution means,
The control unit is set so that the same transfer execution unit executes a plurality of pieces of transfer information for performing a series of DMA transfers when it is determined as a series of DMA transfers based on a transfer source and a transfer destination. Data transfer device.

(Appendix 9)
A data transfer method performed by a data transfer device,
Transfer information for performing DMA (Direct Memory Access) transfer is set, and DMA transfer is performed based on the set transfer information.
A data transfer method for performing DMA transfer based on another transfer information after performing a DMA transfer based on the transfer information and waiting for a predetermined time.

(Appendix 9-1)
A data transfer method according to attachment 9, wherein
When the transfer information including standby information for waiting for execution of the next DMA transfer for a predetermined time is set, after performing data transfer based on the transfer information, wait for a predetermined time, A data transfer method for performing DMA transfer based on transfer information.

(Appendix 9-2)
A data transfer method according to appendix 9 or appendix 9-1,
When the transfer information including the waiting time information indicating the waiting time until the next DMA transfer is set, the waiting time included in the transfer information after performing the DMA transfer based on the transfer information A data transfer method for waiting for the time indicated by the information and performing DMA transfer based on the other transfer information.

(Appendix 10)
In the data transfer device,
Transfer information for performing DMA (Direct Memory Access) transfer is set, and transfer execution means for performing DMA transfer based on the set transfer information is realized.
The transfer execution means performs a DMA transfer based on the transfer information after performing a DMA transfer based on the transfer information and then waiting for a predetermined time.

(Appendix 10-1)
The program according to attachment 10, wherein
The transfer execution means performs data transfer based on the transfer information when the transfer information including standby information for waiting for execution of the next DMA transfer for a predetermined time after the DMA transfer is set. A program for performing a DMA transfer based on another transfer information after waiting for a predetermined time.

(Appendix 10-2)
The program according to Supplementary Note 10 or Supplementary Note 10-1,
When the transfer information including the waiting time information indicating the waiting time until the next DMA transfer is set, the transfer executing means performs the DMA transfer based on the transfer information, and then executes the transfer information. A program that waits for the time indicated by the waiting time information included in and performs DMA transfer based on the other transfer information.

  The programs described in the above embodiments and supplementary notes are stored in a storage device or recorded on a computer-readable recording medium. For example, the recording medium is a portable medium such as a flexible disk, an optical disk, a magneto-optical disk, and a semiconductor memory.

  Although the present invention has been described with reference to the above embodiments, the present invention is not limited to the above-described embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

1 System 2 Host PC
21 processor 211 DMA descriptor setting means 22 host memory 3 acceleration processor 31 DMA unit 311 DMA engine 312 DMA descriptor 32 core 321 register 322 calculator 33 memory 4 communication network 5 data transfer device 51 transfer execution means

Claims (10)

Transfer information for performing DMA (Direct Memory Access) transfer is set, and transfer execution means for performing DMA transfer based on the set transfer information is provided.
The transfer execution unit performs a DMA transfer based on the transfer information, performs a DMA transfer based on another transfer information after waiting for a predetermined time after performing a DMA transfer based on the transfer information. The data transfer device according to claim 1,
The transfer execution means waits for a predetermined time after performing DMA transfer based on the transfer information when the transfer information including standby information for waiting for execution of the next DMA transfer for a predetermined time is set. A data transfer apparatus that performs DMA transfer based on the transfer information. The data transfer device according to claim 1 or 2,
When the transfer information including the waiting time information indicating the waiting time until the next DMA transfer is set, the transfer executing means performs the DMA transfer based on the transfer information, and then executes the transfer information. A data transfer apparatus that waits for the time indicated by the waiting time information included in the data and performs DMA transfer based on the other transfer information. The data transfer device according to claim 3, wherein
The waiting time information indicates a time required for completing the transfer of data from the transfer source to the transfer destination, which is executed by DMA transfer. The data transfer device according to any one of claims 1 to 4,
A data transfer device comprising control means for setting the transfer information. The data transfer device according to claim 5, wherein
The control unit sets the transfer information including waiting time information indicating a waiting time until the next DMA transfer is executed when a transfer source and a transfer destination in executing the DMA transfer satisfy a predetermined condition. Data transfer device. The data transfer device according to claim 6, wherein
The control means performs the preceding DMA transfer when the transfer source and the transfer destination are within a predetermined range and the transfer destination of the preceding DMA transfer is included in the transfer source of the subsequent DMA transfer. A data transfer apparatus for including the waiting time information in the transfer information for The data transfer device according to any one of claims 5 to 7,
It has multiple transfer execution means,
The control unit is set so that the same transfer execution unit executes a plurality of pieces of transfer information for performing a series of DMA transfers when it is determined as a series of DMA transfers based on a transfer source and a transfer destination. Data transfer device. A data transfer method performed by a data transfer device,
Transfer information for performing DMA (Direct Memory Access) transfer is set, and DMA transfer is performed based on the set transfer information.
A data transfer method for performing DMA transfer based on another transfer information after performing a DMA transfer based on the transfer information and waiting for a predetermined time. In the data transfer device,
Transfer information for performing DMA (Direct Memory Access) transfer is set, and transfer execution means for performing DMA transfer based on the set transfer information is realized.
The transfer execution means performs a DMA transfer based on the transfer information after performing a DMA transfer based on the transfer information and then waiting for a predetermined time.

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