JP2017163329A - Device, storing method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem in which a manufacture of a general communication device including a device in a patent literature 1 cannot sufficiently prepare an environment under which a fault has occurred when a reproduction test is conducted.SOLUTION: A device comprises: a memory for storing storage data corresponding to data input by communication; a detection unit for detecting a fault involved in the communication; and a storage unit for sequentially storing the storage data in the memory but stopping storing when the detection unit detects a fault.SELECTED DRAWING: Figure 9

Description

  The present invention relates to an apparatus, a storage method, and a program, and more particularly, to an apparatus, a storage method, and a program for storing data.

  In general, an apparatus for storing data is known. An apparatus for storing data is disclosed in Patent Document 1 below. FIG. 1 is a configuration diagram of an apparatus disclosed in Patent Document 1.

  The device of Patent Document 1 is a device that records music data on an MD (Mini Disc). For this purpose, the apparatus of Patent Document 1 includes a main processing unit and an MD recorder, as shown in FIG. The MD recorder is loaded with an MD (Mini Disc).

  When an operation for purchasing music data is performed, the main processing unit of Patent Document 1 transmits a download request command to the MD recorder. When the MD recorder receives the download request command, the MD recorder measures the error rate using the loaded MD as a measurement target, and returns the measured error rate to the main processing unit. When the returned error rate is smaller than a predetermined value, the main processing unit of Patent Document 1 estimates that data can be recorded in the MD, and downloads music data to the MD recorder. The MD recorder records the downloaded music data on the MD. On the other hand, when the returned error rate is greater than or equal to a predetermined value, the main processing unit of Patent Document 1 estimates that a recording error occurs in the MD and instructs the MD recorder to eject the MD. The MD recorder ejects the MD.

  As described above, the apparatus disclosed in Patent Document 1 can prevent an MD that has a possibility of a recording error from being generated and an MD in which music data cannot be recorded from being generated. As shown in FIG. 1, the device of Patent Document 1 is also a communication device because it is connected to a communication network and performs communication.

  A communication device generally transmits and receives packets. In general, when a communication apparatus receives a packet, the communication apparatus temporarily stores the received packet in a buffer in the apparatus. This is because the received packet is reliably processed in the apparatus. When the newly received packet is stored in the buffer, the communication device overwrites and stores the oldest packet.

  By the way, the manufacturer of the communication device investigates the cause when a communication failure occurs in the communication device. When investigating the cause, the manufacturer of the communication device prepares the environment where the failure occurred as much as possible, and performs a reproduction test to reproduce the failure. This is because if the failure can be reproduced by the reproduction test, it is possible to narrow down in a short time where the communication device is the cause.

JP 2003-331537 A

  However, there has been a problem that general communication device manufacturers (including the device manufacturer of Patent Document 1) cannot sufficiently prepare an environment in which a failure has occurred when performing a reproduction test.

  This is because the communication device overwrites the buffer with a newly received packet and does not store the packet at the time of failure in the buffer. Since the communication device does not store the packet when the failure occurs, the manufacturer of the communication device cannot obtain the packet when the failure occurs. As a result, the manufacturer of the communication device cannot use the packet at the time of the failure in the reproduction test when performing the reproduction test, and cannot sufficiently prepare the environment in which the failure has occurred.

  In addition, the communication device manufacturer cannot sufficiently prepare the environment in which the failure has occurred, so even if the reproduction test is performed, the failure cannot be reproduced, and much time is required to narrow down the suspected place. There was a risk of this.

  An object of this invention is to provide the apparatus, the preservation | save method, and program which solve the said subject.

  In order to achieve the above object, an apparatus according to the present invention includes a memory that stores storage data corresponding to data input by communication, a detection unit that detects a failure related to the communication, and sequentially stores the storage data. And a storage unit that stores in the memory and stops the storage when the detection unit detects the failure.

  In order to achieve the above object, the storage method of the present invention includes a storage step of sequentially storing data corresponding to data input by communication in a memory, and storing the storage when a failure related to the communication is detected. And a stop step for stopping.

  To achieve the above object, a program according to the present invention includes a storage process for sequentially storing data corresponding to data input by communication in a processor mounted in a communication device including a memory, This is a program for performing a detection process for detecting a communication-related failure and a storage stop process for stopping the storage process when the detection process detects the failure.

  According to the present invention, a manufacturer of a communication device can sufficiently prepare an environment in which a failure has occurred when performing a reproduction test.

2 is a configuration diagram of an apparatus disclosed in Patent Document 1. FIG. It is a figure which shows the structural example of the communication apparatus in the 1st Embodiment of this invention. It is a figure which shows the flow (the flow before a failure generate | occur | produces) of the data in the communication apparatus in the 1st Embodiment of this invention, and a signal. It is a figure which shows the flow (data when a failure generate | occur | produces) of the data and signal in the communication apparatus in the 1st Embodiment of this invention. It is a figure which shows the structural example of the integrated circuit of the communication apparatus in the 1st Embodiment of this invention. It is a figure for demonstrating operation | movement of the communication apparatus in the 1st Embodiment of this invention. It is a figure for demonstrating operation | movement (operation | movement implemented when a failure generate | occur | produces) of the communication apparatus in the 1st Embodiment of this invention. It is a figure which shows the structural example of the communication apparatus in the 2nd Embodiment of this invention. It is a figure which shows the structural example of the apparatus in the 3rd Embodiment of this invention.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

<< First Embodiment >>
[Overview]
Each time the communication apparatus according to the present embodiment receives a packet, the communication apparatus stores the received packet in a buffer in the apparatus. When the communication apparatus according to the present embodiment detects a failure in its own apparatus, thereafter, the communication apparatus discards the received packet and does not store it in the buffer. As a result, the communication apparatus does not newly store the packet in the buffer, and stores the packet at the time of failure occurrence in the buffer.

  Since the communication device stores the packet when the failure occurs, the manufacturer of the communication device can acquire the packet when the failure occurs. As a result, the manufacturer of the communication device can use the packet at the time of the failure when performing the reproduction test, and can sufficiently prepare the environment where the failure has occurred.

  The configuration, function, and operation of the communication device according to the first embodiment of the present invention will be described below.

[Description of configuration]
First, the configuration and function of the communication device according to the first embodiment of the present invention will be described. FIG. 2 is a diagram illustrating a configuration example of the communication device according to the first embodiment of the present invention.

(1) Configuration of Communication Device in First Embodiment of Present Invention As shown in FIG. 2, the communication device of the present embodiment includes an integrated circuit 1, 2, 3 and a CPU (Central Processing Unit) 4. , CF (Compact Flash (registered trademark)) 5.

  The integrated circuits 1, 2, and 3 include internal memories 10, 20, and 30, respectively. The integrated circuit 1 includes an external memory 11 and an external memory 12, and the integrated circuits 2 and 3 include external memories 21 and 31, respectively. Although not shown, the integrated circuit 1 includes a general input / output port for connection to an external communication device.

  The integrated circuits 1, 2, and 3 are connected via two types of lines, a data line and a control line, respectively. The integrated circuits 1, 2, and 3 are connected to the CPU 4 and the CF 5 via the CPU bus. The integrated circuit 1 is connected to an external communication device via an input / output port.

(2) Functions of Integrated Circuits 1, 2, and 3 FIGS. 3 and 4 are diagrams showing the flow of data and signals in the communication device according to the first embodiment of the present invention. 3 shows the flow of data and signals in the communication device before the failure occurs, and FIG. 4 shows the flow of data and signals in the communication device when the failure occurs.

  Hereinafter, functions of the integrated circuits 1, 2, and 3 will be described with reference to FIGS. Since the integrated circuits 1, 2, and 3 have the same function, the function of the integrated circuit 1 will be described as a representative. However, for some functions, the functions of the integrated circuits 2 and 3 are also described so that the subsequent description can be easily understood.

(2-1) Function of Granting Packet Transmission Permission First, as shown in FIG. 3, when the integrated circuit 1 is activated, it outputs an enable signal that grants transmission permission to the integrated circuits 2 and 3 to be connected. . The integrated circuits 2 and 3 also output an enable signal to the integrated circuit 1 when activated.

(2-2) Function for Recognizing that Packet Transmission Permission has been Provided The integrated circuit 1 includes two registers (hereinafter referred to as “register A” and “register B”), although not shown. When the integrated circuit 1 receives the enable signal from the integrated circuit 2, the integrated circuit 1 sets the value 1 in the register A. When the integrated circuit 1 receives the enable signal from the integrated circuit 3, the integrated circuit 1 sets the value 1 in the register B.

  The integrated circuits 2 and 3 also include a register, and when the enable signal is received from the connected integrated circuit 1, the value 1 is set in the register. The registers of the integrated circuits 2 and 3 are hereinafter referred to as “register C” in order to distinguish them from the registers of the integrated circuit 1. The value 1 is a value indicating that transmission permission is given from the connected integrated circuit. The initial values of registers A, B, and C are zero.

(2-3) Packet Storage Function The integrated circuit 1 communicates with an external communication device. By communication, the integrated circuit 1 receives a packet from an external communication device as shown in FIG. The integrated circuit 1 stores the received packet in the internal memory 10. The internal memory 10 is a buffer. When the integrated circuit 1 stores the packet in the internal memory 10, the newly received packet is overwritten and stored on the oldest packet. The internal memory 10 is updated with newly received packets.

  The integrated circuit 1 also receives packets from the integrated circuits 2 and 3, as shown in FIG. The integrated circuit 1 stores the received packet in the external memory 11 when receiving the packet from the integrated circuit 2, and stores the received packet in the external memory 12 when receiving the packet from the integrated circuit 3. The external memories 11 and 12 are buffers that temporarily store received packets. When the integrated circuit 1 stores the packet in the external memories 11 and 12, the newly received packet is overwritten and stored on the oldest packet. The external memories 11 and 12 are updated with newly received packets.

  The “(2-3) packet storage function” described above operates independently of the functions of the other integrated circuits 1.

(2-4) Packet Transmission Function The integrated circuit 1 determines whether or not the value of the register A is 1, that is, whether or not transmission permission is given from the integrated circuit 2 at a predetermined timing. The predetermined timing is a timing at regular intervals, and is set in the integrated circuit 1 by the manufacturer of the communication device. The manufacturer of the communication device according to the present embodiment may set the integrated circuit 1 at any timing as long as the timing is constant.

The integrated circuit 1 transmits the packet stored in the internal memory 10 to the integrated circuit 2 when the value of the register A is 1, that is, when the transmission permission is given from the integrated circuit 2.
The integrated circuit 1 does not transmit the packet to the integrated circuit 2 when the value of the register A is not 1.

  Further, the integrated circuit 1 determines whether or not the value of the register B is 1, that is, whether or not transmission permission is given from the integrated circuit 3. The integrated circuit 1 transmits a packet stored in the internal memory 10 to the integrated circuit 3 when the value of the register B is 1, that is, when transmission permission is given from the integrated circuit 3. The integrated circuit 1 does not transmit the packet to the integrated circuit 3 when the value of the register B is not 1.

  Further, after determining whether or not the value of the register B is 1, the integrated circuit 1 stores the packet in the external memories 11 and 12 and transmits the stored packet to an external communication device via the input / output port. Send to.

  The “(2-4) packet transmission function” described above operates independently of the functions of the other integrated circuits 1.

(2-5) Fault Detection Function The integrated circuit 1 detects a fault related to communication with an external communication device.

  For example, the integrated circuit 1 has a failure of a functional unit related to communication with an external communication device (specifically, as shown in “(2-5-1) Function of detecting device failure” below) (Failure of input / output port) may be detected.

  Further, the integrated circuit 1 may detect a failure of the internal memory 10 as shown in “(2-5-2) Function of detecting a memory failure” below. The internal memory 10 is a memory that stores a packet received by communication with an external communication device, and is a functional unit related to communication with the external communication device.

  Further, the integrated circuit 1 detects a failure in which a packet received from an external communication device is broken in the communication device 1 as shown in “(2-5-3) Function for detecting a failure in which a packet is broken” below. May be.

(2-5-1) Function for detecting device failure (an example of a failure detection function)
The integrated circuit 1 may detect a failure of the input / output port. In this case, the integrated circuit 1 has a general port monitoring function, and transmits an ICMP (Internet Control Message Protocol) echo request to the input / output port at regular intervals. After transmitting the echo request, the integrated circuit 1 waits for an echo response to the echo request to return from the input / output port. When the integrated circuit 1 does not return an echo response within a predetermined time after transmission, the integrated circuit 1 considers that a failure (failure of the input / output port) has been detected, and outputs an electrical signal indicating failure detection to the CPU 4.

  The predetermined time described above is set in the integrated circuit 1 by the manufacturer of the communication apparatus of the present embodiment. The manufacturer of the communication apparatus according to the present embodiment actually measures the time until the echo response is returned after transmitting the echo request, and sets the time sufficiently longer than the actually measured time in the integrated circuit 1 as a predetermined time. Moreover, any time may be sufficient as the above-mentioned fixed time.

(2-5-2) Function for detecting a memory failure (an example of a failure detection function)
The integrated circuit 1 may detect a failure of the internal memory 10. In that case, when storing the received packet in the internal memory 10, the integrated circuit 1 once writes a predetermined value (for example, 0x5555) in the internal memory 10 and determines whether or not the written value (0x5555) can be read. Determine. The integrated circuit 1 stores the received packet when the written value (0x5555) can be read. If the written value (0x5555) cannot be read, the integrated circuit 1 considers that a failure (memory failure) has been detected, and outputs an electrical signal indicating failure detection to the CPU 4.

(2-5-3) Function for detecting failure where packet is broken (an example of failure detection function)
The integrated circuit 1 may detect a failure in which the packet is broken in the self-device.

  In that case, the integrated circuit 1 includes two registers. The two registers are hereinafter referred to as “failure detection register A” and “failure detection register B”. The initial value of the failure detection registers A and B is 0. When the integrated circuit 1 receives the packet, the integrated circuit 1 calculates a checksum included in the received packet before it is stored in the internal memory 10, and determines whether or not the calculated value is a normal value. The normal value is preset in the integrated circuit 1 by the manufacturer of the integrated circuit 1. The integrated circuit 1 writes 1 in the failure detection register A when the calculated value is not a normal value. The integrated circuit 1 writes 0 in the failure detection register A when the calculated value is a normal value.

  Further, when transmitting a packet, the integrated circuit 1 calculates a checksum included in the acquired packet when acquiring the packet from the external memories 11 and 12, and determines whether the calculated value is a normal value. The normal value is preset in the integrated circuit 1 by the manufacturer of the integrated circuit 1. The integrated circuit 1 writes 1 in the failure detection register B when the calculated value is not a normal value. The integrated circuit 1 writes 0 in the failure detection register B when the calculated value is a normal value.

  When the failure detection register A is 0 (that is, the packet at the time of reception is normal), but the failure detection register B is 1 (that is, the packet at the time of transmission is not normal), the integrated circuit 1 A signal is output to the CPU 4. This is because a failure that breaks the packet has occurred in its own device.

  The integrated circuit 1 is not limited to the functions shown in the above (2-5-1) to (2-5-3) as long as it has a failure detection function, and may have any function.

(2-6) Packet Storage Stop Function The integrated circuit 1 detects a failure, and when a signal indicating the occurrence of the failure is input from the CPU 4, thereafter, the received packet is discarded as shown in FIG. As a result, the integrated circuit 1 stops storing a new packet in the internal memory 10. Since the internal memory 10 is not updated with a newly received packet, the internal memory 10 stores a packet when a failure occurs.

  Further, the integrated circuit 1 outputs a disable signal not permitting transmission to the connected integrated circuits 2 and 3 as shown in FIG. 4 after a signal indicating the occurrence of a failure is input from the CPU 4. The integrated circuits 2 and 3 that have received the disable signal set the value of the register C included in the integrated circuits 2 and 3 to 0, and stop transmission of packets to the integrated circuit 1.

  The integrated circuit 1 does not receive packets from the integrated circuits 2 and 3. As a result, the integrated circuit 1 does not newly store the packet in the external memories 11 and 12, but stores the packet when the failure occurs.

(2-7) Function for Outputting Packet to CF 5 When the integrated circuit 1 receives a signal for instructing packet transfer from the CPU 4, the integrated circuit 1 outputs the packet at the time of failure stored in the internal memory 10 or the external memories 11 and 12 to the CF 5 Save to. At this time, the integrated circuit 1 transfers and stores the packet at the time of failure from the internal memory 10 or the external memories 11 and 12 to the CF 5 by DMA transfer. DMA is an abbreviation for Direct Memory Access.

(3) Configuration of Integrated Circuits 1, 2, and 3 (3-1) Functional Units of Integrated Circuits 1, 2, and 3 FIG. 5 is a diagram for explaining a configuration example of the integrated circuits 1, 2, and 3.

  In order to realize the functions (2-1) to (2-7) described above, the integrated circuits 1, 2, and 3 include a storage processor, a transmission processor, and a signal processing circuit as shown in FIG. .

  The storage processor implements the above-mentioned “(2-3) packet storage function”, “(2-6) packet storage stop function”, and “(2-5-2) function for detecting a memory failure”. It is a processor. The transmission processor is a processor for realizing the “(2-4) packet transmission function” described above. The signal processing circuit is a processor for realizing the functions described in the above (2-1), (2-2), (2-5-1), and (2-7). The functions of each processor and signal processing circuit will be described in detail in [Description of operation] described later.

(3-2) Connection of Functional Units of Integrated Circuits 1, 2, and 3 The storage processor, transmission processor, and signal processing circuit of the integrated circuit 1 are connected to the internal memory 10 and the external memories 11 and 12. FIG. 5 shows a state in which the storage processor and the transmission processor are connected to the internal memory 10, but actually, they are also connected to the external memories 11 and 12. Similarly, each processor and signal processing circuit of the integrated circuit 2 are connected to the internal memory 20 and the external memory 21. Each processor and signal processing circuit of the integrated circuit 3 are connected to the internal memory 30 and the external memory 31.

  Each processor and signal processing circuit of the integrated circuit 1 are connected to an input / output port as shown in FIG. As shown in FIG. 5, the transmission processor of the integrated circuit 1 is connected to the storage processor and the transmission processor of the integrated circuits 2 and 3.

  Further, although not shown, the signal processing circuit of the integrated circuit 1 is connected to the signal processing circuits of the integrated circuits 2 and 3 facing each other through a signal line. The processors and signal processing circuits of the integrated circuits 1, 2, and 3 are connected to the CPU 4 via the CPU bus.

(3-3) Function of Measuring Packet Reception Interval The storage processor of the integrated circuit 1 described above may have a function of measuring a packet reception interval received from an external communication device. Specifically, the storage processor of the integrated circuit 1 may have a function of measuring the time from when the head of the packet is received until the next head of the packet is received. In that case, the storage processor of the integrated circuit 1 includes a general preamble detection circuit, a clock generation circuit, a counter, and a register. In general, a preamble which is a synchronization signal is added to the head of the packet. By detecting the preamble, the preamble detection circuit described above considers that the head of the packet has been detected, and outputs a signal indicating the head detection to the storage processor.

  The clock generation circuit is a circuit that generates a clock signal so that the storage processor can measure time, and periodically outputs the generated clock signal to the storage processor of the integrated circuit 1. A clock signal is repeatedly input to the storage processor of the integrated circuit 1.

  The storage processor of the integrated circuit 1 can implement the function of measuring the packet reception interval by sequentially performing the following (i) to (iv).

  (I) First, the storage processor of the integrated circuit 1 resets the value of the counter to 0 when receiving a packet, and increments the counter every time a clock signal is input. Specifically, the storage processor of the integrated circuit 1 resets the counter value to 0 when a signal indicating the head detection is input from the preamble detection circuit, and increments the counter every time a clock signal is input. Go. This is because the time is counted until the next packet is received.

  (Ii) The storage processor of the integrated circuit 1 stops incrementing the counter when the next packet is received. Specifically, the storage processor of the integrated circuit 1 stops incrementing the counter when a signal indicating head detection is input again from the preamble detection circuit.

  (Iii) The storage processor of the integrated circuit 1 calculates a multiplication value of the stopped counter value and the clock signal input period, and stores the calculated multiplication value in the internal memory 10.

  The multiplication value described above indicates a packet reception interval. When storing the multiplication value in the internal memory 10, the storage processor of the integrated circuit 1 stores it in an area different from the area for storing the packet. The “clock signal input period” described above is set in the storage processor of the integrated circuit 1 by the manufacturer of the communication apparatus of the present embodiment. The manufacturer of the communication device of this embodiment sets the input period of the clock signal in the storage processor after actually measuring it.

  After (iv) (iii), when the storage processor of the integrated circuit 1 receives the packet, it again performs the above (i) to (iii). The storage processor of the integrated circuit 1 stores the packet reception interval in the internal memory 10.

(4) Function of CPU 4 When a signal indicating failure detection is input, the CPU 4 outputs a signal indicating failure occurrence to the integrated circuits 1, 2, and 3 to be connected. After outputting a signal indicating the occurrence of a failure, the CPU 4 also outputs a signal instructing packet transfer to the integrated circuits 1, 2, and 3.

(5) CF5 CF5 is a general compact flash (registered trademark).

(6) Means for Realizing Each Functional Unit The integrated circuits 1, 2, and 3 include a memory such as a RAM, a general input / output port, a general processor, a register, a general register control circuit, This can be realized by using a general signal generation circuit and a general DMA controller. RAM is an abbreviation for Random Access Memory.

  The general register control circuit, signal generation circuit, and DMA controller described above are circuits for realizing a signal processing circuit. The register control circuit is a circuit provided in the signal processing circuit for writing a value to the register, and is connected to the registers A and B. The registers A and B are the registers described in (2-2) above. As described in (3-2) above, a signal line is connected to the signal processing circuit, and the signal line is connected to a register control circuit in the signal processing circuit.

  The signal generation circuit is a general signal generation circuit that generates an enable signal and a disable signal, and is connected to the CPU 4 and an integrated circuit that is a transmission destination of the generated signal. The DMA controller is a circuit provided in the signal processing circuit for performing the DMA transfer, and is connected to the CPU 4, each memory in the integrated circuit, and the CF 5.

  Further, the integrated circuits 1, 2, and 3 may be realized using a general preamble detection circuit, a clock generation circuit, and a counter in addition to a memory or the like. The preamble detection circuit, the clock generation circuit, and the counter described above are circuits for realizing the function “(3-3) function for measuring packet reception interval” described above, and are connected to the storage processor.

  The CPU 4 can be realized by using a general arithmetic processing device such as a CPU and a memory such as a RAM. CF5 can be realized using a general compact flash.

[Description of operation]
6 and 7 are diagrams for explaining the operation of the communication apparatus according to the first embodiment of the present invention. FIG. 6 shows a basic operation of the communication apparatus of this embodiment, and FIG. 7 shows an operation additionally performed by the communication apparatus of this embodiment when a failure occurs.

  The operation of the communication apparatus of this embodiment will be described below with reference to FIGS.

(1) Operation of communication device before failure (outline)
First, an outline of the operation before a failure occurs will be described. The communication apparatus according to the present embodiment operates as follows before a failure occurs.

(1-1) Transmission Permitting Operation First, when the integrated circuits 1, 2, and 3 are activated, as shown in FIG. 3, they output enable signals that grant transmission permission to each other. The integrated circuits 1, 2, and 3 to which the enable signal is input can transmit a packet.

(1-2) Communication Operation The integrated circuit 1 communicates with an external communication device and receives a packet from the external communication device.

  When the integrated circuit 1 receives a packet from an external communication device, the integrated circuit 1 stores the received packet in the internal memory 10.

  Next, the integrated circuit 1 acquires a packet from the internal memory 10 and transmits it to the integrated circuits 2 and 3 at a predetermined timing.

  The above-mentioned predetermined timing is a fixed interval timing, and is set in the integrated circuit 1 by the manufacturer of the communication apparatus of the present embodiment. The manufacturer of the communication device according to the present embodiment may set an arbitrary timing in the integrated circuit 1 as a predetermined timing as long as the timing is at a constant interval.

  The integrated circuits 2 and 3 store the packets received from the integrated circuit 1 in the internal memories 20 and 30, respectively.

  Next, at a predetermined timing, the integrated circuits 2 and 3 acquire packets from the internal memories 20 and 30, perform predetermined processing, and transmit the packets to the integrated circuit 1.

  The above-mentioned predetermined timing is a fixed interval timing, and is set in the integrated circuits 2 and 3 by the manufacturer of the communication apparatus of the present embodiment. The predetermined process may be a process of encrypting the packet. In that case, each of the integrated circuits 2 and 3 transmits the encrypted packet to the integrated circuit 1.

  Next, when receiving a packet from the integrated circuit 2, the integrated circuit 1 stores the received packet in the external memory 11. Similarly, when the integrated circuit 1 receives a packet from the integrated circuit 3, the integrated circuit 1 stores the received packet in the external memory 12.

  Next, the integrated circuit 1 transmits the packets stored in the external memories 11 and 12 to an external communication device.

(1-3) Details of operation The above-described operations of “(1-1) transmission permission operation” and “(1-2) communication operation” are specifically the following “(2) Before a failure occurs. Operation of communication device (details) ”. Details of the operation of the communication apparatus according to this embodiment before a failure occurs will be described.

(2) Operation of communication device before failure occurs (details)
(2-1) Transmission Permission Operation First, when the integrated circuit 1 is activated, as shown in FIG. 3, the integrated circuit 1 outputs an enable signal that gives permission for transmission to the integrated circuits 2 and 3 to be connected. The output of the enable signal is performed by the signal processing circuit of the integrated circuit 1. Similarly, when the integrated circuits 2 and 3 are activated, the integrated circuits 2 and 3 output an enable signal for permitting transmission to the connected integrated circuit 1. The signal processing circuit of the integrated circuits 2 and 3 outputs the enable signal.

  The enable signal output from the signal processing circuit of the integrated circuit 1 is input to the signal processing circuits of the integrated circuits 2 and 3. The enable signals output from the signal processing circuits of the integrated circuits 2 and 3 are input to the signal processing circuit of the integrated circuit 1.

  When an enable signal is input from the signal processing circuit of the integrated circuit 2, the signal processing circuit of the integrated circuit 1 sets a value 1 in the register A provided therein, and the enable signal is input from the signal processing circuit of the integrated circuit 3. Then, the value 1 is set in the register B provided in itself. On the other hand, when the enable signal is input from the signal processing circuit of the integrated circuit 1, each of the signal processing circuits of the integrated circuits 2 and 3 sets the value 1 in the register C provided therein.

(2-2) Operation of Integrated Circuit 1 (Part 1)
Next, it is assumed that the integrated circuit 1 communicates with an external communication device and receives a packet from the external communication device. The storage processor of the integrated circuit 1 receives a packet from an external communication device via the input / output port.

  The storage processor of the integrated circuit 1 temporarily stores the packet received from the external communication device in the internal memory 10 as shown in FIG. 6 (S1).

  On the other hand, in the integrated circuit 1, the transmission processor operates independently.

  When the predetermined timing is reached, the transmission processor of the integrated circuit 1 determines whether or not the value of the register A is 1, that is, whether or not transmission permission is given from the integrated circuit 2 (S2).

  The above-mentioned predetermined timing is a fixed interval timing, and is set in the transmission processor of the integrated circuit 1 by the manufacturer of the communication apparatus of the present embodiment. The manufacturer of the communication device according to the present embodiment may set an arbitrary timing in the integrated circuit 1 as a predetermined timing as long as the timing is at a constant interval.

  Next, when the value of the register A is 1, that is, when the transmission permission is given from the integrated circuit 2 (Yes in S2), the transmission processor of the integrated circuit 1 is stored in the internal memory 10. The predetermined number of packets are transmitted to the integrated circuit 2 (S3).

  The predetermined number is set in the transmission processor by the manufacturer of the communication apparatus of the present embodiment.

  When the value of the register A is not 1 in the processing of S2 described above, that is, when the transmission permission is not given from the integrated circuit 2 (No in S2), the transmission processor of the integrated circuit 1 The packet stored in 10 is not transmitted to the integrated circuit 2.

  Here, since the value of the register A is 1, the transmission processor of the integrated circuit 1 continues the description on the assumption that the packet stored in the internal memory 10 has been transmitted to the integrated circuit 2.

  Next, after S3, the transmission processor of the integrated circuit 1 determines whether or not the value of the register B is 1, that is, whether or not transmission permission is given from the integrated circuit 3 (S4).

  Next, when the value of the register B is 1, that is, when transmission permission is given from the integrated circuit 3 (Yes in S4), the transmission processor of the integrated circuit 1 is stored in the internal memory 10. The predetermined number of packets are transmitted to the integrated circuit 3 (S5).

  When the value of the register B is not 1 in the processing of S4 described above, that is, when the transmission permission is not given from the integrated circuit 3 (No in S4), the transmission processor of the integrated circuit 1 The packet stored in 10 is not transmitted to the integrated circuit 3.

  Here, since the value of the register B is 1, the transmission processor of the integrated circuit 1 continues the description on the assumption that the packet stored in the internal memory 10 has been transmitted to the integrated circuit 3.

(2-3) Operation in Integrated Circuits 2 and 3 Next, when the storage processor of the integrated circuits 2 and 3 receives the packet transmitted from the integrated circuit 1, each of the received packets is temporarily stored in the internal memories 20 and 30. (S6).

  Next, the transmission processors of the integrated circuits 2 and 3 each determine whether or not the value of the register C is 1, that is, whether or not transmission permission is given from the integrated circuit 1 at a predetermined timing ( S7).

  The predetermined timing in S7 is a fixed interval timing, and is set in the transmission processor of the integrated circuits 2 and 3 by the manufacturer of the communication apparatus of this embodiment. The manufacturer of the communication device according to the present embodiment may set an arbitrary timing in the integrated circuit 1 as a predetermined timing as long as the timing is at a constant interval.

  Next, when the value of the register C is 1, that is, when the transmission permission is given from the integrated circuit 1 (Yes in S7), the transmission processors of the integrated circuits 2 and 3 respectively The packets stored in 20, 30 are acquired (S8).

  Next, the transmission processors of the integrated circuits 2 and 3 each transmit the acquired packet to the integrated circuit 1 (S9). At this time, the transmission processor may encrypt the acquired packet and transmit the encrypted packet to the integrated circuit 1.

  When the value of the register C is not 1 in the processing of S7 described above, that is, when the transmission permission is not given from the integrated circuit 1 (No in S7), the transmission processors of the integrated circuits 2 and 3 Packets stored in the internal memories 20 and 30 are not transmitted to the integrated circuit 1.

  Here, since the value of the register C is 1, the transmission processors of the integrated circuits 2 and 3 will continue the description on the assumption that the packets stored in the internal memories 20 and 30 have been transmitted to the integrated circuit 1, respectively.

  After S9, the transmission processors of the integrated circuits 2 and 3 end the processing and wait for the next predetermined timing.

(2-4) Operation of integrated circuit 1 (part 2)
The transmission processor of the integrated circuit 1 receives a packet from each of the integrated circuits 2 and 3.

  The transmission processor of the integrated circuit 1 temporarily stores the packet received from the integrated circuit 2 in the external memory 11, and temporarily stores the packet received from the integrated circuit 3 in the external memory 12 (S10).

  Next, the transmission processor of the integrated circuit 1 transmits all the packets stored in the external memories 11 and 12 to the external communication device (S11). At this time, the storage processor of the integrated circuit 1 may transmit the packets stored in the external memories 11 and 12 in the order of the sequence numbers included in the packets.

(3) Operation of communication device when failure occurs (outline)
Next, it is assumed that a failure has occurred in the communication apparatus of this embodiment. For example, it is assumed that a failure that a packet is broken occurs in the communication apparatus according to the present embodiment. A broken packet is transmitted from the communication device of this embodiment to an external communication device, and communication cannot be performed correctly.

(3-1) Failure Detection At that time, the signal processing circuit of the integrated circuit 1 has the function shown in “(2-5-1) Function for detecting device failure”, and detects the failure.

  When detecting a failure, the signal processing circuit of the integrated circuit 1 outputs a signal indicating failure detection to the CPU 4 as shown in FIG. 7 (S20).

  Next, when a signal indicating failure detection is input, the CPU 4 outputs a signal indicating the occurrence of a failure to the storage processor of the integrated circuit 1 and the signal processing circuits of the integrated circuits 1, 2, and 3 ( S21).

(3-2) Operation of Integrated Circuit 1 When Failure Occurs Next, when the storage processor of integrated circuit 1 receives a signal indicating the occurrence of a failure from CPU 4, even if it receives a packet from an external communication device, Discard without storing in the internal memory 10 (S22).

  By the process of S22, the integrated circuit 1 prevents a new packet from being stored in the internal memory 10 and stores the packet at the time of occurrence of the failure. The process of S <b> 22 is a process of stopping the packet storage in the internal memory 10.

  On the other hand, when a signal indicating the occurrence of a failure is input from the CPU 4, the signal processing circuit of the integrated circuit 1 outputs a disable signal to the integrated circuits 2 and 3 (S 23). FIG. 4 shows how the disable signal is output to the integrated circuits 2 and 3.

  Next, when the disable signal is input, the integrated circuits 2 and 3 stop transmitting packets to the integrated circuit 1 (S24).

  The processing of S24 is realized by the transmission processor and the signal processing circuit of the integrated circuits 2 and 3. The detailed operation of the process of S24 will be described later in “(4-1) Details of the process of S24”. However, since the integrated circuits 2 and 3 stop transmitting packets to the integrated circuit 1, the integrated circuit 1 Does not receive the packet, and no longer stores the packet in the external memories 11 and 12. As a result, the integrated circuit 1 stores the packet at the time of failure occurrence in the external memories 11 and 12. The processes in S23 and S24 are processes that stop storing packets in the external memories 11 and 12.

(3-3) Operation of Integrated Circuits 2 and 3 when a Fault Occurs On the other hand, a signal indicating the occurrence of a fault is also input to the signal processing circuits of the integrated circuits 2 and 3 from the CPU 4 by the process of S21 described above.

  The signal processing circuits of the integrated circuits 2 and 3 each output a disable signal to the integrated circuit 1, as shown in FIG. (S25). FIG. 4 shows how the disable signal is output to the integrated circuit 1.

  Next, when the disable signal is input, the integrated circuit 1 stops transmitting packets to the integrated circuits 2 and 3 as shown in FIG. 7 (S26).

  The process of S26 is realized by the transmission processor and the signal processing circuit of the integrated circuit 1. The detailed operation of the process of S26 will be described later in “(4-2) Details of the process of S26”. However, since the integrated circuit 1 stops transmitting packets to the integrated circuits 2 and 3, the integrated circuit 2 3 does not receive the packet and does not newly store the packet in the internal memories 20 and 30. As a result, the integrated circuits 2 and 3 store the packet at the time of failure occurrence in the internal memories 20 and 30. The processes of S25 and S26 are processes that stop storing packets in the internal memories 20 and 30.

(3-4) Operation of Saving Packet at Failure in CF5 Next, after a predetermined time has elapsed after S21, the CPU 4 sends a signal for instructing packet transfer to the signal processing circuits of the integrated circuits 1, 2, and 3. Transmit (S27).

  The predetermined time is a time until S22 to S24 and S25 to S26 are completed after S21 (hereinafter referred to as “completion time”), and is set in the CPU 4 by the manufacturer of the communication apparatus of the present embodiment. The manufacturer of the communication apparatus according to the present embodiment actually measures the completion time, and sets the CPU 4 as a predetermined time that is sufficiently longer than the actually measured time. The CPU 4 waits for the packet at the time of failure to be stored in each memory, and transmits a signal instructing packet transfer to the signal processing circuits of the integrated circuits 1, 2, and 3.

  Next, when a signal instructing packet transfer is input, the signal processing circuits of the integrated circuits 1, 2, and 3 receive packets at the time of failure from the internal memories 10, 20, and 30 and the external memories 11 and 12, respectively. The acquired packet when the failure occurs is stored in the CF 5 (S28). At this time, the signal processing circuits of the integrated circuits 1, 2, and 3 may transfer and store the packet at the time of the failure from the internal memories 10, 20, and 30 and the external memories 11 and 12 to the CF 5 by DMA transfer. .

(3-5) CF5 in which a packet is stored A manufacturer of a communication device can acquire a packet at the time of failure from the CF5. Therefore, the manufacturer of the communication device can use the packet at the time of failure when performing the reproduction test.

(4) Details of processing in S24 and S26 (4-1) Details of processing in S24 (Processing in S24 described above (the integrated circuits 2 and 3 to which the disable signal is input stop packet transmission to the integrated circuit 1) Specifically, the processing is as follows.

  First, when the disable signal is input from the signal processing circuit of the integrated circuit 1 in S23, the signal processing circuits of the integrated circuits 2 and 3 each set a value 0 to the register C provided in the integrated circuit 2 and 3 itself. The value 0 is a value indicating that the transmission permission is not given from the integrated circuit 1.

  Here, the transmission processors of the integrated circuits 2 and 3 operate independently in the integrated circuits 2 and 3.

  As shown in FIG. 6, the transmission processors of the integrated circuits 2 and 3 perform the process of S7, that is, the process of determining whether or not the value of the register C is 1 at a predetermined timing (S7).

  The predetermined timing is a timing at regular intervals, as described above in “(2-3) Operation in integrated circuits 2 and 3”.

  The transmission processors of the integrated circuits 2 and 3 store in the internal memories 20 and 30 when the value of the register C is not 1, that is, when transmission permission is not given from the integrated circuit 1 (No in S7). The transmitted packet is not transmitted to the integrated circuit 1. As a result, the integrated circuits 2 and 3 stop transmitting packets to the integrated circuit 1.

(4-2) Details of Processing in S26 Next, the processing in S26 described above (the processing in which the integrated circuit 1 to which the disable signal is input stops packet transmission to the integrated circuits 2 and 3) is specifically described. Is the following process.

  First, when a disable signal is input from the signal processing circuit of the integrated circuit 2 in S25, the signal processing circuit of the integrated circuit 1 sets a value 0 in the register A provided therein. Further, when the disable signal is input from the integrated circuit 3 in S25, the integrated circuit 1 sets the value 0 in the register B provided in the integrated circuit 1.

  Here, the transmission processor of the integrated circuit 1 operates independently in the integrated circuit 1.

  As shown in FIG. 6, the transmission processor of the integrated circuit 1 performs the process of S2, that is, the process of determining whether or not the value of the register A is 1 at a predetermined timing (S2). The predetermined timing is a constant interval timing as described above in “(2-2) Operation of integrated circuit 1”.

  When the value of the register A is not 1 in the determination of S2, that is, when the transmission permission is not given from the integrated circuit 2 (No in S2), the transmission processor of the integrated circuit 1 stores the internal memory 10 in the internal memory 10. The stored packet is not transmitted to the integrated circuit 2. The integrated circuit 1 stops transmission of packets to the integrated circuit 2.

  Next, the transmission processor of the integrated circuit 1 performs the process of S4. Specifically, the transmission processor of the integrated circuit 1 determines whether or not the value of the register B is 1, that is, whether or not transmission permission is given from the integrated circuit 3 (S4).

  When the value of the register B is not 1 in the processing of S4 described above, that is, when the transmission permission is not given from the integrated circuit 3 (No in S4), the transmission processor of the integrated circuit 1 The packet stored in 10 is not transmitted to the integrated circuit 3. As a result, the integrated circuit 1 stops transmitting packets to the integrated circuit 3.

(5) Summary of Operation When a failure occurs, the communication device according to the present embodiment discards the received packet and stops storing the packet in the internal memory 10 by performing the above-described S20 to S24. As a result, the communication apparatus according to the present embodiment stores the packet at the time of failure occurrence in the internal memory 10.

  Furthermore, when a failure occurs, the communication device according to the present embodiment stops storing packets in the internal memories 20 and 30 and the external memories 11 and 12 by performing S25 to S26. As a result, the communication apparatus of the present embodiment stores the packet at the time of failure occurrence in the internal memories 20 and 30 and the external memories 11 and 12.

  The communication device according to the present embodiment stores a packet when a failure occurs in the CF 5 in accordance with a packet transfer instruction from the CPU 4. Therefore, the manufacturer of the communication device can acquire the packet at the time of failure occurrence from the CF 5. As a result, the manufacturer of the communication device can use the packet at the time of the failure when performing the reproduction test, and can sufficiently prepare the environment where the failure has occurred.

(6) Variation Operation (6-1) Variation of Storage Operation In the above description, the integrated circuits 1, 2, and 3 store the packet at the time of failure in the CF5. The integrated circuits 1, 2, and 3 may store not only the packet at the time of the failure but also other data in the CF 5.

  For example, the integrated circuits 1, 2, and 3 have the above-mentioned “(3-3) function of measuring the reception interval of packets”, and when measuring the time interval of received packets, the value indicating the measured time interval is also The data may be stored in the CF 5 together with the packet at the time of failure.

  Further, when the information is set by the manufacturer, the integrated circuits 1, 2, and 3 may store the set information in the CF 5 as well.

(6-2) Variation of Packet Transmission Operation In the above description, the transmission processor of the integrated circuit 1 transmits the packet acquired from the internal memory 10 to the integrated circuits 2 and 3 as they are. The transmission processor of the integrated circuit 1 may perform some processing on the packet acquired from the internal memory 10 and then transmit the packet to the integrated circuits 2 and 3.

  For example, the transmission processor of the integrated circuit 1 determines the priority of the packet acquired from the internal memory 10, and transmits a packet with a high priority to the integrated circuit 2 and a packet with a low priority to the integrated circuit 3. Good. Specifically, the transmission processor of the integrated circuit 1 may determine whether or not the Type of Service value of the packet acquired from the internal memory 10 is greater than a predetermined value. The Type of Service value is a value indicating the priority of the packet. In that case, if the Type of Service value is larger than the predetermined value, the transmission processor of the integrated circuit 1 determines that the packet has a high priority, and transmits the packet acquired from the internal memory 10 to the integrated circuit 2. If the Type of Service value is equal to or less than a predetermined value, the transmission processor of the integrated circuit 1 determines that the packet has a low priority and transmits the packet acquired from the internal memory 10 to the integrated circuit 3. The predetermined value is set in the transmission processor of the integrated circuit 1 by the manufacturer of the communication apparatus of the present embodiment.

(6-3) Variation of Packet Reception Operation In the above description, the case where the storage processor of the integrated circuits 2 and 3 stores the packet received from the integrated circuit 1 in the internal memories 20 and 30 as they are. The storage processors of the integrated circuits 2 and 3 may perform some processing on the packets received from the integrated circuit 1 and store them in the internal memories 20 and 30.

  For example, the storage processor of the integrated circuits 2 and 3 determines whether or not the IP address of the received packet is a private IP address. If the IP address is a private IP address, the storage processor of the integrated circuit 2 or 3 replaces the IP address with the global IP address. It may be stored in the internal memories 20 and 30. In that case, a private IP address and a global IP address are set in association with each other in the storage processors of the integrated circuits 2 and 3 by the manufacturer of the communication apparatus of the present embodiment. IP is an abbreviation for Internet Protocol.

  Further, although the transmission processors of the integrated circuits 2 and 3 performed the encryption on the packets acquired from the internal memories 20 and 30 in the process of S8, other processes may be performed. The processing performed on the packets by the transmission processors of the integrated circuits 2 and 3 is not limited to encryption.

(6-4) Variation of operation for stopping packet transmission In the above description, the signal processing circuits of the integrated circuits 1, 2, and 3 output the disable signal so that the packets are not transmitted from the connected integrated circuit.

  The signal processing circuits of the integrated circuits 1, 2, and 3 may output a known jam signal to the transmission processor of the connected integrated circuit, similarly to a circuit having a general back pressure function. In that case, the signal processing circuits of the integrated circuits 1, 2, and 3 are connected to a transmission processor of the connected integrated circuit through a control line. The transmission processors of the integrated circuits 1, 2, and 3 that have received the jam signal stop transmission.

(6-5) Regarding packet storage destination In the above description, the signal processing circuits of the integrated circuits 1, 2, and 3 store the packet at the time of failure in the CF5, but the storage destination is not limited to the CF5. The signal processing circuits of the integrated circuits 1, 2, and 3 may store a packet when a failure occurs in the external memories 11, 12, 21, and 31 connected thereto.

  In the above description, the storage processor of the integrated circuit 1 stores the packet received from the external communication device in the internal memory 10, but may store it in the external memories 11 and 12 instead of the internal memory 10. In that case, the storage processor of the integrated circuit 1 stores the packets received from the integrated circuits 20 and 30 in the internal memory 10 instead of the external memories 11 and 12.

  Similarly, the storage processor of the integrated circuits 2 and 3 may store the received packet in the external memories 21 and 31 instead of the internal memories 20 and 30.

(6-6) Fault Detection In the above description, the case where the integrated circuit 1 includes the fault detection function described in the above-mentioned “(2-5-1) Function for detecting a fault in the device” has been described. The integrated circuit 1 may include the failure detection function described in the above-mentioned “(2-5-2) Function for detecting a memory failure” and “(2-5-3) A function for detecting a failure in which a packet is broken”. Good.

  Specifically, the storage processor of the integrated circuit 1 may have the failure detection function shown in the above-mentioned “(2-5-2) Function of detecting a memory failure”. When the storage processor of the integrated circuit 1 detects a failure by the failure detection function, it outputs a signal indicating failure detection to the CPU 4.

  Further, the storage processor and the transmission processor of the integrated circuit 1 may be provided with the failure detection function shown in the above-mentioned “(2-5-3) Function for detecting failure of packet corruption”. The storage processor of the integrated circuit 1 performs a process of writing 0 or 1 to the failure detection register A, and the transmission processor of the integrated circuit 1 performs a process of writing 0 or 1 to the failure detection register B. When the failure detection register A is 0 but the failure detection register B is 1, the transmission processor of the integrated circuit 1 outputs an electrical signal indicating failure detection to the CPU 4.

  Each functional unit of the integrated circuit 1 can have any function as long as it is a fault detection function that detects a fault related to communication with an external communication device. Each functional unit of the integrated circuit 1 outputs an electrical signal indicating failure detection to the CPU 4 when a failure is detected by the failure detection function.

  Each functional unit of the integrated circuits 2 and 3 may also have a failure detection function. When a failure is detected by the failure detection function, the integrated circuits 2 and 3 output an electrical signal indicating failure detection to the CPU 4.

(6-8) Configuration of Communication Device of this Embodiment The communication device of this embodiment may have a redundant configuration. Specifically, the communication apparatus of this embodiment includes one CPU 4 and integrated circuits 1, 2, and 3 (hereinafter referred to as “minimum configuration”) shown in FIG. A plurality may be provided.

  Further, the above-described minimum configuration may be mounted on a printed circuit board and provided in the communication device of the present embodiment.

[Description of effects]
According to this embodiment, the manufacturer of the communication device can sufficiently prepare the environment where the failure has occurred when performing the reproduction test.

  This is because the communication device according to the present embodiment stops storing packets in each memory when a failure is detected when a failure occurs, and stores the packet at the time of failure in a buffer.

  Since the communication device stores the packet when the failure occurs, the manufacturer of the communication device can obtain the packet when the failure occurs. As a result, the manufacturer of the communication device can use the packet at the time of the failure when performing the reproduction test, and can sufficiently prepare the environment where the failure has occurred.

<< Second Embodiment >>
Next, a second embodiment of the present invention will be described.

  The communication apparatus of the first embodiment stores the packet at the time of failure in the internal memory 10 by discarding the received packet. The communication apparatus according to the second embodiment stores the packet at the time of failure in the internal memory 10 by stopping the function of receiving the packet itself. The communication device according to the second embodiment can consume less power than the communication device according to the first embodiment because the packet is not discarded.

  The configuration and operation of the communication apparatus according to the second embodiment will be described below. FIG. 8 is a diagram illustrating a configuration example of a system according to the second embodiment of the present invention.

[Description of configuration]
(1) Configuration of Communication Device of Second Embodiment The communication device of the second embodiment includes an integrated circuit 6 instead of the integrated circuit 1 as shown in FIG. Although not shown, the integrated circuit 6 includes a storage processor as in the integrated circuit 1.

(2) Function of Integrated Circuit 6 The integrated circuit 6 supplies power to the storage processor after startup. When a signal indicating the occurrence of a failure is input from the CPU 4, the integrated circuit 6 stops supplying power to the storage processor. When the storage processor stops, the integrated circuit 6 will not receive any packets.

  Since the configuration and functions other than those described above are the same as those of the communication apparatus according to the first embodiment, the same reference numerals are given and description thereof is omitted.

[Description of operation]
The operation of the communication apparatus of this embodiment will be described.

  First, the integrated circuit 6 supplies power to the storage processor after startup.

  The storage processor of the integrated circuit 6 is activated when power is supplied, and performs the above-described processing of S1 and stores the packet received from the external communication device in the internal memory 10 in the same manner as the storage processor of the integrated circuit 1. .

  Next, when a signal indicating the occurrence of a failure is input from the CPU 4, the integrated circuit 6 performs a process of stopping the supply of power to the storage processor instead of S22.

  The storage processor whose supply of power has been stopped stops receiving the packet and no longer stores the packet in the internal memory 10.

  As a result, the communication apparatus according to the present embodiment can save a packet when a failure occurs in the internal memory 10. The process of stopping the supply of power to the storage processor is a process of stopping the storage of packets in the internal memory 10. The integrated circuit 6 can perform any process instead of the process of S22 as long as the process stops packet storage.

[Description of effects]
According to the present embodiment, the manufacturer of the communication device can sufficiently prepare the environment in which the failure has occurred when performing the reproduction test, similarly to the manufacturer of the communication device of the first embodiment. This is because the communication device according to the present embodiment stores a packet when a failure occurs in a buffer, as in the communication device according to the first embodiment.

  Furthermore, the communication device of the present embodiment can reduce the power consumption when a failure occurs, compared to the communication device of the first embodiment. This is because the communication device according to the present embodiment stops the packet reception function by stopping the storage processor, and saves the packet at the time of failure in the buffer without performing the packet discard. The communication device according to the present embodiment can reduce power consumption by not performing packet discard.

<< Third Embodiment >>
FIG. 9 is a diagram illustrating a configuration example of an apparatus according to the third embodiment of the present invention. The configuration and operation of the apparatus according to the third embodiment will be described below.

[Description of configuration]
(1) Configuration of the Device 100 of the Third Embodiment As shown in FIG. 9, the device 100 of the third embodiment includes a memory 101, a storage unit 102, a detection unit 102, a storage unit 103, Is provided.

  The apparatus 100 of 3rd Embodiment may communicate with the apparatus 110 connected, as FIG. 9 shows.

(1) Configuration of Device 100 of Third Embodiment The memory 101 is a memory that stores stored data corresponding to data input by communication.

  The detection unit 102 detects a failure related to communication.

  The storage unit 103 sequentially stores stored data corresponding to data input by communication in the memory 101. The storage unit 103 may store the input data as it is in the memory 101 as stored data, or performs predetermined processing on the input data, and stores the processed data in the memory 101 as storage data. It may be stored.

  The storage unit 103 stops storing the stored data in the memory 101 when the detection unit 102 detects a failure.

  The data described above may be a packet. The storage unit 103 is a functional unit corresponding to the storage processor or transmission processor of the integrated circuit 1 in the first embodiment, and the detection unit 102 stores the integrated circuit 1 that performs failure detection in the first embodiment. It is a functional unit corresponding to a processor or a transmission processor.

[Description of operation]
Next, operation | movement of the apparatus 100 of this embodiment is demonstrated.

  First, it is assumed that the device 100 of this embodiment is communicating with the device 110 to be connected. In the apparatus 100 according to the present embodiment, data is successively input from the apparatus 110 by communication.

  The storage unit 103 sequentially stores stored data corresponding to data input by communication in the memory 101. The storage unit 103 may store the input data as it is in the memory 101 as stored data, or performs predetermined processing on the input data, and stores the processed data in the memory 101 as storage data. It may be stored.

  Next, it is assumed that a failure related to communication with the device 110 occurs in the device 100 of the present embodiment.

  The detection unit 102 detects a failure related to communication with the device 110.

  The storage unit 103 stops storing the stored data in the memory 101 when the detection unit 102 detects a failure.

  The storage unit 103 may stop storing the stored data in the memory 101 by discarding the input data, or may stop the function related to storing the stored data provided in the storage unit 103 to the memory 101. The storage of the stored data may be stopped.

  Since no new data is stored in the memory 101, data when a failure occurs is stored.

[Description of effects]
First, according to this embodiment, the manufacturer of the apparatus 100 can sufficiently prepare the environment in which a failure has occurred when performing a reproduction test.

  This is because the apparatus 100 according to the present embodiment stops storing data in the memory 101 when a failure occurs and saves the data when the failure occurs. Since the device 100 according to the present embodiment stores data at the time of failure, the manufacturer of the communication device 100 according to the present embodiment can acquire data at the time of failure. As a result, the manufacturer of the apparatus 100 of the present embodiment can use the data at the time of the failure when performing the reproduction test, and can sufficiently prepare the environment where the failure has occurred.

  The embodiment described above is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. The directions of the arrows in FIGS. 3 and 4 show an example, and do not limit the direction of signals between the integrated circuits.

Furthermore, a part or all of each of the above embodiments can be described as in the following supplementary notes, but is not limited thereto.
(Appendix 1)
A memory for storing stored data corresponding to data input by communication;
A detection unit for detecting a failure related to the communication;
A storage unit that sequentially stores the storage data in the memory and stops the storage when the detection unit detects the failure;
A device comprising:
(Appendix 2)
The storage unit stops the storage by discarding the input data.
The apparatus according to supplementary note 1, wherein:
(Appendix 3)
The storage unit stops the storage by stopping a function related to the input of the communication device;
The apparatus according to supplementary note 1, wherein:
(Appendix 4)
When it comes to a predetermined timing, it comprises a transmission unit that outputs data corresponding to the data stored in the memory,
The transmitting unit stops the output when the detecting unit detects the failure.
The apparatus according to any one of appendices 1 to 3, characterized in that:
(Appendix 5)
A storage step of sequentially storing data corresponding to data input by communication in a memory;
A stop step of stopping the storage when a failure related to the communication is detected;
The preservation | save method characterized by having.
(Appendix 6)
In the stop step, the storage is stopped by discarding the input data.
The storage method according to appendix 5, characterized by:
(Appendix 7)
A method in a communication device, comprising:
In the stop step, the storage is stopped by stopping the function related to the input of the communication device.
The storage method according to appendix 5, characterized by:
(Appendix 8)
A transmission step of outputting data corresponding to the data stored in the memory at a predetermined timing;
In the transmission step, the output is stopped when the failure is detected in the stop step.
The storage method according to any one of appendices 5 to 7, characterized in that:
(Appendix 9)
In a processor mounted on a communication device equipped with a memory,
A storage process for sequentially storing data corresponding to data input by communication in the memory;
A detection process for detecting a failure related to the communication;
A storage stop process for stopping the storage process when the detection process detects the failure;
A program to let you do.
(Appendix 10)
The program according to appendix 9, which causes the processor to perform the storage stop process that stops the storage process by discarding the input data.
(Appendix 11)
The program according to appendix 9, which causes the processor to perform the storage stop process for stopping the storage process by stopping a function related to the input of the communication device.
(Appendix 12)
The program according to any one of appendices 9 to 11 for causing the processor to perform a transmission process of outputting data corresponding to the data stored in the memory at a predetermined timing.
(Appendix 13)
The program according to appendix 12, for causing the processor to perform a transmission stop process for stopping the transmission process when the detection process detects the failure.

1, 2, 3, 6 Integrated circuit 4 CPU (Central Processing Unit)
5 CF (Compact Flash)
10, 20, 30 Internal memory 11, 12, 21, 31 External memory 100 Device 101 Memory 102 Detection unit 103 Storage unit 110 Device

Claims (10)

A memory for storing stored data corresponding to data input by communication;
A detection unit for detecting a failure related to the communication;
A storage unit that sequentially stores the storage data in the memory and stops the storage when the detection unit detects the failure;
A device comprising: The storage unit stops the storage by discarding the input data.
The apparatus according to claim 1. The storage unit stops the storage by stopping a function related to the input of the communication device;
The apparatus according to claim 1. When it comes to a predetermined timing, it comprises a transmission unit that outputs data corresponding to the data stored in the memory,
The transmitting unit stops the output when the detecting unit detects the failure.
The apparatus according to any one of claims 1 to 3, characterized in that: A storage step of sequentially storing data corresponding to data input by communication in a memory;
A stop step of stopping the storage when a failure related to the communication is detected;
The preservation | save method characterized by having. In the stop step, the storage is stopped by discarding the input data.
The storage method according to claim 5, wherein: A method in a communication device, comprising:
In the stop step, the storage is stopped by stopping the function related to the input of the communication device.
The storage method according to claim 5, wherein: A transmission step of outputting data corresponding to the data stored in the memory at a predetermined timing;
In the transmission step, the output is stopped when the failure is detected in the stop step.
The storage method according to any one of claims 5 to 7, characterized in that: In a processor mounted on a communication device equipped with a memory,
A storage process for sequentially storing data corresponding to data input by communication in the memory;
A detection process for detecting a failure related to the communication;
A storage stop process for stopping the storage process when the detection process detects the failure;
A program to let you do.   The program according to claim 9, which causes the processor to perform the storage stop process that stops the storage process by discarding the input data.

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