JP2017162492A - device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory module that supports different types of memory protocols and supports different types of memory devices.SOLUTION: A device for use in a memory module 8a, 8b coupled to a host memory controller 6 over a bus 10 comprises memory module controller logic 20a, 20b to generate a request signal to a host memory controller, the signal having a pulse width greater than or equal to a minimum pulse width. The minimum pulse width comprises a large number of clock cycles needed to guarantee that the host memory controller detects the request signal. The pulse width of the request signal indicates at least one function in addition to the request signal to the host memory controller.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein generally have a pin layout on a single channel or bus in which the host memory controller is compatible with multiple slots coupled to the channel and the host memory controller. The present invention relates to a memory system that communicates with a plurality of memory modules. The host memory controller supports a protocol used by a plurality of memory modules coupled to the channel, for example, a Double Data Rate Third Generation (DDR3) protocol. The host memory controller is different when multiple memory modules, such as DIMMs, have multiple different timings for outputting data on the bus, as in the case of multiple different types of dual in-line memory modules (DIMMs). There is a need to adjust for differences in timing among multiple concatenated DIMMs. The host memory controller can communicate multiple single cycle commands.

  Prior to using the bus, the host memory controller needs to configure multiple memory modules for multiple operations. In the DDR3 protocol, the host memory controller uses a mode register set (MRS) command to store up to eight mode registers in multiple memory chips, such as multiple dynamic random access memory (DRAM) chips on a memory module package. Can be programmed. The MRS command identifies the mode register on the memory chip and includes an inversion bit that indicates whether the data has been inverted. After the bus is serviced, the host memory controller can then use the bus for read and write commands and to transfer data.

  Multiple commands may be transmitted at 1 bit / lane per command. For example, during a normal timing mode such as 1N timing, a chip select signal is placed on the bus in a command cycle to cause the selected memory module to receive the command. During multiple high speed operations such as 2N timing, the host memory controller places a chip select signal on the bus one clock cycle before the command allows additional setup time.

  A clock enable signal may be used to manage multiple internal clock signals within the memory module. The clock enable (CKE) high signal activates multiple internal clock signals and remains high during read and write accesses. The CKE low signal for the memory module deactivates the multiple internal clock signals, the multiple device input buffers, and the multiple output drivers. By adopting a plurality of CKE low signals, the power is reduced and a plurality of operations are refreshed.

  When multiple writes are communicated from the host memory controller to the memory module, the multiple writes in the memory module can be written directly to the multiple memory chips. However, a credit system can be implemented in a plurality of memory modules having a write buffer. There, the maximum number of write credits is allocated to the host memory controller, and a write command cannot be transmitted unless there are a plurality of available write credits. When the write command is transmitted, the plurality of write credits are decremented. When each write completes returning credit to the host memory controller, the memory module sends a message over the bus. Thereby, when the message is received, the write credit counter is incremented.

  To avoid communicating complex patterns when sending read and write requests, current host memory controllers can reduce the probability of repeatedly generating complex patterns that can cause errors on the bus. Data can be scrambled. Upon receiving scrambled write data with a write address, the memory module stores the scrambled write data at the write address. In response to the read request, the scrambled data is stored, transmitted to the host memory controller via the bus, descrambled, and used.

  Embodiments will now be described for purposes of illustration with reference to the accompanying drawings. The drawings are not to scale and like reference numerals refer to like elements.

1 illustrates one embodiment of a system having a memory system. 1 illustrates one embodiment of a memory module. 1 illustrates one embodiment of a pinout design of a memory system. FIG. 6 illustrates one embodiment of multiple operations for generating and processing a request signal encoding a function. FIG. FIG. 6 illustrates one embodiment of multiple operations for determining timing adjustments for outputs within a memory module. Fig. 4 illustrates an embodiment of a mode register set (MRS) command. FIG. 6 illustrates one embodiment of multiple operations for generating and processing MRS commands. FIG. In two parts, a timing chart for outputting a command is provided. In two parts, a timing chart for outputting a command is provided. Fig. 4 illustrates an embodiment relating to multiple operations for generating and receiving commands sent in multiple clock cycles. Fig. 4 illustrates an embodiment relating to multiple operations for generating and receiving commands sent in multiple clock cycles. FIG. 6 illustrates one embodiment of multiple operations for indicating a supported interface configuration for a memory module controller. FIG. FIG. 7 illustrates an embodiment of operations for a memory module controller to use a plurality of address bits based on a supported interface configuration. FIG. 7 illustrates an embodiment of multiple operations for using multiple commands indicating multiple power management operations. FIG. FIG. 10 illustrates an embodiment of operations that use multiple write credits to send multiple write commands and return multiple write credits to the host memory controller. 6 illustrates one embodiment of a plurality of operations for generating a read data packet with a write credit counter. FIG. 6 illustrates one embodiment of multiple operations for processing a read data packet. FIG. FIG. 6 illustrates an embodiment of a plurality of operations for processing a flow associated with a plurality of error operations using an error signal. FIG. 6 illustrates an embodiment of multiple operations for handling write errors. FIG. FIG. 6 illustrates an embodiment of operations for scrambling and descrambling data transmitted over a bus. 6 illustrates one embodiment of a plurality of operations for descrambling write data in a memory module. 4 illustrates one embodiment of a plurality of operations for setting a parameter indicating a bus interface configuration. FIG. 6 illustrates one embodiment of an operation for selecting a bus interface configuration to process a transfer request. FIG.

  In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. They include, for example, multiple logic implementations, multiple opcodes, means for specifying multiple operands, multiple implementations of resource partitioning / sharing / duplication, multiple types and relationships for multiple system components, and logic parties There are multiple options for shoting / integration. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In other instances, multiple control structures, multiple gate level circuits, and multiple complete software instruction sequences have not been shown in detail in order to avoid obscuring the present invention. Those skilled in the art who have read the detailed description will be able to implement the appropriate functionality without having to repeat experiments.

  References herein to “one embodiment”, “an embodiment”, “an exemplary embodiment”, and the like indicate that the described embodiment may include particular features, structures, or characteristics. , Indicates that each embodiment does not necessarily include that particular function, structure, or characteristic. Moreover, such terms are not necessarily referring to the same embodiment.

  In the following detailed description and claims, the terms “coupled” and “connected” may be used with their derivatives. It should be understood that these terms are not intended as synonyms for each other. “Coupled” is used to indicate that two or more elements, which may or may not be in direct physical or electrical contact with each other, cooperate or interact with each other. “Connected” is used to indicate that communication is established between two or more elements coupled together. Certain embodiments relate to a plurality of electronic assemblies of a plurality of memory devices. Embodiments include both a plurality of devices and methods for forming a plurality of electronic assemblies.

  FIG. 1 shows an embodiment of a computing system 2 that includes one or more processors 4, a host memory controller 6, and a plurality of memory modules 8a, 8b, usually mounted on a motherboard. The plurality of processors 4 may include a central processing unit and a multi-core processor. In response to a plurality of memory access requests from a plurality of processors 4, the host memory controller 6 communicates with a plurality of memory modules 8a and 8b via a bus 10, which is also referred to as a channel or a bus interface. Here, both of the memory modules 8a and 8b are connected to the same bus 10 separately and independently. The host memory controller 6 may include a request counter 7, a write credit counter 9, and a scramble seed value 11. Based on the number of requests indicated by the request counter 7, the request counter 7 is incremented when receiving a request signal for a grant that will be used later when issuing a plurality of grants. The write credit counter 9 indicates a large number or a plurality of credits permitting a plurality of write requests to be transmitted to one of the memory modules 8a and 8b. The scramble seed value 11 is used to descramble the data requested to be read from one of the memory modules 8a, 8b.

  In the embodiment of FIG. 1, the memory modules 8 a and 8 b are mounted in a plurality of slots or memory sockets on the system 2 motherboard. The memory modules 8a, 8b may comprise a plurality of memory modules of the same or different types having a pin arrangement that is compatible with the pin arrangement in the plurality of memory slots on the motherboard. Further, the plurality of memory modules may support the same or different memory protocols, such as the Double Data Rate Fourth Generation (DDR4) protocol and additional protocols. Although only two memory modules 8a, 8b are shown, there may be a plurality of memory modules.

  Each of the memory modules 8a, 8b includes memory chips 12a, 14a, 16a, 18a and 12b, 14b, 16b, 18b for storing data, respectively, on one or both sides of the memory module. A plurality of memory chips, such as a plurality of DRAM chips, disposed on one or both sides of the memory modules 8a, 8b package include a plurality of storage elements for storing data used by the processor 4.

  Each memory module 8a, 8b may include memory module controllers 20a, 20b for coordinating memory management and multiple access operations with the host memory controller 6. The host memory controller 6 manages a plurality of read and write operations and a plurality of memory management operations for the memory modules 8a and 8b connected to the bus 10, and allows the processor 4 to communicate with the memory modules 8a and 8b. Including logic. The host memory controller 6 may be integrated with the processor 4 or may be implemented in logic separate from the processor 4 on the motherboard of the system 2.

  As long as different types of memory modules 8a, 8b are compatible with the pin architecture in multiple memory sockets, the motherboard of system 2 may include memory sockets that are compatible with different multiple types of memory chips and are different. Allow different types of memory modules 8a, 8b that support different types of memory devices that support different types of memory protocols.

  In one embodiment, the memory modules 8a, 8b may comprise the same or different types of dynamic random access memory (DRAM). In one embodiment, the memory modules 8a, 8b may be un-buffered DIMMs (UDIMMs), Load Reduced Dual-inline Memory Modules (LRDIMMs), Small Outline Dual In-line Memory Modules (SODIMMs), etc. (DIMM) may be provided. The memory modules 8a, 8b may implement various forms of memory, including but not limited to NAND type (flash) memory, ferroelectric RAM (FeTRAM), nanowire based non-volatile memory, phase 3D (3D) cross-point memory such as change memory (PCM), memory incorporating Memristor technology, magnetoresistive random access memory (MRAM), Spin Transfer Torque (STT) -MRAM, and the like.

  In certain embodiments, memory modules 8a, 8b may support a plurality of different protocols, since a plurality of different types of memory modules 8a, 8b may be mounted and connected to the bus 10. For example, the memory module 8a may comprise a DIMM of a type that conforms to the Double Data Rate Fourth Generation (DDR4) Static DRAM (SDRAM) protocol, and the memory module 8b is a memory using the DDR4 protocol on the same bus 10. Different protocols compatible with module 8a may be used. Multiple alternative and different protocols may also be used and implemented within the memory modules 8a, 8b.

  When the memory modules 8a and 8b support a plurality of different DRAM protocols, the host memory controller such as DDR4 as the first protocol specific to the memory module 8a and the second memory protocol specific to the memory module 8b. 6 is configured to communicate over the bus 10 using a plurality of different protocols. The read request and the management request for the memory module 8a are implemented using the first memory protocol and the second memory module 8b using the second memory protocol.

  FIG. 2 provides further details of one embodiment of memory module 8 such as memory modules 8a, 8b, and performs a plurality of memory module operations and a plurality of interactions with host memory controller 6. Shown as including. In a plurality of specific implementations, one of the plurality of memory modules, such as 8b, may include the memory module of FIG. 2, and the other memory module, such as 8a, such as the memory module 8a that conforms to the DDR4 standard is a memory. The module controller 20 may not be included. In such embodiments, the memory module 8a may include registers, as in the case of LRDIMMs, as in the case of RDIMMs or buffers.

  The memory module 8 may include a plurality of mode registers 22, a read buffer 24, a power management operation register 26, a write buffer 28, a write credit counter 30, a scramble seed value 32, and an interface parameter 34 in the memory module controller. The plurality of mode registers 22 have data that can be configured using a mode register set (MRS) command within the memory module controller. The read buffer 24 is for buffering the read data returned to the host memory controller 6 in response to the read command. The power management operation register 26 indicates a plurality of power management operations to be executed. The write buffer 28 is for buffering write data before being written to the memory chips 12, 14, 16, 18. The write credit counter 30 indicates a large number of write credits to be returned to the host memory controller 6. The scramble seed value 32 is used to randomize read data transferred to the host memory controller 6 via the bus 10. The interface parameter 34 identifies a supported interface configuration of the bus 10. The plurality of buffers and the plurality of parameters 24, 26, 28, 30, 32 and 34 may be implemented in the memory module controller 20 or in a circuit outside the memory module controller 20 in the memory module 8. Certain specific parameters 26, 30, 32 and 34 may be implemented in the mode register 22.

  In certain embodiments, the memory module 8a may comprise a near memory configured as a caching layer for a far memory that includes the memory module 8b. In such a configuration, the near memory module 8a should have the effect of reducing the access time of the most frequently accessed system memory addresses that are designed to be cached by a particular far memory module 8b. The plurality of near memory devices may be configured as a direct mapped cache for their corresponding fur memory.

  The described embodiments of the memory module controller 20 and the host memory controller 6 may be encoded in hardware logic such as an application specific integrated circuit (ASIC), field programmable gate array (FPGA), or the like.

  A plurality of components according to embodiments of the present invention may also be provided as a machine readable medium storing a plurality of machine executable instructions. Machine-readable media include, but are not limited to, flash memory, multiple optical disks, read-only compact disks (CD-ROM), Digital Versatile / Video Disk (DVD) ROM, random access memory (RAM), erasable programmable ROM (EPROM) ), An electrically erasable programmable ROM (EEPROM), a magnetic or optical card, a propagation medium, or other type of machine-readable medium suitable for storing a plurality of electronic instructions. For example, embodiments of the present invention may be downloaded as a computer program that can be transferred from a remote computer (such as a server) to a requesting computer (such as a client) via a network transmission.

  FIG. 3 shows the arrangement of a plurality of pins on a memory module 8a, 8b having a host memory controller 6, a plurality of bus 10 lines and memory modules 8a, 8b. Such multiple pin designations are described below or are known in the art.

[Encoding of multiple functions in the request signal]
In certain embodiments, the memory module controller 20 sends a request signal, such as REQ # 50, to the host memory to indicate that there is data in the read buffer 24 that the host memory controller 6 should return as part of the read command. It may be transmitted to the controller 6. The request signal may comprise a REQ # clock enable (CKE) signal 50 shown in the pinout diagram of FIG. The memory module controller 18 may send a request signal with a minimum pulse width to ensure detection by the host memory controller 6, which may comprise two clock cycles in some specific implementations. The memory module controller 20 may further encode additional functions performed by the host memory controller 6 in the request signal. Multiple functions may be indicated in a single signal by encoding multiple additional functions in the request signal to maximize the number of operations in the single signal and the information communicated.

  FIG. 4 illustrates one embodiment of operations performed by the host memory controller 6 and memory module controller 20 that use request signals to communicate a plurality of additional functions to the host memory controller 6. At initialization (block 100) of the operation of generating a request signal, which may be part of a read command, transferring data from the read buffer 24 back to the host memory controller 6, the memory module controller 20 includes a function included with the request signal. Are determined (at block 102). Such a function may indicate a plurality of additional operations to be performed by the host memory controller 6, such as a specific error condition or interrupt or other functions. Next, the memory module controller 20 determines the pulse width that is used to indicate or encode the determined function (at block 104). For example, a pulse width equal to the minimum pulse width is used to ensure detection of the request signal by the host memory controller 6 and may indicate or encode the first function, and additional pulse widths greater than the minimum pulse width. May be used to indicate multiple additional functions. For example, if the minimum pulse width to ensure detection is 2 clocks, this minimum pulse width for the request signal may indicate one function, and the pulse widths 6, 10, 14 Different functions may be indicated. The pulse width 14 may indicate a catastrophic failure. Furthermore, in order to ensure proper detection of the pulse width by the host memory controller 6, a plurality of different pulse widths for request signals associated with a plurality of different functions can be obtained in certain embodiments, such as three cycles. May be divided by a minimum number of clock cycles. The memory module controller 20 generates a request signal having the determined pulse width for transmission to the host memory controller 6 (at block 106).

  Upon detecting the request signal REQ0 # on pin 50 having a minimum or first pulse width such as two clocks (at block 108), the host memory controller 6 needs to be sent to the memory module 8b that sends the request signal. The request counter 7 indicating a number of grant signals is incremented (at block 110). After incrementing the request counter 7, the host memory controller 6 uses a bus 10 for issuing a plurality of grant requests so that the requests indicated in the request counter 7 are batch-processed at different random times, That is, it may wait until a slot on the data bus is available. Upon receipt of the grant signal, the memory module controller 20 responds to a read request from the host memory controller 6 and transmits data in the read buffer 24, such as collected and buffered data, to the host memory controller 6 (block 112). In).

  After determining the minimum or first pulse width of the request signal 50, if the request signal 50 does not continue beyond the measured minimum pulse width (at block 114), control ends. Alternatively, if the measured request signal (in block 116) does not continue beyond a second pulse width, such as 6 clocks, the host memory controller 6 may change the second function associated with that second pulse width. May be performed (at block 118). Alternatively, if the request signal 50 does not continue beyond a measured third pulse width, such as 10 clocks (in block 120), the host memory controller 6 may use a third function associated with the third pulse width. May be performed (at block 122). If the pulse width continues and a fourth pulse width such as 14 clocks is measured (at block 124), the host memory controller 6 may perform catastrophic error handling that the host memory controller 6 should perform. (At block 126).

  The described embodiments relate to four functions for four different pulse widths of the request signal, but in specific implementations, more than four as indicated by more or less than four pulse widths. Or there can be fewer functions. Furthermore, one pulse width may indicate a series of functions to be performed.

  In the operations of FIG. 4, functions that exceed the initial request grant function are only processed after it has been determined that the pulse width does not continue beyond the pulse width associated with those additional functions. It is. In an alternative embodiment, each additional function may be performed when measuring the pulse width associated with the function, even if the pulse width continues beyond the measured pulse width. . Therefore, each function is executed when a plurality of measured values of the pulse width exceed the trigger pulse width.

  In the described embodiment of FIG. 4, by using different pulse widths for the memory module controller that can be divided by the minimum number of clocks that guarantees detection of the pulse width by the host memory controller 6, multiple different pulse widths are used. The function may be encoded into the request signal by the memory module controller 20. Thus, with a single request signal, the memory module controller 20 may signal a request signal, such as a request to return data from the read buffer 24, and one of a plurality of different functions.

[Adjusting the output timing from the first memory module based on the difference of the plurality of components from the second memory module to match the timing from the second memory module]
In some specific implementations, the memory modules 8a and 8b may comprise a plurality of different types of memory modules having a plurality of different components. For example, the memory module 8a may or may not include a plurality of registers and a plurality of data buffers not included in the memory module 8b, and vice versa. The memory modules 8a, 8b may support a plurality of different memory protocols. The described embodiments provide a plurality of techniques in which one memory module, eg 8b, adjusts its timing to match the timing of the other memory module, eg 8a. As a result, the host memory controller 6 does not need to adjust to different timings from different memory modules such as different types of DIMMs. By having the memory module controllers 20a, 20b handle multiple timing adjustments, excessive multiple turnaround cycles and performance loss in the host memory controller are avoided.

  FIG. 5 shows a plurality of operations for adjusting the output timing based on the difference in the plurality of components from the other memory modules 8a and 8b on the bus 10 executed by the memory module controller 20 such as the memory module controller 20b. One embodiment which concerns on is shown. Upon initializing the operation of outputting data from the data buffer 24 (at block 200), the memory module controller 20b is based on at least one component in at least one of the memory modules 8a, 8b on the channel. A timing adjustment is determined (at block 202). Blocks 204-208 provide an embodiment of multiple operations for determining timing adjustments. The memory module controller 20b may accelerate the timing in response to the first memory module 8b having at least one component that affects the output timing that is not included in the other second memory module 8a ( In block 204). Further, in response to the other second memory module 8a on the bus 10 having at least one component that affects the output timing in the second memory module 8a, not included in the first memory module 8b, A delay may be added to the timing (at block 206).

  The memory module controller 20b may then determine a net timing adjustment (at block 208) from any added delay or timing acceleration. The memory module controller 20b adjusts the output timing from the data buffer 24 to the host memory controller 6 based on the determined timing adjustment to match the output timing of the second memory module 8a (at block 210).

  For example, when the memory module 8b including the controller 8b that executes a plurality of calculations includes the data buffer 24 not included in the other memory module 8a, the other second memory module 8a is included in the first memory module 8b. When no data buffer is included, the timing adjustment may include acceleration of output timing. In another implementation, as in the case of RDIMM, if the other memory module 8a has a register for performing calculations that is not included in the memory module 8b, in the other memory module 8a that is not included in the memory module 8b. The timing adjustment includes delaying the output timing in order to match the register performing the above calculation. If the timing acceleration for the data buffer 24 is greater than the delay added for the register in the other memory module 8a, the net timing adjustment includes timing acceleration. Similarly, if the added delay is greater than the acceleration, the net adjustment includes adding a delay to the timing. When the memory module 8b that performs a plurality of calculations does not include a plurality of registers or a plurality of data buffers 24 included in the other memory module, for example, when the other memory module 8a is an RDIMM and an LRDIMM, the memory module controller 20b The timing may be delayed to accommodate multiple delays caused by multiple additional components in the other memory module 8a.

  If the memory modules 8a, 8b comprise a plurality of different types of DIMMs such as a plurality of UDIMMs, a plurality of RDIMMs and a plurality of LRDIMMs, the memory modules 8a, 8b You may have on command, address, and multiple control buses.

  In some particular described embodiments, the timing adjusted output comprises a data output from the data buffer 24 on a data bus in the bus 10. In alternative embodiments, the adjusted output signals may comprise outputs other than data outputs.

  Although multiple operations have been described for one memory module that performs multiple timing adjustments, one or more memory modules 8a, 8b on the bus 10 may perform multiple timing adjustments according to FIG. .

  In the multiple timing adjustments described, the memory module controller 20b adjusts the timing of its output, such as the output from the data buffer 24, to match the timing for multiple similar types of output from the other memory module 8a. As a result, the host memory controller 6 does not need to make any timing adjustments to match different configurations of the different memory modules 8a and 8b on the bus 10.

[Encoding of multiple registers in the mode register set (MRS) command]
The memory module controller 20 may include a plurality of mode registers 22. In certain embodiments, the memory module controller 20b may implement a first protocol that is different from the second memory protocol used by the other controller 8a, eg, DDR4. However, the memory module controller 20b may support a specific plurality of commands from the second protocol such as DDR4 of the other memory module 8a, for example, a mode register set (MRS) command, It may be used for a different purpose than that used by the memory module controller 20a that implements one memory protocol.

  FIG. 6 illustrates one embodiment of the MRS command 250. The MRS command 250 may or may not include multiple MRS fields from another memory protocol such as DDR4. The command 250 designates an operation code 252 indicating an MRS operation. Address registers A0-A13 may be used to provide data to one of the plurality of mode registers 22 in memory module controller 20, and the plurality of register bits 254 write the data in addresses A0-A13. The power mode register 22 is shown. For example, if there are 16 mode registers 22, four register bits 254, eg, BA 0, BA 1, BG 0, BG 1, should be used, one of the 16 mode registers 22 in the memory module controller 20. May be shown.

  In one embodiment, the MRS command 250 may be used to provide multiple configuration parameters to the memory module 8 before the bus 10 is serviced for multiple bus operations such as read and write operations. Cycle commands may be provided. Here, the read and write operations may include a two-cycle command. Thus, the MRS command 250 corresponds to the address input signals A0 to A17 indicated by the line 52 in the pinout design of FIG. 3 and the command input signal BG1: indicated by the lines 54 and 56 in the pinout design of FIG. Use 0 and BA1: 0. In certain embodiments, the address input signals A14-16 include MRS command operation codes.

  FIG. 7 illustrates one embodiment of operations performed by the host memory controller 6 and the memory module controller 20 to program the plurality of mode registers 22 in the memory module controller 20. During initialization, such as before the bus 10 is serviced for read and write operations, which may include multiple commands transmitted in two clocks, the host memory controller 6 is configured with the data contained in the address field A13: 0. A MRS command 250 for specifying the mode register 22 in the memory module controller 20 may be generated (at block 280) and transmitted. For address field A13: 0, MRS command 250 may be sent in one clock cycle.

  Memory module controller 20 receives MRS command 250 (at block 282) and determines (at block 284) a mode register 22 indicated by a plurality of register bits 254 on lines 54 and 56 (FIG. 3). The memory module controller 20 then writes the data provided in the address bits A0: A13 to the determined mode register 22 (at block 286).

  The host memory controller 6 further implements a DDR4 protocol in accordance with the DDR4 protocol to program one of eight mode registers in one of the memory chips 12a, 14a, 16a, 18a. An MRS command 250 for sending to a memory module such as 8a may be used. Register bits BA0, BA1, BG0 identify the mode register within the memory chip, and bit BG1 indicates whether those bits are inverted. In this way, the host memory controller 6 causes the memory controllers 20a and 20b implementing a plurality of different memory protocols to generate a plurality of different operations according to the plurality of different protocols using the same MRS command format. It's okay. For example, when the MRS command 250 is used for the memory module 8a that supports DDR4, the MRS command 250 writes data to the mode register in one of the memory chips 12a, 14a, 16a, and 18a. When the MRS command 250 is used for the memory module 8 b having the plurality of mode registers 22 in the memory module controller 20, the MRS command 250 is not in the DRAM chip 12, 14, 16, 18 but in the memory module controller 20. Data is written to the plurality of mode registers 22. Thus, the host memory controller 6 may use the same MRS command format with multiple memory modules that support multiple different memory protocols such as DDR4 and some other protocol.

[If the chip select signal is received only for the first half command, the second half command is received by the memory module]
Multiple described embodiments enable multiple techniques for a memory module to receive commands in multiple parts, such as bisection, that only requires one chip select signal for the memory module 8 to be received. provide. As a result, the memory module 8 automatically receives the latter half command after a delay interval from when the first half command is transmitted. Further embodiments provide multiple techniques for incorporating delays to automatically receive late commands in a fast timing mode such as 2N timing. In the high-speed timing mode, the memory modules 8a and 8b operate at a higher speed than a normal timing mode such as 1N timing.

  In certain embodiments, the commands occupy 2 bits / lane and are transmitted with multiple back-to-back clocks. This allows the entire address to be sent within one command instead of two commands, for example, row and column information is sent in one command. The memory module controller 20 recognizes the high-speed (2N) timing mode via the host memory controller 6 that programs the plurality of mode registers 22 on the memory module controller 20.

  FIG. 8 provides one embodiment of a timing chart for a normal timing mode such as 1N timing for multiple commands such as multiple read commands. A plurality of commands are transmitted in two parts indicated by CMD0a, CMD0b, CMD1a, CMD1b, CMD2a, and CMD2b. For the first memory module 8a, the host memory controller 6 arranges the first half command CMD0a and the chip select signal S0 # 302, also indicated as the SO # line 58 in FIG. When receiving the chip select signal 302, the first memory module 8a may receive the first command CMD0a in the cycle 300, and further, for example, a clock cycle after one clock cycle with a delay interval from the first command CMD0a. At 304, the latter command CMD0b may be automatically received.

  In order to select the second memory module 8b, the host memory controller 6 arranges the command CMD1a in the first half and the chip select signal S2 # 306, which is also shown as the S2 # line 60 in FIG. You can do it. When receiving the chip select signal 306, the second memory module 8b may receive the first half command CMD1a in cycle 308, and may automatically receive the second half command CMD1b in cycle 310 after one clock cycle.

  FIG. 9 provides one embodiment of a timing chart for a fast timing mode, such as 2N timing, which is faster than normal timing. Here, both parts of each command for two clock cycles, shown as CMD0a, CMD0b, CMD1a, CMD1b, CMD2a, CMD2b, are present on the bus 10. The host memory controller 6 arranges the command CMD0a in the first half of the two cycles on the bus at the clock cycle 320 for the first memory module 8a, and the chip select signal S0 # 322 also shown as the SO # line 58 in FIG. May be placed in the clock cycle 324, one cycle after the first command CMD0a is placed on the bus 10, and thus the chip select signal is delayed in the high-speed timing mode. When the first memory module 8a receives the chip select signal 322, the first memory module 8a may receive the first half command CMD0a in the clock cycle 324, and further the delay interval indicated by the second half command CMD0b being two clock cycles after the chip select signal 322. And may be received automatically at the start of clock cycle 328.

  The host memory controller 6 arranges the first half command CMD1a in the cycle 330 and the chip select signal S2 # 332 also indicated as the S2 # line 60 in FIG. 3 in the cycle 332 after one cycle for the second memory module 8b. You can do it. The second memory module 8b may receive the first half command CMD1a in the clock cycle 336 of the chip select signal 332, and may automatically read the second half command CMD1b in a cycle 338 after two clock cycles. In this way, the host memory controller 6 delays the chip signal by one clock cycle in the middle of the first half command, and the memory module controller 20 delays the second half command read by two cycles after the first half command is read.

  FIG. 10 illustrates one embodiment of the operations performed by the host memory controller 6 and the memory module controller 20 for the 1N timing mode for commands that occupy 2 bits in a back-to-back cycle. During initialization for operation in the 1N timing mode, the host memory controller 6 may program the memory module controller 20 via a plurality of bits in a plurality of mode registers 22. When initializing the two-cycle command in the normal timing mode 1N (in block 350), the host memory controller 6 places the first half command (one cycle) on the bus 10 in the first clock cycle (in block 352). ). A chip select command is also placed on the bus 10 in the first clock cycle (at block 354). When the memory module controller 20 is programmed in the normal timing mode, upon detecting a chip select signal addressed to a particular memory module 8 including the memory module controller 20 (at block 356), the memory module controller 20 In the first clock cycle on bus 10 (at block 358).

  Further, the host memory controller 6 places the second half command (in the back-to-back cycle from the first half) on the bus 10 in the second clock cycle one clock cycle after the first clock cycle (in block 360). ). The memory module 8 selected by the chip select signal waits for a delay of one cycle from the time when the chip select signal is received and the first half command is received. (In block 362). The memory module controller 20 may automatically receive the latter half command on the bus 10 without requesting the chip select signal to access the bus 10.

  FIG. 11 illustrates one embodiment of the operations performed by the host memory controller 6 and the memory module controller 20 for a fast timing mode such as 2N for commands that occupy 2 bits in a back-to-back cycle. Indicates. The memory module controller 20 may be programmed via a plurality of bits in the plurality of mode registers 22 during initialization to operate in the fast timing mode. When initializing a two-cycle command in the fast timing mode (in block 380), the host memory controller 6 places the first half command (in one cycle) on the bus 10 in the first clock cycle (in block 382). . Next, a chip select signal is placed on the bus 10 in a second clock cycle (in block 384) that can be one clock cycle from the first clock cycle. In this way, the chip select signal is placed on the bus in a delay such as one clock cycle after the first half command is placed. If the memory module controller 20 is programmed in the fast timing mode, when the memory module controller 20 detects a chip select signal addressed to a specific memory module 8 (at block 386), the memory module controller 20 The first half command on bus 10 is received in two clock cycles (at block 388).

  Further, the host memory controller 6 places the second half command (after two cycles from the first half) on the bus 10 in the third clock cycle two cycles after the first clock cycle (at block 390). The memory module controller 20 in the memory module 8 selected by the chip select signal buses the latter command by waiting for a delay of two cycles from when the chip select signal is received and the first command is received. 10 in a fourth clock cycle (at block 392). The memory module controller 20 may automatically receive the latter half command without waiting for the chip select signal on the bus 10.

  The described embodiments provide that in high speed timing modes such as 2N timing, the chip select signal delays one clock signal after transmitting the first half command. Further, the memory module may automatically receive the latter half command after two clock signals from the chip select signal. This delay in the chip select signal allows additional setup time in the high speed mode. The delay for receiving the second half command allows the command to be automatically received without requesting a chip select signal.

  In alternative embodiments, chip select signals may be placed on the bus at intervals different from the one clock signal described, and later commands may be received. Further, in alternative embodiments, the commands may consist of more than two parts (such as bits), use more than two clock cycles, and the memory modules 8a, 8b receive More than one additional part of a command may be automatically received at multiple clock signal delay intervals from the chip select signal without requiring multiple additional chip select signals for.

[Determine how to set multiple high address bits in memory module]
The memory module controller 20 may be configured to operate with multiple memory modules 8 having different pin and interface configurations. For example, one memory module has more pins for addressing than another memory module with fewer pins, such as SO-DIMM. A memory module with fewer addressing pins may provide a smaller address space than a memory module with more pins available for addressing. The supported interface configuration may vary depending on the functions of the host memory controller 6 and the bus 10, or may vary depending on the functions of the pin and interface configuration such as the SO-DIMM or UDIMM of the memory module 8.

  For such embodiments, a memory module to indicate a plurality of supported interface configurations, for example, indicating whether the memory module has a plurality of pins available for a plurality of high address bits. The controller 20 may use one of the plurality of mode registers 22. In such a case, if the memory module controller 20 is operating on a module 8 that does not have one or more pins for a plurality of high address bits available in other memory modules, the memory module controller 20 A predetermined value, eg, zero, is used for those multiple high address bits that are not available in the module. Thus, the memory module controller 20 assumes a value of zero for a plurality of high address bits when there is no pin for receiving a plurality of values for those high address bits. In one embodiment, the plurality of high address bits may comprise 52 address bits A17 and 62 bits C2: 0 shown in the pinout diagram of FIG. Certain memory modules, such as SO-DIMMs, may not include pins 52 and 62.

  FIG. 12 illustrates one embodiment of the operations performed by the memory module controller 20 to configure multiple settings for addressing. The host memory controller 6 may send an MRS signal indicating a supported interface configuration to the memory module 8. Upon receiving an MRS signal indicating a supported interface configuration (at block 400), the memory module controller 20 may update the mode register 22 addressed by the MRS signal to indicate the supported interface configuration. The MRS signal may indicate a DIMM type such as SO-DIMM, UDIMM, or the contents supported by the interface, such as whether multiple high address bits are supported. Upon response, the memory module controller 20 sets an addressed mode register 22 indicating the interface configuration to indicate the interface configuration to be communicated, eg, indicating whether multiple high address bits are supported ( At block 402).

  FIG. 13 illustrates one embodiment of the operations performed by the memory module controller 20 to handle addressing using higher level address bits. Upon receiving a command having multiple address bits from the host memory controller 6 (at block 420), the memory module controller 20 determines a supported interface configuration from the mode register 22. Such information indicates whether the current memory module 8 supports addressing in multiple high address bits. If the supported interface configuration does not support multiple high address bits (at block 422), for example if the memory module 8 does not have multiple pins 52 and 62, then at least one for the received address The high address bits are set to a predetermined value. That is, if there are no pins for multiple high address bits, multiple high address bits are assumed to be zero. If the supported interface configuration indicated by the mode register 22 indicates that multiple high address bits are available (at block 422), the memory module controller 20 receives on at least one high address pin 52,62. At least one high address bit is used for the address being addressed (at block 426).

  In alternative embodiments, the memory module controller 20 provides a plurality of predetermined values for a plurality of address bits other than a plurality of high address bits on a memory module that does not have a plurality of pins. It's okay.

  The described embodiments provide addressing for the memory module controller to provide a plurality of high order address bits for a memory module configuration that does not have a plurality of pins for providing a plurality of high address bits. It is possible to operate in a plurality of memory modules having a plurality of different pin configurations available for use. In this manner, the memory module controller can be deployed and operated within multiple memory modules such as SO-DIMM and UDIMM, and can provide multiple complete addressing functions for both interface configurations.

[Providing multiple extended operations for CKE low signal]
The described embodiments provide a plurality of techniques that allow the memory module 8 to pre-configure a plurality of power management operations. It is a number of operations that will be performed later when the memory module controller detects a clock enable (CKE) low signal on a CKE pin, such as pin 64 or 66 shown in the pinout diagram of FIG. . This allows an extended series of power management operations to be performed when the CKE low signal is activated, such as entering a defined sleep state.

  The previously transmitted pre-CKE command may activate multiple sleep states that may be different upon receipt of the CKE low signal. Such indicated states may include those specified in the Advanced Configuration and Power Interface (ACPI) standard. For example, the S3 standby state is sleep or interruption for the memory module 8 where a low level of power supply is maintained. The sleep state of S4 is a state in which the contents of the memory module 8 are stored in the non-volatile memory, and the memory module 8 is turned off. In the state of S5, the minimum power is supplied to the power supply unit, but the memory module 8 is turned off. The nonvolatile memory in which the contents are stored may be provided in various forms, including but not limited to NAND (flash) memory, ferroelectric RAM (FeTRAM), nanowire-based nonvolatile memory, phase change memory ( PCM) and other three-dimensional (3D) cross point memories, memories incorporating Memristor technology, magnetoresistive random access memory (MRAM), and Spin Transfer Torque (STT) -MRAM.

  FIG. 14 illustrates an embodiment of operations performed by the host memory controller 6 and the memory module controller 20 to facilitate multiple power management operations using the CKE low signal. For example, to initialize a plurality of operations that change the power management mode, such as switching to one of various recognized sleep modes, the host memory controller 6 communicates to the memory module controller 20 via the bus 10. In contrast, a pre-CKE command is transmitted (at block 500) indicating one or more power management operations. In one embodiment, the pre-CKE command may provide a code that indicates one or more specific actions or represents a series of actions. For example, the pre-CKE command may indicate, for example, a system state such as S3, S4, and S5 related to a plurality of ACPI sleep mode states or a power management state such as a sleep mode. They may be interpreted by the memory module controller 20 as a series of operations to be performed to implement the state.

  Upon receiving the pre-CKE command (at block 502), the memory module controller 20 sets the power management operation register 26 to indicate at least one power management operation indicated by the pre-CKE command. Thereafter, when the host memory controller 6 attempts to cause the memory modules 8a, 8b to implement the indicated power management operation state changes, the host memory controller 6 may be on the pins 64 or 66 (FIG. 3). CKE low signal 56 is asserted (at block 506), such as low. Upon detecting the CKE low signal (at block 508), the memory module controller 20 indicates whether the power management operation register 56 indicates a plurality of operations to be performed, such as a sleep mode state or a specific plurality of operations. Are determined (at block 510). If no operation is indicated, such as null or a default value, the memory module controller 20 outputs a CKE low signal, eg, deactivation of multiple internal clock signals, precharge power down or self refresh operation. A predetermined action for processing may be performed (at block 512). If multiple operations or power modes are indicated by register 26, memory module controller 20 performs multiple power management operations indicated by register 26 to implement a particular power management state, eg, a sleep state. (Block 514).

  The described embodiments provide techniques for configuring a memory module controller to perform a series of power management operations later using the CKE low signal. After the pre-CKE command is sent, the host memory controller 6 triggers more complex power management operations to change the power mode than normally triggered in response to the CKE low signal. Assert CKE low signal. In multiple described embodiments, fewer complex signals are required for power management because more complex power management operations, such as entering a sleep mode, can be initialized with a CKE low signal.

[Provide multiple write credits of host memory controller for multiple write commands]
Multiple described embodiments include a plurality of write credits included in a plurality of read data packets returned to reduce the consumption of bus bandwidth on the bus 10 for transmitting a plurality of write commands. A plurality of techniques for supplying a plurality of write credits of the host memory controller 6 to be used are provided.

  1, the host memory controller 6 includes a write credit counter 9 and transmits a plurality of write commands only when the write credit counter 9 has a plurality of positive credits. The write credit counter 9 is decremented when a write command is transmitted. There may be one write credit counter 9 for each memory module 8a, 8b. The memory module 8 includes a write buffer 28 for buffering received write data, and the received write data is later destaged to a plurality of storage elements in the memory chips 12, 14, 16, 18. Is done. The memory module controller 20 has a write credit counter 30 indicating a plurality of accumulated write credits to be returned to the host memory controller 6. In order to manage the use of the write buffer 28, a plurality of write credits are used. Therefore, the host memory controller 6 does not cause the write buffer 28 to overflow by transmitting write data.

  FIG. 15 shows an embodiment relating to a plurality of operations for the host memory controller 6 and the memory module controller 20 to process a write command. Upon generation of the write command, the host memory controller 6 determines whether the write credit counter 30 is greater than zero, ie, non-empty (at block 602). In that case, a write command is sent to the memory module 8 (at block 604). If the host write credit counter 9 is empty (at block 602), the host memory controller 6 waits until multiple credits are available to send a write command.

  Upon receipt of the write command (at block 610), the memory module controller 20 buffers the write data in the write buffer 30 (at block 612). When the write data from the write buffer 30 is destaged to a plurality of storage elements in the memory chips 12, 14, 16, 18 (at block 614), the memory module controller 20 writes a write credit indicating the credits returned to the host memory controller 6. Counter 30 is incremented (at block 616) to allow another write command. If the write credit counter 30 exceeds the threshold (at block 618), the memory module controller 20 indicates at least one of the plurality of write credits indicated in the write credit counter 30 that does not indicate any read data. A read data packet is generated (at block 620). A read data packet is sent to the host memory controller 6 (at block 622) and the write credit counter 30 is decremented by the number of credits returned (at block 624). In certain embodiments, there may be a limit on the number of credits returned, so the write credit counter 30 may or may not be reduced to zero. Thus, when the read packet is not transmitted for a long time, the memory module controller 20 transmits the read data packet without data and provides a plurality of write credits. As a result, the host memory controller 8 is blocked from transmitting a plurality of write commands without running out of a plurality of write credits. Alternatively, multiple write credits may be returned in multiple packets other than the read data packet.

  FIG. 16 illustrates one embodiment of multiple operations performed by the memory module controller 20 to generate a read data packet to return to the host memory controller 4. When generating a read data packet containing read data to return to a read request from the host memory controller 6 (at block 640), if the write credit counter 30 is greater than zero (at block 642), the memory module controller 20 Some or all of the write credits in 30 are indicated in the read data packet (at block 644) and the read data packet is sent to the host memory controller 6 (at block 646). The write credit counter 30 is decremented by the number of write credits returned (at block 648). The number of write credits returned may or may not be all credits in the counter 30. In this way, the plurality of write credits are collectively processed in the read data packet and returned to the host memory controller 6. This optimizes message usage for communicating information. Since there is a fixed set of responses, the memory module controller 20 does not have to show all credits in one packet. For example, the memory module controller 20 may indicate 0, 1, or 4 for the number of write credits returned in the read packet, or when multiple write credits are returned without read data (FIG. 15). In block 620, 0, 1, 4, or 8 may be indicated for a packet with no data.

  FIG. 17 illustrates one embodiment of multiple operations performed by the host memory controller 6 to process read data packets from the memory module 8. When the read data packet is received (in block 660), if the read data packet indicates multiple write credits (in block 662), the host memory controller 6 sets the write credit counter 9 to the write credit indicated in the read data packet. Increment by number (at block 664). After incrementing the write credit counter 9 (from block 664) or if there are no multiple write credits provided (from the no branch of block 662), if the read data packet contains read data (at block 666), The read data is processed (at block 670). After reading the data or if the packet contains no data (from the no branch of block 666), the read data packet is discarded (at block 668).

  The described embodiments allow the memory module 8 to reduce the bandwidth of the bus 10 by batch processing multiple write credits or other used multiple messages in multiple read packets. A plurality of techniques for communicating a plurality of write credits to the host memory controller 6 are provided.

[Execute multiple error handling operations using multiple error signals]
The described embodiments provide a number of techniques for simple error flow in the memory module 8 that coordinate error handling with the host memory controller 6. In multiple described embodiments, memory module controller 20 may signal an error on error pin 68ERR0 # shown in the pinout design of FIG. The memory module controller 20 may assert an error (ERR) low signal on the error pin 68 to signal the start of multiple error handling operations, and the memory module controller 20 may indicate that the error mode has ended and the bus An error (ERR) high signal may be asserted on the error pin 68 to signal that 10 has been returned to an initial state ready for operation. In this way, communication for adjusting error handling between the memory module controller 20 and the host memory controller 6 on the bus 10 is intended to avoid consuming bandwidth with wider error handling adjustments. , With a limited number of signals.

  FIG. 18 shows an embodiment relating to a plurality of operations between the memory module controller 20 and the host memory controller 6 for managing a plurality of error processing operations when an error is detected in the memory module 8. Upon detecting an error (at block 700), the memory module controller 20 first signals on the bus 10, such as an ERR low signal, to signal to the host memory controller 6 that a plurality of error handling operations have been initiated. An error signal is asserted on pin 68 (FIG. 3) (at block 702). When a first error signal, such as an ERR low signal, is detected on pin 68 (at block 704), the host memory controller 6 sends a receipt confirmation that the first error signal has been received (at block 706), then Subsequently, in response to the first error signal, the read operation and the write operation for the memory module 8 having the error are interrupted (at block 708). The host memory controller 6 may perform a plurality of further error handling operations, such as setting the write credit counter 9 to a maximum value (at block 710). Thus, the host memory controller 6 assumes that all writes are flushed from the write buffer 28 to multiple storage elements in the memory chips 12, 14, 16, 18 as part of error handling. .

  Upon receipt of an acknowledgment for receipt of the first error signal from the host memory controller 6 (at block 712), the memory module controller 20 performs a plurality of error handling operations to return the bus 10 to its initial state. Such multiple operations include discarding all pending read requests (at block 716), deallocating multiple writes in write buffer 28 to multiple storage elements in memory chips 12, 14, 16, and 18. Erasing (at block 722) a plurality of write credits to return from the stage (at block 718) and the write credit counter 30 may be included. After completion of multiple error handling operations, the memory module controller 20 asserts a second error signal, such as ERR high, on the error pin 68 (at block 724) to signal that error handling is complete. Upon detecting this second error signal (at block 726), the host memory controller 6 resumes read and write operations to the memory module in response to detection of the second error signal (at block 728).

  With respect to the described embodiments, the memory module 8 and the host memory controller 6 allow a limited number of signals without exchanging multiple communications over multiple errors and transactions executed over the bus. To perform multiple complete error handling operations. Each component 8 and 20 assumes that the other performs a complete reinitialization of the bus 10 in response to an error in the memory module 8.

[Use error signal to indicate write request error and receipt of write request]
Several described embodiments may indicate that a write request has been successfully completed and an error signal, for example, by not asserting an error signal, such as an error signal low, within a predetermined time since the transmission of the write request. By asserting, the memory module controller 20 provides a plurality of techniques for indicating to the host memory controller 6 that the write request has failed. When the error signal is detected, the host memory controller 6 retransmits the write request when the error signal is received within a predetermined time from the transmission of the write request. In this manner, the bandwidth of the bus 10 is saved by not transmitting a plurality of write completion receipt confirmations to the host memory controller 6 after each write request is completed.

  FIG. 19 illustrates one embodiment of the operations performed by the memory module controller 20 and the host memory controller 6 to illustrate the write request and the receipt of multiple errors within the write request. When memory module controller 20 detects a write error for one of the multiple write requests being processed (at block 750), memory module controller 20 asserts an error signal, such as error low signal ERR0 #, on pin 68 (FIG. 3). To indicate that no error has occurred, the memory module controller 20 maintains the error high signal active. The memory module controller 20 may additionally use the ERR0 # signal on pin 68 to indicate multiple errors unrelated to multiple write request errors. Further, the memory module controller 20 implicitly indicates the normal end of the write request by not transmitting an error low signal within a predetermined time from the write request, such as when a write request is transmitted / received.

  When the host memory controller 6 detects an error low signal (at block 754), if an error low signal is received within a predetermined time from one or more write requests (at block 756), the host memory controller 20 Retransmits (at block 758) one or more determined requests transmitted within a predetermined time from receipt of the error low signal. In certain embodiments, the host memory controller 20 retransmits multiple write requests even if the error signal is irrelevant for multiple write errors. Thus, if the error signal row is not received within a predetermined time, the host memory controller 20 processes a plurality of write requests as having been completed normally, even if the error signal row is a plurality of write requests. Even when signaling an error unrelated to the error. If an error signal low is received within a predetermined time, the write request is processed as having failed.

  After retransmitting multiple write requests (in block 758) or if there are multiple write requests transmitted within a predetermined time (from the no branch of block 756), the host memory controller 6 will generate an error low signal. Is determined (at block 760) to determine if there are error handling operations to be performed that are unrelated to multiple write errors. If present, the host memory controller 6 performs an error handling operation unrelated to multiple write errors (at block 762).

  For the described embodiments, the memory module 8 does not send a plurality of write completion receipt confirmations after completion of each write. Instead, the host memory controller 6 assumes that the write has been completed if no error signal is received within a predetermined time after the write request. Furthermore, even if the memory module controller 20 signals an error unrelated to the write error, if the error signal is received within a predetermined time after the transmission of the write request, the host memory controller 6 Resends the write request.

[Scramble the read data in the memory module]
Multiple described embodiments are stored for returning to a read request, including scrambling of the read address, after the memory module controller 20 descrambles the write data and stores the unscrambled write data. Provides multiple techniques for scrambling data. Scrambling for data being transmitted on the bus 10 for both reads and writes is performed to avoid the probability of complex sequences occurring within the transmission that can cause multiple errors on the bus 10. The

  To allow read data scrambling, the host memory controller 6 and memory module controller 20 maintain scramble seed values 11 and 32 (shown in FIGS. 1 and 2), respectively. Both seed values are initialized to a common value and then incremented after processing the read data packet. As a result, the incremented seed values 32 and 11 are individually set to the same value for the same read data packet, and the read request in the read data packet returned to the host memory controller 6 in response to the read request is made. Used to scramble and descramble data. In addition, the memory module controller 20 and the host memory controller 6 implement circuit logic for the same data scramble algorithm using seed values 11 and 32 to scramble and descramble the data, and the complexity generated on the bus 10 Remove the possibility of a bad sequence. In alternative embodiments, the host memory controller 6 and the memory module controller 20 may update the seed values 11 and 32 by a plurality of additional operations known in the art.

  FIG. 20 illustrates an embodiment of a plurality of operations performed by the memory module controller 20 and the host memory controller 6 to scramble read data transmitted via the bus 10. When the read request for the read address is received from the host memory controller 6 (at block 800), the memory module controller 20 reads the unscrambled read data from the storage elements such as the DRAM chips 12, 14, 16, 18 in the memory module 8. (At block 802). The memory module controller 20 uses the scramble seed 32 (at block 804) to scramble the requested read data and read address back to the read request from the host memory controller 6 (at block 806). Include in the packet. The scrambled 32 is then updated (at block 808). In one embodiment, the scrambled 11, 32 is then updated in a pseudo-random manner using a linear feedback shift register (LFSR) circuit.

  Upon receipt of the read packet, the host memory controller 6 descrambles the read data packet (at block 812) using the scrambled 11 to determine the read data and read address. Next, a read request associated with the unscrambled address is determined (at block 814) so that the read data can be returned to the read request. The scrambled 11 is updated (at block 816). In an alternative embodiment, the scrambled 11 and 32 may be updated before being used for scrambling and descrambling.

  FIG. 21 illustrates one embodiment of multiple operations performed by the memory module controller 20 to manage scrambled write data. Upon receiving a write request with scrambled write data from the host memory controller 6 (at block 830), the memory module controller 20 descrambles the scrambled write data using the write address of the write request (block 832). Then, the unscrambled data is written to the memory chips 12, 14, 16, 18 in the memory module 8 (at block 834).

  In the described embodiments, after the memory module controller 20 stores the unscrambled read data, the seed values 11 and 32 are used to scramble both the read data and the address on the bus 10. Makes it possible to return. Seed values 11 and 32 are updated for each component 8 and 20 to scramble and descramble multiple operations.

[Select one of multiple bus interface configurations to use]
The described embodiments provide interface parameters 34 that are configured within the memory module 8. This parameter is used by the memory controller 20 to determine the bus interface configuration used by the memory module 8. As described above, the memory module controller 20 includes a plurality of different bus interfaces 10, for example, a plurality of bus widths having a plurality of different bus widths, that is, a plurality of bus data widths such as a 9-bit interface, an 18-bit interface, a 72-bit interface, Can work with interface. For example, different types of DIMMs in which the memory module controller 20 may be implemented have multiple different bus width configurations, eg, different numbers of pins such as 72, 168, 184, 240, etc. A width may be implemented.

  FIG. 22 illustrates one embodiment of the operations performed by the memory module controller 20 to determine the interface parameters 34 (at block 900). The memory module controller 20 may determine the bus 10 interface configuration during initialization by scanning the bus 10 or querying the host memory controller 6. Alternatively, the host memory controller 6 or other component may communicate information about the bus 10 interface configuration, such as bus width, pin configuration, etc., via the bus 10 during initialization. In a further embodiment, the memory module 8 may have one or more strapping pins external to the bus 10 coupled to the memory module 8 and communicating the bus 10 interface configuration. The host memory controller 6 or other component may assert the bus interface configuration on at least one strapping pin. If there are only two supported bus interface configurations to communicate, one strapping pin may be used. If there are more than two supported bus interface configurations supported by the memory module controller 20, there may be additional pins to indicate more than two bus interface configurations. Upon determination of the bus interface configuration (at block 900), interface parameters 32 are set to indicate the determined interface parameters.

  FIG. 23 illustrates one embodiment of the operations performed by the memory module controller 20 to process a transfer request based on the bus interface configuration. Upon initialization of the operation to process the transfer request (at block 930), the memory module controller 20 selects the bus interface configuration corresponding to the interface parameter 32 (at block 932). In this case, the selected bus configuration may comprise one of a first, second, third, or further bus configuration, each having a different bus width and pin configuration. For example, the multiple bus configurations may comprise 9-bit, 18-bit, and 72-bit data buses, each of which may have a different number of pins. This selected bus configuration is used in processing multiple transfer requests and other multiple operations.

  The memory module controller 20 generates a number of transfers that process the transfer request based on the bus width of the selected bus interface configuration (at block 934). For example, if the selected bus configuration has a smaller bus width than the other possible configurations supported by the memory module controller 20, the bus configuration should accommodate that smaller bus width. , Requiring more transfers than required for supported bus interface configurations with larger bus widths and more pins. Thus, the memory module controller 20 may split the transfer request into different numbers of bus transactions based on the bus width of the selected bus interface configuration. The generated transfers are transferred over the selected bus interface configuration (at block 936).

  The described embodiments are operable within a memory module 8 having a plurality of different bus interface configurations to allow the memory module controller 20 to support the bus configuration of the memory modules 8 implemented therein. A memory module controller 20 is provided.

  Throughout this specification, reference to “one embodiment” or “an embodiment” includes a particular feature, structure, or characteristic described in connection with that embodiment in at least one embodiment of the invention. Indicates that Thus, references to “an embodiment” or “one embodiment” or “alternative embodiment” in various places in the specification are not necessarily all referring to the same embodiment. It should be emphasized and understood here. Further, a plurality of specific features, structures, or characteristics may be suitably combined in one or more embodiments according to the present invention.

Similarly, in the above description of embodiments of the invention, various features are represented in a single manner in an attempt to simplify the disclosure so as to assist in understanding the various aspects of the invention. It should be understood that the embodiments, figures, or descriptions may be summarized in some cases. This method of disclosure, however, should not be interpreted as reflecting an intention that the claimed subject matter requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all the features of a single embodiment disclosed above. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description. According to the present specification, matters described in the following items are also disclosed.
[Item 1]
A device used in a memory module coupled to a host memory controller via a bus, the device comprising:
A memory module controller logic for generating a request signal having a pulse width greater than or equal to a minimum pulse width for a host memory controller;
The minimum pulse width comprises a plurality of clock cycles necessary to ensure that the host memory controller detects the request signal;
The device wherein the pulse width of the request signal indicates at least one function in addition to the request signal to the host memory controller.
[Item 2]
The request signal causes the host memory controller to generate a grant signal,
The device of claim 1, wherein the memory module controller logic further transmits data to the host memory controller in response to receiving the grant signal.
[Item 3]
The pulse width causes the host memory controller to execute the at least one function indicated by the pulse width in addition to transmitting the grant signal in response to the request signal. device.
[Item 4]
4. The device according to claim 1, wherein a pulse width equal to the minimum pulse width indicates only the request signal and does not indicate an additional function. 5.
[Item 5]
Generating the request signal having at least a first pulse width greater than the minimum pulse width indicates at least a first function;
Generating the request signal having at least a second pulse width greater than the first pulse width indicates at least a second function;
Item 5. The device of any of items 1-4, wherein generating the request signal having at least a third pulse width greater than the second pulse width indicates at least a third function.
[Item 6]
When the request signal having the first pulse width is generated, the first function is indicated;
When the request signal having the second pulse width is generated, the second function is indicated,
Item 6. The device of item 5, wherein the third function is indicated when the request signal having the third pulse width is generated.
[Item 7]
The generated pulse width comprises one of a plurality of pulse widths equal to the minimum pulse width or a plurality of the minimum pulse widths;
The plurality of pulse widths are divided by a minimum number of clock cycles required to ensure detection of the pulse width by the host memory controller;
Item 7. The device of any one of items 1-6, wherein a plurality of different generated pulse widths encode a plurality of different functions in the request signal.
[Item 8]
The minimum pulse width comprises two clocks;
In item 7, generating the request signal with one of a pulse width of 6, 10, and 14 clocks indicates a different function that the host memory controller performs in addition to processing the request signal. The device described.
[Item 9]
Item 9. The device of any one of items 1 to 8, wherein the request signal includes a clock enable signal.
[Item 10]
A device coupled to at least one memory module via a bus, the device comprising host memory controller logic;
The host memory controller logic is
Detecting a request signal from the memory module having a pulse width greater than or equal to a minimum pulse width;
Determine the function corresponding to the pulse width of the request signal,
For executing the determined function,
The minimum pulse width has a plurality of clock cycles necessary to ensure that the host memory controller detects the request signal;
A device wherein the pulse width of the request signal indicates at least one function in addition to the request signal to the host memory controller.
[Item 11]
The host memory controller logic further comprises:
11. The device of item 10, wherein the device generates a grant signal to be transmitted to the memory module via the bus in response to receiving the request signal.
[Item 12]
The host memory controller logic further comprises:
Determining that the pulse width is equal to the minimum pulse width;
Item 12. The device of item 10 or 11, wherein the determined function comprises the request signal without an additional function in response to the pulse width of the request signal equal to the minimum pulse width.
[Item 13]
The host memory controller logic further comprises:
Determining the pulse width;
The determined function is
The first function,
A second function, and
Contains at least one of the third functions,
The first function is responsive to the determined pulse width including at least a first pulse width greater than or equal to the minimum pulse width;
The second function is responsive to the determined pulse width including at least a second pulse width greater than the first pulse width;
13. The device of any one of items 10 to 12, wherein the third function is responsive to the determined pulse width including at least a third pulse width that is greater than the second pulse width.
[Item 14]
When the request signal having the first pulse width is generated, only the first function is shown,
When the request signal having the second pulse width is generated, the second function is indicated,
14. The device of item 13, wherein the third function is indicated when the request signal having the third pulse width is generated.
[Item 15]
A device mounted in a first memory module coupled to a host memory controller and a second memory module via a bus,
The device comprises memory module controller logic,
The memory module controller logic is:
Determining a timing adjustment based on at least one component in at least one of the first memory module and the second memory module;
A device for adjusting output timing to the host memory controller based on the determined timing adjustment to match output timing in the second memory module.
[Item 16]
Determining the timing adjustment is
Accelerating the timing in response to the first memory module having at least one component that affects output timing not included in the second memory module; and
Adding a delay to the timing in response to the second memory module having at least one component that affects the output timing in the second memory module not included in the first memory module. The device according to item 15, comprising:
[Item 17]
Determining the timing adjustment includes both accelerating the timing and adding the delay;
The device of claim 16, wherein the determined timing adjustment includes a net of the accelerating and adding the delay.
[Item 18]
The at least one component includes a data buffer in the first memory module;
The device of claim 16, wherein the timing adjustment includes delaying the output timing when the second memory module does not include a data buffer as included in the first memory module.
[Item 19]
The at least one component includes a register in the second memory module;
The device of claim 16, wherein the timing adjustment includes delaying the output timing when the second memory module includes the register not included in the first memory module.
[Item 20]
20. The device of item 19, wherein the register in the second memory module is on a command, address, and multiple control buses.
[Item 21]
21. A device according to any one of items 15 to 20, wherein the output having the adjusted timing comprises an output from a data buffer of the first memory module.
[Item 22]
22. The device according to any one of items 15 to 21, wherein the first memory module and the second memory module include a plurality of different types of dual in-line memory modules (DIMMs).
[Item 23]
24. The device of item 22, wherein the second memory module comprises one of unbuffered DIMM (UDIMM), registered DIMM (RDIMM), and load-reduced DIMM (LRDIMM).
[Item 24]
24. The device of item 23, wherein the timing adjustment includes accelerating the output timing when the first memory module includes a data buffer and the second memory module includes a UDIMM.
[Item 25]
The timing adjustment is
Delaying the output timing when the second memory module includes an RDIMM and the first memory module does not include a register; and
24. The device of item 23, comprising accelerating the output timing when the first memory module includes a data buffer on the output.
[Item 26]
The timing adjustment includes delaying the output timing when the second memory module includes the LRDIMM and the first memory module does not include a data buffer on the output. Device described in.
[Item 27]
A device coupled to a memory module via a bus,
The device comprises host memory controller logic,
The host memory controller logic is for sending a mode register command to the memory module over a channel to program one of a plurality of mode registers in the memory module;
The device wherein the mode register command indicates one of the plurality of mode registers and includes data for the indicated mode register.
[Item 28]
28. The device of item 27, wherein the mode register command is sent to the memory module during initialization of the memory module before a bus for the memory module is serviced for multiple bus operations.
[Item 29]
The mode register command includes a single cycle command; and
29. The device of item 28, wherein a two-cycle command is used after servicing the memory module to communicate with the memory module via the bus.
[Item 30]
The mode register command uses a plurality of address input signals and a plurality of command input signals to indicate one of the plurality of mode registers and provide data for the indicated mode register. 29. The device according to item 28.
[Item 31]
The mode register command uses the command input signals on the bus to indicate the mode register to use, and
The device of item 30, wherein the mode register command uses the plurality of address input signals on the bus to provide data for the indicated mode register.
[Item 32]
The memory module includes a first memory module, and the mode register command includes a first mode register command, and the host memory controller logic further includes:
Sending a second mode register command to the second memory module via the bus;
The first mode register command and the second mode register command have the same format;
In the second mode register command, the data in the second mode register command in the mode register is transmitted to the second memory module as one of a plurality of memory chips on the second memory module. 32. The device according to any one of items 27 to 31, which is stored in a device.
[Item 33]
From item 27, there are 16 mode registers in the memory module, the mode register including four input bits indicating one of the 16 mode registers for storing the data. 33. The device according to any one of 32.
[Item 34]
A device implemented in a memory module that communicates with a host memory controller via a bus, the device comprising:
Multiple mode registers,
Memory module controller logic, and
The memory module controller logic is:
Receiving a mode register command from the host memory controller via a channel to program one of the plurality of mode registers;
Writing data contained in the mode register command to the indicated mode register in the memory module controller;
The device wherein the mode register command indicates one of the plurality of mode registers and includes data for the indicated mode register.
[Item 35]
35. The device of item 34, wherein the mode register command is received during initialization of the memory module before the bus for the memory module is serviced for multiple bus operations.
[Item 36]
The mode register command includes a single cycle command; and
36. The device of item 35, wherein a two-cycle command is used after servicing the memory module to communicate between the memory module and the host memory controller via the bus.
[Item 37]
To indicate one of the plurality of mode registers and provide the data for the indicated mode register, the mode register command includes a plurality of address input signals and a plurality of commands to the memory module 37. A device according to any one of items 34 to 36, wherein an input signal is used.
[Item 38]
The mode register command uses the command input signals on the bus to indicate the mode register to use, and
38. The device of item 37, wherein the mode register command uses the plurality of address input signals on the bus to provide the data for the indicated mode register.
[Item 39]
A device for transferring data to a memory module via a bus,
The device comprises host memory controller logic,
The host memory controller logic is
Placing the first half command for the memory module on the bus in a first clock cycle;
A chip select command for the memory module corresponding to the first half command is arranged on the bus,
Placing a second half command on the bus in a second clock cycle after the first clock cycle;
The device, wherein the memory module receives the second half command after receiving the first half command at a delay interval.
[Item 40]
40. The device of item 39, wherein the host memory controller does not issue an additional chip select command on the bus to instruct the memory module to access the second half command.
[Item 41]
Item 39 or wherein the second clock cycle is one or two clocks from the first clock cycle and the delay interval is one or two clock cycles since the first half command was received. 40. The device according to 40.
[Item 42]
Item 41, wherein the second clock cycle is one clock from the first clock cycle, and the delay interval is one clock cycle after the chip select command is received in a normal timing mode. Device described in.
[Item 43]
The host memory controller logic further initializes a fast timing mode,
In the fast timing mode,
The first half command and the second half command are respectively arranged on the bus in two clock cycles,
The chip select command is arranged on the bus in one clock cycle from the first clock cycle when the first half command is arranged on the bus,
The second clock cycle is two clocks from the first clock cycle; and
43. A device according to item 42, wherein the delay interval has two clock cycles.
[Item 44]
The host memory controller logic further includes
Programming the memory module during initialization to indicate the fast timing mode; and
44. The device of item 43, wherein the memory module is programmed during initialization to indicate the normal timing mode.
[Item 45]
45. The device according to any one of items 39 to 44, wherein the first half command and the second half command include a plurality of portions related to one address for a read command.
[Item 46]
A device implemented in a memory module that communicates with a host memory controller via a bus,
The device comprises memory module controller logic,
The memory module controller logic is:
Receiving a chip select command for the first half command placed on the bus in the first clock cycle by the host memory controller;
In response to the chip select command, receiving the first half command on the bus; and
Receiving a second half command placed on the bus in a second clock cycle after the first clock cycle by the host memory controller;
The second clock cycle after the first clock cycle is a delay interval from receipt of the first half command.
[Item 47]
47. The device of item 46, wherein the memory module automatically receives the second half command on the bus without automatically receiving an additional chip select signal from the host memory controller.
[Item 48]
The second clock cycle is 1 or 2 clocks from the first clock cycle, and the delay interval is 1 or 2 clock cycles since the chip select command was received, Item 46 or 48. The device according to 47.
[Item 49]
Item 48, wherein the second clock cycle is one clock from the first clock cycle, and the delay interval is one clock cycle after the chip select command is received in a normal timing mode. Device described in.
[Item 50]
The memory module controller logic further initializes a fast timing mode,
In the fast timing mode,
The first half command and the second half command are respectively arranged on the bus in two clock cycles,
The chip select command is arranged on the bus in one clock cycle from the first clock cycle when the first half command is arranged on the bus,
The second clock cycle is two clocks from the first clock cycle, and
50. The device of item 49, wherein the delay interval used by the memory module to determine when to receive the second half command has two clock cycles from receipt of the first half command.
[Item 51]
The memory module controller logic further includes
Determining whether the timing mode is the fast timing mode, and in response to determining that the timing mode is the fast timing mode, the fast timing mode is initialized;
51. The device of item 50, wherein the device operates in the normal timing mode in response to determining that the timing mode is not the fast timing mode.
[Item 52]
52. The device according to any one of items 46 to 51, wherein the first half command and the second half command include a plurality of portions related to one address for a read command.
[Item 53]
A device in a memory module for processing a plurality of addresses in a plurality of commands transmitted from a host memory controller via a bus,
The device comprises a memory module controller;
The memory module controller
Determining whether a plurality of high address bits for the memory module are available;
At least one address having a plurality of addresses communicated from the host memory controller in response to determining that the plurality of high address bits are not available to specify a first address space in the memory module Use a predetermined value for the two high address bits, and
On at least one pin used for the at least one high address bit in response to determining that the plurality of high address bits are available to specify a second address space , For using a plurality of values communicated from the host memory controller,
The device, wherein the second address space is larger than the first address space.
[Item 54]
The memory module controller further includes
Receiving a command from the host memory controller indicating that the plurality of high address bits are available; and
Set a register to indicate that the plurality of high address bits are available;
54. The device of item 53, wherein the determination of whether the plurality of high address bits are available is made by reading a value in the register.
[Item 55]
55. The device of item 54, wherein the plurality of high address bits are not available based on at least one of the plurality of functions of the bus and an interface configuration of the memory module.
[Item 56]
56. The device of item 55, wherein the plurality of high address bits are not available when the memory module has pins that are used for addressing less than that supported on the bus.
[Item 57]
57. The device according to item 56, wherein the plurality of high address bits are not available when the memory module includes a Small Outline Dual In-line Memory Module (SODIMM).
[Item 58]
The command includes a mode register set command (MRS command); and
55. A device according to item 54, wherein the register to be set includes one of a plurality of mode registers set by the MRS command.
[Item 59]
59. A device according to any of items 53 to 58, wherein the memory module controller supports different addressing functions for different supported interface configurations on the bus and on the memory module. .
[Item 60]
A device coupled to a memory module via a bus,
The device comprises host memory controller logic,
The host memory controller logic is
A pre-clock enable (CKE) command indicating at least one power management operation to be performed is sent to the memory module via the bus; and
Assert the CKE low signal to the memory module after sending the pre-clock enable (CKE) command to cause the memory module controller to perform the indicated at least one power management operation in response to the CKE low signal. To the device.
[Item 61]
The pre-clock enable (CKE) command indicates one power management state among a plurality of power management states,
61. The device of item 60, wherein the at least one power management operation shown comprises a plurality of operations that are performed to configure the memory module to the one power management state shown.
[Item 62]
Each of the plurality of power management states includes a plurality of different sleep states, wherein the plurality of different sleep states apply a plurality of different levels of power to a plurality of different components within the memory module;
Item 62. The sending of the CKE low signal causes the memory module controller to perform a plurality of operations to enter a power management sleep state specified in the preclock enable (CKE) command. device.
[Item 63]
A device implemented in a memory module controller coupled to a host memory controller via a bus,
The device comprises memory module controller logic,
The memory module controller logic is:
Receiving a pre-clock enable (CKE) command indicating at least one power management operation to be performed;
Detecting a CKE low signal after receiving the pre-clock enable (CKE) command; and
A device for performing the at least one power management operation indicated in the pre-clock enable (CKE) command in response to the CKE low signal.
[Item 64]
The memory module controller logic further includes
Set a register to indicate the at least one power management operation;
64. The device of item 63, wherein the device determines the at least one power management operation to be performed by reading the register in response to the CKE low signal.
[Item 65]
The memory module controller logic further includes
65. The device of item 64, wherein the device performs a predetermined CKE low processing operation in response to the register not indicating at least one power management operation to be performed.
[Item 66]
The pre-clock enable (CKE) command indicates one power management state among a plurality of power management states,
66. The item of any one of items 63 through 65, wherein the at least one power management operation performed includes a plurality of operations performed to configure the memory module to the one power management state shown. device.
[Item 67]
Each of the plurality of power management states includes a plurality of different sleep states, wherein a plurality of different levels of power are applied to a plurality of different components in the memory module,
67. The device of any one of items 63 to 66, wherein performing the indicated at least one power management operation enters a power management sleep state specified in the pre-clock enable (CKE) command.
[Item 68]
A device coupled to a memory module via a bus,
The device comprises a host memory controller,
The host memory controller is
Determining whether a read data packet returned from the memory module indicates at least one write credit; and
A device that increments a plurality of write credits in response to determining that the read data packet represents at least one write credit.
[Item 69]
The host memory controller further includes
In response to determining that there are a plurality of available write credits, sending a write command to the memory module; and
69. The device of item 68, wherein the device decrements the plurality of write credits in response to sending the write command.
[Item 70]
70. A device according to item 68 or 69, wherein the read data packet is returned in response to a read request sent by the host memory controller to the memory module to read data in the memory module.
[Item 71]
71. A device according to any one of items 68 to 70, wherein a plurality of read data packets indicate a plurality of write credits.
[Item 72]
A device in a memory module for processing a plurality of write requests from a host memory controller via a bus, the device comprising:
A light credit counter,
Memory module controller logic, and
The memory module controller logic increments the write credit counter in response to the completion of the write request from the host memory controller,
In response to a read request from the host memory controller, a read data packet is generated,
A device for indicating a plurality of write credits indicated in the write credit counter in the read data packet for return to the host memory controller.
[Item 73]
The memory module controller logic further includes
75. The device of item 72, wherein the write request is completed by destaging write data in a write buffer for the write request to a plurality of memory storage elements.
[Item 74]
74. A device according to item 72 or 73, wherein a plurality of write credits are indicated in the read data packet.
[Item 75]
The memory module controller logic further includes
Determining whether the light credit counter exceeds a threshold; and
75. In any one of items 72 through 74, in response to a determination that the write credit counter exceeds the threshold, a packet is returned to the host memory controller that returns at least one write credit in the write credit counter. The device described.
[Item 76]
76. The device of item 75, wherein the packet indicating the number of write credits transmitted to the host when the write credit counter exceeds the threshold includes a read data packet having no read data.
[Item 77]
A device in a memory module that communicates with a host memory controller via a bus, the device comprising a memory module controller;
The memory module controller
In response to detecting the error, assert a first error signal to the error pin on the bus to signal to the host memory controller that a plurality of error handling operations are being performed;
In response to detecting an error, performing a plurality of error handling operations to return the bus to an initial state; and
A device that asserts a second error signal to the error pin on the bus to signal that a plurality of error handling operations have been completed and the bus has been returned to the initial state.
[Item 78]
78. The device according to item 77, wherein the first error signal includes an error signal low and the second error signal includes an error signal high.
[Item 79]
The plurality of error handling operations are:
Discard all pending read requests,
Destages a plurality of writes in a write buffer to a plurality of storage elements in the memory module; and
79. A device according to item 77 or 78, wherein the device resets a plurality of memory module controller buffers.
[Item 80]
80. A device according to any one of items 77 to 79, wherein the plurality of error handling operations includes resetting a write credit counter for a plurality of write credits to return.
[Item 81]
81. The item according to any one of items 77 to 80, wherein the plurality of error processing operations are executed in response to receiving a reception confirmation from the host memory controller that the first error signal has been received. device.
[Item 82]
A device coupled to a memory module via a bus,
The device comprises host memory controller logic,
The host memory controller logic is
Detecting a first error signal from the memory module on an error pin;
In response to the first error signal, interrupting a plurality of read and write operations on the memory module;
Detecting a second error signal from the memory module on the error pin; and
A device for resuming a plurality of read and write operations to the memory module in response to detection of the second error signal.
[Item 83]
83. A device according to item 82, wherein the first error signal includes an error signal low and the second error signal includes an error signal high.
[Item 84]
The host memory controller logic further includes
Sending an acknowledgment to the memory module that the first error signal has been received;
84. A device according to item 82 or 83, wherein in response to sending the acknowledgment, the plurality of read and write operations are interrupted and a plurality of error handling operations are performed.
[Item 85]
The host memory controller logic further includes
85. The device according to any one of items 82 to 84, wherein a plurality of write credits indicating when a plurality of write commands can be transmitted are set to a maximum amount in response to the first error signal.
[Item 86]
A device in a memory module that communicates with a host memory controller via a bus,
The device comprises memory module controller logic,
The memory module controller logic is:
Detecting a write error for a write request in the memory module; and
A device that asserts an error signal on the bus to the host memory controller in response to detecting the write error.
[Item 87]
90. The device of item 86, wherein the error signal is the only communication with the host memory controller regarding the detected write error.
[Item 88]
88. A device according to item 86 or 87, wherein the error signal comprises an error low signal asserted on an error pin on the bus.
[Item 89]
89. A device according to any one of items 86 to 88, wherein failure to transmit the error signal within a predetermined time of the write request indicates that the write request has been successfully completed.
[Item 90]
A device coupled to a memory module via a bus,
The device comprises host memory controller logic,
The host memory controller logic is
Send a write request to the memory module;
Detecting an error signal asserted from the memory module; and
A device that resends the write request in response to detecting the error signal within a predetermined time of transmission of the write request.
[Item 91]
94. The device of item 90, wherein the error signal comprises an error low signal asserted on an error pin on the bus.
[Item 92]
The host memory controller logic further includes
92. A device according to item 90 or 91, wherein the write request is processed as being normally completed in response to not receiving the error signal after the predetermined time.
[Item 93]
Item 90, when the error signal is transmitted in response to an error unrelated to a write request error and the error signal is received within the predetermined time, the write request is retransmitted. 99. The device according to any one of 1 to 92.
[Item 94]
Retransmitting the write request includes determining a plurality of write requests transmitted within the predetermined time of the error signal;
94. The device according to any one of items 90 to 93, wherein the retransmission includes retransmitting the determined plurality of write requests.
[Item 95]
The host memory controller logic further includes
95. A device according to any one of items 90 to 94, which performs an error handling operation determined for the error signal and unrelated to a plurality of write request errors.
[Item 96]
96. The device of item 95, wherein in addition to retransmitting the write request, the error handling operation unrelated to multiple write errors is performed.
[Item 97]
A device in a memory module that communicates with a host memory controller via a bus, the device comprising:
With scrambled,
Memory module controller logic, and
The memory module controller logic is:
In response to a read request, obtain data stored in the storage element of the memory module;
Using the scrambled to scramble the acquired data for inclusion in a read data packet;
Returning the read data packet with the scrambled data to the host memory controller; and
A device for updating the scrambled.
[Item 98]
98. The device of item 97, wherein the scrambled scrambles an address of the read data included in the read data packet.
[Item 99]
99. The device of item 97 or 98, wherein updating the scrambled includes updating the scrambled to a pseudo-random manner.
[Item 100]
The memory module controller logic uses a scrambler algorithm to scramble the read data;
97. The scrambler algorithm comprises the same scrambler / descrambler algorithm implemented in the host memory controller for scrambling / descrambling the scrambled read data in the read data packet. 100. The device according to any one of 1 to 99.
[Item 101]
The memory module controller logic is:
Receiving a write request having scrambled write data indicating a write address in the memory module;
Descrambling the scrambled write data using the write address to generate unscrambled write data; and
101. The device according to any one of items 97 to 100, wherein the unscrambled write data is stored at the write address in the memory module.
[Item 102]
A device that communicates with a memory module via a bus,
The device is
With scrambled,
Host memory controller logic, and
The host memory controller logic is
In response to the read request, receive a read data packet having scrambled read data returned;
In response to receiving the read data packet, updating the scrambled, and
A device for using the scrambled blade to descramble the scrambled read data.
[Item 103]
The address of the read data is scrambled in the read data packet;
103. The device of item 102, wherein descrambling the scrambled read data further comprises descrambling the scrambled address to determine the read request for the read data packet to be returned. .
[Item 104]
104. The device of item 103, wherein updating the scrambled includes updating the scrambled in a pseudo-random manner.
[Item 105]
The host memory controller logic uses a scrambler algorithm to scramble the read data,
Items 102-104, wherein the scrambler algorithm includes the same scrambler / descrambler algorithm implemented in the host memory controller for scrambling / descrambling the scrambled read data in the read data packet. The device according to any one of the above.
[Item 106]
A device in a memory module that communicates with a host memory controller via a bus,
The device comprises memory module controller logic,
The memory module controller logic is:
In response to an interface parameter indicating a first interface parameter, selecting a first bus interface configuration having a first bus width used to transmit data over the bus; and
Responsive to the interface parameter indicating a second interface parameter, for selecting a second bus interface configuration having a second bus width used to transmit data over the bus;
The device, wherein the first bus width has a plurality of bits that are even smaller than the second bus width.
[Item 107]
The memory module controller logic further includes
Responsive to the interface parameter indicating the first interface parameter to generate a first transfer number for the first bus interface configuration to execute a transfer request;
Responsive to the interface parameter indicating the second interface parameter to generate a second transfer number for the first bus interface configuration to execute the transfer request;
107. A device according to item 106, wherein the first transfer number is greater than the second transfer number.
[Item 108]
The memory module controller logic further includes
In response to an interface parameter indicating a third interface parameter, selecting a third bus interface configuration having a third bus width used to transmit data over the bus;
108. A device according to item 106 or 107, wherein the second bus width has a plurality of bits that are even smaller than the third bus width.
[Item 109]
109. The device of item 108, wherein the first bus width comprises 9 bits, the second bus width comprises 18 bits, and the third bus width comprises 72 bits.
[Item 110]
The memory module controller logic further includes
110. A device according to any of items 106 to 109, wherein the device sets the interface parameter based on at least one received signal on the bus.
[Item 111]
The memory module controller logic further includes
Determining the bus width of the bus by accessing the bus;
111. A device according to any one of items 106 to 110, wherein the interface parameter indicates the determined bus width.
[Item 112]
The memory module controller logic further includes
Setting the interface parameter based on a signal asserted on at least one strapping pin;
The at least one strapping pin is external to the bus and is coupled to the memory module and indicates at least one of the first bus interface configuration and the second bus interface configuration of the bus. 111. A device according to any one of 106 to 111.

Claims (14)

A device used in a memory module coupled to a host memory controller via a bus, the device comprising:
A memory module controller logic for generating a request signal having a pulse width greater than or equal to a minimum pulse width for a host memory controller;
The minimum pulse width comprises a plurality of clock cycles necessary to ensure that the host memory controller detects the request signal;
The device wherein the pulse width of the request signal indicates at least one function in addition to the request signal to the host memory controller. The request signal causes the host memory controller to generate a grant signal,
The device of claim 1, wherein the memory module controller logic further transmits data to the host memory controller in response to receiving the grant signal.   The pulse width causes the host memory controller to execute the at least one function indicated by the pulse width in addition to transmitting the grant signal in response to the request signal. Devices.   4. The device according to claim 1, wherein a pulse width equal to the minimum pulse width indicates only the request signal and does not indicate an additional function. 5. Generating the request signal having at least a first pulse width greater than the minimum pulse width indicates at least a first function;
Generating the request signal having at least a second pulse width greater than the first pulse width indicates at least a second function;
5. The device according to claim 1, wherein generating the request signal having at least a third pulse width greater than the second pulse width indicates at least a third function. 6. When the request signal having the first pulse width is generated, the first function is indicated;
When the request signal having the second pulse width is generated, the second function is indicated,
The device of claim 5, wherein the third function is indicated when the request signal having the third pulse width is generated. The generated pulse width comprises one of a plurality of pulse widths equal to the minimum pulse width or a plurality of the minimum pulse widths;
The plurality of pulse widths are divided by a minimum number of clock cycles required to ensure detection of the pulse width by the host memory controller;
7. A device according to any one of the preceding claims, wherein a plurality of different generated pulse widths encode a plurality of different functions in the request signal. The minimum pulse width comprises two clocks;
8. Generating the request signal with one of a pulse width of 6, 10, and 14 clocks indicates a different function that the host memory controller performs in addition to processing the request signal. Device described in.   The device according to claim 1, wherein the request signal includes a clock enable signal. A device coupled to at least one memory module via a bus, the device comprising host memory controller logic;
The host memory controller logic is
Detecting a request signal from the memory module having a pulse width greater than or equal to a minimum pulse width;
Determine the function corresponding to the pulse width of the request signal,
For executing the determined function,
The minimum pulse width has a plurality of clock cycles necessary to ensure that the host memory controller detects the request signal;
A device wherein the pulse width of the request signal indicates at least one function in addition to the request signal to the host memory controller. The host memory controller logic further comprises:
The device of claim 10, wherein the device generates a grant signal to be transmitted to the memory module via the bus in response to receiving the request signal. The host memory controller logic further comprises:
Determining that the pulse width is equal to the minimum pulse width;
12. A device according to claim 10 or 11, wherein the determined function comprises the request signal without an additional function in response to the pulse width of the request signal equal to the minimum pulse width. The host memory controller logic further comprises:
Determining the pulse width;
The determined function is
The first function,
Including at least one of a second function and a third function;
The first function is responsive to the determined pulse width including at least a first pulse width greater than or equal to the minimum pulse width;
The second function is responsive to the determined pulse width including at least a second pulse width greater than the first pulse width;
13. A device according to any one of claims 10 to 12, wherein the third function is responsive to the determined pulse width including at least a third pulse width greater than the second pulse width. When the request signal having the first pulse width is generated, only the first function is shown,
When the request signal having the second pulse width is generated, the second function is indicated,
14. The device of claim 13, wherein the third function is indicated when the request signal having the third pulse width is generated.

Images