JP2017152579A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can suppress operation of a parasitic transistor.SOLUTION: A semiconductor device according to one embodiment comprises a first conductivity type first semiconductor region, a second conductivity type second semiconductor region, a first conductivity type third semiconductor region, a second conductivity type fourth semiconductor region, a gate electrode and, a gate insulation layer. The second semiconductor region is provided on the first semiconductor region. The second semiconductor region has a first portion and a second portion. A lower end of the second portion is located below a lower end of the first portion. The third semiconductor region is provided on the first portion. The fourth semiconductor region is provided on the second portion. A second conductivity type carrier concentration of the fourth semiconductor region is higher than that of the second semiconductor region. The gate insulation layer is provided between the second semiconductor region and the gate electrode.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a semiconductor device.

  Semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) have parasitic transistors inside. Since the semiconductor device may be destroyed when the parasitic transistor operates, it is desirable that the parasitic transistor is difficult to operate.

JP2015-56482A

  The problem to be solved by the present invention is to provide a semiconductor device capable of suppressing the operation of a parasitic transistor.

The semiconductor device according to the embodiment includes a first conductivity type first semiconductor region, a second conductivity type second semiconductor region, a first conductivity type third semiconductor region, and a second conductivity type fourth semiconductor region. And a gate electrode and a gate insulating layer.
The second semiconductor region is provided on the first semiconductor region. The second semiconductor region has a first portion and a second portion. The lower end of the second part is located below the lower end of the first part.
The third semiconductor region is provided on the first portion.
The fourth semiconductor region is provided on the second portion. The carrier concentration of the second conductivity type of the fourth semiconductor region is higher than that of the second semiconductor region.
The gate insulating layer is provided between the second semiconductor region and the gate electrode.

It is a perspective sectional view showing a part of semiconductor device concerning an embodiment. It is a process perspective sectional view showing a manufacturing process of a semiconductor device concerning an embodiment. It is a process perspective sectional view showing a manufacturing process of a semiconductor device concerning an embodiment. It is a perspective sectional view showing a part of semiconductor device concerning the 1st modification of an embodiment. It is a top view showing a part of semiconductor device concerning the 2nd modification of an embodiment. (A) It is a perspective sectional view containing the A-A 'cross section of FIG. FIG. 6B is a perspective sectional view including a B-B ′ section in FIG. 5. It is a perspective sectional view showing a part of semiconductor device concerning the 3rd modification of an embodiment. It is a top view showing a part of semiconductor device concerning the 4th modification of an embodiment. FIG. 9 is a perspective sectional view including an A-A ′ section of FIG. 8. It is a perspective sectional view showing a part of semiconductor device concerning the 5th modification of an embodiment. It is a perspective sectional view showing a part of semiconductor device concerning the 6th modification of an embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
In the present specification and each drawing, the same elements as those already described are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.
In the description of each embodiment, an XYZ orthogonal coordinate system is used. A direction from the n ⁻ -type semiconductor region 1 to the p-type base region 2 is defined as a Z direction (first direction), and two directions perpendicular to the Z direction and orthogonal to each other are defined as an X direction and a Y direction (second direction). ).
In the following description, the notation of n ⁺ , n, n ⁻ and p ⁺ , p, p ⁻ represents the relative level of the impurity concentration in each conductivity type. That is, the notation with “+” has a relatively higher impurity concentration than the notation without both “+” and “−”, and the notation with “−” It shows that the impurity concentration is relatively lower than the notation.
About each embodiment described below, each embodiment may be implemented by inverting the p-type and n-type of each semiconductor region.

FIG. 1 is a perspective sectional view showing a part of the semiconductor device 100 according to the embodiment.
The semiconductor device 100 is a MOSFET.
As shown in FIG. 1, the semiconductor device 100 includes an n ^{+ -type} (first conductivity type) drain region 7, an n ⁻ -type semiconductor region 1 (first semiconductor region), a p-type (second conductivity type) base region 2 ( (Second semiconductor region), n ^{+ -type} source region 3 (third semiconductor region), p ^{+ -type} contact region 4 (fourth semiconductor region), gate electrode 10, gate insulating layer 11, drain electrode 31, and source electrode 32. Have.

The drain electrode 31 is provided on the lower surface of the semiconductor device 100.
The n ⁺ -type drain region 7 is provided on the drain electrode 31 and is electrically connected to the drain electrode 31.
The n ^{− type} semiconductor region 1 is provided on the n ^{+ type} drain region 7.
The p-type base region 2 is provided on the n ⁻ -type semiconductor region 1. A plurality of p-type base regions 2 are provided in the X direction, and each extend in the Y direction.

The p-type base region 2 has a first portion 2a and a second portion 2b.
The lower end of the second part 2b is located below the lower end of the first part 2a. In other words, the distance in the Z direction between the lower end of the second portion 2 b and the source electrode 32 is longer than the distance in the Z direction between the lower end of the first portion 2 a and the source electrode 32. Further, the pn junction surface between the n ⁻ -type semiconductor region 1 and the second portion 2 b is located below the pn junction surface between the n ⁻ -type semiconductor region 1 and the first portion 2 a.

  The p-type impurity concentration in the second portion 2b is, for example, equal to the p-type impurity concentration in the first portion 2a. Alternatively, the p-type impurity concentration in the second portion 2b may be higher than the p-type impurity concentration in the first portion 2a.

The n ^{+ -type} source region 3 is provided on the first portion 2a.
The p ^{+ -type} contact region 4 is provided on the second portion 2b.
In the example shown in FIG. 1, the first portions 2a and the second portions 2b are alternately provided in the Y direction. For this reason, the n ^{+ -type} source regions 3 and the p ^{+ -type} contact regions 4 are also provided alternately in the Y direction.

  The gate electrode 10 is aligned with the p-type base region 2 in the X direction. A gate insulating layer 11 is provided between the gate electrode 10 and the p-type base region 2. A plurality of gate electrodes 10 are provided in the X direction, and each extends in the Y direction.

The source electrode 32 is provided on the upper surface of the semiconductor device 100 and is located on the gate electrode 10, the n ^{+ -type} source region 3, and the p ^{+ -type} contact region 4. Source electrode 32 is electrically connected to n ^{+ -type} source region 3 and p ^{+ -type} contact region 4. In addition, the gate insulating layer 11 is provided between the source electrode 32 and the gate electrode 10, and these electrodes are electrically separated.

Here, the operation of the semiconductor device 100 will be described.
When a positive voltage or higher is applied to the drain electrode 31 with respect to the source electrode 32, a voltage higher than the threshold value is applied to the gate electrode 10, and the semiconductor device is turned on. At this time, a channel (inversion layer) is formed in a region near the gate insulating layer 11 in the p-type base region 2.
After that, when the voltage applied to the gate electrode 10 becomes less than the threshold value, the channel disappears, and the semiconductor device is switched from the on state to the off state. At this time, a surge voltage is generated in the drain electrode 31 with respect to the source electrode 32 due to an inductance component in the electric circuit to which the semiconductor device 100 is connected. When a large voltage is temporarily applied to the drain electrode 31, impact ionization occurs in a portion where the electric field strength is high, such as near the lower end of the gate insulating layer 11. Electrons generated by impact ionization are discharged from the drain electrode 31 through the n ^{− -type} semiconductor region 1 and the n ⁺ -type drain region 7, and holes are discharged from the source electrode 32 through the p ^{+ -type} contact region 4. The

Next, an example of the material of each component will be described.
The n ⁺ -type drain region 7, the n ⁻ -type semiconductor region 1, the p-type base region 2, the n ^{+ -type} source region 3, and the p ^{+ -type} contact region 4 are made of silicon, silicon carbide, gallium nitride, or gallium as a semiconductor material. Contains arsenic. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity.
The gate electrode 10 includes a conductive material such as polysilicon.
The gate insulating layer 11 includes an insulating material such as silicon oxide.
The drain electrode 31 and the source electrode 32 include a metal such as aluminum or nickel.

Next, an example of a method for manufacturing the semiconductor device 100 according to the embodiment will be described.
2 and 3 are process perspective sectional views showing the manufacturing process of the semiconductor device 100 according to the embodiment.

First, a semiconductor substrate having an n ^{+ -type} semiconductor layer 7a and an n ⁻ -type semiconductor layer 1a is prepared. Next, p-type impurities are ion-implanted into the surface of the n ⁻ -type semiconductor layer 1 a to form the p-type base region 2. At this time, the p-type base region 2 is formed so that a part of the lower end of the p-type base region 2 is positioned below the other part of the lower end. Thereby, as shown in FIG. 2A, the p-type base region 2 having the first portion 2a and the second portion 2b is formed.

Such a p-type base region 2 is formed, for example, by ion-implanting a p-type impurity into a part of the surface of the n ⁻ -type semiconductor layer 1a deeper than the other part.
Alternatively, the p-type base region 2 may be formed by ion-implanting a larger amount of p-type impurity than the other part into a part of the surface of the n ⁻ -type semiconductor layer 1a. This is because the p-type impurity diffuses further downward in the region where a large amount of the p-type impurity is ion-implanted. When the p-type base region 2 is formed by this method, the p-type impurity concentration in the second portion 2b is higher than the p-type impurity concentration in the first portion 2a.

Next, a plurality of trenches that penetrate the p-type base region 2 and reach the n ⁻ -type semiconductor layer 1a are formed. Subsequently, an insulating layer IL1 is formed on the inner wall of the trench and the upper surface of the p-type base region 2 by performing thermal oxidation. Subsequently, a conductive layer is formed over the insulating layer IL1. By etching back this conductive layer, the gate electrode 10 is formed inside each trench, as shown in FIG.

Next, n-type impurities are ion-implanted into the surface of the first portion 2a, and p-type impurities are ion-implanted into the surface of the second portion 2b. As a result, as shown in FIG. 3A, the n ^{+ -type} source region 3 is formed on the first portion 2a, and the p ^{+ -type} contact region 4 is formed on the second portion 2b.

Next, an insulating layer IL2 that covers the gate electrode 10 is formed over the insulating layer IL1. Subsequently, the n ^{+ -type} source region 3 and the p ^{+ -type} contact region 4 are exposed by patterning the insulating layers IL1 and IL2. Subsequently, a metal layer is formed to cover the patterned insulating layers IL1 and IL2. By patterning this metal layer, the source electrode 32 is formed as shown in FIG.

Next, the back surface of the n ^{+ -type} semiconductor layer 7a is ground until the n ^{+ -type} semiconductor layer 7a has a predetermined thickness. Thereafter, the drain electrode 31 is formed on the back surface of the n ^{+ -type} semiconductor layer 7a, whereby the semiconductor device 100 shown in FIG. 1 is obtained.

Here, the operation and effect of this embodiment will be described.
In the semiconductor device according to the present embodiment, the p-type base region 2 includes a first portion 2a and a second portion 2b. The lower end of the second portion 2 b positioned below the p ^{+ -type} contact region 4 is positioned below the lower end of the first portion 2 a positioned below the n ^{+ -type} source region 3.
When the semiconductor device has such a structure, holes generated by impact ionization near the lower end of the gate insulating layer 11 are second than the lower end of the first portion 2a when flowing toward the p-type base region 2. It is drawn toward the lower end of the portion 2b. As the holes are attracted to the second portion 2b, the amount of holes flowing through the second portion 2b to the p ^{+ -type} contact region 4 is increased, and through the first portion 2a to the p ^{+ -type} contact region 4 The amount of flowing holes can be reduced. By reducing the amount of holes flowing through the first portion 2a located under the n ^{+ -type} source region 3, an increase in voltage in the first portion 2a can be suppressed.
Therefore, according to this embodiment, n ^- suppressing the operation of the formed parasitic npn transistor from type semiconductor region 1, p-type base region 2 (first portion 2a), and the n ⁺ -type source region 3, the semiconductor It becomes possible to improve the destruction tolerance of the apparatus.

At this time, by making the p-type impurity concentration in the second portion 2b higher than the p-type impurity concentration in the first portion 2a, the resistance to holes in the second portion 2b is made smaller than that in the first portion 2a. Can do. For this reason, it is possible to further reduce the amount of holes flowing through the first portion 2a to the p ^{+ -type} contact region 4 and further improve the breakdown tolerance of the semiconductor device.

(First modification)
FIG. 4 is a perspective cross-sectional view showing a part of the semiconductor device 110 according to the first modification of the embodiment.
In the semiconductor device 110, the first portion 2a and the second portion 2b are arranged in the X direction between the gate electrodes 10, and each extends in the Y direction. Similarly, the n ^{+ -type} source region 3 on the first portion 2a and the p ^{+ -type} contact region 4 on the second portion 2b also extend in the Y direction.

Also in this modification, the lower end of the 2nd part 2b is located below rather than the lower end of the 1st part 2a. An n ^{+ -type} source region 3 is provided on the first portion 2a, and a p ^{+ -type} contact region 4 is provided on the second portion 2b. Therefore, similarly to the semiconductor device 100, it is possible to suppress the operation of the parasitic transistor and improve the breakdown tolerance of the semiconductor device.

(Second modification)
FIG. 5A and FIG. 5B are plan views showing a part of the semiconductor device 120 according to the second modification of the embodiment.
6A is a perspective sectional view including the AA ′ section of FIG. 5, and FIG. 6B is a perspective sectional view including the BB ′ section of FIG. 5.
In FIG. 5A and FIG. 5B, the gate insulating layer 11 and the source electrode 32 are omitted. In FIG. 5B, only the outer edge of the gate electrode 10 is represented by a broken line, and the gate electrode 10 is transmitted therethrough.

The semiconductor devices 100 and 110 described with reference to FIGS. 1 to 4 have a trench type gate structure in which a gate electrode 10 and a gate insulating layer 11 are provided in a semiconductor region.
In contrast, the semiconductor device 120 shown in FIGS. 5 and 6 has a planar gate structure in which the gate electrode 10 is provided on the semiconductor region via the gate insulating layer 11.

As shown in FIG. 6, the p-type base region 2 is selectively provided on the n ⁻ -type semiconductor region 1. A plurality of p-type base regions 2 are provided in the X direction, and each extend in the Y direction.
The n ^{+ -type} source region 3 and the p ^{+ -type} contact region 4 are selectively provided on the p-type base region 2.

As shown in FIG. 5, the p ^{+ -type} contact region 4 extends in the Y direction.
A plurality of n ^{+ -type} source regions 3 are provided apart from each other in the X direction.
The gate electrode 10 is provided on the n ^{− -type} semiconductor region 1, the p-type base region 2, and the n ^{+ -type} source region 3 via the gate insulating layer 11 and extends in the Y direction.

As shown in FIGS. 6A and 6B, in the semiconductor device 120, the first portions 2a and the second portions 2b are alternately provided in the X direction.
The p ^{+ -type} contact region 4 is provided on both the first portion 2a and the second portion 2b, whereas the n ^{+ -type} source region 3 is provided only on the first portion 2a. Yes.

When the semiconductor device has a planar gate structure, impact ionization occurs mainly at the lower end of the p-type base region 2 when a surge voltage is applied to the drain electrode 31. At this time, by placing the lower end of the second portion 2b below the lower end of the first portion 2a, impact ionization is more likely to occur at the lower end of the second portion 2b than at the lower end of the first portion 2a.
Holes generated at the lower end of the second portion 2 b move upward as they are and are discharged to the source electrode 31 through the p ^{+ -type} contact region 4. That is, impact ionization is likely to occur at the lower end of the second portion 2b, so that the amount of holes flowing through the first portion 2a to the p ^{+ -type} contact region 4 can be reduced.
For this reason, also by this modification, like the semiconductor devices 100 and 110, it is possible to suppress the operation of the parasitic transistor and improve the breakdown tolerance of the semiconductor device.

(Third Modification)
FIG. 7 is a perspective cross-sectional view illustrating a part of a semiconductor device 130 according to a third modification of the embodiment.
The semiconductor device 130 is different from the semiconductor device 120 in that it further has a p ⁻ -type pillar region 8.

As represented in FIG. 7, p ^- form pillar region 8, n ^- provided in type semiconductor region 1, along an X-Y plane the n ^- surrounded by type semiconductor region 1. The p-type base region 2 is provided on the p ⁻ -type pillar region 8.
Further, a part of the n ⁻ -type semiconductor region 1 and the p ⁻ -type pillar region 8 are alternately provided in the X direction, and constitute a super junction structure (hereinafter referred to as an SJ structure).

By providing the p ⁻ -type pillar region 8 to form the SJ structure, the breakdown voltage of the semiconductor device can be increased. That is, according to this modification, it is possible to further increase the breakdown voltage of the semiconductor device as compared with the second modification.

In FIG. 7, the p ⁻ -type pillar region 8 is aligned with only the upper portion of the n ⁻ -type semiconductor region 1 in the X direction. However, the p ⁻ -type pillar region 8 further includes the lower portion of the n ⁻ -type semiconductor region 1. They may be arranged in the X direction. That, p ^- form pillar region 8, n ^- extends type semiconductor region 1 medium in the -Z direction, it may be in contact with the n ⁺ -type drain region 7.

(Fourth modification)
FIG. 8A and FIG. 8B are plan views showing a part of a semiconductor device 140 according to a fourth modification of the embodiment.
FIG. 9 is a perspective sectional view including the AA ′ section of FIG. 8.
In FIG. 8, the gate insulating layer 11 and the source electrode 32 are omitted. In FIG. 8B, only the outer edge of the gate electrode 10 is represented by a broken line, and the gate electrode 10 is transmitted therethrough.

As shown in FIGS. 8B and 9, in the semiconductor device 140, a plurality of p-type base regions 2 are provided in the X direction and the Y direction on the n ⁻ -type semiconductor region 1.
The n ^{+ -type} source region 3 is provided in a ring shape on the p-type base region 2, and the p ^{+ -type} contact region 4 is provided inside the n ^{+ -type} source region 3.
The gate electrode 10 extends along the X direction and the Y direction. Further, as shown in FIG. 8A, a plurality of openings OP formed corresponding to the n ^{+ -type} source region 3 and the p ^{+ -type} contact region 4 are provided.
The n ^{+ -type} source region 3 and the p ^{+ -type} contact region 4 are electrically connected to the source electrode 32 through the opening OP.

In the semiconductor device 140, the first portion 2 a is provided in a ring shape like the n ^{+ -type} source region 3. The second portion 2b is provided inside the first portion 2a and is surrounded by the first portion 2a.

Also in this modification, the n ^{+ -type} source region 3 is provided on the first portion 2a, and the p ^{+ -type} contact region 4 is provided on the second portion 2b. In addition, it is possible to improve the breakdown tolerance of the semiconductor device.
Similar to the semiconductor device 130, it is possible to provide the p ⁻ -type pillar region 8 below the p-type base region 2 with respect to the semiconductor device 140 to configure the SJ structure.

(5th modification)
FIG. 10 is a perspective cross-sectional view illustrating a part of a semiconductor device 150 according to a fifth modification of the embodiment.
The semiconductor device 150 is an IGBT.
In comparison with the semiconductor device 100, the semiconductor device 150 further includes an n-type barrier region 6 (sixth semiconductor region), and a p ^{+ -type} collector region 5 (fifth semiconductor region) instead of the n ⁺ -type drain region 7. And an n-type field stop region (hereinafter referred to as an n-type FS region) 9. In the semiconductor device 150, the electrode 31 functions as a collector electrode, and the electrode 32 functions as an emitter electrode.

The p ^{+ -type} collector region 5 is provided on the collector electrode 31 and is electrically connected to the collector electrode 31.
The n-type FS region 9 is provided on the p ^{+ -type} collector region 5.
The n ^{− type} semiconductor region 1 is provided on the n type FS region 9.
An n-type barrier region 6 is provided on the n ⁻ -type semiconductor region 1 and between the gate electrodes 10.
The p-type base region 2 is provided on the n-type barrier region 6.

The p-type base region 2 has a first portion 2a and a second portion 2b.
The n-type barrier region 6 has a third portion 6c and a fourth portion 6d.
The first portion 2a is provided on the third portion 6c, and the n ^{+ -type} source region 3 is provided on the first portion 2a.
The second portion 2b is provided on the fourth portion 6d, and the p ^{+ -type} contact region 4 is provided on the second portion 2b.

  The lower end of the second portion 2b is located below the lower end of the first portion 2a, and the upper end of the fourth portion 6d is located below the upper end of the third portion 6c. That is, the pn junction surface between the second portion 2b and the fourth portion 6d is located below the pn junction surface between the first portion 2a and the third portion 6c.

  Also in the semiconductor device 150, when switching from the on state to the off state, a surge voltage is generated in the collector electrode 31, and impact ionization occurs in the vicinity of the lower end of the gate insulating layer 11. For this reason, by positioning the lower end of the second portion 2b below the lower end of the first portion 2a, the operation of the parasitic npn transistor is suppressed and the breakdown tolerance of the semiconductor device is improved as in the semiconductor device 100. be able to.

Further, as shown in FIG. 10, by reducing the thickness of the fourth portion 6d to be smaller than the thickness of the third portion 6c, the resistance to holes in the fourth portion 6d is reduced, and the resistance to holes in the third portion 6c is reduced. Can be made smaller. Therefore, the amount of holes flowing through the first portion 2a provided on the third portion 6c can be further reduced.
At this time, by making the n-type impurity concentration in the fourth portion 6d lower than the n-type impurity concentration in the third portion 6c, the resistance in the fourth portion 6d is made smaller than the resistance in the third portion 6c. Is possible.

  Further, by providing the lower end of the fourth portion 6d below the lower end of the third portion 6c, the amount of holes flowing into the third portion 6c is reduced, and the amount of holes flowing toward the fourth portion 6d Can be increased. For this reason, it is possible to further reduce the amount of holes flowing through the first portion 2a.

(Sixth Modification)
FIG. 11 is a perspective cross-sectional view showing a part of a semiconductor device 160 according to a sixth modification of the embodiment.
The semiconductor device 160 is different from the semiconductor device 150 in that the n-type barrier region 6 is not provided under the p ^{+ -type} contact region 4 (under the second portion 2b). That is, the n-type barrier region 6 is provided only under the n ^{+ -type} source region 3 (under the first portion 2a).
Since the n-type barrier region 6 is not provided under the p ^{+ -type} contact region 4, holes easily pass between the n-type barrier regions 6 and flow into the second portion 2b. For this reason, according to this modification, it is possible to further reduce the amount of holes flowing through the first portion 2a and further improve the breakdown tolerance of the semiconductor device as compared with the fifth modification.

In the fifth and sixth modifications, only the case where the semiconductor devices 150 and 160, which are IGBTs, have a trench-type gate structure has been described. However, the present embodiment can also be applied to the case where the IGBT has a planar gate structure as in the second to fourth modifications. That is, in semiconductor devices 120 and 140, p ^{+ -type} collector region 5 and n-type FS region 9 are provided in place of n ⁺ -type drain region 7, and n-type barrier region 6 is provided below base region 2, whereby IGBT Can also be used.

The relative level of the impurity concentration between the semiconductor regions in each of the embodiments described above can be confirmed using, for example, an SCM (scanning capacitance microscope). The carrier concentration in each semiconductor region can be regarded as being equal to the impurity concentration activated in each semiconductor region. Therefore, the relative level of the carrier concentration between the semiconductor regions can also be confirmed using the SCM.
The impurity concentration in each semiconductor region can be measured by, for example, SIMS (secondary ion mass spectrometry).

As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. For example, the n ^{− -type} semiconductor region 1, the p-type base region 2, the n ^{+ -type} source region 3, the p ^{+ -type} contact region 4, the p ^{+ -type} collector region 5, the n-type barrier region 6 and n ^{+ included in the} embodiment. forms the drain region 7, p ^- form pillar region 8, n-type FS region 9, a gate electrode 10, gate insulating layer 11, with respect to the specific configuration of each element, such as electrodes 31, and electrodes 32, those skilled in the art known It is possible to appropriately select from technologies. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof. Further, the above-described embodiments can be implemented in combination with each other.

100-160 ... semiconductor device, 1 ... n ^- type semiconductor region, 2 ... p-type base region, 3 ... ^{n +} -type source region, 4 ... ^{p +} -type contact region, 5 ... ^{p +} form collector region, 6 ... n-type Barrier region, 7... N ^{+ type} drain region, 10... Gate electrode, 31, 32.

Claims (5)

A first semiconductor region of a first conductivity type;
A first part;
A second portion having a lower end positioned below the lower end of the first portion;
A second semiconductor region of the second conductivity type provided on the first semiconductor region;
A third semiconductor region of a first conductivity type provided on the first portion;
A fourth semiconductor region of a second conductivity type provided on the second portion and having a carrier concentration of the second conductivity type higher than that of the second semiconductor region;
A gate electrode;
A gate insulating layer provided between the second semiconductor region and the gate electrode;
A semiconductor device comprising: A fifth semiconductor region of the second conductivity type;
A sixth semiconductor region of the first conductivity type;
Further comprising
The first semiconductor region is provided on the fifth semiconductor region,
The sixth semiconductor region is provided between the first semiconductor region and the second semiconductor region,
The semiconductor device according to claim 1, wherein a carrier concentration of the first conductivity type in the sixth semiconductor region is higher than a carrier concentration of the first conductivity type in the first semiconductor region. The sixth semiconductor region includes
A third portion provided between the first semiconductor region and the first portion;
A fourth portion provided between the first semiconductor region and the second portion;
Have
The semiconductor device according to claim 2, wherein a carrier concentration of the first conductivity type in the third portion is higher than a carrier concentration of the first conductivity type in the fourth portion. The sixth semiconductor region includes
A third portion provided between the first semiconductor region and the first portion;
A fourth portion provided between the first semiconductor region and the second portion;
Have
3. The semiconductor device according to claim 2, wherein a thickness of the third portion in a first direction from the first semiconductor region toward the second semiconductor region is larger than a thickness of the fourth portion in the first direction.   The semiconductor device according to claim 1, wherein a carrier concentration of the second conductivity type in the second portion is higher than a carrier concentration of the second conductivity type in the first portion.

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