JP2017147751A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2017147751A
JP2017147751A JP2017084424A JP2017084424A JP2017147751A JP 2017147751 A JP2017147751 A JP 2017147751A JP 2017084424 A JP2017084424 A JP 2017084424A JP 2017084424 A JP2017084424 A JP 2017084424A JP 2017147751 A JP2017147751 A JP 2017147751A
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voltage value
semiconductor elements
semiconductor device
load
fets
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JP6265293B2 (en
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克馬 塚本
Katsuma Tsukamoto
克馬 塚本
佑典 矢野
Yusuke Yano
佑典 矢野
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Sumitomo Wiring Systems Ltd
AutoNetworks Technologies Ltd
Sumitomo Electric Industries Ltd
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Sumitomo Wiring Systems Ltd
AutoNetworks Technologies Ltd
Sumitomo Electric Industries Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing burning of a semiconductor element without incorporating a fuse.SOLUTION: A semiconductor device comprises a plurality of semiconductor elements 3 and 4 parallel-connected between a DC power supply and a load 2, and is configured to turn on and off the plurality of semiconductor elements 3 and 4 simultaneously. The semiconductor device comprises: voltage detection means 9 that detects a voltage value between a connection node of the plurality of semiconductor elements 3 and 4 and the load 2, and a fixed potential; means 1 that determines whether or not the voltage value detected by the voltage detection means 9 is higher than a predetermined voltage value in a case where the plurality of semiconductor elements 3 and 4 are in an off state; and means 1 that turns on the plurality of semiconductor elements 3 and 4 when the determining means 1 determined that the voltage value is higher the predetermined voltage value.SELECTED DRAWING: Figure 1

Description

本発明は、直流電源及び負荷間に接続される複数の半導体素子を備え、複数の半導体素子を同時的にオン又はオフにするように構成してある半導体装置に関するものである。   The present invention relates to a semiconductor device including a plurality of semiconductor elements connected between a DC power supply and a load, and configured to simultaneously turn on or off the plurality of semiconductor elements.

従来の半導体装置では、半導体リレーとして使用される半導体素子（例えばＭＯＳＦＥＴ（金属酸化膜半導体電界効果トランジスタ））がショート故障した場合は、半導体素子のパッケージ内部に設けられたヒューズ機構で電流を遮断することにより、半導体素子自身の焼損防止、並びに下流側の電線及び負荷の保護を行っている。
また、半導体素子（半導体リレー）は、電流容量を増加させる為に、複数を並列に接続して使用されることが多く、また、ボディダイオード（寄生ダイオード）経由で逆流しないように、逆直列に接続した対で使用されることが多い。 In a conventional semiconductor device, when a semiconductor element used as a semiconductor relay (for example, a MOSFET (metal oxide semiconductor field effect transistor)) is short-circuited, current is cut off by a fuse mechanism provided inside the package of the semiconductor element. In this way, the semiconductor element itself is prevented from being burned out and the downstream wires and loads are protected.
In addition, semiconductor elements (semiconductor relays) are often used by connecting a plurality of them in parallel to increase the current capacity, and in reverse series so as not to reversely flow through the body diode (parasitic diode). Often used in connected pairs.

特許文献１には、回路基板上に半導体装置に隣接して形成され、上面に溝が形成された導体のパターンと、パターンの上面かつ前記溝の一側端周縁部を含む領域に低融点金属部材で形成された電極とからなるヒューズ機構と、一端が前記半導体装置の電極に接続され他端が前記ヒューズ機構の電極に接続されたワイヤとを備えたヒューズ付き半導体装置が開示されている。前記パターンに過電流が流れたときに、前記ヒューズ機構の電極が溶けて前記溝に流れ込み、前記ワイヤの他端と切断されて前記半導体装置と前記パターンとが遮断される。   Patent Document 1 discloses a conductor pattern formed on a circuit board adjacent to a semiconductor device and having a groove formed on the upper surface, and a low melting point metal in a region including the upper surface of the pattern and the peripheral edge of one side of the groove. There is disclosed a fuse-equipped semiconductor device including a fuse mechanism including an electrode formed of a member and a wire having one end connected to an electrode of the semiconductor device and the other end connected to an electrode of the fuse mechanism. When an overcurrent flows through the pattern, the electrode of the fuse mechanism melts and flows into the groove, and is cut off from the other end of the wire to cut off the semiconductor device and the pattern.

特許第４５９３５１８号公報Japanese Patent No. 4593518

上述したような半導体装置では、半導体素子のパッケージ内にヒューズ機構を設けることは、オン抵抗が増加する為、半導体素子の性能が低下する上、部品コストが増加するという問題がある。
本発明は、上述したような事情に鑑みてなされたものであり、ヒューズを内蔵することなく、半導体素子の焼損防止ができる半導体装置を提供することを目的とする。 In the semiconductor device as described above, the provision of the fuse mechanism in the package of the semiconductor element has a problem that the on-resistance increases, so that the performance of the semiconductor element is deteriorated and the component cost is increased.
The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a semiconductor device capable of preventing burning of a semiconductor element without incorporating a fuse.

第１発明に係る半導体装置は、直流電源及び負荷間に逆直列に接続される２つの半導体素子を備え、該２つの半導体素子を同時的にオン又はオフにするように構成してある半導体装置において、前記２つの半導体素子の接続節点及び固定電位間の電圧値を検出する電圧検出手段と、前記２つの半導体素子がオフである場合に、前記電圧検出手段が検出した電圧値の所定電圧値との高低を判定する手段と、該手段が所定電圧値より高いと判定したときに、前記２つの半導体素子をオンにする手段とを備えることを特徴とする。   A semiconductor device according to a first aspect of the present invention includes two semiconductor elements connected in reverse series between a DC power source and a load, and is configured to simultaneously turn on or off the two semiconductor elements. And a voltage detection means for detecting a voltage value between a connection node of the two semiconductor elements and a fixed potential, and a predetermined voltage value detected by the voltage detection means when the two semiconductor elements are off. And means for turning on the two semiconductor elements when it is determined that the means is higher than a predetermined voltage value.

この半導体装置では、２つの半導体素子が、直流電源及び負荷間に逆直列に接続され、２つの半導体素子を同時的にオン又はオフにするように構成してある。電圧検出手段が、２つの半導体素子の接続節点及び固定電位間の電圧値を検出する。２つの半導体素子がオフである場合に、電圧検出手段が検出した電圧値の所定電圧値との高低を判定し、所定電圧値より高いと判定したときに、２つの半導体素子をオンにする。   In this semiconductor device, two semiconductor elements are connected in anti-series between a DC power source and a load, and the two semiconductor elements are simultaneously turned on or off. The voltage detection means detects the voltage value between the connection node of the two semiconductor elements and the fixed potential. When the two semiconductor elements are off, it is determined whether the voltage value detected by the voltage detection means is higher or lower than the predetermined voltage value, and when it is determined that the voltage value is higher than the predetermined voltage value, the two semiconductor elements are turned on.

第２発明に係る半導体装置は、直流電源及び負荷間に逆直列に接続される２つの半導体素子を備え、該２つの半導体素子を同時的にオン又はオフにするように構成してある半導体装置において、前記２つの半導体素子の接続節点及び固定電位間の電圧値を検出する電圧検出手段と、前記２つの半導体素子がオフである場合に、前記電圧検出手段が検出した電圧値の所定電圧値との高低を判定する手段と、該手段が所定電圧値より低いと判定したときに、前記２つの半導体素子をオンにする手段とを備えることを特徴とする。   A semiconductor device according to a second aspect of the present invention includes two semiconductor elements connected in reverse series between a DC power source and a load, and is configured to simultaneously turn on or off the two semiconductor elements. And a voltage detection means for detecting a voltage value between a connection node of the two semiconductor elements and a fixed potential, and a predetermined voltage value detected by the voltage detection means when the two semiconductor elements are off. And means for turning on the two semiconductor elements when it is determined that the means is lower than a predetermined voltage value.

この半導体装置では、２つの半導体素子が、直流電源及び負荷間に逆直列に接続され、２つの半導体素子を同時的にオン又はオフにするように構成してある。電圧検出手段が、２つの半導体素子の接続節点及び固定電位間の電圧値を検出する。２つの半導体素子がオフである場合に、電圧検出手段が検出した電圧値の所定電圧値との高低を判定し、所定電圧値より低いと判定したときに、２つの半導体素子をオンにする。   In this semiconductor device, two semiconductor elements are connected in anti-series between a DC power source and a load, and the two semiconductor elements are simultaneously turned on or off. The voltage detection means detects the voltage value between the connection node of the two semiconductor elements and the fixed potential. When the two semiconductor elements are off, it is determined whether the voltage value detected by the voltage detection means is higher or lower than the predetermined voltage value, and when it is determined that the voltage value is lower than the predetermined voltage value, the two semiconductor elements are turned on.

本発明に係る半導体装置によれば、ヒューズを内蔵することなく、半導体素子の焼損防止ができる半導体装置を実現することができる。   According to the semiconductor device of the present invention, it is possible to realize a semiconductor device that can prevent burning of a semiconductor element without incorporating a fuse.

本発明に係る半導体装置の実施の形態の要部構成を示す回路図である。It is a circuit diagram which shows the principal part structure of embodiment of the semiconductor device which concerns on this invention. 図１に示す半導体装置の動作の例を説明する為の説明図である。FIG. 2 is an explanatory diagram for explaining an example of the operation of the semiconductor device shown in FIG. 1. 本発明に係る半導体装置の実施の形態の要部構成を示す回路図である。It is a circuit diagram which shows the principal part structure of embodiment of the semiconductor device which concerns on this invention. 図３に示す半導体装置の動作の例を説明する為の説明図である。FIG. 4 is an explanatory diagram for explaining an example of the operation of the semiconductor device shown in FIG. 3. 本発明に係る半導体装置の実施の形態の要部構成を示す回路図である。It is a circuit diagram which shows the principal part structure of embodiment of the semiconductor device which concerns on this invention. 図５に示す半導体装置の動作の例を説明する為の説明図である。FIG. 6 is an explanatory diagram for explaining an example of the operation of the semiconductor device shown in FIG. 5.

以下に、本発明をその実施の形態を示す図面に基づき説明する。
（実施の形態１）
図１は、本発明に係る半導体装置の実施の形態１の要部構成を示す回路図である。この半導体装置は、直流電源及び負荷２間に、Ｎチャネル型ＭＯＳＦＥＴ（半導体素子）３，４が並列に接続されている。ＦＥＴ３，４の各ドレインが直流電源に、各ソースが負荷２の一方の端子にそれぞれ接続され、負荷２の他方の端子は接地されている（固定電位に接続されている）。 Hereinafter, the present invention will be described with reference to the drawings illustrating embodiments thereof.
(Embodiment 1)
FIG. 1 is a circuit diagram showing the main configuration of the first embodiment of the semiconductor device according to the present invention. In this semiconductor device, N-channel MOSFETs (semiconductor elements) 3 and 4 are connected in parallel between a DC power source and a load 2. Each drain of the FETs 3 and 4 is connected to a DC power source, each source is connected to one terminal of the load 2, and the other terminal of the load 2 is grounded (connected to a fixed potential).

ＦＥＴ３，４の各ソース（負荷２の一方の端子）の電圧値が、制御部１が内蔵する電圧検出手段９により検出される。ＦＥＴ３，４は、それぞれ逆並列に形成されたボディダイオード（寄生ダイオード）を有している。制御部１は、マイクロコンピュータを備えており、ＦＥＴ３，４の各ゲートに接続され、ＦＥＴ３，４を同時的にオン又はオフに作動させる。   The voltage value of each source (one terminal of load 2) of FET3, 4 is detected by the voltage detection means 9 which the control part 1 incorporates. Each of the FETs 3 and 4 has a body diode (parasitic diode) formed in antiparallel. The control unit 1 includes a microcomputer, is connected to the gates of the FETs 3 and 4, and operates the FETs 3 and 4 simultaneously to be turned on or off.

このような構成の半導体装置では、制御部１は、負荷２を駆動させる指示信号を受けたときは、ＦＥＴ３，４を同時的にオンにし、負荷２を停止させる指示信号を受けたときは、ＦＥＴ３，４を同時的にオフにする。ＦＥＴ３，４がオフである場合、ＦＥＴ３，４が正常であれば、電圧検出手段９が検出する電圧値は０である。   In the semiconductor device having such a configuration, when the control unit 1 receives an instruction signal for driving the load 2, the control unit 1 simultaneously turns on the FETs 3 and 4 and receives an instruction signal for stopping the load 2. The FETs 3 and 4 are simultaneously turned off. When the FETs 3 and 4 are off, the voltage value detected by the voltage detection means 9 is 0 if the FETs 3 and 4 are normal.

ここで、例えば、図１に示すように、ＦＥＴ３，４がオフである場合に、ＦＥＴ３がショート故障したとき、ＦＥＴ３は、オン抵抗が通常より大きい状態で半導通になり、電圧検出手段９が検出する電圧値は上昇する。制御部（判定する手段、オンにする手段）１は、電圧検出手段９が検出した電圧値が所定電圧値より高いか否かを判定しており、所定電圧値より高いと判定したときは、ＦＥＴ３，４をオンにする。   Here, for example, as shown in FIG. 1, when the FETs 3 and 4 are off, and the FET 3 is short-circuited, the FET 3 becomes semi-conductive with the on-resistance larger than normal, and the voltage detection means 9 The detected voltage value increases. The control unit (determining means, turning on means) 1 determines whether or not the voltage value detected by the voltage detecting means 9 is higher than a predetermined voltage value. When it is determined that the voltage value is higher than the predetermined voltage value, The FETs 3 and 4 are turned on.

これにより、図２に示すように、ＦＥＴ４にも電流が流れて、ショート故障したＦＥＴ３に流れる電流が減少し、ＦＥＴ３での発熱量を低減でき、焼損を防止できるので、フェールセーフが実現する。また、負荷２は、ＦＥＴ３の半導通により、中途半端に駆動する状態になっているので、ＦＥＴ３，４をオンにしても、負荷２への新たな負担は小さい。   As a result, as shown in FIG. 2, a current also flows in the FET 4, the current flowing in the short-circuited FET 3 is reduced, the amount of heat generated in the FET 3 can be reduced, and burnout can be prevented, thereby realizing fail-safe. Further, since the load 2 is driven halfway due to the semi-conduction of the FET 3, even if the FETs 3 and 4 are turned on, a new burden on the load 2 is small.

尚、上述した実施の形態１では、半導体素子を２つ並列に接続してある例を説明しているが、半導体素子を３つ以上並列に接続してある場合でも、同様に作動させることが可能である。また、上述した実施の形態１では、半導体素子としてＮチャネル型ＭＯＳＦＥＴ３，４を使用しているが、Ｐチャネル型ＭＯＳＦＥＴを使用した場合でも、同様に作動させることが可能である。   In the first embodiment described above, an example in which two semiconductor elements are connected in parallel has been described. However, even when three or more semiconductor elements are connected in parallel, the same operation can be performed. Is possible. In the first embodiment described above, the N-channel MOSFETs 3 and 4 are used as semiconductor elements. However, even when a P-channel MOSFET is used, it can be operated in the same manner.

（実施の形態２）
図３は、本発明に係る半導体装置の実施の形態２の要部構成を示す回路図である。この半導体装置は、直流電源及び負荷２間に、Ｎチャネル型ＭＯＳＦＥＴ（半導体素子）５，６が逆直列に接続されている。ＦＥＴ５のドレインが直流電源に接続され、ＦＥＴ５，６の各ソースが共通接続され、ＦＥＴ６のドレインが負荷２の一方の端子に接続され、負荷２の他方の端子は接地されている（固定電位に接続されている）。 (Embodiment 2)
FIG. 3 is a circuit diagram showing a main configuration of the semiconductor device according to the second embodiment of the present invention. In this semiconductor device, N-channel MOSFETs (semiconductor elements) 5 and 6 are connected in reverse series between a DC power source and a load 2. The drain of the FET 5 is connected to a DC power source, the sources of the FETs 5 and 6 are connected in common, the drain of the FET 6 is connected to one terminal of the load 2, and the other terminal of the load 2 is grounded (at a fixed potential). It is connected).

ＦＥＴ５，６の各ソース及び接地端子間に抵抗Ｒが接続され、抵抗Ｒの両端電圧値が、制御部１が内蔵する電圧検出手段９により検出される。ＦＥＴ５，６は、それぞれ逆並列に形成されたボディダイオード（寄生ダイオード）を有している。制御部１は、マイクロコンピュータを備えており、ＦＥＴ５，６の各ゲートに接続され、ＦＥＴ５，６を同時的にオン又はオフに作動させる。尚、負荷２は、バッテリ等のサブ電源であっても良く、この場合、ＦＥＴ５のドレインから他の負荷へ分岐させ、ＦＥＴ５，６は、サブ電源の充電時及び放電時はオンになって、電源及びサブ電源の切替えを行う。   A resistor R is connected between the sources of the FETs 5 and 6 and the ground terminal, and the voltage value across the resistor R is detected by the voltage detection means 9 built in the control unit 1. The FETs 5 and 6 each have a body diode (parasitic diode) formed in antiparallel. The control unit 1 includes a microcomputer and is connected to the gates of the FETs 5 and 6 to simultaneously turn on or off the FETs 5 and 6. The load 2 may be a sub power source such as a battery. In this case, the FET 5 is branched from the drain of the FET 5 to another load, and the FETs 5 and 6 are turned on when the sub power source is charged and discharged. Switch between power supply and sub power supply.

このような構成の半導体装置では、制御部１は、負荷２を駆動させる指示信号を受けたときは、ＦＥＴ５，６を同時的にオンにし、負荷２を停止させる指示信号を受けたときは、ＦＥＴ５，６を同時的にオフにする。ＦＥＴ５，６がオフである場合、ＦＥＴ５，６が正常であれば、電圧検出手段９が検出する電圧値は０である。   In the semiconductor device having such a configuration, when the control unit 1 receives an instruction signal for driving the load 2, the control unit 1 simultaneously turns on the FETs 5 and 6 and receives an instruction signal for stopping the load 2. The FETs 5 and 6 are turned off simultaneously. When the FETs 5 and 6 are off, and the FETs 5 and 6 are normal, the voltage value detected by the voltage detection means 9 is zero.

ここで、例えば、図３に示すように、ＦＥＴ５，６がオフである場合に、ＦＥＴ５がショート故障したとき、ＦＥＴ５は、オン抵抗が通常より大きい状態で半導通になり、ＦＥＴ６のボディダイオード及び抵抗Ｒを通じて電流が流れて、電圧検出手段９が検出する電圧値は上昇する。但し、抵抗Ｒは、大きくしてあるので、電流が殆ど流れない。制御部（判定する手段、オンにする手段）１は、電圧検出手段９が検出した電圧値が所定電圧値より高いか否かを判定しており、所定電圧値より高いと判定したときは、ＦＥＴ５，６をオンにする。   Here, for example, as shown in FIG. 3, when the FETs 5 and 6 are OFF and the FET 5 is short-circuited, the FET 5 becomes semi-conductive with the ON resistance larger than normal, and the body diode of the FET 6 and A current flows through the resistor R, and the voltage value detected by the voltage detecting means 9 increases. However, since the resistance R is increased, almost no current flows. The control unit (determining means, turning on means) 1 determines whether or not the voltage value detected by the voltage detecting means 9 is higher than a predetermined voltage value. When it is determined that the voltage value is higher than the predetermined voltage value, The FETs 5 and 6 are turned on.

これにより、図４に示すように、ＦＥＴ６にも電流が流れて、ＦＥＴ６のボディダイオードに流れる電流が減少し、ＦＥＴ６での発熱量を低減でき、焼損を防止できるので、フェールセーフが実現する。尚、逆直列に接続したＦＥＴ５，６の対を複数並列に接続した場合は、ＦＥＴ５，６をオンにすることにより、ショート故障したＦＥＴ５に流れる電流も減少し、ＦＥＴ５での発熱量も低減できる。また、負荷２は、ＦＥＴ５の半導通、及びＦＥＴ６のボディダイオードの導通により、中途半端に駆動する状態になっているので、ＦＥＴ５，６をオンにしても、負荷２への新たな負担は小さい。   As a result, as shown in FIG. 4, a current also flows through the FET 6, the current flowing through the body diode of the FET 6 decreases, the amount of heat generated in the FET 6 can be reduced, and burnout can be prevented, thereby realizing fail-safe. When a plurality of pairs of FETs 5 and 6 connected in anti-series are connected in parallel, by turning on FETs 5 and 6, the current flowing through the short-circuited FET 5 is reduced and the amount of heat generated in the FET 5 can be reduced. . In addition, since the load 2 is in a state of being driven halfway due to the half-conduction of the FET 5 and the conduction of the body diode of the FET 6, even if the FETs 5 and 6 are turned on, a new burden on the load 2 is small. .

（実施の形態３）
図５は、本発明に係る半導体装置の実施の形態３の要部構成を示す回路図である。この半導体装置は、直流電源及び負荷２間に、Ｎチャネル型ＭＯＳＦＥＴ（半導体素子）７，８が逆直列に接続されている。ＦＥＴ７のソースが直流電源に接続され、ＦＥＴ７，８の各ドレインが共通接続され、ＦＥＴ８のソースが負荷２の一方の端子に接続され、負荷２の他方の端子は接地されている（固定電位に接続されている）。 (Embodiment 3)
FIG. 5 is a circuit diagram showing a main configuration of the semiconductor device according to the third embodiment of the present invention. In this semiconductor device, N-channel MOSFETs (semiconductor elements) 7 and 8 are connected in reverse series between a DC power source and a load 2. The source of the FET 7 is connected to a DC power source, the drains of the FETs 7 and 8 are connected in common, the source of the FET 8 is connected to one terminal of the load 2, and the other terminal of the load 2 is grounded (at a fixed potential). It is connected).

ＦＥＴ７，８の各ドレイン及び接地端子間に抵抗Ｒが接続され、抵抗Ｒの両端電圧値が、制御部１が内蔵する電圧検出手段９により検出される。ＦＥＴ７，８は、それぞれ逆並列に形成されたボディダイオード（寄生ダイオード）を有している。制御部１は、マイクロコンピュータを備えており、ＦＥＴ７，８の各ゲートに接続され、ＦＥＴ７，８を同時的にオン又はオフに作動させる。尚、負荷２は、バッテリ等のサブ電源であっても良く、この場合、ＦＥＴ７のソースから他の負荷へ分岐させ、ＦＥＴ７，８は、サブ電源の充電時及び放電時はオンになって、電源及びサブ電源の切替えを行う。   A resistor R is connected between the drains of the FETs 7 and 8 and the ground terminal, and the voltage value across the resistor R is detected by the voltage detection means 9 built in the control unit 1. The FETs 7 and 8 each have a body diode (parasitic diode) formed in antiparallel. The control unit 1 includes a microcomputer, is connected to the gates of the FETs 7 and 8, and operates the FETs 7 and 8 simultaneously on or off. The load 2 may be a sub power source such as a battery. In this case, the source of the FET 7 is branched to another load, and the FETs 7 and 8 are turned on when the sub power source is charged and discharged. Switch between power supply and sub power supply.

このような構成の半導体装置では、制御部１は、負荷２を駆動させる指示信号を受けた
ときは、ＦＥＴ７，８を同時的にオンにし、負荷２を停止させる指示信号を受けたときは
、ＦＥＴ７，８を同時的にオフにする。ＦＥＴ７，８がオフである場合、ＦＥＴ７，８が正常であれば、ＦＥＴ７のボディダイオードが導通しているので、電圧検出手段９が検出する電圧値は略電源の電圧値である。但し、抵抗Ｒは、大きくしてあるので、電流が殆ど流れない。 In the semiconductor device having such a configuration, when the control unit 1 receives an instruction signal for driving the load 2, the control unit 1 simultaneously turns on the FETs 7 and 8 and receives an instruction signal for stopping the load 2. The FETs 7 and 8 are turned off simultaneously. When the FETs 7 and 8 are off, if the FETs 7 and 8 are normal, the body diode of the FET 7 is conductive, so that the voltage value detected by the voltage detection means 9 is substantially the voltage value of the power supply. However, since the resistance R is increased, almost no current flows.

ここで、例えば、図５に示すように、ＦＥＴ７，８がオフである場合に、ＦＥＴ８がショート故障したとき、ＦＥＴ８は、オン抵抗が通常より大きい状態で半導通になり、ＦＥＴ７のボディダイオードを通じて負荷２に電流が流れて、電圧検出手段９が検出する電圧値は降下する。但し、抵抗Ｒは、上述したように、電流が殆ど流れない。制御部（判定する手段、オンにする手段）１は、電圧検出手段９が検出した電圧値が所定電圧値より低いか否かを判定しており、所定電圧値より低いと判定したときは、ＦＥＴ７，８をオンにする。   Here, for example, as shown in FIG. 5, when the FETs 8 and 8 are OFF, when the FET 8 is short-circuited, the FET 8 becomes semi-conductive in a state where the ON resistance is larger than normal, and passes through the body diode of the FET 7. A current flows through the load 2 and the voltage value detected by the voltage detecting means 9 drops. However, almost no current flows through the resistor R as described above. The control unit (determination means, turning on means) 1 determines whether or not the voltage value detected by the voltage detection means 9 is lower than a predetermined voltage value. When it is determined that the voltage value is lower than the predetermined voltage value, The FETs 7 and 8 are turned on.

これにより、図６に示すように、ＦＥＴ７にも電流が流れて、ＦＥＴ７のボディダイオードに流れる電流が減少し、ＦＥＴ７での発熱量を低減でき、焼損を防止できるので、フェールセーフが実現する。尚、逆直列に接続したＦＥＴ７，８の対を複数並列に接続した場合は、ＦＥＴ７，８をオンにすることにより、ショート故障したＦＥＴ８に流れる電流も減少し、ＦＥＴ８での発熱量も低減できる。また、負荷２は、ＦＥＴ８の半導通、及びＦＥＴ７のボディダイオードの導通により、中途半端に駆動する状態になっているので、ＦＥＴ７，８をオンにしても、負荷２への新たな負担は小さい。   As a result, as shown in FIG. 6, a current also flows through the FET 7, the current flowing through the body diode of the FET 7 is reduced, the amount of heat generated in the FET 7 can be reduced, and burnout can be prevented, thereby realizing fail-safe. When a plurality of pairs of FETs 7 and 8 connected in anti-series are connected in parallel, by turning on the FETs 7 and 8, the current flowing through the short-circuited FET 8 is reduced and the amount of heat generated in the FET 8 can be reduced. . Further, since the load 2 is in a state of being driven halfway due to the half-conduction of the FET 8 and the conduction of the body diode of the FET 7, even if the FETs 7 and 8 are turned on, a new burden on the load 2 is small. .

尚、上述した実施の形態２，３では、２つの半導体素子を逆直列に接続した１対の例を説明しているが、２つの半導体素子を逆直列に接続した対を２つ以上並列に接続してある場合でも、同様に作動させることが可能である。また、上述した実施の形態２，３では、半導体素子としてＮチャネル型ＭＯＳＦＥＴを使用しているが、Ｐチャネル型ＭＯＳＦＥＴを使用した場合でも、同様に作動させることが可能である。   In the second and third embodiments described above, an example of a pair in which two semiconductor elements are connected in anti-series is described. However, two or more pairs in which two semiconductor elements are connected in anti-series are connected in parallel. Even when connected, it is possible to operate similarly. In the second and third embodiments described above, an N-channel MOSFET is used as a semiconductor element. However, even when a P-channel MOSFET is used, it can be operated similarly.

１ 制御部（判定する手段、オンにする手段）
２ 負荷
３，４，５，６，７，８ ＦＥＴ（半導体素子）
９ 電圧検出手段
Ｒ 抵抗 1 Control unit (means for judging, means for turning on)
2 Load 3, 4, 5, 6, 7, 8 FET (semiconductor element)
9 Voltage detection means R Resistance

Claims (2)

直流電源及び負荷間に逆直列に接続される２つの半導体素子を備え、該２つの半導体素子を同時的にオン又はオフにするように構成してある半導体装置において、
前記２つの半導体素子の接続節点及び固定電位間の電圧値を検出する電圧検出手段と、前記２つの半導体素子がオフである場合に、前記電圧検出手段が検出した電圧値の所定電圧値との高低を判定する手段と、該手段が所定電圧値より高いと判定したときに、前記２つの半導体素子をオンにする手段とを備えることを特徴とする半導体装置。 In a semiconductor device comprising two semiconductor elements connected in reverse series between a DC power source and a load, and configured to turn on or off the two semiconductor elements simultaneously,
A voltage detection means for detecting a voltage value between a connection node of the two semiconductor elements and a fixed potential; and a predetermined voltage value detected by the voltage detection means when the two semiconductor elements are off. A semiconductor device comprising: means for determining a level; and means for turning on the two semiconductor elements when it is determined that the means is higher than a predetermined voltage value. 直流電源及び負荷間に逆直列に接続される２つの半導体素子を備え、該２つの半導体素子を同時的にオン又はオフにするように構成してある半導体装置において、
前記２つの半導体素子の接続節点及び固定電位間の電圧値を検出する電圧検出手段と、前記２つの半導体素子がオフである場合に、前記電圧検出手段が検出した電圧値の所定電圧値との高低を判定する手段と、該手段が所定電圧値より低いと判定したときに、前記２つの半導体素子をオンにする手段とを備えることを特徴とする半導体装置。 In a semiconductor device comprising two semiconductor elements connected in reverse series between a DC power source and a load, and configured to turn on or off the two semiconductor elements simultaneously,
A voltage detection means for detecting a voltage value between a connection node of the two semiconductor elements and a fixed potential; and a predetermined voltage value detected by the voltage detection means when the two semiconductor elements are off. A semiconductor device comprising: means for determining a level; and means for turning on the two semiconductor elements when it is determined that the means is lower than a predetermined voltage value.
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JPH11150461A (en) * 1997-11-13 1999-06-02 Nissin High Voltage Co Ltd High voltage switch circuit
JP2003158447A (en) * 2001-11-22 2003-05-30 Denso Corp Abnormality detecting device of device for driving electrical load and ic for driving electrical load
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