JP2017147353A - Solid state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging device capable of extending a dynamic range.SOLUTION: The solid-state imaging device includes a plurality of photoelectric conversion elements and extension gates. The photoelectric conversion elements are provided in a semiconductor layer, convert incident light into signal charge corresponding to an amount of received light, and store it. The extension gates are provided on a region of the semiconductor layer adjacent to the photoelectric conversion elements, and expand a charge accumulation region of the photoelectric conversion elements by applying a voltage. The photoelectric conversion elements and the extension gates are arranged in a staggered lattice pattern in plan view.SELECTED DRAWING: Figure 3A

Description

  The present embodiment relates to a solid-state imaging device.

  Conventionally, a solid-state imaging device includes a plurality of photoelectric conversion elements provided in a matrix corresponding to each pixel of a captured image. Each photoelectric conversion element converts incident light into a signal charge corresponding to the amount of light and accumulates it, and outputs a voltage corresponding to the accumulated signal charge as a pixel signal indicating the luminance of each pixel.

  In such a solid-state imaging device, as the size and thickness of the solid-state imaging device are reduced, the charge accumulation region of the photoelectric conversion element is reduced, and the number of saturation signal charges that can be accumulated in the photoelectric conversion element is reduced. As a result, the solid-state imaging device has a narrow dynamic range of luminance that can be imaged.

JP 2014-112580 A

  An object of one embodiment is to provide a solid-state imaging device capable of extending a dynamic range.

  According to one embodiment, a solid-state imaging device is provided. The solid-state imaging device includes a photoelectric conversion element and an expansion gate. The photoelectric conversion element is provided in the semiconductor layer and converts incident light into signal charges and accumulates them. The extension gate is provided on a region of the semiconductor layer adjacent to the photoelectric conversion element, and extends a charge accumulation region of the photoelectric conversion element when a voltage is applied thereto. The photoelectric conversion element and the extension gate are arranged in a staggered pattern in plan view.

FIG. 1 is a block diagram illustrating a schematic configuration of a digital camera including the solid-state imaging device according to the first embodiment. FIG. 2 is a block diagram illustrating a schematic configuration of the solid-state imaging device according to the first embodiment. FIG. 3A is an explanatory diagram illustrating a part of the pixel array according to the first embodiment in plan view. FIG. 3B is an explanatory diagram illustrating a circuit corresponding to one pixel of the pixel array according to the first embodiment. FIG. 4 is an explanatory diagram illustrating a correspondence relationship between a part of the pixel array according to the first embodiment in a cross-sectional view and a potential distribution inside the pixel array. FIG. 5A is an explanatory diagram of an operation performed by the pixel array according to the first embodiment in a high saturation mode. FIG. 5B is an explanatory diagram illustrating a modification of the operation performed by the pixel array according to the first embodiment in the high saturation mode. FIG. 6 is an explanatory diagram of an operation performed by the pixel array according to the first embodiment in the high saturation mode. FIG. 7 is an explanatory diagram of an operation performed by the pixel array according to the first embodiment in the high saturation mode. FIG. 8 is an explanatory diagram of an operation performed by the pixel array according to the first embodiment in the low noise mode. FIG. 9 is an explanatory diagram of an operation performed by the pixel array according to the first embodiment in the low noise mode. FIG. 10 is an explanatory diagram of an operation performed by the pixel array according to the first embodiment in the low noise mode. FIG. 11 is an explanatory diagram of an operation performed by the pixel array according to the first embodiment in the low noise mode. FIG. 12 is an explanatory diagram of an operation performed by the pixel array according to the first embodiment in the global shutter mode. FIG. 13 is an explanatory diagram of an operation performed by the pixel array according to the first embodiment in the global shutter mode. FIG. 14 is an explanatory diagram of an operation performed by the pixel array according to the first embodiment in the global shutter mode. FIG. 15 is an explanatory diagram of an operation performed by the pixel array according to the first embodiment in the global shutter mode. FIG. 16 is an explanatory diagram of an operation performed by the pixel array according to the first embodiment in the global shutter mode. FIG. 17 is an explanatory diagram of an operation performed in the HDR mode by the pixel array according to the first embodiment. FIG. 18 is an explanatory diagram of an operation performed by the pixel array according to the first embodiment in the HDR mode. FIG. 19 is an explanatory diagram of an operation performed by the pixel array according to the first embodiment in the HDR mode. FIG. 20 is an explanatory diagram of an operation performed by the pixel array according to the first embodiment in the HDR mode. FIG. 21 is an explanatory diagram of an operation performed by the pixel array according to the first embodiment in the HDR mode. FIG. 22 is an explanatory diagram of an operation performed by the pixel array according to the first embodiment in the HDR mode. FIG. 23A is an explanatory diagram illustrating a part in a cross-sectional view of a pixel array according to Modification 1 of the first embodiment. FIG. 23B is an explanatory diagram illustrating a part in a cross-sectional view of a pixel array according to Modification 2 of the first embodiment. FIG. 24 is an explanatory diagram illustrating a part of the pixel array according to the second embodiment in plan view. FIG. 25A is an explanatory diagram illustrating a part of a pixel array according to the second embodiment in a cross-sectional view. FIG. 25B is an explanatory diagram illustrating a part in a cross-sectional view of a pixel array according to Modification 1 of the second embodiment. FIG. 26 is an explanatory diagram illustrating a part in a cross-sectional view of a pixel array according to Modification 2 of the second embodiment. FIG. 27 is an explanatory diagram viewed from above showing a modification of the arrangement of the photoelectric conversion elements and the extension gates according to the embodiment.

  Hereinafter, a solid-state imaging device according to an embodiment will be described in detail with reference to the accompanying drawings. In addition, this invention is not limited by this embodiment.

(First embodiment)
FIG. 1 is a block diagram illustrating a schematic configuration of a digital camera 1 including a solid-state imaging device 14 according to the first embodiment. As shown in FIG. 1, the digital camera 1 includes a camera module 11 and a post-processing unit 12.

  The camera module 11 includes an imaging optical system 13 and a solid-state imaging device 14. The imaging optical system 13 takes in light from a subject and forms a subject image. The solid-state imaging device 14 captures a subject image formed by the imaging optical system 13 and outputs an image signal obtained by the imaging to the post-processing unit 12. In addition to the digital camera 1, the camera module 11 is applied to an electronic device such as a mobile terminal with a camera.

  The post-processing unit 12 includes an ISP (Image Signal Processor) 15, a storage unit 16, and a display unit 17. The ISP 15 performs signal processing of the image signal input from the solid-state imaging device 14. The ISP 15 performs high image quality processing such as noise removal processing, defective pixel correction processing, and resolution conversion processing.

  Then, the ISP 15 outputs the image signal after the signal processing to the signal processing circuit 21 (see FIG. 2) described later provided in the storage unit 16, the display unit 17, and the solid-state imaging device 14 in the camera module 11. An image signal fed back from the ISP 15 to the camera module 11 is used for adjustment and control of the solid-state imaging device 14.

  The storage unit 16 stores the image signal input from the ISP 15 as an image. In addition, the storage unit 16 outputs an image signal of the stored image to the display unit 17 according to a user operation or the like. The display unit 17 displays an image according to an image signal input from the ISP 15 or the storage unit 16. The display unit 17 is, for example, a liquid crystal display.

  Next, the solid-state imaging device 14 included in the camera module 11 will be described with reference to FIG. FIG. 2 is a block diagram illustrating a schematic configuration of the solid-state imaging device 14 according to the first embodiment. As shown in FIG. 2, the solid-state imaging device 14 includes an image sensor 20 and a signal processing circuit 21.

  Here, a case where the image sensor 20 is a so-called surface-irradiation type CMOS (Complementary Metal Oxide Semiconductor) image sensor in which a wiring layer is formed on a surface on which incident light is incident in a pixel that photoelectrically converts incident light will be described. To do. Note that the case where the image sensor 20 is a backside illumination type will be described later in the second embodiment.

  The image sensor 20 includes a peripheral circuit 22 and a pixel array 23. The peripheral circuit 22 includes a vertical shift register 24, a timing control unit 25, a CDS (correlated double sampling) 26, an ADC (analog / digital conversion unit) 27, and a line memory 28, and these are mainly configured by analog circuits. Is done.

  The pixel array 23 is provided in the imaging region of the image sensor 20. In the pixel array 23, a plurality of photoelectric conversion elements corresponding to each pixel of the captured image are arranged in a two-dimensional array (matrix) in the horizontal direction (row direction) and the vertical direction (column direction). In the pixel array 23, the photoelectric conversion element of each pixel generates a signal charge (for example, electrons) corresponding to the amount of incident light, and accumulates it in a charge accumulation region in each pixel.

  Here, when a general pixel array is reduced in size and thickness, the number of saturated electrons that can be stored in the charge storage region is reduced, and the dynamic range of luminance that can be captured becomes narrow. Therefore, the pixel array 23 of this embodiment is provided on a region adjacent to the photoelectric conversion element in the semiconductor layer, and includes an expansion gate that expands the charge storage region of the photoelectric conversion element when a voltage is applied. As a result, the pixel array 23 can expand the dynamic range of luminance that can be imaged. A specific configuration and operation of the pixel array 23 will be described later with reference to FIGS. 3A to 22.

  The timing control unit 25 is a processing unit that outputs a control signal serving as an operation instruction to the vertical shift register 24, the CDS 26, the ADC 27, and the line memory 28. The timing control unit 25 also performs control for switching between application and non-application of the voltage to the expansion gate, and control for switching application and non-application of a voltage to the discharge gate described later.

  Control signals for the expansion gate and the discharge gate are input from the timing control unit 25 to the corresponding expansion gate and discharge gate in the pixel array 23 via the vertical shift register 24. The flow of the control signal is an example, and the timing control unit 25 may be configured to output the control signal directly to the extension gate or the discharge gate.

  The timing control unit 25 also performs voltage application control on a transfer gate, a first reset gate, a second reset gate, a discharge gate, an amplifier transistor gate, and an address transistor gate, which will be described later.

  The vertical shift register 24 is a processing unit that outputs, to the pixel array 23, a selection signal for sequentially selecting pixels for reading signal charges from a plurality of pixels that are two-dimensionally arranged in an array (matrix). .

  The pixel array 23 outputs a pixel signal corresponding to the signal charge accumulated in each pixel from each pixel selected in units of rows by the selection signal input from the vertical shift register 24 to the CDS 26.

  The CDS 26 is a processing unit that removes noise from the pixel signal input from the pixel array 23 by correlated double sampling and outputs the noise to the ADC 27. The ADC 27 is a processing unit that converts an analog pixel signal input from the CDS 26 into a digital pixel signal and outputs the digital pixel signal to the line memory 28. The line memory 28 is a processing unit that temporarily holds the pixel signal input from the ADC 27 and outputs the pixel signal to the signal processing circuit 21 for each row of pixels in the pixel array 23.

  The signal processing circuit 21 is a processing unit that performs predetermined signal processing on the pixel signal input from the line memory 28 and outputs the processed signal to the subsequent processing unit 12, and is mainly configured by a digital circuit. The signal processing circuit 21 performs signal processing such as lens shading correction, flaw correction, and noise reduction processing on the pixel signal.

  As described above, in the image sensor 20, a plurality of pixels arranged in the pixel array 23 photoelectrically converts incident light into signal charges of an amount corresponding to the amount of received light, and accumulates the peripheral circuit 22 in each pixel. Imaging is performed by reading a pixel signal corresponding to the signal charge.

  Next, the configuration of the pixel array 23 in plan view will be described with reference to FIGS. 3A and 3B. FIG. 3A is an explanatory diagram illustrating a part of the pixel array 23 according to the first embodiment in plan view. FIG. 3B is an explanatory diagram illustrating a circuit corresponding to one pixel of the pixel array 23 according to the first embodiment.

  As shown in FIG. 3A, the pixel array 23 includes, for example, a plurality of photoelectric conversion elements PD arranged in a matrix in a plan view on a semiconductor layer 31 formed of silicon doped with a P-type impurity such as boron. Prepare. For example, the photoelectric conversion element PD is a semiconductor region doped with an N-type impurity such as phosphorus.

  On the light receiving surface of each photoelectric conversion element PD, for example, the area is larger than the light receiving surface of the photoelectric conversion element PD via a P-type region 34 (see FIG. 4) doped with a P-type impurity such as boron. A microlens ML is provided.

  Specifically, the microlens ML has a light receiving area larger than the light receiving area in the plan view of the photoelectric conversion element PD, and the outer periphery reaches the center in the plan view of the extension gate ST. Thereby, the microlens ML can condense the light that comes toward the extension gate ST onto the photoelectric conversion element PD. The photoelectric conversion element PD converts the incident light condensed by each microlens ML into a signal charge corresponding to the amount of received light and accumulates it.

  In addition, the pixel array 23 includes an extension gate ST that is stacked in a region adjacent to each photoelectric conversion element PD in the semiconductor layer 31 (for example, a region located at 45 ° diagonally to the lower right of each photoelectric conversion element PD). The extension gate ST is a gate formed of, for example, polysilicon. When a voltage is applied, the extension gate ST has a potential continuous to the charge accumulation region of the photoelectric conversion element PD in a region immediately below the extension gate ST in the semiconductor layer 31. Forming a well.

  As a result, the pixel array 23 is a charge storage region for storing signal charges in addition to the region of the photoelectric conversion element PD in the semiconductor layer 31 and the region immediately below the extension gate ST. Can be extended.

  Therefore, according to the pixel array 23, more signal charges can be accumulated as compared with other pixel arrays that can accumulate signal charges only in the region of the photoelectric conversion element PD. Can be extended.

  The photoelectric conversion elements PD and the expansion gates ST are arranged in a staggered pattern in plan view. Thereby, the pixel array 23 can reduce the area compared to the case where the photoelectric conversion elements PD and the expansion gates ST are alternately arranged in one direction of either the row or the column of the photoelectric conversion elements PD, for example. And miniaturization is possible.

  In addition, each extension gate ST is stacked at approximately the center of a region surrounded on all sides by four photoelectric conversion elements PD adjacent to each other. As a result, the pixel array 23 can reduce the distance between the pixels in the matrix direction as compared to the case where the photoelectric conversion elements PD and the extension gates ST are alternately arranged in either one of the rows or columns of the photoelectric conversion elements PD. Both can be reduced evenly, and further miniaturization becomes possible.

  Note that the arrangement of the photoelectric conversion elements PD and the expansion gates ST is not limited to a staggered lattice shape, and may be a lattice shape. An example of the case where the photoelectric conversion elements PD and the expansion gates ST are arranged in a lattice shape will be described later with reference to FIG.

  The pixel array 23 includes a transfer gate TG, a first floating diffusion FD1, a first reset gate RS1, a second floating diffusion FD2, a second reset gate RS2, and a reset drain RD.

  The transfer gate TG, the first floating diffusion FD1, the first reset gate RS1, the second floating diffusion FD2, the second reset gate RS2, and the reset drain RD are, for example, a plan view between two extension gates ST adjacent in the row direction. In a row.

  The first floating diffusion FD1 and the second floating diffusion FD2 are regions that can hold signal charges by being doped with N-type impurities such as phosphorus, for example. The reset drain RD is a region doped with N-type impurities such as phosphorus, and is a region where signal charges are discharged.

  The transfer gate TG is a gate that is formed of, for example, polysilicon and transfers signal charges from the region immediately below the extension gate ST in the semiconductor layer 31 to the first floating diffusion FD1 when a voltage is applied.

  The first reset gate RS1 is a gate formed of, for example, polysilicon, and electrically connects the first floating diffusion FD1 and the second floating diffusion FD2 when a voltage is applied.

  The second reset gate RS2 is formed of, for example, polysilicon, and is a gate that discharges signal charges from the second floating diffusion FD2 to the reset drain RD when a voltage is applied.

  The direction in which the transfer gate TG, the first floating diffusion FD1, the first reset gate RS1, the second floating diffusion FD2, the second reset gate RS2, and the reset drain RD are arranged, and the direction in which the photoelectric conversion element PD and the extension gate ST are arranged. Intersect at an angle of approximately 45 degrees in plan view.

  Thereby, the pixel array 23 can reduce the area occupied by one pixel, for example, compared with the case where the photoelectric conversion element, the expansion gate, the transfer gate, the floating diffusion, the reset gate, and the reset drain are arranged on a straight line. .

  Further, the pixel array 23 includes an amplifier transistor AMP and an address transistor ADR arranged in a line in a plan view between two extension gates ST adjacent in the column direction. The amplifier transistor AMP is a transistor in which the first floating diffusion FD1 or the second floating diffusion FD2 is connected to the gate by a multilayer wiring described later, and amplifies the signal charge photoelectrically converted by the photoelectric conversion element PD. The address transistor ADR is a transistor whose voltage is applied to the gate when a pixel from which signal charges are read is selected.

  As described above, the pixel array 23 includes the amplifier transistor AMP and the address transistor ADR on the boundary line of each pixel. The pixel array 23 includes a transfer gate TG, a first floating diffusion FD1, a first reset gate RS1, a second floating diffusion FD2, a second reset gate RS2, and a reset drain RD on the boundary line of each pixel. Thereby, the pixel array 23 can make the light-receiving surface of each pixel as wide as possible.

  The pixel array 23 includes a discharge gate ICG and a drain DD for each pixel. The discharge gate ICG is formed of, for example, polysilicon, and is stacked in a region adjacent to each photoelectric conversion element PD in the semiconductor layer 31.

  The drain DD is a region doped with an N-type impurity such as phosphorus, and is a region from which signal charges are discharged. The drain DD is provided at a position facing the photoelectric conversion element PD via the discharge gate ICG in plan view. The discharge gate ICG is a gate that discharges signal charges from the photoelectric conversion element PD to the drain DD when a voltage is applied.

  The pixel array 23 can suppress the charge storage region of the photoelectric conversion element PD from easily reaching a saturated state by discharging a part of the signal charge stored in the photoelectric conversion element PD to the drain DD. Thereby, the pixel array 23 can further expand the dynamic range of the luminance to be imaged.

  Although not shown here, a color filter CF, which will be described later, is provided immediately below the microlens ML, and an interlayer insulating film 35 is provided between the color filter CF and the semiconductor layer 31 (FIG. 4). A multilayer wiring 36 is provided in the interlayer insulating film 35.

  The multilayer wiring 36 includes a plurality of vertical signal lines extending in the vertical direction in plan view and a plurality of horizontal signal lines extending in the horizontal direction in plan view while avoiding the light receiving region of each photoelectric conversion element PD. Among these, the horizontal signal line is a control signal from the vertical shift register 24 (see FIG. 2) to the discharge gate ICG, the extension gate ST, the transfer gate TG, the first reset gate RS1, the second reset gate RS2, and the gate of the address transistor ADR. Is a signal line for transmitting.

  Specifically, as shown in FIG. 3B, the discharge gate ICG is connected to a horizontal signal line for the discharge gate ICG. In the transistor whose drain gate ICG is the gate, the photoelectric conversion element PD is the source and the drain DD is the drain.

  The extension gate ST is connected to a horizontal signal line for the extension gate ST. In the transistor whose extension gate ST is the gate, the photoelectric conversion element PD is the source, and the source of the transistor whose transfer gate TG is the gate is the drain.

  The transfer gate TG is connected to a horizontal signal line for the transfer gate. In the transistor whose transfer gate TG is a gate, the drain of the transistor whose extension gate ST is a gate becomes a source, and the first floating diffusion FD1 becomes a drain.

  The first reset gate RS1 is connected to the horizontal signal line for the first reset gate RS1. The transistor whose gate is the first reset gate RS1 has the first floating diffusion FD1 as the source and the second floating diffusion FD2 as the drain.

  The second reset gate RS2 is connected to the horizontal signal line for the second reset gate RS2. In the transistor whose gate is the second reset gate RS2, the second floating diffusion FD2 is the source, and the reset drain RD is the drain.

  The address transistor ADR has a gate connected to the horizontal signal line for the address transistor ADR, a source connected to the CDS 26 (see FIG. 2), and a drain connected to the source of the amplifier transistor AMP.

  The amplifier transistor AMP has a gate connected to the first floating diffusion FD1, a source connected to the drain of the address transistor ADR, and a drain connected to the drain DD.

  Next, the cross-sectional structure of the pixel array 23 and the potential distribution inside the pixel array 23 will be described with reference to FIG. FIG. 4 is an explanatory diagram illustrating a correspondence relationship between a part of the pixel array 23 according to the first embodiment in a cross-sectional view and the potential distribution inside the pixel array 23. The cross section shown in FIG. 4 schematically shows a cross section of the pixel array 23 shown in FIG.

  As shown in the upper part of FIG. 4, the pixel array 23 includes a semiconductor layer 31, an interlayer insulating film 35, a color filter CF, and a microlens ML that are sequentially stacked. The microlens ML is a plano-convex lens that condenses received light onto the photoelectric conversion element PD. The color filter CF is, for example, a color filter that selectively transmits any one of red light, green light, and blue light. The color filter CF is, for example, a Bayer array.

  The interlayer insulating film 35 is a silicon oxide layer formed of, for example, TEOS (tetraethoxysilane). The interlayer insulating film 35 is provided with a multilayer wiring 36 therein. The multilayer wiring 36 is provided at a position avoiding the optical path condensed by the microlens ML. The interlayer insulating film 35 is provided with the above-described discharge gate ICG, extension gate ST, transfer gate TG, first reset gate RS1, and second reset gate RS2 in the deep layer portion.

  The semiconductor layer 31 is provided with a drain DD, a P-type region 34, a photoelectric conversion element PD, and a well 33 on the surface layer. The well 33 is a region doped with a P-type impurity such as boron. In the surface layer of the well 33, a first floating diffusion FD1, a second floating diffusion FD2, and a reset drain RD are provided.

  Further, the semiconductor layer 31 is provided with an N-type region 32 doped with an N-type impurity such as phosphorus, for example, between the photoelectric conversion element PD and the well 33. The N-type region 32 is provided at a position closer to the first floating diffusion FD1 than the photoelectric conversion element PD below the expansion gate ST. As a result, the N-type region 32 can prevent the accumulated signal charge from flowing backward to the photoelectric conversion element PD when a voltage is applied to the extension gate ST to become a charge accumulation region.

  When the voltage is not applied to the discharge gate ICG, the extension gate ST, the transfer gate TG, the first reset gate RS1, and the second reset gate RS2, the inside of the semiconductor layer 31 has a potential distribution as shown in the lower part of FIG. Become.

  Specifically, in the semiconductor layer 31, the potentials of the drain DD, the first floating diffusion FD1, the second floating diffusion FD2, and the reset drain RD are described as predetermined upper limit values (hereinafter simply referred to as “upper limit value”). )

  The potential of the region below the discharge gate ICG, the region below the extension gate ST where the N-type region 32 is not provided, the region below the transfer gate TG, the region below the first reset gate RS1 and the second reset gate RS2 Becomes a predetermined lower limit (hereinafter, simply referred to as “lower limit”).

  Here, the lower limit value of the potential in the region below the discharge gate ICG is V (IGC), and the lower limit value of the potential in the region below the extension gate ST where the N-type region 32 is not provided is V (STa). The lower limit value of the potential in the region below the gate TG is V (TG).

  When the lower limit values of the potentials in the first reset gate RS1 and the second reset gate RS2 are V (RS1) and V (RS2), the magnitude relationship between the lower limit values is V (RS1) = V (RS2) = V (IGC)> V (STa)> V (TG). The potentials of the photoelectric conversion element PD and the N-type region 32 are lower than the upper limit voltage described above and higher than the lower limit potential.

  Here, in the semiconductor layer 31, a region having a high potential surrounded by a region having a low potential is a region serving as a potential well capable of accumulating or holding signal charges. For this reason, in the state shown in the lower part of FIG. 4, the photoelectric conversion element PD, the N-type region 32, the first floating diffusion FD1, and the second floating diffusion FD2 are potential well regions.

  From this state, the pixel array 23 switches the application and non-application of voltages to the discharge gate ICG, the expansion gate ST, the transfer gate TG, the first reset gate RS1, and the second reset gate RS2, thereby enabling a plurality of types of modes. Is possible.

  Specifically, the pixel array 23 can operate in four types of modes: a high saturation mode, a low noise mode, a global shutter mode, and an HDR (High Dynamic Range) mode. Hereinafter, operations performed by the pixel array 23 in each mode will be described.

(High saturation mode)
The high saturation mode is an operation mode for capturing an image with relatively high luminance. The charge accumulation region for accumulating the photoelectrically converted signal charge is extended from the region of the photoelectric conversion element PD in the semiconductor layer 31 to the extension gate ST. In this mode, the image is expanded to the lower area and imaged. As a result, the number of saturation signal charges in the charge storage region increases in the pixel array 23, so that the dynamic range of luminance that can be imaged can be expanded.

  FIG. 5A, FIG. 6 and FIG. 7 are explanatory diagrams of the operation performed by the pixel array 23 according to the first embodiment in the high saturation mode. FIG. 5A shows the timing at which a voltage is applied to the transfer gate TG, the expansion gate ST, the first reset gate RS1, and the second reset gate RS2. 6 and 7 show changes in potential distribution in the semiconductor layer 31 in the high saturation mode. FIG. 5B is an explanatory diagram illustrating a modification of the operation performed by the pixel array 23 according to the first embodiment in the high saturation mode.

  In the timing chart shown in FIG. 5A, the low level period is a low voltage state, and the high level period is a high voltage state. Hereinafter, a state where the timing chart is at a high level is referred to as ON, and a state where the timing chart is at a low level is referred to as OFF. In the high saturation mode, the discharge gate ICG is not turned on.

  As shown in FIG. 5A, in the high saturation mode, the first reset gate RS1 is always ON. Therefore, as shown in FIGS. 6 and 7, the potentials of the first floating diffusion FD1, the lower region of the first reset gate RS1, and the second floating diffusion FD2 are maintained at the upper limit values.

  That is, in the high saturation mode, the first floating diffusion FD1, the lower region of the first reset gate RS1, and the entire second floating diffusion FD2 function as one floating diffusion. For this reason, this region is referred to as a floating diffusion here.

  When the pixel array 23 enters the high saturation mode, as shown in FIG. 5A, the transfer gate TG and the second reset gate RS2 are OFF, and the extension gate ST and the first reset gate RS1 are ON until the time reaches t10. It becomes.

Thereby, the potential distribution in the semiconductor layer 31 changes from the state shown in the lower part of FIG. 4 to the state shown in FIG. In this state, in addition to the photoelectric conversion element PD in the semiconductor layer 31, the region below the extension gate ST is also a charge storage region, and signal charges (e ⁻ in the figure) are stored in both regions.

  Thereafter, as shown in FIG. 5A, when the time reaches t10, the transfer gate TG is turned on, the extension gate ST is turned off, and the potential distribution in the semiconductor layer 31 is in the state shown in FIG. 6B. As a result, part of the signal charge accumulated in the charge accumulation region is transferred to the floating diffusion.

  Further, the potential V (IGC) in the lower region of the discharge gate IGC is formed so as to be higher than the potential V (STa) of the barrier portion when the extension gate ST is OFF, and the charge from the photoelectric conversion element PD to the extension gate ST side. So that it does n’t overflow.

  Subsequently, as shown in FIG. 5A, when the time reaches t11, the extension gate ST is turned on, and the potential distribution in the semiconductor layer 31 is in the state shown in FIG. 6C. Thereby, in addition to the photoelectric conversion element PD in the semiconductor layer 31, the region below the extension gate ST also becomes a charge storage region, and the signal charge accumulated in the photoelectric conversion element PD is N below the extension gate ST in the semiconductor layer 31. Move to the mold area 32.

  Thereafter, as shown in FIG. 5A, the potential distribution in the semiconductor layer 31 is in the state shown in FIG. 6B until the time t12 when the image capturing of one frame ends, and in FIG. The state shown in c) is repeated.

  As described above, even if the amount of charge that can be transferred to the floating diffusion FD at a time by the expansion gate ST is small by repeating the state shown in FIG. 6B and the state shown in FIG. 6C a plurality of times. The amount of charge multiplied by the number of times can be transferred to the floating diffusion FD.

  Moreover, in the high saturation mode, as described above, in addition to the first floating diffusion FD1, the region below the first reset gate RS1 and the second floating diffusion FD2 in the semiconductor layer 31 also function as the floating diffusion. This also increases the storage capacity of the floating diffusion FD, so that the pixel array 23 can suppress the overflow of the floating diffusion.

  Thereafter, as shown in FIG. 5A, when the time reaches t12, the transfer gate TG is turned off, the extension gate ST is turned on, and the potential distribution in the semiconductor layer 31 is in the state shown in FIG. Thereby, the signal charge for one frame of the image is held in the floating diffusion. The pixel array 23 outputs an image signal corresponding to the signal charge held in the floating diffusion from each pixel.

  Subsequently, as shown in FIG. 5A, when the time reaches t13, the second reset gate RS2 is turned on, and the potential distribution in the semiconductor layer 31 is in the state shown in FIG. 7B. Thereby, the signal charge held in the floating diffusion is discharged to the reset drain RD.

  Thereafter, as shown in FIG. 5A, when the time reaches t14, the second reset gate RS2 is turned OFF, and the potential distribution in the semiconductor layer 31 is again in the state shown in FIG. After time t15, the pixel array 23 repeats the operation performed from time t10 to t14 every time one frame of an image is captured.

  Note that the operation performed by the pixel array 23 shown in FIG. 5A in the high saturation mode is an example, and the present invention is not limited to this. For example, as shown in FIG. 5B, the pixel array 23 adds a charge discharging operation between times t16 and t17 between the times t14 and t15 in the high saturation mode, and sets the effective exposure time to the times t17 to t17. It can also be between t15. Thereby, exposure time can be made shorter than the predetermined period shown to FIG. 5A. Further, the charge discharging operation may be performed with the discharging gate ICG turned ON.

(Low noise mode)
The low noise mode is an operation mode for capturing an image with relatively low luminance, and is an image capturing mode without using the N-type region 32 below the extension gate ST in the semiconductor layer 31 as a charge storage region. Thereby, the pixel array 23 can reduce the adverse effect of noise generated near the expansion gate ST on the captured image.

  8 to 11 are explanatory diagrams of operations performed by the pixel array 23 according to the first embodiment in the low noise mode. FIG. 8 shows timing when the transfer gate TG, the extension gate ST, the first reset gate RS1, and the second reset gate RS2 are turned on or off. 9 to 11 show changes in potential distribution in the semiconductor layer 31 in the low noise mode.

  In the low noise mode, the discharge gate ICG is not turned on, and the second reset gate RS2 is not turned off. In the low noise mode, the pixel array 23 first performs an imaging operation after resetting the signal charges remaining in the photoelectric conversion element PD.

  When the pixel array 23 enters the low noise mode, as shown in FIG. 8, the transfer gate TG and the second reset gate RS2 are turned on until the time reaches t20, and the expansion gate ST and the first reset gate RS1 are turned on. It becomes OFF. Thereby, the potential distribution in the semiconductor layer 31 is in the state shown in FIG. In this state, as shown in FIG. 9A, signal charges may remain in the photoelectric conversion element PD.

  Therefore, as shown in FIG. 8, when the time reaches t20, the extension gate ST is turned on. Subsequently, when the time reaches t21, the extension gate ST is turned off. As a result, the potential distribution in the semiconductor layer 31 is in the state shown in FIG. 9B, and then in the state shown in FIG. 9C, the signal charge is below the expansion gate ST in the semiconductor layer 31. The data is transferred to the first floating diffusion FD1 via the N-type region 32.

  Also here, the potential V (IGC) in the lower region of the discharge gate IGC is formed to be higher than the potential V (STa) of the barrier portion when the extension gate ST is OFF, and from the photoelectric conversion element PD to the extension gate ST side. Avoid overflowing the charge.

  As a result, the photoelectric conversion element PD is temporarily reset at time t20 and accumulates signal charges of an image captured from the time t21. Thereafter, as shown in FIG. 8, when the time reaches t22, the transfer gate TG is turned off, and the potential distribution in the semiconductor layer 31 is in the state shown in FIG. As a result, the signal charge remaining in the photoelectric conversion element PD is held in the first floating diffusion FD1.

  Subsequently, as shown in FIG. 8, when the time reaches t23, as shown in FIG. 10B, the extension gate ST is turned on, and the signal charge of the photoelectric conversion element PD moves to a region below the extension gate ST. . Thereafter, as shown in FIG. 8, when the time reaches t24, the extension gate ST is turned off, and the signal charge is held in the region below ST as shown in FIG. 10 (c).

  Subsequently, as shown in FIG. 8, when the time reaches t25, the first reset gate RS1 is turned ON, and the potential distribution in the semiconductor layer 31 becomes the state shown in FIG. 11A, and the first floating diffusion FD1. Is discharged to the reset drain RD via the second floating diffusion FD2. Thereafter, as shown in FIG. 8, when the time reaches t26, the first reset gate RS1 is turned OFF, and the potential distribution in the semiconductor layer 31 is in the state shown in FIG.

  Subsequently, as shown in FIG. 8, when the time reaches t27, the transfer gate TG is turned on, and as shown in FIG. 11C, the signal charge is transferred from the region below the expansion gate ST to the first floating diffusion FD1. Moving. Thereafter, as shown in FIG. 8, when the time reaches t28, the transfer gate TG is turned off.

  Thereby, the potential distribution in the semiconductor layer 31 shifts to the level shown in FIG. 11D, and the signal charge is transferred from the photoelectric conversion element PD to the first floating diffusion FD1 and held. Then, the pixel array 23 outputs an image signal corresponding to the signal charge held in the first floating diffusion FD1 of each pixel.

(Global shutter mode)
The global shutter mode is an operation mode for capturing an image of a subject moving at a relatively high speed, and is a mode in which signal charges are read out from all pixels at once. Thereby, the pixel array 23 can suppress the occurrence of distortion in the image of the subject moving at high speed in the moving image.

  12 to 16 are explanatory diagrams of operations performed by the pixel array 23 according to the first embodiment in the global shutter mode. FIG. 12 shows the timing when the transfer gate TG, the extension gate ST, the first reset gate RS1, and the second reset gate RS2 are turned on or off. 13 to 16 show the transition of the potential distribution in the semiconductor layer 31 in the global shutter mode. In the global shutter mode, the discharge gate ICG is not turned on, and the second reset gate RS2 is not turned off.

  When the pixel array 23 enters the global shutter mode, as shown in FIG. 12, the transfer gate TG and the second reset gate RS2 are turned on until the time reaches t30, and the expansion gate ST and the first reset gate RS1 are turned on. It becomes OFF. As a result, the potential distribution in the semiconductor layer 31 becomes the state shown in FIG. 13A, and signal charges are accumulated in the photoelectric conversion element PD.

  Thereafter, as shown in FIG. 12, when the time reaches t30, the extension gate ST is turned ON, and when the time becomes t31, the extension gate ST is turned OFF. As a result, the potential distribution in the semiconductor layer 31 is in the state shown in FIG. 13B, and subsequently in the state shown in FIG. 13C, and the signal charge is transferred from the photoelectric conversion element PD to the first floating diffusion FD1. Forwarded to At this time, in the pixel array 23, the signal charges are transferred from the photoelectric conversion element PD to the first floating diffusion FD1 all at once.

  Subsequently, as shown in FIG. 12, when the time reaches t32, the transfer gate TG is turned OFF and at the same time the extension gate ST is turned ON. Subsequently, when the time becomes t33, the extension gate ST is turned OFF. As a result, the potential distribution in the semiconductor layer 31 is in the state shown in FIG. 14A, and then in the state shown in FIG. 14B, from the photoelectric conversion element PD to the region below the expansion gate ST in the semiconductor layer 31. Signal charges are transferred to the N-type region 32. At this time, the pixel array 23 transfers signal charges from the photoelectric conversion element PD to the N-type region 32 below the extension gate ST in the semiconductor layer 31 all at once.

  Subsequently, as shown in FIG. 12, when the time reaches t34, the first reset gate RS1 is turned ON for each read row, and subsequently, when the time becomes t35, the first reset gate RS1 is turned OFF. As a result, the potential distribution in the semiconductor layer 31 is in the state shown in FIG. 14C, and subsequently in the state shown in FIG. 15A, and the signal charge is transferred from the first floating diffusion FD1 to the reset drain. Discharged to RD.

  After that, as shown in FIG. 12, when the time reaches t36, the transfer gate TG is turned on. Subsequently, when the time reaches t37, the transfer gate TG is turned off. As a result, the potential distribution in the semiconductor layer 31 becomes the state shown in FIG. 15B, and then the state shown in FIG. 15C, so that the signal charge is below the expansion gate ST in the semiconductor layer 31. It is transferred from the N-type region 32 to the first floating diffusion FD1 and held.

  At this time, the pixel array 23 transfers the signal charge from the N-type region 32 below the expansion gate ST in the semiconductor layer 31 to the first floating diffusion FD1 for each readout row. Then, the pixel array 23 outputs an image signal corresponding to the signal charge held in the first floating diffusion FD1 of each pixel.

  Thereafter, as shown in FIG. 12, when the time reaches t38, the transfer gate TG is turned ON. Thereby, the potential distribution in the semiconductor layer 31 is in the state shown in FIG. Thereafter, the transfer gate TG is turned ON, and the potential distribution in the semiconductor layer 31 returns to the state before time t30 shown in FIG.

(HDR mode)
The HDR mode is an operation mode for capturing an image with higher brightness than an image captured in the high saturation mode. The HDR mode is an operation for discharging the signal charge that is photoelectrically converted to the drain DD, and N under the semiconductor layer 31. In this mode, the transfer to the mold region 32 is repeated to capture an image. Thereby, the pixel array 23 can capture an image with higher brightness than an image captured in the high saturation mode.

  Further, the pixel array 23 performs imaging by a multiple exposure method when operating in the HDR mode. The multiple exposure method performed by the pixel array 23 in this embodiment will be described later with reference to FIG.

  FIGS. 17 to 22 are explanatory diagrams of operations performed by the pixel array 23 according to the first embodiment in the HDR mode. FIG. 17 shows the timing when the discharge gate ICG, the transfer gate TG, the expansion gate ST, the first reset gate RS1, and the second reset gate RS2 are turned on or off.

  18 to 21 show changes in potential distribution in the semiconductor layer 31 in the HDR mode. FIG. 22 shows the timing when the discharge gate ICG and the extension gate ST are turned ON or OFF in the multiple exposure method in the HDR mode. In the HDR mode, an example in which the second reset gate RS2 is always ON is shown.

  When the pixel array 23 enters the HDR mode, as shown in FIG. 17, the discharge gate ICG, the transfer gate TG, the extension gate ST, the first reset gate RS1, and the second reset gate until just before time t41. RS2 is all turned on, and only the extension gate ST is turned off just before time t41. As a result, the potential distribution in the semiconductor layer 31 becomes the state shown in FIG. 18A, and the signal charge accumulated in the photoelectric conversion element PD is output to the drain DD and reset.

  Thereafter, as shown in FIG. 17, when the time reaches t41, the discharge gate ICG, the transfer gate TG, and the first reset gate RS1 are turned OFF. As a result, the potential distribution in the semiconductor layer 31 is in the state shown in FIG. 18B, and the signal charges photoelectrically converted are accumulated in the photoelectric conversion element PD.

  Subsequently, as shown in FIG. 17, when the time reaches t42, the discharge gate ICG is turned ON, and when the time becomes t43, the discharge gate ICG is turned OFF. As a result, the potential distribution in the semiconductor layer 31 is in the state shown in FIG. 18C, and then in the state shown in FIG. 19A, and the photoelectrically converted signal charge is transferred from the photoelectric conversion element PD. The signal charges discharged to the drain DD and newly photoelectrically converted are accumulated in the photoelectric conversion element PD.

  After that, as shown in FIG. 17, when the time reaches t44, the extension gate ST is turned on. Subsequently, when the time becomes t45, the extension gate ST is turned off. As a result, the potential distribution in the semiconductor layer 31 is in the state shown in FIG. 19B, and then in the state shown in FIG. 19C, and the signal charge photoelectrically converted is transferred from the photoelectric conversion element PD. The data is transferred and stored in the N-type region 32 below the extension gate ST.

  Thereafter, as shown in FIG. 17, until the time reaches t50, the potential distribution in the semiconductor layer 31 is as shown in FIG. 18C, FIG. 19A, and FIG. The state shown in (b) and the state shown in (c) in FIG. 19 are sequentially repeated. Thereby, in the N-type region 32 below the extension gate ST in the semiconductor layer 31, the signal charges that have not been discharged to the drain DD among the photoelectrically converted signal charges are accumulated.

  Then, as shown in FIG. 17, when the time reaches t50, the first reset gate RS1 is turned on. Subsequently, when the time reaches t51, the first reset gate RS1 is turned off. As a result, the potential distribution in the semiconductor layer 31 is in the state shown in FIG. 20A, and then in the state shown in FIG. 20B, and the first floating diffusion FD1 is once reset.

  After that, as shown in FIG. 17, when the time reaches t52, the transfer gate TG is turned ON. Subsequently, when the time becomes t53, the transfer gate TG is turned OFF. As a result, the potential distribution in the semiconductor layer 31 is in the state shown in FIG. 21A, and then in the state shown in FIG. 20B, in the semiconductor layer 31, the N-type region 32 below the expansion gate ST. The signal charge is transferred to and held from the first floating diffusion FD1. Then, the pixel array 23 outputs an image signal corresponding to the signal charge held in the first floating diffusion FD1 from each pixel.

  Further, the pixel array 23 performs imaging by a multiple exposure method when operating in the HDR mode. For example, the pixel array 23 performs imaging by setting the exposure time of the pixels in the odd rows to a relatively short time and the exposure time of the pixels in the even rows from the pixels provided in a matrix.

  Then, the signal processing circuit 21 (see FIG. 2) generates a captured image by synthesizing the video signal output from the odd row pixels and the video signal output from the even row pixels. Thereby, the signal processing circuit 21 (see FIG. 2) can reproduce from a very dark subject appearing in one captured image to a very bright subject with high definition.

  Specifically, as shown in FIG. 22A, the pixel array 23 has an imaging time of T for one frame, and the discharge gate ICG is turned off for odd-numbered pixels. The time until the extension gate ST is turned off is controlled to a relatively short time T1.

  Thereby, the signal charges photoelectrically converted during the relatively short time T1 in the time T are sequentially transferred and held in the first floating diffusion FD1 of the pixels in the odd-numbered rows. Thereby, the signal processing circuit 21 (see FIG. 2) can reproduce a bright subject in the captured image with high definition from the image signal output from each pixel in the odd-numbered rows.

  On the other hand, in the pixel array 23, as shown in FIG. 22B, in even-numbered pixels, the time from when the discharge gate ICG is turned off to when the expansion gate ST is turned off is a relatively long time T <b> 2. Be controlled.

  Thereby, the signal charges photoelectrically converted during the relatively long time T2 in the time T are sequentially transferred and held in the first floating diffusion FD1 of the pixels in the even-numbered rows. Thereby, the signal processing circuit 21 (see FIG. 2) can reproduce a dark subject in the captured image with high definition from the image signal output from each pixel in the even-numbered rows.

  Then, the signal processing circuit 21 (see FIG. 2) synthesizes the video signal output from the odd-numbered row pixels and the video signal output from the even-numbered row pixels, thereby forming a very dark subject in the captured image. To very bright subjects.

  Note that the configuration of the pixel array 23 illustrated in FIG. 4 is an example of the first embodiment, and is not limited thereto. Here, with reference to FIG. 23A and FIG. 23B, the pixel arrays 23a and 23b which concern on the modification of 1st Embodiment are demonstrated.

  FIG. 23A is an explanatory diagram illustrating a part in a cross-sectional view of a pixel array 23a according to Modification 1 of the first embodiment. FIG. 23B is an explanatory diagram illustrating a part in a cross-sectional view of the pixel array 23b according to the second modification of the first embodiment.

  Here, among the components of the pixel array 23a shown in FIG. 23A and the pixel array 23b shown in FIG. 23B, the same reference numerals as those shown in FIG. 4 are given to the same components as those shown in FIG. Therefore, the description is omitted.

  As shown in FIG. 23, the pixel array 23a according to Modification 1 is different from that shown in FIG. 4 in that the extension gate is divided into a first extension gate ST1 and a second extension gate ST2, and that the N-type region 32 is not provided. Unlike the pixel array 23 shown, the other configuration is the same as that of the pixel array 23 shown in FIG.

  The first extension gate ST1 is a gate that transfers signal charges from the photoelectric conversion element PD to a region below the second extension gate ST2 in the semiconductor layer 31 when a voltage is applied. The second expansion gate ST2 is a gate that accumulates signal charges by expanding a charge accumulation region of the photoelectric conversion element PD to a region below the second extension gate ST2 in the semiconductor layer 31 when a voltage is applied. is there.

As described above, the pixel array 23a can switch between expansion and contraction of the charge storage region by switching between application and non-application of the voltage to the first extension gate ST1 and the second extension gate ST2.
Then, the pixel array 23a is subjected to the same voltage application control as the pixel array 23 with respect to the discharge gate ICG, the transfer gate TG, the first reset gate RS1, and the second reset gate RS2, so that A similar imaging operation can be performed.

  As shown in FIG. 23B, the pixel array 23b of Modification 2 includes a second extension gate ST2a including an N-type region 32b and a high-concentration P-type layer 32a provided on the surface layer of the N-type region 32b. Thus, in the pixel array 23b, a region that becomes a fixed potential well similar to the photoelectric conversion element PD is formed in the N-type region 32b.

  In addition, the pixel array 23a suppresses the voltage applied to the first extension gate ST1 to be lower than the voltage applied to the second extension gate ST2, so that the photoelectric conversion element PD starts from the region below the second extension gate ST2 in the semiconductor layer 31. The backflow of the signal charge to the can be suppressed.

  As described above, the pixel array according to the first embodiment includes the extended gates stacked in the regions adjacent to the photoelectric conversion elements. When a voltage is applied to the extension gate, a well having a potential continuous with the charge accumulation region of the photoelectric conversion element is formed in a region immediately below the extension gate in the semiconductor layer.

  As a result, the pixel array can increase the number of saturation signal charges that can be accumulated by expanding the charge accumulation region of the photoelectric conversion element, so that the dynamic range of the luminance to be imaged can be expanded.

  The photoelectric conversion elements and the expansion gates are arranged in a staggered pattern in plan view. Thereby, the area of the pixel array can be reduced as compared with, for example, a case where the photoelectric conversion elements and the extension gates are alternately arranged in one direction of the row or column of the photoelectric conversion elements.

(Second Embodiment)
Next, pixel arrays 23c, 23d, and 23e according to the second embodiment will be described with reference to FIGS. The pixel arrays 23c, 23d, and 23e according to the second embodiment described below are all back-illuminated CMOS image sensors.

  FIG. 24 is an explanatory diagram illustrating a part of the pixel array 23c according to the second embodiment in plan view. FIG. 25A is an explanatory diagram illustrating a part of a pixel array 23c according to the second embodiment as viewed in cross section. FIG. 25A schematically shows a cross section of the pixel array 23c shown in FIG. 24 taken along a broken line indicated by a double-headed arrow in the same drawing.

  FIG. 25B is an explanatory diagram illustrating a part in a cross-sectional view of the pixel array 23d according to Modification 1 of the second embodiment. FIG. 26 is an explanatory diagram illustrating a part of a pixel array 23e according to a second modification of the second embodiment as seen in cross section.

  Here, among the constituent elements of the pixel array 23c shown in FIGS. 24 and 25A, the pixel array 23d shown in FIG. 25B, and the pixel array 23e shown in FIG. 26, the constituent elements of the pixel array 23 shown in FIGS. About the component of the substantially same shape which has the same function, the code | symbol same as the code | symbol shown to FIG. 3A and FIG. 4 is attached | subjected, and the description is abbreviate | omitted.

  Since the pixel arrays 23, 23a, and 23b according to the first embodiment described above are all surface-illuminated CMOS image sensors, the multilayer wiring 36 is provided at a position that avoids the light receiving surface of each pixel on the light receiving surface side of the semiconductor layer 31. Is provided (see FIG. 4).

  Thereby, in the pixel arrays 23, 23a, and 23b according to the first embodiment, the light incident on the photoelectric conversion element PD from the oblique direction is shielded by the multilayer wiring 36, and therefore, the occurrence of color mixing can be suppressed.

  On the other hand, in the backside illumination type CMOS image sensor, a multilayer wiring is provided on the front surface side opposite to the back surface serving as the light receiving surface of the semiconductor layer on which the photoelectric conversion element is provided. For this reason, the back-illuminated CMOS image sensor cannot block light incident on the photoelectric conversion element from an oblique direction by the multilayer wiring.

  Therefore, as illustrated in FIG. 24, the pixel array 23c according to the second embodiment includes a DTI (Deep Trench Isolation) 40 that partitions each pixel in plan view. Specifically, the pixel array 23c is provided with a cross-shaped (lattice) DTI 40 that partitions the photoelectric conversion element PD in the semiconductor layer 31 and the region below the extension gate ST.

  The DTI 40 is formed, for example, by forming a trench in the semiconductor layer 31 and providing silicon oxide inside the trench. The DTI 40 can shield light incident on the photoelectric conversion element PD from an oblique direction due to a difference in refractive index between silicon oxide inside the trench and silicon that is a material of the semiconductor layer 31.

  The arrangement of the photoelectric conversion elements PD and the extension gates ST in the pixel array 23c is substantially the same as that of the photoelectric conversion elements PD and the extension gates ST in the pixel array 23 shown in FIG. 3A. That is, the photoelectric conversion elements PD and the expansion gates ST are arranged in a staggered pattern in plan view. As a result, the pixel array 23 c can reduce the occupation area in the same manner as the pixel array 23.

  Note that the transfer gate TG, the reset gate RS, the discharge gate ICG, the reset drain RD, the drain DD, the floating diffusion FD, and the like are provided in the vicinity of the intersection of the lattice formed by the DTI 40. The amplifier transistor AMP and the address transistor ADR are also provided near the intersection of the lattice formed by the DTI 40.

  As a result, the pixel array 23c can sufficiently secure the region occupied by the photoelectric conversion element PD in the semiconductor layer 31 and the region below the expansion gate ST, so that the light receiving sensitivity can be improved and the number of saturation signal charges can be increased. Become.

  The cross-sectional structure of the pixel array 23c is as shown in FIG. 25A. Specifically, as shown in FIG. 25A, in the pixel array 23c, an interlayer insulating film 35 is stacked on the front surface side of the semiconductor layer 31, and a color filter CF and a micro lens ML are provided on the back surface side of the semiconductor layer 31. This is a so-called back-illuminated CMOS image sensor.

  An antireflection film 43 formed of, for example, silicon nitride is provided between the back surface of the region where the photoelectric conversion element PD is provided in the semiconductor layer 31 and the color filter CF. In addition, a light shielding film 44 made of tungsten or the like is provided in a region of the back surface of the semiconductor layer 31 where the antireflection film 43 is not provided.

  As illustrated in FIG. 25B, the pixel array 23d according to the first modification of the second embodiment may be configured to include the antireflection film 43a on the entire back surface (here, the bottom surface) of the semiconductor layer 31. In such a case, in the pixel array 23d, the interlayer insulating film 44 is provided on the back surface (here, the lower surface) of the antireflection film 43a, and the light shielding film 44a is provided at a position facing the extension gate ST inside the interlayer insulating film.

  In the pixel array 23d, the color filter CF is provided at a position facing the photoelectric conversion element PD on the back surface (here, the bottom surface) of the insulating film, and the microlens ML is provided on the back surface (here, the bottom surface) of the color filter. It is done. Thus, the pixel array 23d may have a configuration in which the antireflection film 43 is provided on the entire back surface of the semiconductor layer 31, and the light shielding film 44 is provided below the extension gate ST region.

  The structure of the surface layer of the semiconductor layer 31 and the structure in the interlayer insulating film 35 in the pixel arrays 23c and 23d are basically the same as those of the pixel array 23 shown in FIG. That is, the photoelectric conversion element PD is provided on the surface layer of the semiconductor layer 31, the drain DD and the N-type region 32 are provided adjacent to the photoelectric conversion element PD, and the floating diffusion FD is provided adjacent to the N-type region 32. It is done. In the interlayer insulating film 35, a multilayer wiring 36, a discharge gate ICG, an extension gate ST, a transfer gate TG, and the like are provided.

  However, the semiconductor layer 31 is different from the pixel array 23 shown in FIG. Specifically, the semiconductor layer 31 includes impurity diffusion regions 41 and 42 doped with a P-type impurity such as phosphorus, for example, below the photoelectric conversion element PD and below the N-type region 32.

  Further, the semiconductor layer 31 includes a DTI 40 that partitions the semiconductor layer 31 between the impurity diffusion regions 41 and 42. For example, the DTI 40 is formed from the back surface of the semiconductor layer 31 to a position shallower than the center position in the depth direction of the semiconductor layer 31.

  In the pixel arrays 23c and 23d, voltage is applied or not applied to the gates such as the expansion gate ST, the transfer gate TG, and the discharge gate ICG at the same timing as the pixel array 23 shown in FIG. A signal charge flow indicated by a thick arrow can be formed.

  In other words, the pixel arrays 23c and 23d can store signal charges by applying a voltage to the extension gate ST so that the photoelectric conversion element PD to the N-type region 32 function as a charge storage region.

  The pixel arrays 23c and 23d can transfer signal charges from the N-type region 32 to the floating diffusion FD by applying a voltage to the transfer gate TG. As a result, the pixel arrays 23c and 23d can operate in the same manner as the pixel array 23 shown in FIG. 4, and the dynamic range of luminance that can be imaged can be expanded.

  In addition, since the pixel arrays 23c and 23d can accumulate signal charges in the impurity diffusion region 41 below the photoelectric conversion element PD and the impurity diffusion region 42 below the extension gate ST, the dynamic luminance of the imageable luminance can be obtained. The range can be further expanded.

  In addition, since the pixel arrays 23c and 23d include the DTI 40 that partitions the impurity diffusion regions 41 and 42 in the semiconductor layer 31, the occurrence of color mixing is suppressed by blocking light incident on the photoelectric conversion element PD from an oblique direction. can do.

  In addition, since the DTI 40 can also block light incident on the impurity diffusion region 42 from an oblique direction, generation of parasitic sensitivity due to unnecessary photoelectric conversion by the impurity diffusion region 42 can be suppressed. In addition, since the DTI 40 separates the impurity diffusion regions 41 and 42 not only optically but also electrically, it is possible to suppress the occurrence of signal charge leakage between the impurity diffusion regions 41 and 42. .

  In addition, since the pixel arrays 23c and 23d have a simple pattern in which the DTI 40 has a grid shape in plan view, the pattern formation of the DTI 40 is easy. The shape of the DTI 40 is not limited to a cross-beam shape, and the region where the DTI 40 surrounds the photoelectric conversion element PD (impurity diffusion region 41) in a plan view is a region below the expansion gate ST (impurity diffusion region 42). ) May be larger than the area surrounding. Thereby, the pixel arrays 23c and 23d can further improve sensitivity because the light receiving area of each pixel is enlarged.

  Next, with reference to FIG. 26, a pixel array 23e according to Modification 2 of the second embodiment will be described. As shown in FIG. 26, the pixel array 23e has a structure in which the photoelectric conversion element PD protrudes to the extension gate STa side from the DTI 40, a shape of the extension gate STa, and a structure of a region below the extension gate STa in the semiconductor layer 31. Is different from the pixel array 23c shown in FIG. 25A.

  Specifically, the pixel array 23e includes an N-type impurity diffusion region 52 having an impurity concentration lower than that of the N-type region 32 at a position where the N-type region 32 is provided in the pixel array 23c illustrated in FIG. Further, the pixel array 23e includes an N-type region 51 having an impurity concentration equivalent to that of the N-type region 32 (see FIG. 25A) below the impurity diffusion region 52. The extension gate STa is a trench gate that reaches from the interlayer insulating film 35 to the inside of the impurity diffusion region 52 of the semiconductor layer 31.

  The pixel array 23e is applied with or without applying a voltage to each gate such as the expansion gate STa, the transfer gate TG, and the discharge gate ICG at the same timing as the pixel array 23 shown in FIG. A signal charge flow indicated by

  That is, the pixel array 23e causes the photoelectric conversion element PD to the N-type region 51 to function as a charge storage region when a voltage is applied to the extension gate STa, and more signal charges are transferred to the deep portion of the semiconductor layer 31. Can be accumulated. In addition, since the periphery of the N-type region 51 is surrounded by the DTI 40, leakage of signal charges to the periphery is suppressed.

  The pixel array 23e can transfer signal charges from the N-type region 51 to the floating diffusion FD by applying a voltage to the transfer gate TG. As a result, the pixel array 23e can operate in the same manner as the pixel array 23 shown in FIG. 4, and the dynamic range of luminance that can be imaged can be expanded.

  As described above, the pixel array according to the second embodiment is substantially the same as the pixel array according to the first embodiment in the structure of the surface layer in the semiconductor layer and the structure in the interlayer insulating film provided on the surface side of the semiconductor layer. The back-illuminated type photoelectrically converts light incident from the back side of the semiconductor layer. The pixel array according to the second embodiment includes a DTI that partitions the pixels on the back side of the semiconductor layer.

  As a result, the pixel array according to the second embodiment can expand the dynamic range of luminance that can be imaged, and suppresses the occurrence of color mixing due to light incident from an oblique direction while being a back-illuminated type. Can do.

  In the first and second embodiments described above, the light receiving area of the microlens is set to the plane of the photoelectric conversion element until the outer periphery of the microlens provided on the light receiving surface of the photoelectric conversion element reaches the center of the expansion gate in plan view. It is larger than the light receiving area in view. Thereby, the microlens can condense the light coming toward the extension gate onto the photoelectric conversion element.

  In the first and second embodiments described above, the case where the photoelectric conversion elements PD and the extension gates ST are arranged in a staggered pattern has been described. However, the photoelectric conversion elements PD and the extension gates ST are arranged in a grid pattern. It may be arranged. FIG. 27 is an explanatory diagram viewed from above showing a modification of the arrangement of the photoelectric conversion elements and the extension gates according to the embodiment.

  FIG. 27 is an explanatory diagram viewed from above showing a modification of the arrangement of the photoelectric conversion elements and the extension gates according to the embodiment. FIG. 27 shows a part of the pixel array 23f in plan view. Here, among the components shown in FIG. 27, components having the same functions as those shown in FIG. 3A are given the same reference numerals as those shown in FIG. Description is omitted.

  As shown in FIG. 27, in the pixel array 23f, a row of photoelectric conversion elements PD in which photoelectric conversion elements PD are arranged in the horizontal direction and a row of expansion gates ST in which the extension gates ST are arranged in the horizontal direction are alternately arranged in the vertical direction. Be placed. The photoelectric conversion elements PD and the expansion gates ST are alternately arranged in the column direction.

  Further, on the semiconductor layer 31 between the photoelectric conversion elements PD arranged in the row direction, a set of address transistors ADR and amplifier transistors AMP and drains DD are alternately arranged. A discharge gate ICG is provided between the drain DD and the photoelectric conversion element PD.

  In addition, every other floating diffusion FD is provided on the semiconductor layer 31 between the expansion gates ST arranged in the row direction. A transfer gate TG is provided between the floating diffusion FD and the extension gate ST. A reset gate RS is provided between the floating diffusion FD and the drain DD.

  According to the pixel array 23f, the floating diffusion FD, the drain of the discharge gate ICG, the amplifier transistor AMP, the address transistor ADR, the reset gate RS, and the drain of the reset gate RS can be shared by two pixels.

  Thereby, the pixel array 23f can reduce the area compared to the case where the floating diffusion FD, the drain of the discharge gate ICG, the amplifier transistor AMP, the address transistor ADR, the reset gate RS, and the drain of the reset gate RS are not shared by two pixels. Can do.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 Digital camera, 11 Camera module, 12 Subsequent processing part, 13 Imaging optical system, 14 Solid-state imaging device, 16 Storage part, 17 Display part, 20 Image sensor, 21 Signal processing circuit, 22 Peripheral circuit, 23, 23a, 23b, 23c, 23d, 23e, 23f pixel array, 24 vertical shift register, 25 timing control unit, 28 line memory, 31 semiconductor layer, 32a P type layer, 32, 32b, 51 N type region, 33 well, 34 P type region, 35, 45 interlayer insulation film, 36 multilayer wiring, 41, 42, 52 impurity diffusion region, 43, 43a antireflection film, 44 light shielding film, ADR address transistor, AMP amplifier transistor, CF color filter, DD drain, FD floating device Fusion, FD1 first floating diffusion, FD2 second floating diffusion, ICG discharge gate, ML microlens, PD photoelectric conversion element, RD reset drain, RS reset gate, RS1 first reset gate, RS2 second reset gate, ST, STa Expansion gate, ST1 first expansion gate, ST2 second expansion gate, TG transfer gate.

Claims (5)

A photoelectric conversion element that is provided in the semiconductor layer and converts incident light into signal charges and accumulates, and a photoelectric conversion element that is provided on a region adjacent to the photoelectric conversion element in the semiconductor layer and that is applied with a voltage, thereby the photoelectric conversion A solid-state imaging device, wherein expansion gates that extend the charge storage region of the element are arranged in a staggered pattern in plan view. The expansion gate is
The solid-state imaging device according to claim 1, wherein the solid-state imaging device is provided on substantially the center position of a region surrounded on all sides by the four photoelectric conversion elements adjacent to each other. A floating diffusion provided in the semiconductor layer between two adjacent extension gates;
The solid-state imaging device according to claim 1, further comprising: a transfer gate provided on the semiconductor layer between the extension gate and the floating diffusion. A photoelectric conversion element that is provided in the semiconductor layer and converts incident light into a signal charge and stores it;
An extension gate provided in a region adjacent to the photoelectric conversion element in the semiconductor layer and extending a charge accumulation region of the photoelectric conversion element by applying a voltage;
A solid-state imaging device comprising: a control unit that controls a voltage applied to the expansion gate. A drain provided in a region adjacent to the photoelectric conversion element in the semiconductor layer;
A discharge gate provided on a region between the drain and the photoelectric conversion element in the semiconductor layer, and discharging the signal charge from the photoelectric conversion element to the drain by applying a voltage;
The controller is
The solid-state imaging device according to claim 4, wherein control is performed to alternately apply a voltage to the extension gate and the discharge gate.

Images