JP2017135217A - Nonvolatile semiconductor memory device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device having a structure in which a leak current of an inter-electrode insulating film in writing is reduced.SOLUTION: A nonvolatile semiconductor memory device of an embodiment, comprises: a semiconductor substrate; a first insulator layer formed on the semiconductor substrate; a plurality of charge storage layers formed on the first insulator layer; an element isolation insulating film that is arranged between lower part side surfaces of the plurality of charge storage layers adjacent to each other in a first direction, and is formed up to a depth reaching the semiconductor substrate through the first isolation layer below; a metal film that is formed on the plurality of charge storage layers along an upper part side surface and an upper part that are extended to an upper part from the lower part side surface in the plurality of charge storage layers, and is divided on the element isolation insulation film; a second insulator layer that is formed on the metal film and the element isolation insulating film; and a control gate that is formed on the second insulator layer, and is extended in the first direction. The upper part side surface and the upper surface in the plurality of charge storage layers is opposed to the control gate via the metal film and the second isolation layer.SELECTED DRAWING: Figure 2

Description

  Embodiments described herein relate generally to a nonvolatile semiconductor memory device and a method for manufacturing the same.

  A nonvolatile semiconductor memory device is a NAND type in which a floating gate is formed on a semiconductor substrate through a tunnel insulating film, and a stacked gate structure transistor in which a control gate is formed on the floating gate through an interelectrode insulating film is connected in series. Memory cells are known.

JP 2006-310661 A

  The problem to be solved by the present invention is to provide a nonvolatile semiconductor memory device having a structure in which the leakage current of the interelectrode insulating film during writing is reduced.

  The nonvolatile semiconductor memory device according to the embodiment includes a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, and a plurality of charge storage layers formed on the first insulating layer, adjacent in the first direction. An element isolation insulating film disposed between the lower side surfaces of the plurality of charge storage layers and formed to a depth reaching the semiconductor substrate through the first insulating layer below the plurality of charge storage layers; and A metal film formed on the plurality of charge storage layers along the upper side surface and the upper part extending upward from the lower side surface and divided on the element isolation insulating film, and the metal film and the element A second insulating layer formed on the isolation insulating film; and a control gate formed on the second insulating layer and extending in the first direction. The upper side surface of the plurality of charge storage layers and The upper surface is the metal film Opposed to the control gate via a fine second insulating layer.

1 is a plan view showing a schematic configuration of a nonvolatile semiconductor memory device according to an embodiment. Sectional drawing cut | disconnected in the AA 'direction and B-B' direction of FIG. FIG. 3 is an energy band diagram of the nonvolatile semiconductor memory device according to the embodiment. Sectional drawing explaining the 1st process of the manufacturing method of the non-volatile semiconductor memory device which concerns on this embodiment. Sectional drawing explaining the 2nd process of the manufacturing method of the non-volatile semiconductor memory device which concerns on this embodiment. Sectional drawing explaining the 3rd process of the manufacturing method of the non-volatile semiconductor memory device which concerns on this embodiment.

  Hereinafter, the present embodiment will be described with reference to FIGS. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, in the drawings, the relationship between the thickness and the planar dimension, the ratio of the thickness of each layer, and the like are different from the actual ones and are schematic.

  In the present embodiment, a NAND flash memory will be described as an example of a nonvolatile semiconductor memory device.

  FIG. 1 is a plan view showing a schematic configuration of a memory cell array of the nonvolatile semiconductor memory device according to this embodiment. As shown in FIG. 1, the surface region of the semiconductor substrate 1 is composed of an element region AA (active region) sandwiched between element isolation insulating films STI (Shallow Trench Isolation). A plurality of memory cells MC and selection transistors STD and STS are provided on the element region.

  2A is a cross-sectional view of the memory cell cut along the A-A ′ direction in FIG. 1, and FIG. 2B is a cross-sectional view of the memory cell cut along the B-B ′ direction in FIG. 1. 2A corresponds to a cross section in the channel length direction (gate length direction) of the memory cell MC, and FIG. 2B corresponds to a cross section in the channel width direction (gate width direction) of the memory cell. 2A and 2B, four memory cells are illustrated, but the actual number is different.

  As shown in FIGS. 2A and 2B, the memory cell of the nonvolatile semiconductor memory device used in the present embodiment is a transistor having a stack gate structure in which a control gate 6 is stacked on a floating gate 3.

  The memory cell includes a tunnel oxide film 2 provided on the channel region of the semiconductor substrate 1, a floating gate 3 provided on the tunnel oxide film 2 and having side portions 3a and top portions 3b, and a side portion 3a of the floating gate 3. A metal film 4 covering the top 3b. An interelectrode insulating film 5 provided so as to cover the metal film 4 and a control gate 6 provided on the interelectrode insulating film 5 are provided on the metal film 4. A plurality of such stacked gate structures are arranged along the direction in which the element region AA extends as shown in FIG. The plurality of stack gate structures are connected in series via source / drain regions (not shown) provided on the surface of the semiconductor substrate 1 between adjacent stack gate structures to form a NAND cell string. In FIG. 2B, the top 3 b of the floating gate 3 has a narrower structure than the bottom of the floating gate 3. That is, the length in the channel width direction is smaller in the upper part than in the lower part of the floating gate 3. Such a structure is effectively used because even if the memory cell is miniaturized, the filling of the control gate 6 between the adjacent floating gates 3 in FIG.

  The tunnel oxide film 2 is an arbitrary oxide film such as a silicon oxide film (SiO 2) and has a thickness of about 7 nm.

  The floating gate 3 uses, for example, N + type polysilicon, but is not limited to this. In the present embodiment, the floating gate 3 is a layer for accumulating charges.

  For the metal film 4, for example, ruthenium (Ru) having a work function higher than that of the N + type polysilicon of the floating gate 3 is used. The work function of N + type polysilicon is 4.17 eV. The work function of Ru is 4.68 eV.

  The metal film 4 is not limited to Ru, and can be any metal having a higher work function than N + type polysilicon or a compound thereof. For metals, gold (Au), platinum (Pt), cobalt (Co), beryllium (Be), nickel (Ni), rhodium (Rh), palladium (Pd), tellurium (Te), rhenium (Re), Molybdenum (Mo) or the like is conceivable.

  In the present embodiment, the metal film 4 is a silicided metal. The reason for silicidation is that the metal is dissolved by etching when the metal film 4 is not silicided in the wet etching process of the manufacturing method described later. Further, since the metal film 4 is divided on the element isolation insulating film 7, there is no metal film 4. The thickness of the metal film 4 is preferably about 0.1 nm, for example, but the thickness of the metal film 4 is not limited to this, and can be 0.05 to 0.3 nm.

  The interelectrode insulating film 5 has, for example, a three-layer structure (ONO structure) of silicon oxide film (SiO 2) / silicon oxynitride film (SiN) / silicon oxide film (SiO 2), but is not limited thereto. Other insulating materials may be used, or four or more layers may be used. A single-layer film of a high dielectric film may be used. The film thickness of the interelectrode insulating film 5 is, for example, about 7 nm.

  For example, a silicide film is used for the control gate 6 in order to reduce electric resistance. However, the present invention is not limited to this, and a single-layer structure of a polysilicon film or a two-layer structure (polycide structure) in which a polysilicon film and a silicide film are stacked on the polysilicon film may be used. For example, tungsten silicide (WSi2) is used as the silicide film.

  The control gate 6 functions as a word line WL and is shared between adjacent memory cells with the element isolation insulating film 7 interposed therebetween. Therefore, the control gate 6 is provided not only on the floating gate 3 but also on the element isolation insulating film 7.

  Next, the operation of the nonvolatile semiconductor memory device according to this embodiment will be described.

  3 shows a state in which the floating gate 3 and the control gate 6 face each other through the interelectrode insulating film 5 and the metal film 4 in the memory cell shown in FIGS. 1 and 2, and FIG. It is an energy band figure which shows the state (b) to which Vpgm was applied.

  Note that the write operation in the nonvolatile semiconductor memory device is an operation in which a positive voltage is applied to the control gate 6 with respect to the semiconductor substrate 1 and electrons are injected into the floating gate 3.

  In FIG. 3A, the Fermi level between the silicon substrate (Si-Sub) as the semiconductor substrate 1 and the N + type polysilicon (N + poly-Si) as the floating gate 3 is constant via the tunnel oxide film (TNL). It is kept in. On the other hand, in FIG. 3B, an electric field is generated by applying a voltage, and the Fermi level of N + type polysilicon is reduced. Therefore, an FN (Fowler-Nordheim) tunnel current flows through the tunnel oxide film 2, and electrons e are injected from the semiconductor substrate 1 into the floating gate 3 (S1).

  Similarly, in FIG. 3A, a Schottky junction is formed for the N + type polysilicon and the metal film 4 (Metal layer) 4, and the Fermi level is kept uniform. In FIG. An electric field is generated by the application, and the Fermi level of the metal film 4 becomes smaller than that of N + polysilicon. That is, the energy barrier for the interelectrode insulating film (IPD) 5 is larger in the metal film 4 than in the N + type polysilicon. At this time, since the Fermi level of the N + type polysilicon is higher than the Fermi level of the metal film 4, electrons flow into the metal film 4 side (S2). Due to the presence of the metal film 4, the energy barrier of the interelectrode insulating film 5 is larger than when the metal film 4 is not present, and thus electrons cannot pass through the interelectrode insulating film 5 (S3). Therefore, the leakage current of the interelectrode insulating film 5 can be reduced by disposing the metal film 4 between the floating gate 3 and the interelectrode insulating film 5.

  Next, a method for manufacturing the nonvolatile semiconductor memory device according to the present embodiment will be described.

  4 to 6 are diagrams showing a series of steps of the method for manufacturing the nonvolatile semiconductor memory device of the present embodiment, and show a schematic cross section of a portion along the line B-B 'in FIG.

  As shown in FIG. 4A, a tunnel oxide film 2 having a thickness of about 7 nm is formed on the surface of a semiconductor substrate 1 made of p-type silicon by thermal oxidation. Subsequently, the floating gate 3 made of N + type polysilicon containing impurities is formed on the tunnel oxide film 2 with a thickness of about 70 nm by the CVD (Chemical Vapor Deposition) method.

  Thereafter, the element isolation insulating film 7 is formed so as to be disposed between the floating gates 3 adjacent to each other in the B-B ′ direction of FIG. 1. The element isolation insulating film 7 is formed to a depth reaching the semiconductor substrate 1 through the tunnel oxide film 2. The element isolation insulating film 7 is formed by forming a silicon oxide film (SiO 2) by CVD or applying polysilazane by SOG (Spin On Glass). When forming the element isolation insulating film 7 in an air gap in a later process, it is preferable to form the element isolation insulating film 7 by the SOG method.

  Next, as shown in FIG. 4B, a part of the element isolation insulating film 7 is removed by lithography and RIE (Reactive Ion Etching) to expose the side portion 3a of the floating gate 3. At this time, the top 3b of the floating gate 3 is processed so as to be thinner than the bottom. Here, only the upper side of the side surface of the floating gate 3 is exposed, and the element isolation insulating film 7 disposed adjacent to the lower side of the side surface of the floating gate 3 remains without being removed. . That is, the lower side surface of the floating gate 3 is in contact with the element isolation insulating film 7. Here, the exposed upper side surface among the side surfaces of the floating gate 3 is represented as a side portion 3a, and the following is also treated in the same manner. The top 3b represents the upper surface of the floating gate 3 continuous from the side 3a.

  Next, as shown in FIG. 5A, a metal film 4a is formed on the floating gate 3 and the element isolation insulating film 7 by sputtering. The metal film 4a is, for example, a ruthenium (Ru) film having a thickness of about 0.1 nm. The metal film 4a is in contact with the side 3a and the top 3b of the floating gate 3.

  Next, as shown in FIG. 5B, the metal film 4a in contact with the side 3a and the top 3b of the floating gate 3 is silicided by annealing to form the silicided metal film 4. Silicidation is performed in order to prevent the metal film 4 from being dissolved during wet etching in a later step. Note that the metal film 4a on the element isolation insulating film 7 is not silicided because it does not contact silicon.

  Next, as shown in FIG. 6A, the unnecessary metal film 4a is removed by wet etching. At this time, the non-silicided metal film 4a on the element isolation insulating film 7 is removed. If this step is not performed, the metal film 4a through which electrons pass is positioned between the floating gates 3, and the electrons cannot be stored in the floating gate 3. In addition, this may cause a short circuit between the floating gates 3.

  Next, as shown in FIG. 6B, an interelectrode insulating film 5 is formed on the metal film 4 and the element isolation insulating film 7 which are silicided by the CVD method. A control gate 6 made of N + type polysilicon containing impurities is formed on the interelectrode insulating film 5 by CVD. Thereafter, the stack gate structure including the floating gate 3, the metal film 4, the interelectrode insulating film 5, and the control gate 6 is processed into a line and space shape extending along the B-B ′ direction in FIG. 1.

  Thus, the nonvolatile semiconductor memory device of this embodiment is completed.

According to the nonvolatile semiconductor memory device according to this embodiment, the leakage current generated when the film thickness of the interelectrode insulating film 5 is reduced is reduced by forming the metal film 4 under the interelectrode insulating film 5. can do. The film thickness of the metal film 4 is, for example, 0.1 nm. When the metal film 4 is present, the film thickness of the interelectrode insulating film 5 can be reduced from, for example, 10 nm to 7 nm (original). Therefore, even if the metal film 4 is formed, the memory cell can be miniaturized as a result.
Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Tunnel oxide film 3 Floating gate 3a Side part 3b Top part 4 Silicided metal film
4a Metal film 5 Interelectrode insulating film 6 Control gate 7 Element isolation insulating film

Claims (6)

A semiconductor substrate;
A first insulating layer formed on the semiconductor substrate;
A plurality of charge storage layers formed on the first insulating layer;
An element isolation insulating film disposed between the lower side surfaces of the plurality of charge storage layers adjacent in the first direction and formed to a depth reaching the semiconductor substrate through the first insulating layer below the charge storage layer;
A metal film formed on the plurality of charge storage layers along an upper side surface and an upper part extending upward from the lower side surface of the plurality of charge storage layers, and divided on the element isolation insulating film;
A second insulating layer formed on the metal film and the element isolation insulating film;
A control gate formed on the second insulating layer and extending in the first direction;
With
The nonvolatile semiconductor memory device in which the upper side surface and the upper surface of the plurality of charge storage layers are opposed to the control gate through the metal film and the second insulating layer.   2. The nonvolatile semiconductor memory device according to claim 1, wherein the metal film includes a silicided metal.   The nonvolatile semiconductor memory device according to claim 1, wherein the metal film contains ruthenium. Forming a first insulating layer on the semiconductor substrate;
Forming a plurality of charge storage layers adjacent in a first direction on the first insulating layer;
Forming an element isolation insulating film to a depth reaching the semiconductor substrate through the first insulating layer between the plurality of charge storage layers;
Etching back the element isolation insulating film;
Forming a metal film along the upper side surface, the upper surface, and the upper portion of the element isolation insulating film of the plurality of charge storage layers;
Siliciding the metal film in contact with the plurality of charge storage layers;
Removing the metal film on the element isolation insulating film;
Forming a second insulating layer and a film serving as a control gate on the silicided metal film and the element isolation insulating film;
Processing the plurality of charge storage layers, the silicided metal film, the second insulating layer, and the film serving as the control gate into a line and space shape extending along the first direction;
A method for manufacturing a nonvolatile semiconductor memory device, comprising:   5. The method of manufacturing a nonvolatile semiconductor memory device according to claim 4, wherein, in the step of etching back the element isolation insulating film, an upper side of the plurality of charge storage layers is narrowed from a lower side.   6. The method for manufacturing a nonvolatile semiconductor memory device according to claim 4, wherein the metal film contains ruthenium.

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