JP2017123602A - Control circuit, data processing device, and logic circuit management method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently allocate a logic circuit to an integrated circuit whose logic configuration is rewritable.SOLUTION: A control circuit comprises: a configuration unit that writes a writing target logic circuit and a monitoring circuit for monitoring a data transfer amount of the writing target logic circuit, in any one of a plurality of circuit regions; an acquisition unit that acquires information indicating the data transfer amount of the logic circuit from the monitoring circuit written in the circuit region together with the logic circuit; and a detector that detects a combination of logic circuits that can be allocated to one circuit region among the plurality of logic circuits, on the basis of a determination result that indicates whether or not the data transfer amounts of the plurality of logic circuits included in the combination satisfy a predetermined transfer condition, and a determination result that indicates whether or not the plurality of logic circuits included in the combination fall into one circuit region. The configuration unit, in a case where the combination is detected, writes the plurality of logic circuits included in the combination in the one circuit region to reconfigure a logic configuration of the circuit region.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a control circuit, a data processing device, and a logic circuit management method.

  A data processing device such as a server may have an FPGA (Field Programmable Gate Array) which is a kind of integrated circuit whose logic configuration can be rewritten. For example, a logic circuit (hereinafter also referred to as a user module) designed by a server user is written in the FPGA. In recent years, a system in which a plurality of users jointly use the same FPGA has been proposed (see, for example, Patent Document 1). This type of system writes a plurality of user modules respectively designed by a plurality of users into one FPGA.

  Further, in an FPGA in which circuit functions can be partially reconfigured in a predetermined unit (hereinafter also referred to as a cell), a configuration having a plurality of cells of different sizes has been proposed in order to improve the utilization efficiency of the FPGA. (For example, refer to Patent Document 2). In this type of FPGA, even when cells other than the cell to be rewritten are operating, the circuit function of the cell to be rewritten is reconfigured.

JP 2014-230174 A JP 2002-16489 A

  In an FPGA in which one user module is written for each of a plurality of circuit areas in which the logic configuration can be rewritten, the use efficiency of the FPGA decreases as the user module becomes smaller. On the other hand, when the number of user modules written in one circuit area is simply increased, the data transfer rate of a plurality of user modules written in one circuit area is limited by the data transfer rate of the circuit area, and the performance of the user module May decrease.

  In one aspect, an object of the present invention is to efficiently assign a logic circuit to an integrated circuit whose logic configuration can be rewritten.

  According to one aspect, a control circuit that writes a logic circuit to an integrated circuit having a plurality of circuit regions in which the logic configuration can be rewritten includes a monitoring circuit that monitors a data transfer amount of the writing target logic circuit and the writing target logic circuit; Among the plurality of circuit areas, an acquisition section for acquiring information indicating the data transfer amount of the logic circuit from the monitoring circuit written in the circuit area together with the logic circuit, and a plurality of logic circuits. From the combination of logic circuits that can be assigned to one circuit area, the determination result whether the data transfer amount of the plurality of logic circuits included in the combination satisfies a predetermined transfer condition, and the plurality of logic circuits included in the combination are And a detection unit that detects based on a determination result of whether or not a single circuit region fits. Writing a logic circuit into a single circuit region, to reconstruct the logical structure of the circuit region.

  According to another aspect, the data processing apparatus includes an integrated circuit having a plurality of circuit areas in which the logic configuration can be rewritten, and a control circuit that writes the logic circuits in the plurality of circuit areas. A logic circuit and a monitoring circuit that monitors the data transfer amount of the logic circuit to be written, a configuration unit that writes the data transfer amount to one of a plurality of circuit regions, and information indicating the data transfer amount of the logic circuit together with the logic circuit The data transfer amount of a plurality of logic circuits included in the combination is a combination of an acquisition unit that acquires from the monitoring circuit written in the logic circuit and a combination of logic circuits that can be assigned to one circuit area among the plurality of logic circuits. A detection unit configured to detect based on a determination result whether the transfer condition is satisfied and a determination result whether a plurality of logic circuits included in the combination fits in one circuit area, , When combined is detected, writes the plurality of logic circuits included in the combination in a single circuit region, to reconstruct the logical structure of the circuit region.

  According to another aspect, in a logic circuit management method in which a computer that writes a logic circuit to an integrated circuit having a plurality of circuit areas in which the logic configuration can be rewritten manages the allocation of the logic circuit to the circuit area, the computer The logic circuit and the monitoring circuit that monitors the data transfer amount of the logic circuit to be written are written to one of a plurality of circuit areas, and information indicating the data transfer amount of the logic circuit is written to the circuit area together with the logic circuit. A combination of logic circuits that can be assigned to one circuit area from a plurality of logic circuits and whether the data transfer amount of the plurality of logic circuits included in the combination satisfies a predetermined transfer condition. Based on the determination result and the determination result of whether a plurality of logic circuits included in the combination fit in one circuit area, the combination is detected. If issued, writes a plurality of logic circuits included in the combination in a single circuit region, to reconstruct the logical structure of the circuit region.

  A logic circuit can be efficiently allocated to an integrated circuit whose logic configuration can be rewritten.

It is a figure which shows one Embodiment of a control circuit, a data processor, and a logic circuit management method. It is a figure which shows another embodiment of a control circuit, a data processor, and a logic circuit management method. FIG. 3 is a diagram illustrating an example of a logic circuit and a monitoring circuit illustrated in FIG. 2. It is a figure which shows an example of operation | movement of the data processor shown in FIG. It is a figure which shows an example of the integration process shown in FIG. It is a figure which shows an example of the division candidate search process shown in FIG. It is a figure which shows an example of the division | segmentation process shown in FIG. It is a figure which shows another example of operation | movement of the data processor shown in FIG. It is a figure which shows an example of management of the logic circuit by CPU shown in FIG.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1 shows an embodiment of a control circuit, a data processing device, and a logic circuit management method. A data processing apparatus 10 illustrated in FIG. 1 is an information processing apparatus such as a server having an integrated circuit 100 and a control circuit 200, for example. The integrated circuit 100 is a programmable device such as an FPGA that can program the logic circuit 120 (120A, 120B) used by the user of the data processing apparatus 10, for example. For example, the integrated circuit 100 includes a plurality of circuit areas 110 (110A, 110B, 110C, 110D) whose logic configuration can be rewritten, and a bus BUS connected to the plurality of circuit areas 110. The wiring such as the bus BUS outside the circuit area 110 is, for example, fixedly arranged.

  As shown in parentheses in FIG. 1, the control circuit 200 writes the logic circuit 120 and a monitoring circuit 130 (130A, 130B) that monitors the data transfer amount of the logic circuit 120 in the circuit area 110. For example, the logic circuit 120 executes data transfer with a block (not shown). An example of the state of the circuit areas 110A and 110B in the first stage and the second stage is shown in parentheses shown in FIG. The first stage and the second stage in parentheses shown in FIG. 1 will be described when the reconfiguration operation by the control circuit 200 is described.

  The control circuit 200 writes the logic circuit 120 and the like to the integrated circuit 100 using the circuit area 110 as a writing unit. For example, the control circuit 200 includes a configuration unit 210, an acquisition unit 220, and a detection unit 230. The configuration unit 210, the acquisition unit 220, and the detection unit 230 may be realized only by hardware, or may be realized by controlling the hardware by software. For example, the control circuit 200 may be realized by a processor such as a CPU (Central Processing Unit) executing software. When the control circuit 200 is realized by executing software by a computer including a processor, the operation of the computer is an aspect of a logic circuit management method for managing allocation of the logic circuit 120 to the circuit area 110.

  The configuration unit 210 writes the write target logic circuit 120 and the monitoring circuit 130 that monitors the data transfer amount of the write target logic circuit 120 in any of the plurality of circuit areas 110. Further, the configuration unit 210 reconfigures the logical configuration of the circuit region 110 when the detection unit 230 detects a combination of the logic circuits 120 that can be assigned to one circuit region 110. The reconfiguration operation will be described after the operation of the detection unit 230 is described.

  The acquisition unit 220 acquires information indicating the data transfer amount of the logic circuit 120 written in the circuit area 110 from the monitoring circuit 130 and notifies the detection unit 230 of the information acquired from the monitoring circuit 130.

  For example, the detection unit 230 acquires information indicating the scale of the logic circuit 120 from circuit information for realizing the logic circuit 120, and acquires information indicating the data transfer amount of the logic circuit 120 from the monitoring circuit 130 via the acquisition unit 220. Get. The detection unit 230 then selects a combination of the logic circuits 120 that can be assigned to one circuit area 110 from among the plurality of logic circuits 120, the data transfer amount of the logic circuit 120, the scale of the logic circuit 120, and the circuit area 110. Detect based on scale.

  For example, the detection unit 230 selects a combination of the logic circuits 120 to be determined from the plurality of logic circuits 120. Then, the detection unit 230 determines whether or not a plurality of logic circuits 120 included in the combination of the logic circuits 120 selected as the determination target (hereinafter also referred to as a plurality of determination target logic circuits 120) fits in one circuit area 110. Determine. Further, the detection unit 230 determines whether the data transfer amount of the plurality of logic circuits 120 to be determined satisfies a predetermined transfer condition. Then, the detection unit 230 detects a plurality of determination target logic circuits 120 that fit in one circuit area 110 and satisfy a predetermined transfer condition as combinations of logic circuits 120 that can be assigned to one circuit area 110. .

  Here, in determining whether or not the plurality of logic circuits 120 to be determined fit within one circuit area 110, for example, the detection unit 230 determines that the sum of the scales of the plurality of logic circuits 120 and the monitoring circuit 130 to be determined is. It is determined whether or not the size of one circuit area 110 is less than or equal to. When the sum of the scales of the plurality of logic circuits 120 and the monitoring circuit 130 to be determined is equal to or smaller than the scale of one circuit area 110, the detection unit 230 allows the plurality of logic circuits 120 to be determined to fit in one circuit area 110. Is determined. Note that the detection unit 230 may determine whether the total size of the plurality of logic circuits 120 to be determined is equal to or less than the size of one circuit area 110. That is, the detection unit 230 determines that the plurality of determination target logic circuits 120 can be accommodated in one circuit area 110 when the total size of the determination target logic circuits 120 is equal to or less than the size of one circuit area 110. May be.

  In determining whether the data transfer amount of the plurality of logic circuits 120 to be determined satisfies a predetermined transfer condition, for example, the detection unit 230 calculates the sum of the data transfer amounts of the plurality of logic circuits 120 to be determined. When the average is equal to or less than the first threshold, it is determined that a predetermined transfer condition is satisfied. The first threshold value is set to a value equal to or lower than the data transfer rate of the circuit area 110 corresponding to the bus band between the circuit area 110 and the bus BUS. For example, the first threshold value is set to a value that is about 70% of the data transfer rate of the circuit area 110. Note that the detection unit 230 has an average sum of data transfer amounts of the plurality of logic circuits 120 to be determined that is equal to or less than a first threshold value and a sum of peaks of data transfer amounts of the plurality of logic circuits 120 to be determined. May be determined to satisfy a predetermined transfer condition. In this case, the second threshold value is set to a value larger than the first threshold value. For example, the second threshold value is set to a value that is several times the data transfer rate of the circuit area 110.

  Note that for combinations of logic circuits 120 that do not fit in one circuit area 110, determination as to whether or not a predetermined transfer condition is satisfied may be omitted. In other words, the detection unit 230 may determine whether or not the data transfer amount of the plurality of logic circuits 120 included in the combination of the logic circuits 120 that fits in one circuit region 110 satisfies a predetermined transfer condition. In this case, the detection unit 230 detects a combination satisfying a predetermined transfer condition among combinations of the logic circuits 120 that can be accommodated in one circuit area 110 as a combination of the logic circuits 120 that can be assigned to the one circuit area 110.

  When a combination of logic circuits 120 that can be assigned to one circuit area 110 is detected, the configuration unit 210 writes a plurality of logic circuits 120 included in the detected combination to one circuit area 110. As a result, the logic configuration of the circuit area 110 in which the plurality of logic circuits 120 included in the combination detected by the detection unit 230 is written is reconfigured.

  The operation of the control circuit 200 when reconfiguring the integrated circuit 100 will be described using circuit regions 110A and 110B shown in parentheses in FIG. In the integrated circuit 100, the logic configuration of the circuit areas 110A and 110B can be reconfigured even when the circuit areas 110C and 110D other than the circuit areas 110A and 110B to be rewritten are operating.

  First, in the first stage, the control circuit 200 writes the monitoring circuit 130 that monitors the data transfer amount of the logic circuit 120 and the logic circuit 120 in the integrated circuit 100 for each circuit area 110. As a result, the logic circuit 120A and the monitoring circuit 130A are written in the circuit area 110A, and the logic circuit 120B and the monitoring circuit 130B are written in the circuit area 110B.

  Then, the control circuit 200 repeatedly executes a determination as to whether or not to perform reconfiguration of writing a plurality of logic circuits 120 written in different circuit areas 110 in one circuit area 110 at a predetermined time interval. For example, the control circuit 200 acquires information indicating the data transfer amount during the operation of the logic circuits 120A and 120B from the monitoring circuits 130A and 130B, respectively.

  In the example shown in FIG. 1, the data transfer amount of the logic circuits 120A and 120B satisfies the predetermined transfer condition described above. For example, the average of the total data transfer amounts of the logic circuits 120A and 120B is equal to or less than the first threshold value. The total scale of the logic circuits 120A and 120B and the monitoring circuits 130A and 130B is smaller than the scale of the circuit area 110A. That is, the logic circuits 120A and 120B and the monitoring circuits 130A and 130B are programmable (writable) in one circuit area 110. For this reason, the control circuit 200 determines to execute the reconfiguration of writing the logic circuits 120A and 120B into one circuit area 110A.

  Therefore, in the second stage, the control circuit 200 writes the logic circuits 120A and 120B to the circuit area 110A, and reconfigures the logic configuration of the circuit areas 110A and 110B. The control circuit 200 writes the monitoring circuits 130A and 130B in the circuit area 110A together with the logic circuits 120A and 120B. The logic circuits 120A and 120B and the monitoring circuits 130A and 130B are connected to an internal bus IBUS included in the circuit area 110A. For example, a part of the wiring in the circuit area 110A is used as the internal bus IBUS. In the second stage, the control circuit 200 may cause the logic circuits 120A and 120B to share one monitoring circuit that monitors the data transfer amounts of both the logic circuits 120A and 120B.

  By reconfiguring the logic configuration of the circuit areas 110A and 110B, the logic circuits 120A and 120B and the monitoring circuits 130A and 130B are written into the circuit area 110A, and the circuit area 110B becomes unused. As a result, the circuit area 110B can be assigned to the new logic circuit 120, and the utilization efficiency of the integrated circuit 100 can be improved. That is, the mounting efficiency of the logic circuit 120 can be improved.

  Further, as described above, since the first threshold is a value less than or equal to the data transfer rate of the circuit area 110, the average of the total data transfer amounts of the logic circuits 120A and 120B is less than or equal to the data transfer rate of the circuit area 110. . For this reason, it is possible to suppress the amount of data transfer between the bus BUS outside the circuit area 110 and the logic circuits 120A and 120B from being limited by the bus band between the circuit area 110 and the bus BUS. As a result, it is possible to suppress the performance of the logic circuits 120A and 120B from being degraded.

  The configuration of the data processing device 10 and the configuration of the integrated circuit 100 are not limited to the example shown in FIG. For example, the data processing device 10 may include a plurality of integrated circuits 100. Further, for example, the number of circuit regions 110 may be two or more, and is not limited to four. Further, the data processing apparatus 10 may have a package including a plurality of FPGA chips as the integrated circuit 100. In this case, the data processing apparatus 10 may assign one FPGA chip to one circuit area 110.

  As described above, in the embodiment illustrated in FIG. 1, the data processing apparatus 10 uses combinations of logic circuits 120 that can be assigned to one circuit area 110 as predetermined transfer conditions regarding the data transfer amount of the logic circuit 120, and the scale of the logic circuit 120. And it detects based on the scale of the circuit area 110, etc. By assigning a plurality of logic circuits 120 to one circuit area 110, the utilization efficiency of the integrated circuit 100 can be improved. Further, in a combination that satisfies a predetermined transfer condition, it is possible to prevent the data transfer rate of the plurality of logic circuits 120 included in the combination from being limited by the data transfer rate of the circuit area 110. As a result, it is possible to prevent the performance of the logic circuit 120 from deteriorating. As described above, in the embodiment shown in FIG. 1, the logic circuit 120 can be efficiently allocated to the integrated circuit 100 whose logic configuration can be rewritten.

  FIG. 2 shows another embodiment of an integrated circuit, data processing apparatus, and logic circuit management method. The same or similar elements as those described in FIG. 1 are denoted by the same or similar reference numerals, and detailed description thereof will be omitted. The data processing device 12 illustrated in FIG. 2 includes a CPU 202 instead of the control circuit 200 illustrated in FIG. In the data processing device 12, a memory 300 and an input / output interface 320 are added to the data processing device 10 shown in FIG. Other configurations of the data processing device 12 are the same as or similar to those of the data processing device 10. For example, the data processing device 12 is an information processing device such as a server having the integrated circuit 100, the CPU 202, the memory 300, and the input / output interface 320.

  The integrated circuit 100, the CPU 202, the memory 300, and the input / output interface 320 are connected to the bus BUS2. The integrated circuit 100 is the same as or similar to the integrated circuit 100 shown in FIG. For example, the logic circuit 120 and the monitoring circuit 130 are written in the circuit area 110 of the integrated circuit 100. The logic circuit 120 and the monitoring circuit 130 are connected to an internal bus IBUS that is a part of wiring in the circuit area 110. The internal bus IBUS is connected to a bus BUS arranged outside the circuit area 110, and the bus BUS is connected to a bus BUS2 arranged outside the integrated circuit 100. As a result, the logic circuit 120 and the monitoring circuit 130 are communicably connected to the CPU 202 and the like. Details of the logic circuit 120 and the monitoring circuit 130 written in the circuit area 110 will be described with reference to FIG.

  The CPU 202 is an example of a control circuit that writes the logic circuit 120 or the like into the integrated circuit 100. Hereinafter, the CPU 202 is also referred to as a control circuit 202. The CPU 202 implements the functions of the configuration unit 212, the acquisition unit 220, and the detection unit 232 by executing software stored in the memory 300 or the like, for example. That is, the control circuit 202 includes a configuration unit 212, an acquisition unit 220, and a detection unit 232. The acquisition unit 220 is the same as or similar to the acquisition unit 220 illustrated in FIG.

  The configuration unit 212 has a function of executing division processing in addition to the function of the configuration unit 210 illustrated in FIG. 1. The division process is, for example, a process in which a plurality of logic circuits 120 written in one circuit area 110 are written in a plurality of circuit areas 110. For example, when the circuit area 110 to be divided is detected by the detection unit 232, the configuration unit 212 writes the plurality of logic circuits 120 written in the circuit area 110 to be divided into the plurality of circuit areas 110. Then, the logical configuration of the circuit area to be divided is reconfigured.

  The detection unit 232 has a function of detecting the circuit area 110 to be divided in addition to the function of the detection unit 230 shown in FIG. For example, the detection unit 232 divides the circuit area 110 in which the data transfer amount of the plurality of logic circuits 120 is out of a predetermined transfer condition, among the circuit areas 110 in which the plurality of logic circuits 120 are written, into the circuit area to be divided. 110 is detected.

  The memory 300 stores, for example, programs for the CPU 202 to execute the operations of the configuration unit 212, the acquisition unit 220, and the detection unit 232. The memory 300 stores circuit information for realizing the logic circuit 120. The memory 300 is used as a temporary storage area when the logic circuit 120 executes processing, for example. Note that the data processing device 12 may have a memory including a temporary storage area when the logic circuit 120 executes processing separately from the memory 300.

  The input / output interface 320 communicates with the outside of the data processing device 12. For example, the input / output interface 320 receives various types of information such as circuit information for realizing the logic circuit 120 from the outside of the data processing device 12 and transfers the received information to the CPU 202, the memory 300, and the like.

  The configuration of the data processing device 12 is not limited to the example shown in FIG. For example, the data processing device 12 may include a plurality of integrated circuits 100. Further, the data processing device 12 may have a package including a plurality of FPGA chips as the integrated circuit 100. In this case, the data processing device 12 may assign one FPGA chip to one circuit area 110. In addition, the control circuit 202 including the configuration unit 212, the acquisition unit 220, and the detection unit 232 may be realized only by hardware.

  FIG. 3 is a diagram illustrating an example of the logic circuit 120 and the monitoring circuit 130 illustrated in FIG. The logic circuit 120 has a bus interface 121 connected to the internal bus IBUS. The bus interface 121 executes communication with a device such as the CPU 202 connected to the bus BUS2. For example, the bus interface 121 transfers data DATA (DATAi, DATAo) to and from the CPU 202 using the control signal BCNT (BCNTi, BCNTo).

  3 indicates data DATA output from the logic circuit 120 to the internal bus IBUS, and data DATAi indicates data DATA received by the logic circuit 120 via the internal bus IBUS. The control signal BCNTo indicates the control signal BCNT output from the logic circuit 120 to the internal bus IBUS, and the control signal BCNTi indicates the control signal BCNT that the logic circuit 120 receives via the internal bus IBUS. The control signal BCNT includes a signal notifying a request, information indicating a data size such as an address and a burst length. Therefore, the monitoring circuit 130 can monitor the data transfer amount of the logic circuit 120 by monitoring the control signal BCNT transferred between the bus interface 121 and the internal bus IBUS. In the example illustrated in FIG. 3, the monitoring circuit 130 is provided for each logic circuit 120.

  The monitoring circuit 130 includes a bus interface 131 connected to the internal bus IBUS, a monitoring control unit 132, a data transfer amount calculation unit 133, counters 134 and 135, an average calculation unit 136, a peak calculation unit 137, and a storage Parts 138 and 139.

  The bus interface 131 executes communication with a device such as the CPU 202 connected to the bus BUS2. For example, the CPU 202 uses the control signal CINF to acquire data ADATA and PDATA indicating the average and peak of the data transfer amount of the logic circuit 120 as monitoring results of the monitoring circuit 130, respectively. Hereinafter, the data ADATA is also referred to as an average data transfer amount ADATA, and the data PDATA is also referred to as a peak data transfer amount PDATA.

  The monitoring control unit 132 controls the operation of the monitoring circuit 130. For example, the monitoring control unit 132 includes timers TM1 and TM2. Setting of the time (hereinafter also referred to as timer value) measured by the timers TM1 and TM2 is executed from the CPU 202 through the bus interface 131, for example. For example, the CPU 202 uses the control signal CINF to set timer values indicating the first period and the second period used when calculating the average and peak of the data transfer amount of the logic circuit 120 to the timers TM1 and TM2, respectively. Set. The first period is, for example, a period of several seconds to several minutes. Further, the second period is, for example, a period shorter than the first period, and is a period of about several milliseconds to several seconds.

  Then, every time the first period set in the timer TM1 elapses, the monitoring control unit 132 notifies the counter 134 and the average calculation unit 136 that the first period set in the timer TM1 has elapsed. In addition, every time the second period set in the timer TM2 elapses, the monitoring control unit 132 notifies the counter 135 and the peak calculation unit 137 that the second period set in the timer TM2 has elapsed.

  The data transfer amount calculation unit 133 acquires a control signal BCNT transferred between the bus interface 121 in the logic circuit 120 and the internal bus IBUS. Then, the data transfer amount calculation unit 133 calculates the data transfer amount of the logic circuit 120 based on information indicating the data size included in the control signal BCNT. Then, the data transfer amount calculation unit 133 transfers information indicating the data transfer amount of the logic circuit 120 calculated based on the control signal BCNT to the counters 134 and 135.

  The counter 134 is a counter for calculating the average data transfer amount of the logic circuit 120. For example, the counter 134 resets the counter value to 0 each time a signal indicating that the first period has elapsed is received from the monitoring control unit 132. Each time the counter 134 receives information indicating the data transfer amount of the logic circuit 120 from the data transfer amount calculation unit 133, the counter 134 adds the data transfer amount indicated by the information received from the data transfer amount calculation unit 133 to the counter value. Accordingly, the counter value of the counter 134 indicates the data transfer amount of the logic circuit 120 per first period. The counter value of the counter 134 is notified to the average calculation unit 136.

  The counter 135 is a counter for calculating the peak of the data transfer amount of the logic circuit 120. For example, the counter 135 resets the counter value to 0 every time a signal indicating that the second period has elapsed is received from the monitoring control unit 132. Each time the counter 135 receives information indicating the data transfer amount of the logic circuit 120 from the data transfer amount calculation unit 133, the counter 135 adds the data transfer amount indicated by the information received from the data transfer amount calculation unit 133 to the counter value. Thereby, the counter value of the counter 135 indicates the data transfer amount of the logic circuit 120 per second period shorter than the first period. The counter value of the counter 135 is notified to the peak calculation unit 137.

  The average calculation unit 136 repeatedly acquires the counter value before the counter 134 is reset as the data transfer amount per first period, and the data transfer amount per first period is the data transfer amount (bytes / second) per second. ). Thereby, the data transfer amount per second is repeatedly calculated every first period. Then, the average calculation unit 136 stores the maximum value in the holding unit 138 as the average data transfer amount ADATA among the repeatedly calculated data transfer amounts per second. That is, the average calculation unit 136 updates the average data transfer amount ADATA held in the holding unit 138 every time the data transfer amount per second calculated from the counter value of the counter 134 updates the maximum value. The resetting of the maximum value is executed from the CPU 202 through the bus interface 131, for example.

  The peak calculation unit 137 repeatedly obtains the counter value before the counter 135 is reset as the data transfer amount per second period, and calculates the data transfer amount per second period as the data transfer amount per second (byte / second). ). Thereby, the data transfer amount per second is repeatedly calculated every second period. Then, the peak calculation unit 137 stores the maximum value among the repeatedly calculated data transfer amount per second as the peak data transfer amount PDATA in the holding unit 139. That is, the peak calculation unit 137 updates the peak data transfer amount PDATA held in the holding unit 139 every time the data transfer amount per second calculated from the counter value of the counter 135 updates the maximum value. The resetting of the maximum value is executed from the CPU 202 through the bus interface 131, for example.

  The holding unit 138 holds the average data transfer amount ADATA calculated by the average calculation unit 136. The average data transfer amount ADATA held in the holding unit 138 is transferred to the CPU 202 via the bus interface 131, for example.

  The holding unit 139 holds the peak data transfer amount PDATA calculated by the peak calculation unit 137. The peak data transfer amount PDATA held in the holding unit 139 is transferred to the CPU 202 via the bus interface 131, for example.

  Here, an example of the bit widths of the counters 134 and 135 of the monitoring circuit 130 is shown below. When the bus width between the circuit area 110 and the bus BUS is 128 bits (16 bytes) and the clock frequency used for data transfer is 1 GHz (gigahertz), the upper limit of the data transfer amount per second is 16 gigabytes. It is. In this case, the cumulative value of the data transfer amount between several seconds to several minutes is a value of 64 bits or less without a sign. The average data transfer amount ADATA and the peak data transfer amount PDATA converted to the data transfer amount per second (bytes / second) are also 64 bits or less with no sign. Therefore, the total number of bits of the two counters 134 and 135 and the two holding units 138 and 139 is four times 64 bits and is 32 bytes or less. As described above, since the circuit scale of the monitoring circuit 130 can be reduced with respect to the scale of the circuit area 110, the logic circuit 120 is not accommodated in the circuit area 110 because the monitoring circuit 130 is provided in the circuit area 110. The occurrence frequency of disappearance can be reduced.

  Note that the configurations of the logic circuit 120 and the monitoring circuit 130 are not limited to the example shown in FIG. For example, the CPU 202 may execute the process of converting the data transfer amount per first period and the data transfer amount per second period into the data transfer amount per second. In this case, the data transfer amount indicated by the data ADATA held in the holding unit 138 is the data transfer amount per first period, and the data transfer amount indicated by the data PDATA held in the holding unit 139 is per second period. Data transfer amount.

  When a plurality of logic circuits 120 are written in the circuit area 110, the monitoring circuit 130 may be shared by the plurality of logic circuits 120. In this case, the data transfer amount calculation unit 133 acquires the control signal BCNT transferred between each of the plurality of logic circuits 120 and the internal bus IBUS. That is, the data transfer amount calculation unit 133 acquires the control signal BCNT transferred between the circuit area 110 including itself and the bus BUS shown in FIG. Further, in this case, the monitoring circuit 130 may be fixedly provided outside the circuit area 110.

  FIG. 4 shows an example of the operation of the data processing device 12 shown in FIG. The logic circuit addition process and the reconfiguration process shown in FIG. 4 are realized by controlling the CPU 202 with software, for example. Note that the logic circuit addition process and the reconfiguration process illustrated in FIG. 4 are an aspect of a logic circuit management method in which the computer manages the allocation of the logic circuit 120 to the circuit area 110. For example, the reconfiguration process is repeatedly executed at predetermined time intervals and can be executed in parallel with the logic circuit addition process. First, the logic circuit addition process will be described.

  In step S <b> 100, the CPU 202 adds the monitoring circuit 130 to the logic circuit 120. For example, the CPU 202 adds circuit information for realizing the monitoring circuit 130 to circuit information for realizing the logic circuit 120.

  Next, in step S110, the CPU 202 searches for an empty circuit area 110.

  Next, in step S120, the CPU 202 determines whether there is an empty circuit area 110 or not. If there is a free circuit area 110, the operation of the CPU 202 proceeds to step S130. That is, when an empty circuit area 110 is detected in step S110, the operation of the CPU 202 moves to step S130. On the other hand, if there is no free circuit area 110, the operation of the CPU 202 returns to step S110. That is, when the empty circuit area 110 is not detected in step S110, the operation of the CPU 202 returns to step S110. In this case, the process of step S130 is on standby until an empty circuit area 110 is secured by the integration process of the reconfiguration process or by erasing the logic circuit 120.

  In step S <b> 130, the CPU 202 writes the logic circuit 120 and the monitoring circuit 130 in the empty circuit area 110. For example, the CPU 202 divides the logic circuit 120 and the monitoring circuit 130 into an empty circuit area 110 based on circuit information for realizing the logic circuit 120 to which the monitoring circuit 130 is added, that is, circuit information generated in the process of step S100. Write to. Thereby, the logic circuit addition process is completed. Next, the reconstruction process will be described.

  In step S200, the CPU 202 acquires the data transfer amount of the logic circuit 120 written in each circuit area 110. For example, the CPU 202 acquires the average data transfer amount ADATA and the peak data transfer amount PDATA from the monitoring circuit 130 written in each circuit area 110.

  Next, in step S300, the CPU 202 executes integration processing. In the integration process, when the CPU 202 detects a plurality of logic circuits 120 that can be assigned to one circuit area 110, the CPU 202 writes the detected plurality of logic circuits 120 in one circuit area 110. Details of the integration process will be described with reference to FIG.

  Next, in step S400, the CPU 202 executes a division candidate search process for searching for candidates for the circuit area 110 to be divided (hereinafter also referred to as division candidates). Note that the circuit area 110 to be divided is the circuit area 110 to be divided in step S600. Details of the division candidate search processing will be described with reference to FIG.

  Next, in step S500, the CPU 202 determines whether there is a division candidate. When there is a division candidate, the operation of the CPU 202 moves to step S600. That is, when a division candidate is detected in the division candidate search process in step S400, the operation of the CPU 202 moves to step S600. On the other hand, when there is no division candidate, the current reconstruction process ends. That is, when no division candidate is detected in the division candidate search process in step S400, the current reconstruction process ends.

  Next, in step S <b> 600, the CPU 202 executes a dividing process in which a plurality of logic circuits 120 written in one circuit area 110 are written in a plurality of circuit areas 110. Details of the division processing will be described with reference to FIG. With the end of the division process, the current reconstruction process ends.

  Since the reconfiguration process is repeatedly executed at a predetermined time interval, the process for detecting the circuit area 110 to be divided and the integration process are also repeatedly executed at a predetermined time interval. Further, the operation of the data processing device 12 is not limited to the example shown in FIG. For example, the data processing device 12 may execute either a division process or an integration process as shown in FIG.

  FIG. 5 shows an example of the integration process shown in FIG. That is, FIG. 5 shows an example of step S300 shown in FIG. For example, the process of step S310 is executed after the process of step S200 illustrated in FIG. In addition, the process from step S310 to step S314 may be performed in parallel with the process of step S200 shown in FIG.

  In step S310, the CPU 202 selects two circuit areas 110 from the circuit area 110 in which the logic circuit 120 is written.

  Next, in step S312, the CPU 202 calculates the total size SZ of the logic circuits 120 in the two circuit areas 110 selected in step S310. For example, when two logic circuits 120 are written in one of the two circuit areas 110 and one logic circuit 120 is written in the other of the two circuit areas 110, the CPU 202 increases the scale of the three logic circuits 120. The total value is calculated as the total SZ.

  Next, in step S <b> 314, the CPU 202 determines whether the total size SZ of the plurality of logic circuits 120 in the two circuit areas 110 is less than or equal to the scale of one circuit area 110. As described above, in the example illustrated in FIG. 5, the CPU 202 determines that the size of the monitoring circuit 130 is negligible with respect to the size of the circuit region 110, and the plurality of logic circuits 120 in the two circuit regions 110 are one circuit. It is determined whether or not it fits in the area 110.

  If the total SZ is less than or equal to the scale of one circuit area 110, the operation of the CPU 202 moves to step S316. In other words, when the CPU 202 determines that the plurality of logic circuits 120 in the two circuit areas 110 can be accommodated in one circuit area 110, the CPU 202 moves the operation to step S316. On the other hand, when the total SZ exceeds the scale of one circuit area 110, the operation of the CPU 202 proceeds to step S326. In other words, when the CPU 202 determines that the plurality of logic circuits 120 in the two circuit areas 110 do not fit in one circuit area 110, the CPU 202 moves the operation to step S326.

  In step S <b> 316, the CPU 202 calculates the total average data amount ADy of the plurality of logic circuits 120 in the two circuit areas 110. For example, the CPU 202 selects the average data transfer amount ADATA of each of the plurality of logic circuits 120 in the two circuit areas 110 from the average data transfer amount ADATA acquired in step S200 illustrated in FIG. Then, the CPU 202 calculates the total of the average data transfer amount ADATA of each of the plurality of logic circuits 120 in the two circuit areas 110 as the average data amount ADy.

  Next, in step S318, the CPU 202 determines whether or not the average data amount ADy is equal to or less than the first threshold value. The first threshold value is set in advance to a value equal to or less than the bus bandwidth between the circuit area 110 and the bus BUS (data transfer rate of the circuit area 110). For example, the first threshold is set in advance to a value of about 70% of the bus band between the circuit area 110 and the bus BUS.

  When the average data amount ADy is less than or equal to the first threshold value, the operation of the CPU 202 moves to step S320. On the other hand, when the average data amount ADy exceeds the first threshold, the operation of the CPU 202 proceeds to step S326.

  In step S320, the CPU 202 calculates the total peak data amount PDy of the plurality of logic circuits 120 in the two circuit areas 110. For example, the CPU 202 selects the peak data transfer amount PDATA of each of the plurality of logic circuits 120 in the two circuit areas 110 from the peak data transfer amount PDATA acquired in step S200 illustrated in FIG. Then, the CPU 202 calculates the total peak data transfer amount PDATA of each of the plurality of logic circuits 120 in the two circuit areas 110 as the total peak data amount PDy.

  Next, in step S322, the CPU 202 determines whether or not the total peak data amount PDy is equal to or smaller than a second threshold value. The second threshold is set in advance to a value greater than the first threshold. For example, the second threshold value is set in advance to a value that is several times the bus bandwidth between the circuit area 110 and the bus BUS.

  When the total peak data amount PDy is equal to or smaller than the second threshold value, the operation of the CPU 202 moves to step S324. On the other hand, when the total peak data amount PDy exceeds the second threshold, the operation of the CPU 202 moves to step S326.

  Next, in step S324, the CPU 202 registers the two circuit areas 110 selected in step S310 in the integration candidate Y as a combination of the integration candidate circuit areas 110. The integration candidate Y is, for example, an array or table used in a program for realizing the operation shown in FIG.

Next, in step S326, the CPU 202 determines whether all combinations of the two circuit areas 110 have been selected from the circuit area 110 in which the logic circuit 120 is written. For example, when the logic circuit 120 is written in all of the circuit areas 110A, 110B, 110C, and 110D shown in FIG. 2, there are six combinations shown below.
The breakdown of the six combinations includes the circuit areas 110A and 110B, the circuit areas 110A and 110C, the circuit areas 110A and 110D, the circuit areas 110B and 110C, the circuit areas 110B and 110D, and the circuit area. 110C and 110D.

  When all the combinations are selected, the operation of the CPU 202 moves to step S328. On the other hand, when there is an unselected combination, the operation of the CPU 202 returns to step S310. In the second and subsequent steps S310, the CPU 202 selects the two circuit areas 110 so as not to overlap with the already selected combination.

  In step S328, the CPU 202 determines whether there is a combination registered in the integration candidate Y. In other words, the CPU 202 determines whether or not at least one combination of the circuit areas 110 selected in step S310 is registered in the integration candidate Y. When the combination of the circuit areas 110 is registered in the integration candidate Y, the operation of the CPU 202 moves to step S330. On the other hand, when the combination of the circuit areas 110 is not registered in the integration candidate Y, the integration process ends, and the operation of the CPU 202 moves to step S400 shown in FIG.

  In step S330, the CPU 202 selects a combination having the smallest average data amount ADy calculated in step S316 from the combinations registered in the integration candidate Y. The logic circuit 120 included in the circuit area 110 having the smallest average data amount ADy is a combination of the logic circuits 120 assigned to one circuit area 110. That is, the CPU 202 detects combinations of logic circuits 120 that can be assigned to one circuit area 110 by executing the processing from step S310 to step S324. Then, the CPU 202 determines the combination of the logic circuits 120 to be assigned to one circuit area 110 by executing the process of step S330.

  By selecting a combination having the smallest average data amount ADy, it is possible to reduce the frequency at which the data transfer amounts of the plurality of logic circuits 120 assigned to one circuit area 110 deviate from predetermined transfer conditions.

  Next, in step S <b> 332, the CPU 202 writes the logic circuit 120 included in the combination of circuit areas 110 having the smallest average data amount ADy selected in step S <b> 330 in one circuit area 110.

  For example, when the combination selected in step S330 is a combination of the circuit areas 110A and 110C, the CPU 202 writes the logic circuit 120 included in the circuit area 110A and the logic circuit 120 included in the circuit area 110C into the circuit area 110A. . As a result, the circuit area 110 </ b> C becomes an empty circuit area 110. As a result, the circuit area 110C can be allocated to the new logic circuit 120, and the utilization efficiency of the integrated circuit 100 can be improved. That is, the mounting efficiency of the logic circuit 120 can be improved.

  By executing the process of step S332, the integration process is completed, and the operation of the CPU 202 moves to step S400 shown in FIG.

  Note that the example of the integration process is not limited to the example illustrated in FIG. For example, steps S320 and S322 may be omitted. In step S312, the CPU 202 may calculate the sum of the scales of the logic circuit 120 and the monitoring circuit 130 in the two circuit areas 110 as the total SZ. That is, the CPU 202 may determine whether or not the total scale of the logic circuit 120 and the monitoring circuit 130 in the two circuit areas 110 is less than or equal to the scale of one circuit area 110 in step S314.

  In addition, the CPU 202 may execute the process in step S332 after the determination in step S500 illustrated in FIG. For example, if it is determined in step S500 illustrated in FIG. 4 that there is a division candidate, the CPU 202 may execute the process in step S332 together with the process in step S616 of the division process illustrated in FIG. Further, when it is determined in step S500 illustrated in FIG. 4 that there is no division candidate, the CPU 202 may execute the process of step S332 and end the reconstruction process. When the process of step S332 is executed after the determination of step S500 shown in FIG. 4, the processes after step S400 shown in FIG. 4 are executed based on the state assumed that the process of step S332 is executed. For example, assuming that the process of step S332 is executed, the number of free circuit areas 110 used in step S610 shown in FIG. 7 is a number obtained by adding 1 to the current number of free circuit areas 110. .

  FIG. 6 shows an example of the division candidate search process shown in FIG. That is, FIG. 6 shows an example of step S400 shown in FIG. For example, the process of step S410 is executed after the integration process of step S300 illustrated in FIG.

  In step S410, the CPU 202 determines whether or not the circuit area 110 in which the plurality of logic circuits 120 are written exists. If there is a circuit area 110 in which a plurality of logic circuits 120 are written, the operation of the CPU 202 proceeds to step S412. On the other hand, if there is no circuit area 110 in which a plurality of logic circuits 120 are written, the division candidate search process ends, and the operation of the CPU 202 moves to step S500 shown in FIG.

  In step S412, the CPU 202 selects one circuit area 110 from the circuit area 110 in which the plurality of logic circuits 120 are written.

  Next, in step S414, the CPU 202 calculates the entire average data amount ADz of the plurality of logic circuits 120 in the one circuit area 110 selected in step S412. For example, the CPU 202 selects the average data transfer amount ADATA of each of the plurality of logic circuits 120 in one circuit area 110 selected in step S412 from the average data transfer amount ADATA acquired in step S200 shown in FIG. To do. Then, the CPU 202 calculates the total of the average data transfer amount ADATA of each of the plurality of logic circuits 120 in one circuit area 110 selected in step S412 as the average data amount ADz.

  Next, in step S416, the CPU 202 determines whether or not the average data amount ADz exceeds the first threshold value. For example, the first threshold is the same as the first threshold used in the integration process illustrated in FIG. When the average data amount ADz exceeds the first threshold value, the operation of the CPU 202 moves to step S422. On the other hand, when the average data amount ADz is less than or equal to the first threshold value, the operation of the CPU 202 moves to step S418.

  In step S418, the CPU 202 calculates the total peak data amount PDz of the plurality of logic circuits 120 in one circuit area 110 selected in step S412. For example, the CPU 202 selects the peak data transfer amount PDATA of each of the plurality of logic circuits 120 in the one circuit area 110 selected in step S412 from the peak data transfer amount PDATA acquired in step S200 illustrated in FIG. To do. Then, the CPU 202 calculates the total peak data transfer amount PDATA of each of the plurality of logic circuits 120 in one circuit area 110 selected in step S412 as the total peak data amount PDz.

  Next, in step S420, the CPU 202 determines whether or not the total peak data amount PDz exceeds the second threshold value. For example, the second threshold is the same as the second threshold used in the integration process illustrated in FIG. If the total peak data amount PDz exceeds the second threshold, the operation of the CPU 202 moves to step S422. On the other hand, when the total peak data amount PDz is equal to or smaller than the second threshold value, the operation of the CPU 202 moves to step S424.

  In step S422, the CPU 202 registers one circuit area 110 selected in step S412 as a division candidate circuit area 110 in the division candidate Z. The division candidate Z is, for example, an array or a table used in a program for realizing the operation shown in FIG. That is, the CPU 202 executes the processing from step S412 to step S422, so that the data transfer amount of the plurality of logic circuits 120 is determined from the predetermined transfer condition in the circuit area 110 in which the plurality of logic circuits 120 are written. The detached circuit area 110 is detected.

  Next, in step S424, the CPU 202 determines whether or not all circuit areas 110 to be searched have been selected. That is, the CPU 202 determines whether or not all the circuit areas 110 in which the plurality of logic circuits 120 are written are selected. When there is an unselected circuit area 110 in the search target, the operation of the CPU 202 returns to step S412. That is, the processing from step S412 to step S422 is executed for all circuit regions 110 in which a plurality of logic circuits 120 are written.

  On the other hand, when all the circuit areas 110 to be searched are selected, the division candidate search process ends, and the operation of the CPU 202 moves to step S500 shown in FIG. For example, in step S500 illustrated in FIG. 4, the CPU 202 determines whether there is a division candidate by determining whether the circuit area 110 registered in the division candidate Z exists. That is, when registering the circuit area 110 in the division candidate Z, the CPU 202 determines that there is a division candidate in step S500 shown in FIG. Note that the example of the division candidate search process is not limited to the example shown in FIG. For example, steps S418 and S420 may be omitted.

  FIG. 7 shows an example of the dividing process shown in FIG. That is, FIG. 7 shows an example of step S600 shown in FIG. For example, the process of step S610 is executed when it is determined in step S500 shown in FIG.

  In step S610, the CPU 202 determines whether or not the number of free circuit areas 110 is greater than the reserve number R (R is an integer equal to or greater than 0). The reserve number R is a number reserved in advance for adding a new logic circuit 120. The CPU 202 can easily detect the number of logic circuits 120 that can be newly added by referring to the reserve number R. If the circuit area 110 does not have to be reserved for adding a new logic circuit 120, the reserve number R is set to zero.

  If the number of free circuit areas 110 is greater than the reserve number R, the operation of the CPU 202 moves to step S612. On the other hand, when the number of free circuit areas 110 is equal to or less than the reserve number R, the division process ends. As described above, in the dividing process shown in FIG. 7, it is possible to prevent the empty circuit area 110 reserved for adding the new logic circuit 120 from being used in the dividing process.

  In step S612, the CPU 202 selects the circuit area 110 having the maximum average data amount ADz calculated in step S414 shown in FIG. 6 as the circuit area 110 to be divided among the circuit areas 110 registered in the division candidate Z. To do. The plurality of logic circuits 120 included in the circuit area 110 having the maximum average data amount ADz are logic circuits 120 that are allocated to the two circuit areas 110 separately. That is, the CPU 202 determines a plurality of logic circuits 120 to be allocated to the two circuit areas 110 by executing the process of step S612. By selecting the circuit area 110 having the maximum average data amount ADz, it is possible to improve the performance of the logic circuit 120 that is expected to have the lowest performance.

  Next, in step S614, the CPU 202 divides the plurality of logic circuits 120 included in the circuit area 110 having the maximum average data amount ADz into two groups. For example, the CPU 202 divides the plurality of logic circuits 120 into two groups so that the average data amount AD of each of the two groups is equal to or less than the first threshold value. Note that when the circuit area 110 having the maximum average data amount ADz includes three or more logic circuits 120, the CPU 202 includes a plurality of logic circuits 120 so that the average data amounts AD of the two groups are as equal as possible. May be divided into two groups.

  Next, in step S616, the CPU 202 writes the logic circuits 120 divided into two groups in step S614 in the two circuit areas 110, respectively. That is, the CPU 202 writes the logic circuit 120 included in one of the two groups into one of the two circuit areas 110 and writes the logic circuit 120 included in the other of the two groups into the other of the two circuit areas 110. Thereby, the division process ends.

  Note that the example of the dividing process is not limited to the example shown in FIG. For example, when the number of empty circuit areas 110 is larger than the value obtained by adding 1 to the reserve number R, the CPU 202 may select two circuit areas 110 in step S612. In this case, the CPU 202 may divide the plurality of logic circuits 120 included in the two circuit areas 110 into four groups in step S614. Then, in step S616, the CPU 202 may write the logic circuits 120 divided into four groups into the four circuit areas 110, respectively.

  FIG. 8 shows another example of the operation of the data processing device 12 shown in FIG. The logic circuit addition process and the reconfiguration process shown in FIG. 8 are realized by controlling the CPU 202 with software, for example. Note that the logic circuit addition process and the reconfiguration process illustrated in FIG. 8 are one mode of a logic circuit management method in which the computer manages the allocation of the logic circuit 120 to the circuit area 110.

  The logic circuit addition process shown in FIG. 8 is the same as the logic circuit addition process shown in FIG. The reconstruction process shown in FIG. 8 is the same as or similar to the reconstruction process shown in FIG. 4 except for the timing at which the integration process of step S300 is executed. Step S that is the same as or similar to step S described in FIG. 4 is assigned the same or similar reference numeral, and detailed description thereof is omitted. For example, the reconfiguration process shown in FIG. 8 is repeatedly executed at predetermined time intervals, and can be executed in parallel with the logic circuit addition process.

  After executing the process of step S200, the CPU 202 executes the division candidate search process of step S400. The division candidate search process in step S400 is the same as the division candidate search process shown in FIG. For example, the process of step S410 illustrated in FIG. 6 is executed after the process of step S200 is completed.

  Then, after the division candidate search process in step S400 is completed, the CPU 202 executes the determination in step S500, and when determining that there is no division candidate, executes the integration process in step S300. The integration process in step S300 is the same as the integration process shown in FIG. For example, the process of step S310 illustrated in FIG. 5 is executed when it is determined in step S500 that there is no division candidate. Then, upon completion of the integration process in step S300, the current reconstruction process ends.

  If it is determined in step S500 that there is a division candidate, the division process in step S600 is executed. The dividing process in step S600 is the same as the dividing process shown in FIG. The current reconstruction process ends when the division process in step S600 ends.

  FIG. 9 shows an example of management of the logic circuit 120 by the CPU 202 shown in FIG. In FIG. 9, the monitoring circuit 130 and the like are not shown for easy understanding of the drawing. In the example shown in FIG. 9, the reserve number R is set to zero. In the example shown in FIG. 9, the data transfer amount of the logic circuit 120q is larger than that of the other logic circuits 120, and is almost the same as the bus bandwidth between the circuit area 110 and the bus BUS. Therefore, the data transfer amount when the logic circuit 120q and another logic circuit 120 such as the logic circuit 120p are integrated does not satisfy a predetermined transfer condition. For this reason, the logic circuit 120q is not integrated with other logic circuits 120.

  In the state where the logic circuits 120m and 120n are written in the circuit area 110A and the logic circuits 120o, 120p and 120q are written in the circuit areas 110B, 110C and 110D, respectively, there is no empty circuit area 110 (FIG. 9A). ). In this case, addition of a new logic circuit 120 is put on standby until an empty circuit area 110 is secured by integration processing or erasure of the logic circuit 120.

  For example, when the CPU 202 receives an instruction to erase the logic circuit 120o from the outside of the data processing device 12 via the input / output interface 320 shown in FIG. 2, the CPU 202 erases the logic circuit 120o written in the circuit area 110B. (FIG. 9B). Thereby, an empty circuit area 110B is secured.

  When the CPU 202 receives an instruction to add the logic circuit 120r from the outside of the data processing device 12 via the input / output interface 320, the CPU 202 writes the logic circuit 120r in the circuit area 110B (FIG. 9C).

  Further, the CPU 202 reconstructs the logic circuit 120r as a combination of the logic circuits 120 that can be assigned to one circuit area 110 by reconfiguration processing (reconfiguration processing shown in FIG. 4 or FIG. 8) that is repeatedly executed at predetermined time intervals. , 120p is detected. Then, the CPU 202 writes the logic circuits 120r and 120p in one circuit area 110B. As a result, the logic circuits 120r and 120p are integrated into one circuit area 110B, and an empty circuit area 110C is secured (FIG. 9D).

  In addition, the CPU 202 reconfigures the data transfer amount of the logic circuits 120m and 120n written in one circuit area 110A to a predetermined value as the data transfer amount of the logic circuit 120m increases. It is detected that the transfer condition is not met (dotted line x in FIG. 9E). That is, the CPU 202 detects the circuit area 110A as a division candidate.

  Then, the CPU 202 writes the logic circuits 120m and 120n in two circuit areas 110A and 110C (FIG. 9F). As described above, the management of the logic circuit 120 by the CPU 202 can improve the mounting efficiency of the logic circuit 120 while suppressing the performance degradation of the logic circuit 120.

  Here, for example, in a management method that does not consider the data transfer amount of the logic circuit 120, the logic circuit 120 q and the logic circuit 120 p may be written in one circuit area 110. In this case, the data transfer rate of the logic circuits 120q and 120p written in one circuit area 110 is limited by the data transfer rate of the circuit area 110, and the performance of the logic circuits 120q and 120p may be degraded. Even when the data transfer amount of the logic circuit 120m increases and the data transfer rate of the logic circuits 120m and 120n written in the circuit area 110A is limited by the data transfer rate of the circuit area 110A, the logic of the circuit area 110A The configuration is not reconfigured. In this case, the performance of the logic circuits 120q and 120p deteriorates.

  On the other hand, when the CPU 202 integrates the logic circuit 120q and another logic circuit 120 such as the logic circuit 120q, the data transfer amount does not satisfy a predetermined transfer condition. Do not merge. Therefore, it is possible to suppress the performance of the logic circuit 120q and the like from being degraded. Further, as described above, when the data transfer rate of the logic circuits 120m and 120n written in the circuit area 110A changes to a state limited by the data transfer rate of the circuit area 110A, the CPU 202 determines the logical configuration of the circuit area 110A. Reconfigure. Since the logic circuits 120m and 120n are divided into two circuit areas 110A and 110C, the data transfer amount of each circuit area 110A and 110C satisfies a predetermined transfer condition. Thereby, it can suppress that the performance of each logic circuit 120 falls.

  As described above, also in the embodiment shown in FIG. 2 to FIG. 9, the same effect as that of the embodiment shown in FIG. 1 can be obtained. For example, the CPU 202 writes the combination of the logic circuits 120 satisfying a predetermined transfer condition among the combinations of the logic circuits 120 that can be accommodated in the one circuit area 110 into the one circuit area 110. Thereby, the utilization efficiency of the integrated circuit 100 can be improved while suppressing the performance of the logic circuit 120 from being deteriorated.

  Further, the CPU 202 detects a circuit area 110 in which the data transfer amount of the plurality of logic circuits 120 is out of a predetermined transfer condition from among the circuit areas 110 in which the plurality of logic circuits 120 are written. Reconfigure the configuration. For example, a plurality of logic circuits 120 written in the circuit area 110 whose data transfer amount deviates from a predetermined transfer condition are divided and written in the plurality of circuit areas 110. Thereby, it can suppress that the performance of the logic circuit 120 falls. As described above, the CPU 202 can efficiently assign the logic circuit 120 to the integrated circuit 100 whose logic configuration can be rewritten.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Also, any improvement and modification should be readily conceivable by those having ordinary knowledge in the art. Therefore, there is no intention to limit the scope of the inventive embodiments to those described above, and appropriate modifications and equivalents included in the scope disclosed in the embodiments can be used.

  DESCRIPTION OF SYMBOLS 10, 12 ... Data processing apparatus; 100 ... Integrated circuit; 110 ... Circuit area | region; 120 ... Logic circuit; 121, 131 ... Bus interface; 130 ... Monitoring circuit; 132 ... Monitoring control part; 135, counter, 136, average calculation unit, 137, peak calculation unit, 138, 139, holding unit, 200, control circuit, 202, CPU, 210, 212, component unit, 220, acquisition unit, 230, 232, detection 300; Memory; 320 ... I / O interface; BUS, BUS2 ... Bus; IBUS ... Internal bus; TM1, TM2 ... Timer

Claims (9)

In a control circuit for writing a logic circuit to an integrated circuit having a plurality of circuit regions in which the logic configuration can be rewritten,
A writing unit and a monitoring circuit for monitoring a data transfer amount of the writing target logic circuit, the writing unit in any of the plurality of circuit areas,
An acquisition unit for acquiring information indicating the data transfer amount of the logic circuit from the monitoring circuit written in the circuit area together with the logic circuit;
A combination of logic circuits that can be assigned to one circuit area from among a plurality of logic circuits, a determination result of whether the data transfer amount of the plurality of logic circuits included in the combination satisfies a predetermined transfer condition, and the combination And a detection unit that detects based on a determination result of whether or not a plurality of logic circuits included in the one circuit area fits,
When the combination is detected, the configuration unit writes a plurality of logic circuits included in the combination to the one circuit area, and reconfigures the logic configuration of the circuit area. The control circuit according to claim 1,
The detection unit detects a first circuit area in which a data transfer amount of the plurality of logic circuits included in the combination is out of the transfer condition among circuit areas in which the plurality of logic circuits included in the combination is written. And
When the first circuit region is detected, the configuration unit writes the plurality of logic circuits written in the first circuit region into a plurality of circuit regions, and the logical configuration of the first circuit region A control circuit characterized by reconfiguring. The control circuit according to claim 2,
The detection unit repeatedly executes a process of detecting the first circuit area at a predetermined time interval. The control circuit according to any one of claims 1 to 3,
The control unit, wherein the detection unit repeatedly executes a process of detecting the combination at a predetermined time interval. The control circuit according to any one of claims 1 to 4,
The transfer circuit is characterized in that the average of the total data transfer amounts of a plurality of logic circuits included in the combination is equal to or less than a first threshold value. The control circuit according to any one of claims 1 to 4,
The transfer condition is that a sum of data transfer amounts of a plurality of logic circuits included in the combination is equal to or less than a first threshold value, and a sum of peaks of data transfer amounts of the plurality of logic circuits included in the combination. Is less than or equal to a second threshold value greater than the first threshold value. The control circuit according to any one of claims 1 to 6,
The control circuit written to the one circuit area together with the plurality of logic circuits included in the combination is shared by the plurality of logic circuits included in the combination. In a data processing apparatus including an integrated circuit having a plurality of circuit areas in which a logic configuration can be rewritten, and a control circuit for writing logic circuits in the plurality of circuit areas,
The control circuit includes:
A writing unit and a monitoring circuit for monitoring a data transfer amount of the writing target logic circuit, the writing unit in any of the plurality of circuit areas,
An acquisition unit for acquiring information indicating the data transfer amount of the logic circuit from the monitoring circuit written in the circuit area together with the logic circuit;
A combination of logic circuits that can be assigned to one circuit area from among a plurality of logic circuits, a determination result of whether the data transfer amount of the plurality of logic circuits included in the combination satisfies a predetermined transfer condition, and the combination And a detection unit that detects based on a determination result of whether or not a plurality of logic circuits included in the one circuit area fits,
When the combination is detected, the configuration unit writes a plurality of logic circuits included in the combination into the one circuit area, and reconfigures the logic configuration of the circuit area. In a logic circuit management method in which a computer that writes a logic circuit to an integrated circuit having a plurality of circuit areas in which the logic configuration can be rewritten manages allocation of the logic circuit to the circuit area.
The computer is
Writing a logic circuit to be written and a monitoring circuit for monitoring a data transfer amount of the logic circuit to be written into any of the plurality of circuit areas;
Information indicating the data transfer amount of the logic circuit is acquired from the monitoring circuit written in the circuit area together with the logic circuit,
A combination of logic circuits that can be assigned to one circuit area from among a plurality of logic circuits, a determination result of whether the data transfer amount of the plurality of logic circuits included in the combination satisfies a predetermined transfer condition, and the combination And a plurality of logic circuits included in the one circuit area is detected based on the determination result,
When the combination is detected, a plurality of logic circuits included in the combination are written in the one circuit area, and the logic configuration of the circuit area is reconfigured.

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